Semiconductor device, method for manufacturing semiconductor device, storage device, and electronic apparatus

Abstract

A semiconductor device, a manufacturing method thereof, a storage device, and an electronic apparatus are disclosed. The semiconductor device includes first and second transistor layers and a capacitance layer. The first transistor layer includes a first transistor and first to third conductive structures. The second transistor layer comprises a second transistor; the capacitance layer includes a capacitor. The first transistor comprises a first oxide structure; the first conductive structure and the second conductive structure are respectively connected with the first part and the second part of the first oxide structure, and respectively form a first terminal and a second terminal of the first transistor at the first part and the second part; a first channel is formed in the first oxide structure between the first and second terminals; the third conductive structure comprises a part formed on the first channel and used for a first driving terminal of the first transistor, and a first dielectric layer is arranged between the third conductive structure and the first oxide structure. The first terminal, the second driving terminal and the first end structure are electrically connected. The semiconductor device can realize stable and reliable storage of weight data with a small space size.

Description

Semiconductor device and manufacturing method thereof, computing and storage device, and electronic device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a computing and storage device, and an electronic device. BACKGROUND

[0002] In a conventional computing mode (for example, in a Von Neumann architecture), storage and computing are physically separated. When data processing is performed using the computing mode, data is frequently transmitted between a storage device and a computing device, which causes data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the amount of data processing rapidly increases, and the demand for data transmission also rapidly increases, thereby increasingly highlighting the transmission latency and energy consumption, which restricts the development of data processing capability, making it difficult for the conventional computing mode to meet the demand for processing capability.

[0003] An all-in-one computing and storage architecture can physically fuse storage and computing, and perform computing through a storage device or store data in a computing device, thereby reducing the demand for data transmission, reducing transmission latency and energy consumption, and greatly improving data processing efficiency. However, the all-in-one computing and storage architecture still faces challenges, for example, how to improve the reliability of the all-in-one computing and storage architecture. SUMMARY

[0004] The present disclosure provides a semiconductor device and a manufacturing method thereof, a computing and storage device, and an electronic device to improve the reliability of the all-in-one computing and storage architecture.

[0005] In a first aspect, a semiconductor device is provided, comprising: a first transistor layer comprising a first transistor, a first conductive structure, a second conductive structure, and a third conductive structure, wherein the first transistor comprises a first oxide structure, the first conductive structure connects a first part of the first oxide structure, a first terminal of the first transistor is formed at the first part, the second conductive structure connects a second part of the first oxide structure, a second terminal of the first transistor is formed at the second part, and a first channel is formed in the first oxide structure between the first terminal and the second terminal, the third conductive structure comprises a part formed on the first channel, and is used as a first driving terminal of the first transistor, and has a first dielectric layer between the first oxide structure; a second transistor layer comprising a second transistor, the second transistor comprises a third terminal, a fourth terminal, and a second driving terminal, a second channel is formed between the third terminal and the fourth terminal, the second driving terminal is formed on the second channel, and has a second dielectric layer between the second channel; and a capacitor layer comprising a capacitor, the capacitor comprises a first terminal structure and a second terminal structure, and has a third dielectric layer between the first terminal structure and the second terminal structure, wherein the first terminal, the second driving terminal, and the first terminal structure are electrically connected.

[0006] Optionally, the first conductive structure and the second conductive structure are located in the same conductive layer or in different conductive layers.

[0007] Optionally, the second conductive structure is located in the first conductive layer, and the third conductive structure includes a portion located in the second conductive layer; the first conductive layer extends along a first direction and connects the second terminals of the plurality of first transistors arranged along the first direction in the first transistor layer; and the second conductive layer extends along a second direction and connects the first driving terminals of the plurality of first transistors arranged along the second direction in the first transistor layer.

[0008] Optionally, the first direction and the second direction intersect in the same projection direction.

[0009] Optionally, the capacitor layer is located between the first transistor layer and the second transistor layer.

[0010] Optionally, the first conductive structure and the first terminal structure are formed in the same conductive layer.

[0011] Optionally, the first portion of the first oxide structure and the first terminal structure of the capacitor have a second oxide structure therebetween.

[0012] Optionally, the second portion of the first oxide structure and the second conductive structure have a third oxide structure therebetween.

[0013] Optionally, the first transistor layer includes a first opening formed on the first conductive structure, and the second conductive structure is connected to the sidewall of the first opening; and the first oxide structure includes a portion formed in the first opening, the first portion is located at the bottom of the first opening, and the second portion is located at the sidewall of the first opening and connected to the second conductive structure.

[0014] Optionally, the first transistor layer includes a first opening, the first oxide structure includes a portion formed in the first opening, the third conductive structure is formed on the outer sidewall of the first opening, and the first conductive structure and the second conductive structure are respectively formed at two ends of the first opening.

[0015] Optionally, the second transistor layer includes a second transistor, a fourth conductive structure, a fifth conductive structure, and a sixth conductive structure, wherein the second transistor includes a fourth oxide structure, the fourth conductive structure connects a third portion of the fourth oxide structure and forms a third terminal at the third portion, the fifth conductive structure connects a fourth portion of the fourth oxide structure and forms a fourth terminal at the fourth portion, a second channel is formed between the third terminal and the fourth terminal in the fourth oxide structure, the sixth conductive structure includes a portion formed on the second channel, is used as a second driving terminal of the second transistor, and has a second dielectric layer between the sixth conductive structure and the fourth oxide structure.

[0016] Optionally, the second transistor includes a silicon transistor.

[0017] Optionally, the semiconductor device further comprises: a third conductive layer extending along a third direction and connected to third terminals of a plurality of second transistors arranged along the third direction in the second transistor layer; and a fourth conductive layer extending along a fourth direction and connected to fourth terminals of a plurality of second transistors arranged along the fourth direction in the second transistor layer, wherein the third direction and the fourth direction cross in the same projection direction.

[0018] Optionally, the second transistor layer comprises a first group of second transistors and a second group of second transistors arranged along the fourth direction, and the fourth conductive layer is connected to the fourth terminals of the second transistors in the first group and the second group.

[0019] Optionally, the second transistor layer comprises a second transistor set comprising second transistors arranged along the third direction and sharing the third terminals, and the third conductive layer is connected to the third terminals of the second transistors in the second transistor set.

[0020] In a second aspect, a method for manufacturing a semiconductor device is provided, comprising: forming a first transistor layer comprising a first transistor, a first conductive structure, a second conductive structure and a third conductive structure, wherein the first transistor comprises a first oxide structure, the first conductive structure is connected to a first part of the first oxide structure and forms a first terminal of the first transistor at the first part, the second conductive structure is connected to a second part of the first oxide structure and forms a second terminal of the first transistor at the second part, a first channel is formed in the first oxide structure between the first terminal and the second terminal, and the third conductive structure comprises a part formed on the first channel and serving as a first driving terminal of the first transistor, and has a first dielectric layer between the first oxide structure; forming a second transistor layer comprising a second transistor, the second transistor comprising a third terminal, a fourth terminal and a second driving terminal, a second channel being formed between the third terminal and the fourth terminal, and the second driving terminal being formed on the second channel and having a second dielectric layer between the second channel; and forming a capacitor layer comprising a capacitor, the capacitor comprising a first terminal structure and a second terminal structure, and having a third dielectric layer between the first terminal structure and the second terminal structure, wherein the first terminal, the second driving terminal and the first terminal structure are electrically connected.

[0021] In a third aspect, a memory-computing device is provided, comprising: a memory circuit comprising the semiconductor device as described above; and a control circuit configured to control an operating state of the memory circuit.

[0022] In a fourth aspect, an electronic device is provided, comprising the memory-computing device as described above. BRIEF DESCRIPTION OF DRAWINGS

[0023] The embodiments shown in the drawings are merely illustrative and do not limit the scope of the claims. In the drawings, like numerals refer to like but not necessarily identical elements.

[0024] FIG. 1 shows a schematic diagram of a storage and computing device according to an exemplary embodiment of the present disclosure;

[0025] FIG. 2 shows a schematic diagram of a storage and computing device according to an exemplary embodiment of the present disclosure;

[0026] FIG. 3 shows a cross-sectional side view of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0027] FIG. 4 shows another cross-sectional side view of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0028] FIG. 5 shows a cross-sectional top view of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0029] FIG. 6 shows a cross-sectional side view of another semiconductor device according to an exemplary embodiment of the present disclosure;

[0030] FIG. 7 shows another cross-sectional side view of another semiconductor device according to an exemplary embodiment of the present disclosure;

[0031] FIG. 8 shows a cross-sectional side view of yet another semiconductor device according to an exemplary embodiment of the present disclosure;

[0032] FIG. 9 shows a cross-sectional side view of yet another semiconductor device according to an exemplary embodiment of the present disclosure;

[0033] FIG. 10 shows a cross-sectional side view of yet another semiconductor device according to an exemplary embodiment of the present disclosure;

[0034] FIG. 11 shows a cross-sectional side view of yet another semiconductor device according to an exemplary embodiment of the present disclosure;

[0035] FIG. 12 shows a cross-sectional top view of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0036] FIG. 13 shows a cross-sectional top view of another semiconductor device according to an exemplary embodiment of the present disclosure;

[0037] FIG. 14 shows a cross-sectional top view of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0038] FIG. 15 shows a cross-sectional top view of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0039] FIG. 16 shows a cross-sectional top view of a semiconductor device according to an example embodiment of the present disclosure;

[0040] FIG. 17 shows a flowchart of an example method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0041] FIG. 18 shows a schematic diagram of an electronic device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In the drawings, only parts related to the corresponding embodiments are schematically shown in each of the drawings in the embodiments of the present disclosure, and they do not represent actual structures of products. In addition, in order to make the drawings simple and easy to understand, in some drawings, only some structures or components are schematically shown, and there can be more or less the same or similar structures or components.

[0043] In the present disclosure, unless explicitly specified and limited, ordinal numbers such as "first", "second", and the like are used only to distinguish the described objects, and cannot be understood as indicating or implying the relative importance or order of the described objects. In addition, the ordinal numbers do not represent the number of the described objects. "Plural" includes two or more, and other quantifiers are similar. "Or", "and / or" are used to describe the relationship between the objects, which means non-exclusive inclusion. For example, "A and / or B", "A or B" can include: "A alone", "B alone", or "A and B". For another example, "A, B, and / or C", "A, B, or C" can include: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B, and C". In addition, " / " in the present disclosure is used to represent the "or" relationship between the front and rear objects. "One or more of A and B" or "at least one of A and B" in the present disclosure has the same meaning as "A and / or B", "A or B" above. "One or more of A, B, and C" or "at least one of A, B, and C" has the same meaning as "A, B, and / or C", "A, B, or C" above.

[0044] In the present disclosure, unless explicitly specified and limited, "connection" includes direct connection or indirect connection between objects: the connection between the objects can be directly connected through a medium (for example, a wire, a trace, etc.), or can be indirectly connected through other elements, or can be internal communication. "Coupling" includes signal connection between objects, which can be directly connected through a medium (for example, a wire, a trace, etc.), or can be connected through other elements, etc. "Ground" includes direct grounding or indirect grounding, and indirect grounding includes grounding through other elements, for example.

[0045] In the storage-computing integrated technology, a storage-computing device can implement in-memory computing (or operation) by taking a memory as a carrier. The memory can include a non-volatile memory (NVM) or a volatile memory (VM). The volatile memory may, for example, include but is not limited to a static random access memory (SRAM), and the non-volatile memory may, for example, include but is not limited to a flash, a resistive random access memory (RRAM), a magnetoresistive random access memory (MRAM), or a phase change memory (PCM), etc.

[0046] For ease of understanding, FIG. 1 shows a schematic diagram of a storage-computing device according to an example embodiment of the present disclosure.

[0047] As shown in FIG. 1, the storage-computing device 100 can include a storage circuit 110 and a control circuit 120. The storage circuit 110 can be configured to store weight data (which can also be referred to as weights), and the control circuit 120 can be configured to control the working state of the storage circuit 110. The working state of the storage circuit 110 may, for example, include a programming state and a computing state. In the programming state, the weight data is written into the storage circuit. In the computing state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store a plurality of weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store the weight data in units of cells, which can also be referred to as storage units or storage structures. For example, the storage circuit 110 can include a cell array including a plurality of cells arranged in an array.

[0048] The cell can utilize the on-state capability of a semiconductor device, such as an electric conductance or a transconductance, to implement the storage of the weight data. For example, the cell can include a resistive memory device or a transistor memory device. For example, the storage of the weight data can be implemented by controlling the electric conductance of the resistive memory device, or by controlling the transconductance of the transistor memory device.

[0049] The storage circuit 110 can perform calculation in groups. For example, the storage unit array can include at least one storage unit group, the storage unit group includes a plurality of storage units, and a plurality of weight data can be stored in the plurality of storage units, which can be equivalent to a first data vector (or a first data matrix). In the programming state, the weight data is written into the storage units, which is equivalent to writing the first data vector (or the first data matrix) into the storage unit group in the storage unit array. In the calculation state, the storage circuit 110 receives an input signal, the conduction capability of the storage units can change the input signal to obtain an output signal, and the cumulative output of the output signal in the storage unit group can realize equivalent multiplication operation. The storage unit array can include a one-dimensional array or a two-dimensional array, and the storage unit group can include a plurality of storage units in the same row or the same column in the storage unit array, or a plurality of storage units in multiple rows or multiple columns, and the like. The plurality of storage units can output their output signals in line.

[0050] According to some embodiments, the storage and calculation device 100 can further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert the input data D1 into at least one input signal Sin provided to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on the weight data; and the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of the first data vector (or the first data matrix) and the second data vector (or the second data matrix).

[0051] As an example, FIG. 2 shows a schematic diagram of a storage and calculation device according to an exemplary embodiment of the present disclosure.

[0052] As shown in FIG. 2, the storage-computing device 200 includes a storage cell array 210 including a plurality of storage cells Sij, where i∈[1, m], j∈[1, n], m is the number of rows of the storage cell array, and n is the number of columns of the storage cell array. The storage cells Sij can store weight data Wij. A control circuit 220 is configured to control the working state of the storage cell array 210, for example, including a programming state and a computing state. When the storage cell array 210 is in the programming state, the on-state capability of the storage cells Sij can be controlled based on the weight data to reach a target state, so as to achieve storage of the weight data. When the storage cell array 210 is in the computing state, an input signal, for example, an input voltage Vi, can be provided to the storage cells Sij through the input terminals IN of the storage cells Sij, and the storage cells Sij output their output signals, for example, output currents, at the output terminals OUT. The output terminals of a plurality of storage cells (for example, S1j-Smj) can be output in parallel, and according to Kirchhoff's law, the output signals of the plurality of storage cells are accumulated, and the obtained output signal Ij satisfies the following formula:

[0053] According to some embodiments, the input data can include digital input signals, and the input signals Vi of the storage cell array 210 can include analog signals. The input circuit 230 can include, for example, a digital to analog converter (DAC) to convert the digital signals into analog signals and provide the analog signals to the storage cell array 210. According to some embodiments, the input signals of the storage cell array 210 can include digital signals, which can be represented by the waveform characteristics of the signals, for example, the pulse width, amplitude, or area of the signals, etc. The input circuit 230 can adjust the waveform of the signals based on the input data to obtain the input signals and provide the input signals to the storage cell array.

[0054] According to some embodiments, the output circuit 240 can include an analog to digital converter (ADC) to convert the output signals of the storage cell array 210 into digital signals and provide the digital signals to a subsequent circuit. In some embodiments of the present disclosure, the input signals can include voltage signals, and the output signals can include current signals. The storage-computing device 200 can further include a conversion circuit 250 configured to convert the current signals into voltage signals and provide the voltage signals to the output circuit 240 for analog to digital conversion. For example, the conversion circuit 250 can include a transimpedance amplifier (TIA).

[0055] The accurate and stable storage of weight data by the storage circuit is related to the reliability of the compute-in-memory architecture. Embodiments of the present disclosure provide a semiconductor device to improve the accuracy and stability of the storage of weight data by the storage circuit through the structural design of the semiconductor device, thereby improving the reliability of the compute-in-memory architecture. For example, the semiconductor device is used to implement the above storage circuit, which includes a first transistor layer, a second transistor layer, and a capacitor layer. The first transistor layer can integrate a plurality of first transistors, the second transistor layer can integrate a plurality of second transistors, and the capacitor layer can integrate a plurality of capacitors. The first transistor, the second transistor, and the capacitor can be used to implement a storage cell of the above storage circuit. In the storage cell, the non-driving terminal of the first transistor, the driving terminal of the second transistor, and one end of the capacitor are connected. The storage of weight data is implemented by using the charge (e.g., voltage) at the driving terminal of the second transistor. The driving terminal of the second transistor or any voltage node connected thereto can be understood as a storage node (SN) of the storage cell. The first transistor can also be referred to as a write transistor (abbreviated as write tube), and the second transistor can also be referred to as a read transistor (abbreviated as read tube). The arrangement of the capacitor can make the charge at the storage node remain for a longer time, so that the weight data stored in the storage cell has a longer stability. In addition, the layered implementation of different parts in the storage cell can make the space utilization of the semiconductor device higher and the size smaller. In addition, the transistor with an oxide structure is manufactured between the conductive structures. Not only can the oxide structure be used to reduce the leakage current of the transistor and reduce the leakage of the stored charge of the capacitor, so that the storage of weight data is more stable and reliable, but also a smaller size transistor can be implemented, further saving chip area and reducing cost. Moreover, in combination with the layered structure, the storage performance is further improved. Therefore, more stable and reliable storage of weight data can be implemented in a smaller space size or area, improving the reliability of the compute-in-memory architecture. In addition, due to the reduction of the space size or area, more available space or area can be provided for other circuits in the chip, such as a logic circuit, which is beneficial to the performance improvement of the logic circuit.

[0056] According to some embodiments, the oxide structure can include an oxide semiconductor with a band gap greater than or equal to 1.65 eV. For example, the oxide semiconductor can include indium gallium zinc oxide (IGZO), germanium (Ge) doped indium germanium oxide (InGeO), or indium tin oxide (ITO), etc. The selection of the oxide semiconductor can make the leakage performance of the write tube better, and can better inhibit the leakage at the storage node, so that the stored weight data of the storage cell can be stably maintained for a longer time.

[0057] A "layer" can refer to a spatial region where a plurality of elements, factors or structures distributed along a certain direction are located. The present disclosure does not limit the distribution manner, for example, the elements, factors or structures can be continuously distributed, regularly or irregularly spaced. The present disclosure does not limit the height of the spatial region, which can have different heights based on the size of the included elements, factors or structures. There can be partial overlap between layers, without necessarily being a plurality of regions that are completely independent of each other in space.

[0058] It should be understood that the positional relationship of the elements, factors or structures presented in the schematic diagrams of the present disclosure is only for example, and is shown for the purpose of convenience of explanation, and the elements, factors or structures shown in the figures do not necessarily mean that they are at substantially the same height in a certain direction in the device, or necessarily exist in a certain single cross section of the device at the same time, just because they are shown in the figure at the same time.

[0059] The following will be described with reference to the accompanying drawings:

[0060] FIG. 3 shows a cross-sectional side view of a semiconductor device according to an exemplary embodiment of the present disclosure. As shown in FIG. 3, the semiconductor device 300 can include a first transistor layer 310, a second transistor layer 320 and a capacitor layer 330. The first transistor layer 310 can include a first transistor T1, a first conductive structure 311, a second conductive structure 312 and a third conductive structure 313. The first transistor T1 includes a first oxide structure O1; the first conductive structure 311 connects a first portion (shown in a rectangular dashed line box in FIG. 3) of the first oxide structure O1, at which a first terminal T11 of the first transistor T1 is formed; the second conductive structure 312 connects a second portion (shown in a circular dashed line box in FIG. 3) of the first oxide structure O1, at which a second terminal T12 of the first transistor T1 is formed. A first channel (shown in an elliptical dashed line box in FIG. 3) is formed within the first oxide structure O1 between the first terminal T11 and the second terminal T12. The third conductive structure 313 includes a portion formed on the first oxide structure O1, which is used as a first driving terminal T13 of the first transistor, and has a first dielectric layer D1 between the first oxide structure O1. The second transistor layer 320 includes a second transistor T2. The second transistor T2 includes a third terminal T21, a fourth terminal T22 and a second driving terminal T23, and a second channel (shown in an elliptical dashed line box in FIG. 3) is formed between the third terminal T21 and the fourth terminal T22. The second driving terminal T23 is formed on the second channel and has a second dielectric layer D2 between the second channel. The capacitor layer 330 includes a capacitor C, which includes a first end structure C11 and a second end structure C12, and has a third dielectric layer D3 between the first end structure C11 and the second end structure C12. The first terminal T11, the second driving terminal T23 and the first end structure C11 are electrically connected.

[0061] To show the connection relationship between the elements, factors or structures in the semiconductor device 300, FIG. 4 shows another cross-sectional side view of a semiconductor device according to an example embodiment of the present disclosure. FIG. 5 shows a cross-sectional top view of a semiconductor device according to an example embodiment of the present disclosure. Among them, FIG. 5 schematically shows the partial layout relationship of the elements, factors or structures obtained by viewing the second transistor layer 320 of the semiconductor device 300 from above and the conductive layer connected to the second transistor layer 320. FIG. 3 schematically shows the partial layout relationship of the elements, factors or structures obtained by viewing the semiconductor device 300 from the side at the cross-section of position A-A' in FIG. 5, and FIG. 4 schematically shows the partial layout relationship of the elements, factors or structures obtained by viewing the semiconductor device 300 from the side at the cross-section of position B-B' in FIG. 5.

[0062] In the above embodiment, the second transistor T2 is described by taking the example of including a silicon transistor. The second transistor T2 (or read tube) adopts a silicon transistor, and the manufacturing process of the silicon transistor is relatively mature and stable, and the yield and consistency parameters are good. By adopting the silicon transistor, not only can the existing mature process be reused to reduce the process modification cost, but also the consistency of the read tube in the second transistor layer can be improved, so that when the semiconductor device is used for computing in the storage-computing integrated architecture, the read tube consistency between the storage units is good, and the noise is low, thereby further improving the reliability of the storage-computing integrated architecture. In addition, the channel carrier mobility of the silicon transistor is large, so that a larger current can be generated; and the logic circuit process steps can be shared, thereby reducing the introduction of additional manufacturing processes.

[0063] For ease of display, only two transistors or capacitors in a transistor layer (for example, a first transistor layer or a second transistor layer) or a capacitor layer are shown in FIGS. 3 and 4, but the disclosure is not limited thereto. The transistor layer or the capacitor layer can include a larger number of transistors (for example, first transistors or second transistors) or capacitors. The transistors or capacitors in the transistor layer or the capacitor layer can be arranged in an array, which can include a one-dimensional array or a two-dimensional array, etc.

[0064] According to some embodiments, the first conductive structure 311 and the second conductive structure 312 can be located in different conductive layers, that is, at different heights in the semiconductor device 300; for example, in the conductive layer 340 and the conductive layer 350, respectively. In this way, a first channel can be formed between the first terminal T11 and the second terminal T12 by utilizing the vertical space. The size and area of the first transistor T1 are further reduced, so that the size or area of the first transistor layer 310 is further reduced.

[0065] For example, referring to FIG. 3 and FIG. 4, the first transistor layer 310 can include a first opening H1 formed on the first conductive structure 311, and the second conductive structure 312 is connected to the sidewall of the first opening H1. The first oxide structure O1 includes a portion formed in the first opening H1, a first portion is located at the bottom of the first opening H1, and a second portion is located at the sidewall of the first opening H1. The third conductive structure 313 includes a portion formed in the first opening H1, i.e., a portion formed on the first channel can be used as a first driving terminal T13.

[0066] For another example, FIG. 6 shows a sectional side view of another semiconductor device according to an example embodiment of the present disclosure. FIG. 7 shows another sectional side view of another semiconductor device according to an example embodiment of the present disclosure. Similar to FIG. 3 and FIG. 4, FIG. 6 schematically shows the partial layout relationship of elements, factors or structures obtained by observing the semiconductor device 600 from the side at the section of position A-A’ in FIG. 5, and FIG. 7 schematically shows the partial layout relationship of elements, factors or structures obtained by observing the semiconductor device 600 from the side at the section of position B-B’ in FIG. 5.

[0067] Referring to FIG. 6 and FIG. 7, the semiconductor device 600 includes a first transistor layer 610, a second transistor layer 620 and a capacitor layer 630. The descriptions of the first transistor layer 610, the second transistor layer 620 and the capacitor layer 630 refer to the above embodiments. The difference between the semiconductor device 600 and the above embodiments includes that the structure of the first transistor T1 is different. The first transistor layer 610 includes a first opening H1, and the first oxide structure O1 includes a portion formed in the first opening H1. The first conductive structure and the second conductive structure are respectively formed at two ends of the first opening H1. The third conductive structure 613 is formed on the outer sidewall of the first opening H1, for example, the first dielectric layer D1 surrounds the inner sidewall of the first opening H1, and the third conductive structure 613 surrounds a portion of the outer sidewall of the first dielectric layer D1. The first conductive structure 611 connects a first portion of the first oxide structure O1 (schematically shown by a rectangular dashed line frame in FIG. 6) to form a first terminal T11 of the first transistor T1 at the first portion; the second conductive structure 612 connects a second portion of the first oxide structure O1 (schematically shown by a rectangular dashed line frame in FIG. 6) to form a second terminal T12 of the first transistor T1 at the second portion. A first channel (schematically shown by an oval dashed line frame in FIG. 6) is formed in the first oxide structure O1 between the first terminal T11 and the second terminal T12. The third conductive structure 613 can be used as a first driving terminal T13 of the first transistor, and has the first dielectric layer D1 between the first oxide structure O1.

[0068] The structure of the first transistor shown in FIG. 3 or FIG. 6 has a vertical channel, which can save chip area and improve performance while reducing size compared to a transistor with a horizontal channel. In addition, the structure of the first transistor with a vertical channel can more easily form an electrical connection between the first terminal and the driving terminal of the second transistor T2 or the first terminal structure of the capacitor, reducing the setting of the electrical connection structure and facilitating further reduction of the size of the chip. In addition, the structure of the first transistor shown in FIG. 6 can increase the control ability of the driving terminal on the channel in terms of electrical properties.

[0069] Similarly to the above embodiment, referring to FIG. 6 and FIG. 7, the first conductive structure 611 and the second conductive structure 612 can be located at different conductive layers, i.e., at different heights in the semiconductor device 600; for example, at the conductive layer 640 and the conductive layer 650, respectively. In this way, the vertical space can be used to form a first channel between the first terminal T11 and the second terminal T12. This further reduces the size and area of the first transistor T1, so that the size or area of the first transistor layer 610 can be further reduced.

[0070] According to some embodiments, the second conductive structure 312 / 612 is located in the first conductive layer (e.g., the conductive layer 350 / 650), and the third conductive structure 313 / 613 includes a portion located in the second conductive layer (e.g., the conductive layer 360 / 660). The first conductive layer can extend along a first direction (e.g., the y direction in FIG. 3 or FIG. 6) to connect the second terminals T12 of a plurality of first transistors T1 arranged along the first direction in the first transistor layer 310 / 610; and the second conductive layer can extend along a second direction (e.g., the x direction in FIG. 3 or FIG. 6) to connect the first driving terminals T13 of a plurality of first transistors T1 arranged along the second direction in the first transistor layer 310 / 610.

[0071] The above arrangement of conductive layers can reduce the complexity of the wiring in the semiconductor device, which can not only reduce the size or area of the semiconductor device, but also reduce the interference caused by the wiring and improve the performance of the semiconductor device. Moreover, this arrangement of conductive layers can facilitate quick gating of the first transistors for programming operations, reducing the complexity of programming and improving programming efficiency.

[0072] According to some embodiments, the first direction and the second direction intersect in the same projection direction. For example, the first direction and the second direction can be perpendicular, or the smaller included angle between the first direction and the second direction can be greater than or equal to 60 degrees and less than or equal to 90 degrees. The above arrangement of wiring directions can not only simplify the complexity of the wiring in the semiconductor device, but also facilitate the row-by-row or column-by-column connection between the first transistors T1 in the first transistor layer 310, which facilitates the gating of the first transistors to be written with weight data, realizes fast programming, and reduces the complexity of programming control.

[0073] The dielectric layer (the first dielectric layer D1, the second dielectric layer D2 or the third dielectric layer D3) can include a non-conductive material. The present disclosure does not limit the material of the dielectric layer, and the materials of different dielectric layers can be the same or different, which can be selected according to the process requirement and the type of the transistor. For example, the first dielectric layer D1 or the second dielectric layer D2 can use one or more materials of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum oxide (Al2O3), etc. For example, the first dielectric layer D1 or the second dielectric layer D2 can use one or more materials of high-k dielectric material, such as hafnium oxide (HfO2), aluminum oxide (Al2O3), or a combination of HfSiON, etc., to reduce the leakage current of the first transistor T1 and improve the charge retention time of the storage node. For example, the third dielectric layer D3 can use one or more materials of silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium aluminum oxide (HfAlO4), zirconium dioxide (ZrO2), zirconium aluminum oxide (ZrAlO4), titanium dioxide (TiO2), strontium titanate (STO / SrTiO3), etc. The above materials can also be doped as needed, for example, lanthanide metal-doped HfO2. In summary, the present disclosure does not limit the material of the dielectric layer. y O x y N x z O y N x y O x y O x x x x x x x In summary, the present disclosure does not limit the material of the dielectric layer.

[0074] ​​​​​​​​​​The present disclosure does not limit the way of electrical connection between the first terminal T11, the second driving terminal T23 and the first end structure C11. According to some embodiments, referring to FIG. 3 and FIG. 6, the first terminal T11 and the first end structure C11 can be electrically connected through the via V1 and the electrode E1. According to some other embodiments, the first terminal T11 and the first end structure C11 can be directly electrically connected or indirectly electrically connected through an oxide, which will be described in subsequent embodiments. Referring to FIG. 4 and FIG. 7, the second driving terminal T23 and the first end structure C11 can be electrically connected through one or more electrodes and one or more vias. For example, as shown in FIG. 4, the electrical connection is achieved through the electrodes E1-E4 and the vias V1-V5. This is only an example, and the present disclosure is not limited thereto. In some other embodiments, more or less electrodes or via structures can be provided.

[0075] According to some embodiments, the first conductive structure and the second conductive structure can be located in the same conductive layer. For example, FIG. 8 shows a cross-sectional side view of another semiconductor device according to an exemplary embodiment of the present disclosure. As shown in FIG. 8, the semiconductor device 800 includes a first transistor layer 810, a second transistor layer 820 and a capacitor layer 830. The descriptions of the first transistor layer 810, the second transistor layer 820 and the capacitor layer 830 refer to the above embodiments. The difference between the above embodiments and the present embodiment includes that the structure of the first transistor T1 is different. For example, the first conductive structure 811 and the second conductive structure 812 can be located in the same conductive layer, such as the conductive layer 840. The first conductive structure 811 and the second conductive structure 812 are formed on the first oxide structure O1, and the first portion and the second portion of the first oxide structure O1 (shown in FIG. 8 as a rectangular dashed line frame) form the first terminal T11 and the second terminal T12, respectively. The first terminal T11 and the second terminal T12 form a first channel (shown in FIG. 8 as an oval dashed line frame). The third conductive structure 813 includes a portion formed on the first channel, which is used as the first driving terminal T13 of the first transistor T1, and has the first dielectric layer D1 between the first oxide structure O1. The way of electrical connection between the first terminal T11, the second driving terminal T23 and the first end structure C11 can refer to the description of the above embodiments, which will not be described here. The planar oxide transistor structure has a simple preparation process and can be compatible with the silicon MOS process flow.

[0076] In some embodiments above, the capacitor layer 330 / 630 / 830 is located between the first transistor layer 310 / 610 / 810 and the second transistor layer 320 / 620 / 820. In some other embodiments, the capacitor layer can also be formed at other locations, for example, on the first transistor layer. The present disclosure does not limit the implementation location, and different interlayer electrical connection structures can be used in different implementation locations, so that the first terminal T11, the second driving terminal T23 and the first terminal structure C11 are electrically connected.

[0077] The capacitor layer is located between the first transistor layer and the second transistor layer, and can be used to reduce the capacitance and the electrical connection structure between the first transistor and / or the second transistor by using the hierarchical distribution of the three-dimensional structure in the process manufacturing. In some embodiments, the first terminal T11 of the first transistor T1 and the first terminal structure C11 of the capacitor can be electrically connected without adding additional conductive structures (for example, metal wires), which helps to reduce the size of the storage unit. Moreover, the structure can reduce the arrangement of conductive structures in the semiconductor device, thereby reducing interference and improving the anti-interference performance of the semiconductor device.

[0078] For example, refer to FIG. 9, which shows a cross-sectional side view of another semiconductor device according to an example embodiment of the present disclosure. The semiconductor device 900 includes a first transistor layer 910, a second transistor layer 920 and a capacitor layer 930. The descriptions of the first transistor layer 910, the second transistor layer 920 and the capacitor layer 930 refer to the above embodiments. The structure of the first transistor layer 910 is similar to the embodiments shown in FIG. 3 and FIG. 4, and will not be described again. According to some embodiments, the first terminal structure C11 of the capacitor C and the first conductive structure 911 of the first transistor T1 are formed in the same conductive layer, for example, the conductive layer 940. That is, the first terminal structure C11 is the first conductive structure 911 at the same time, or in other words, the first terminal structure C11 and the first conductive structure 911 share the same conductive structure. In this way, the wiring complexity in the semiconductor device can be simplified, and the interference caused by noise coupling can be reduced, and the energy loss caused by charge transfer can be reduced.

[0079] By comparing FIG. 3, FIG. 4, FIG. 6 and FIG. 7, it can be seen that the electrical connection structure between the capacitor C and the first transistor T1 can be greatly simplified by using the above structure, and even the electrical connection structure can be omitted to achieve direct connection. Moreover, the electrical connection structure between the capacitor and the second transistor T2 can also be simplified. When the second transistor T2 adopts the structure similar to any of the above first transistors T1, the electrical connection structure between the capacitor and the second transistor T2 can be further simplified.

[0080] Referring to FIG. 10, a cross-sectional side view of yet another semiconductor device is shown, according to an example embodiment of the present disclosure. The difference between the embodiment shown in FIG. 10 and the embodiment shown in FIG. 9 includes that a second oxide structure O2 is between a first portion of the first oxide structure O1 (shown in FIG. 10 as a rectangular dashed box) and the first end structure C11 of the capacitor C. The first oxide structure O1 and the second oxide structure O2 can include the same or different oxides. For example, the first oxide structure O1 includes IGZO; and the second oxide structure O2 includes ITO. The introduction of the second oxide structure O2 can lower the Schottky barrier formed by the contact of the conductive structure (either the first conductive structure 911 or the first end structure C11 of the capacitor C) and the first oxide structure O1 (e.g., IGZO material), reduce the contact resistance, and increase the on-current of the write tube (the first transistor T1). Optionally, a third oxide structure O3 is between a second portion of the first oxide structure O1 (shown in FIG. 10 as an oval dashed box) and the second conductive structure 912. The third oxide structure O3 can be made of the same material as the second oxide structure O2, e.g., ITO.

[0081] The capacitor structure of the embodiments shown in FIG. 9 and FIG. 10 can be combined with the structure of the first transistor T1 shown in FIG. 3, and in addition, can be combined with the structure of the first transistor shown in FIG. 6 or FIG. 8. For example, referring to FIG. 11, a cross-sectional side view of yet another semiconductor device is shown, according to an example embodiment of the present disclosure. The semiconductor device 1100 includes a first transistor layer 1110, a second transistor layer 1120, and a capacitor layer 1130. The descriptions of the first transistor layer 1110, the second transistor layer 1120, and the capacitor layer 1130 refer to the above embodiments. The structure of the first transistor layer 1110 is similar to the embodiment shown in FIG. 6. The first end structure C11 of the capacitor C is formed in the same conductive layer as the first conductive structure 1111 of the first transistor T1, e.g., the conductive layer 1140. That is, the first end structure C11 is the same as the first conductive structure 1111, or in other words, the first end structure C11 and the first conductive structure 1111 share the same conductive structure.

[0082] Optionally, similar to the above embodiments, a second oxide structure can be between a first portion of the first oxide structure O1 (shown in FIG. 11 as a lower rectangular dashed box) and the first end structure C11 of the capacitor C. Optionally, a third oxide structure can be between a second portion of the first oxide structure O1 (shown in FIG. 11 as an upper rectangular dashed box) and the second conductive structure 1112.

[0083] According to some embodiments, the second transistor T2 can include an oxide transistor. The second transistor T2 can include a similar structure as any of the above first transistors T1.

[0084] For example, please continue to refer to FIG. 9 and FIG. 10. The second transistor layer 920 includes the second transistor T2, a fourth conductive structure 921, a fifth conductive structure 922 and a sixth conductive structure 923. The second transistor T2 includes a fourth oxide structure O4; the fourth conductive structure 921 connects a third part (shown in a rectangular dashed line frame in FIG. 9) of the fourth oxide structure O4, forming a third terminal T21 at the third part; the fifth conductive structure 922 connects a fourth part (shown in a circular dashed line frame in FIG. 9) of the fourth oxide structure O4, forming a fourth terminal T22 at the fourth part. A second channel (shown in an elliptical dashed line frame in FIG. 9) is formed in the fourth oxide structure O4 between the third terminal T21 and the fourth terminal T22. The sixth conductive structure includes a part formed on the second channel, serving as a second driving terminal T23 of the second transistor T2, and having a second dielectric layer D2 between the fourth oxide structure O4.

[0085] For another example, please continue to refer to FIG. 11. The second transistor layer 1120 includes the second transistor T2, a fourth conductive structure 1121, a fifth conductive structure 1122 and a sixth conductive structure 1123. The second transistor T2 includes a fourth oxide structure O4; the fourth conductive structure 1121 connects a third part (shown in a lower rectangular dashed line frame in FIG. 11) of the fourth oxide structure O4, forming a third terminal T21 at the third part; the fifth conductive structure 1122 connects a fourth part (shown in an upper rectangular dashed line frame in FIG. 11) of the fourth oxide structure O4, forming a fourth terminal T22 at the fourth part. A second channel (shown in an elliptical dashed line frame in FIG. 11) is formed in the fourth oxide structure O4 between the third terminal T21 and the fourth terminal T22. The sixth conductive structure T23 includes a part formed on the second channel, serving as a second driving terminal T23 of the second transistor T2, and having a second dielectric layer D2 between the fourth oxide structure O4.

[0086] In the embodiments shown in FIG. 9 and FIG. 11, the structures of the first transistor T1 and the second transistor T2 in the semiconductor device are similar, and in some other embodiments, the structures of the first transistor T1 and the second transistor T2 in the semiconductor device can be different. For example, the second transistor in FIG. 9 can adopt the structure shown in FIG. 11; or adopt the structure similar to the first transistor shown in FIG. 8. For another example, the second transistor in FIG. 11 can adopt the structure shown in FIG. 9; or adopt the structure similar to the first transistor shown in FIG. 8.

[0087] Using oxide transistors as the second transistor (read transistor), the threshold voltage can be optimized or the channel current (or on current) can be improved, more weight data can be stored in the compute-in-memory cell, which is helpful for training or inference of large data and large models. Manufacturing the second transistor with oxide structure between the conductive structures can not only optimize the threshold voltage or improve the channel current using the oxide structure to improve the accuracy of weight data storage, but also realize smaller size transistors to further save chip area and reduce chip size, and the preparation process is simple, which is conducive to reducing chip cost. In addition, due to the reduction of the spatial size or area of the storage circuit, more available space or area can be provided for other circuits in the chip, such as logic circuits, which is conducive to the performance improvement of the logic circuits.

[0088] According to some embodiments, the fourth oxide structure O4 can include ITO or IGZO. Using ITO as the channel material of the read transistor (second transistor) in the storage unit can improve the channel current, which is conducive to training and inference calculation; using IGZO as the channel material of the read transistor (second transistor) in the storage unit can optimize the threshold voltage (for example, to be positive), which is convenient for circuit design.

[0089] The present disclosure does not limit the connection of the second end structure C12 of the capacitor C. For example, the second end structure C12 can be coupled to a voltage signal, for example, including a positive voltage, a negative voltage, or a ground voltage. Alternatively, the second end structure C12 can be grounded. According to some embodiments, as shown in FIGS. 3, 4, and 6-11, the second end structure C12 is directly connected or connected through a via to a ground electrode GND or an electrode for receiving a voltage signal. According to some embodiments, the ground electrode GND or the electrode for receiving a voltage signal can extend along the x direction in the figure to connect multiple capacitors arranged along the x direction in the capacitor layer.

[0090] According to some embodiments, please continue to refer to FIGS. 3-7, the semiconductor device 300 / 600 can further include a third conductive layer 370 / 670 and a fourth conductive layer 380 / 680. The third conductive layer 370 / 670 extends along a third direction (e.g., the x direction in the figure) and connects the third terminals T21 of the plurality of second transistors T2 arranged along the third direction in the second transistor layer 320 / 620. The fourth conductive layer 380 / 680 extends along a fourth direction (e.g., the y direction in the figure) and connects the fourth terminals T22 of the plurality of second transistors T2 arranged along the fourth direction in the second transistor layer 320 / 620. The third direction and the fourth direction intersect in the same projection direction. For example, the third direction and the fourth direction can be perpendicular, or for another example, the smaller included angle between the third direction and the fourth direction can be greater than or equal to 60 degrees and less than or equal to 90 degrees. Alternatively, the third direction can be the same as the second direction, i.e., the third conductive layer 370 / 670 can have the same extension direction as the conductive layer 360 / 660 in which the third conductive structure 313 / 613 is located. Alternatively, the fourth direction can be the same as the first direction, i.e., the fourth conductive layer 380 / 680 can have the same extension direction as the conductive layer 350 / 650 in which or to which the second conductive structure 312 / 612 is connected, which can simplify the manufacturing process of the semiconductor device.

[0091] According to some embodiments, please continue to refer to FIG. 8, the semiconductor device 800 can further include a third conductive layer 870 and a fourth conductive layer 880. The third conductive layer 870 extends along a third direction (e.g., the x direction in the figure) and connects the third terminals T21 of the plurality of second transistors T2 arranged along the third direction in the second transistor layer 820. The fourth conductive layer 880 extends along a fourth direction (e.g., the y direction in the figure) and connects the fourth terminals T22 of the plurality of second transistors T2 arranged along the fourth direction in the second transistor layer 820. The third direction and the fourth direction intersect in the same projection direction. For example, the third direction and the fourth direction can be perpendicular, or for another example, the smaller included angle between the third direction and the fourth direction can be greater than or equal to 60 degrees and less than or equal to 90 degrees. The second conductive structure 812 can be connected to a conductive layer 850 that can extend along a first direction (e.g., the y direction in FIG. 8) and connect the second terminals T12 of the plurality of first transistors T1 arranged along the first direction in the first transistor layer 810. Alternatively, the third direction can be the same as the second direction, i.e., the third conductive layer 870 can have the same extension direction as the conductive layer 860 in which the third conductive structure 813 is located. Alternatively, the fourth direction can be the same as the first direction, i.e., the fourth conductive layer 880 can have the same extension direction as the conductive layer 850 to which the second conductive structure 812 is connected, which can simplify the manufacturing process of the semiconductor device.

[0092] According to some embodiments, please continue to refer to FIGS. 9-11, the semiconductor device 900 / 1100 can further include a third conductive layer 970 / 1170 and a fourth conductive layer 980 / 1180. The third conductive layer 970 / 1170 extends along a third direction (for example, the x direction in the figure) and connects the third terminals T21 of the plurality of second transistors T2 arranged along the third direction in the second transistor layer 920 / 1120. The fourth conductive layer 980 / 1180 extends along a fourth direction (for example, the y direction in the figure) and connects the fourth terminals T22 of the plurality of second transistors T2 arranged along the fourth direction in the second transistor layer 920 / 1120. The third direction and the fourth direction intersect in the same projection direction. For example, the third direction and the fourth direction can be perpendicular, and for another example, the smaller included angle between the third direction and the fourth direction can be greater than or equal to 60 degrees and less than or equal to 90 degrees. Alternatively, the third direction can be the same as the second direction, that is, the third conductive layer 970 / 1170 can be in the same extension direction as the conductive layer 960 / 1160 in which the third conductive structure 913 / 1113 is located. Alternatively, the fourth direction can be the same as the first direction, that is, the fourth conductive layer 980 / 1180 can be in the same extension direction as the conductive layer 950 / 1150 in which the second conductive structure 912 / 1112 is located, so as to simplify the manufacturing process of the semiconductor device.

[0093] According to some embodiments, the semiconductor device 300 / 600 / 800 / 900 / 1100 can further include more electrical connection structures to realize the connection between elements, structures or factors in different layers, or to provide connection to external leads, for example, connection to a logic circuit. The present disclosure does not limit the arrangement of the electrical connection structures.

[0094] According to some embodiments, the first driving terminal and the second driving terminal can include a gate. The first terminal can include a drain, and the second terminal can include a source; or the first terminal can include a source, and the second terminal can include a drain. According to some embodiments, the third terminal can include a drain, and the fourth terminal can include a source; or the third terminal can include a source, and the fourth terminal can include a drain.

[0095] In the embodiments of the present disclosure, using an oxide semiconductor material as the write pipe channel material in the storage unit can reduce the leakage current of the storage unit, prolong the charge retention time of the storage node, and make the storage of weight data more stable and reliable. Using an oxide semiconductor material (for example, ITO) as the read pipe channel material in the storage unit can improve the channel current, which is beneficial to training and inference calculation; using an oxide semiconductor material (for example, IGZO) can optimize the threshold voltage, which is convenient for the design of the control circuit.

[0096] Layers not described in the above embodiments can include interlayer insulating layers, or interlayer dielectric layers, etc., which are not limited by the present disclosure.

[0097] The present disclosure does not limit the way of electrically connecting the first terminal T11, the second driving terminal T23 and the first terminal structure C11. According to some embodiments, please refer to FIG. 12, which shows a cross-sectional top view of a semiconductor device according to an exemplary embodiment of the present disclosure. In FIG. 12, a partial layout relationship of elements, factors or structures resulting from a first transistor layer 910 and a conductive layer connected to the first transistor layer 910 of a semiconductor device 900 is schematically shown. In FIG. 12, SN1 represents a node (e.g. a via) having an electrically connecting relationship with the first terminal structure C11 or the first conductive structure 911 of the capacitor C, and SN2 represents a node (e.g. a via) having an electrically connecting relationship with the second driving terminal T23 of the second transistor T2. The node SN1 and the node SN2 can be connected through a conductive structure E. The conductive structure E in FIG. 12 is only for example, and the present disclosure does not limit the composition of the conductive structure E. For example, the conductive structure E can include at least one electrode and / or at least one via. The electrode can include one or more of an interlayer electrode (e.g. the electrode Em in FIG. 3, FIG. 4, FIG. 6-FIG. 8), a top electrode (e.g. the electrode Et in FIG. 3, FIG. 4, FIG. 6, FIG. 9 or FIG. 10) or a bottom electrode Eb (e.g. the electrode Eb in FIG. 9 or FIG. 10). For example, the node SN1 and the node SN2 can be connected to the same electrode through at least one via and / or electrode, which can include an interlayer electrode, a top electrode or a bottom electrode. The positions of the interlayer electrode, the top electrode or the bottom electrode in the figures are only for example, and do not limit whether these electrodes are included in the semiconductor device and the positions of these electrodes. For example, the semiconductor device can include part or all of the interlayer electrode, the top electrode or the bottom electrode. The node SN1 and the node SN2 can be connected to the same electrode through vias and / or electrodes of the same or different structures; the node SN1 and the node SN2 can be connected to the same electrode through vias and / or electrodes of the same or different numbers. The electrically connecting structure for connecting the node SN1 and the node SN2 can not include a top electrode or a bottom electrode, and the semiconductor device can include a top electrode or a bottom electrode, which can provide an external lead, for example, for connecting with a lead of a logic circuit.

[0098] According to some embodiments, please refer to FIG. 13, which shows a cross-sectional top view of another semiconductor device according to exemplary embodiments of the present disclosure. In FIG. 13, the first transistor layer 1110 and the conductive layer connected to the first transistor layer 1110 of the semiconductor device 1100 are shown schematically to illustrate the partial layout relationship of the elements, components or structures resulted from the semiconductor device 1100. In FIG. 13, SN1 represents a node (e.g. a via) having an electrical connection relationship with the first end structure C11 or the first conductive structure 1111 of the capacitor C, and SN2 represents a node (e.g. a via) having an electrical connection relationship with the second driving terminal T23 of the second transistor T2. The node SN1 and the node SN2 can be connected by a conductive structure E. The conductive structure E is described above in FIG. 12, and thus will not be described again here. Optionally, the semiconductor device 1100 can further include a filling structure 1190 of the first driving terminal, which is used to remove the conductive layer and to fill part of the first driving terminal when the first driving terminal is manufactured by a dummy gate process. The filling structure 1190 can include, for example, an opening.

[0099] The present disclosure does not limit the structure of the capacitor. For example, the planar capacitor shown in FIGS. 3-8 can be used, or the three-dimensional capacitor shown in FIGS. 9-11 can be used, or other capacitor structures such as a MOM (Metal Oxide Metal) capacitor can be used.

[0100] FIGS. 14-16 show cross-sectional top views of several semiconductor devices according to exemplary embodiments of the present disclosure, which schematically show the partial layout relationship of the elements, components or structures resulted from the second transistor layer and the conductive layer connected to the second transistor layer of the semiconductor device. In the figures, the silicon transistor shown in FIGS. 3-8 is taken as an example, and the present disclosure does not limit this. The silicon transistor can be replaced by any of the oxide transistors provided in the above embodiments, with the difference being the connection manner between the conductive structure and the transistor.

[0101] Referring to FIG. 14, the semiconductor device 1400 can include a plurality of second transistors T2 arranged in an array. S41 represents a node electrically connected to the third terminal of the second transistor T2; S42 represents a node electrically connected to the fourth terminal of the second transistor T2; and S43 represents a node electrically connected to the second driving terminal of the second transistor T2. The third conductive layer 1470 is connected to the third terminal of the second transistor T2 arranged along the extension direction of the third conductive layer 1470, and the fourth conductive layer 1480 is connected to the fourth terminal of the second transistor T2 arranged along the extension direction of the fourth conductive layer 1480. The storage units connected to the same fourth conductive layer 1480 can be taken as a storage unit group; the third terminals of the second transistors T2 in the storage unit group can be connected to a plurality of input terminals through a plurality of third conductive layers 1470 respectively, and the fourth terminals can be connected to the same output terminal through the fourth conductive layer 1480. The write of the weight data of the storage unit can be controlled through the first conductive layer and the second conductive layer, so that the second driving terminal of the second transistor T2 has a voltage corresponding to the target weight data, so that the channel between the third terminal and the fourth terminal has a corresponding conduction capability. The second transistor T2 outputs an output signal adjusted by the conduction capability of the channel in response to the input signal input by the plurality of input terminals. The fourth terminals of the second transistors T2 in the storage unit group commonly output an output signal through the third conductive layer 1470, which equivalently realizes the multiplication operation between vectors (or matrices).

[0102] According to some embodiments, two second transistors T2 adjacent in the channel extension direction (source-drain conduction direction) of the second transistor T2 can be mirror arranged. For example, the third terminals (e.g. source or drain) of the two adjacent second transistors T2 can be arranged adjacent to each other, and the fourth terminals (e.g. drain or source) can be arranged distally; or the fourth terminals of the two adjacent second transistors T2 can be arranged adjacent to each other, and the third terminals can be arranged distally. According to some embodiments, the two adjacent third terminals or the two adjacent fourth terminals can be formed integrally with each other, for example, formed as a common source structure or a common drain structure, or the two adjacent third terminals or the two adjacent fourth terminals can be separated from each other, for example, with an isolation structure arranged therebetween.

[0103] According to some embodiments, the second transistor T2 can be homotypically arranged with the second transistor T2 adjacent in the channel extension direction thereof. The third terminal of the second transistor T2 can be arranged adjacent to the fourth terminal of the adjacent second transistor T2; and the fourth terminal of the second transistor T2 can be arranged adjacent to the third terminal of the adjacent second transistor T2.

[0104] Referring to FIG. 15, the semiconductor device 1500 can include a plurality of second transistors T2 arranged in an array. S51 represents a node electrically connected to the third terminal of the second transistor T2; S52 represents a node electrically connected to the fourth terminal of the second transistor T2; and S53 represents a node electrically connected to the second driving terminal of the second transistor T2. The third conductive layer 1570 is connected to the third terminals of the second transistors T2 arranged along the extension direction of the third conductive layer 1570, and the fourth conductive layer 1580 is connected to the fourth terminals of the second transistors T2 arranged along the extension direction of the fourth conductive layer 1580. According to some embodiments, the second transistor layer includes a second transistor set T2S including second transistors T2 arranged along a third direction (the direction in which the third conductive layer 1570 extends) adjacently and sharing a third terminal, and the third conductive layer 1570 is connected to the third terminals of the second transistors of the second transistor set.

[0105] The fourth terminals of the second transistors T2 in a storage unit group connected to the same fourth conductive layer 1580 can serve as a storage unit group; the third terminals of the second transistors T2 in the storage unit group can be connected to a plurality of input terminals through a plurality of third conductive layers 1570 respectively, and the fourth terminals can be connected to the same output terminal through the fourth conductive layer 1580. The write of the weight data of the storage unit can be controlled through the first conductive layer and the second conductive layer, so that the second driving terminal of the second transistor T2 has a voltage corresponding to the target weight data, so that the channel between the third terminal and the fourth terminal has a corresponding conduction capability. The second transistor T2 responds to the input signal input by the plurality of input terminals, and outputs an output signal adjusted by the conduction capability of the channel at the fourth terminal. The fourth terminals of the second transistors T2 in the storage unit group collectively output an output signal through the fourth conductive layer 1580, which equivalently realizes the multiplication operation between vectors (or matrices).

[0106] The sharing of the third terminals can simplify the routing complexity of the semiconductor device, further reduce the size or area of the semiconductor device, and simplify the manufacturing process. In addition, the above structure can save the electrical connection structure, for example, the through hole or the electrode and the like electrical connection structure can be saved.

[0107] Referring to FIG. 16, the semiconductor device 1600 can include a plurality of second transistors T2 arranged in an array. S61 represents a node electrically connected to the third terminal of the second transistor T2; S62 represents a node electrically connected to the fourth terminal of the second transistor T2; and S63 represents a node electrically connected to the second driving terminal of the second transistor T2. The third conductive layer 1670 is connected to the third terminals of the second transistors T2 arranged along the extension direction of the third conductive layer 1670, and the fourth conductive layer 1680 is connected to the fourth terminals of the second transistors T2 arranged along the extension direction of the fourth conductive layer 1680. According to some embodiments, the second transistor layer includes a first group G1 of second transistors (which can be referred to as a first sub-group of storage units) and a second group G2 of second transistors (which can be referred to as a second sub-group of storage units) arranged along the fourth direction (the direction in which the fourth conductive layer 1680 extends), and the fourth conductive layer 1680 is connected to the fourth terminals of the first group of second transistors and the second group of second transistors.

[0108] The storage units connected to the same fourth conductive layer 1680 can be regarded as a group of storage units; the third terminals of the second transistors T2 in the group of storage units can be connected to a plurality of input terminals through a plurality of third conductive layers 1670 respectively, and the fourth terminals can be connected to the same output terminal through the fourth conductive layer 1680. The write of the weight data of the storage units can be controlled through the first conductive layer and the second conductive layer, so that the second driving terminal of the second transistor T2 has a voltage corresponding to the target weight data, so that the channel between the third terminal and the fourth terminal has a corresponding conduction capability. The second transistor T2 outputs an output signal adjusted by the conduction capability of the channel in response to the input signal input by the plurality of input terminals. The output signal output by the fourth terminals of the second transistors T2 in the group of storage units through the fourth conductive layer 1680 is equivalent to the multiplication operation between vectors (or matrices).

[0109] In this way, the size of the storage circuit can be reduced, and the process complexity can be reduced; a ping-pong structure can also be formed to perform grouped calculation within the group (for example, first calculate the odd sub-group, and then calculate the even sub-group), so as to reduce the calculation difference between the two sub-groups of storage units and improve the calculation accuracy. The storage units in different sub-groups can be connected to the same input terminal or different input terminals. For example, referring to FIG. 16, the storage units in different sub-groups can be connected to different input terminals to couple independent input signals, and the storage units in different sub-groups can combine the calculation results. In this way, the number of storage units in the output line direction can be reduced, and the RC delay of the signals in this direction can be effectively reduced, and the calculation speed can be improved.

[0110] Embodiments of the present disclosure further provide a method for manufacturing a semiconductor device. For example, FIG. 17 shows a flow chart of an example method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 17, the method can include steps S171-S173.

[0111] At step S171, a first transistor layer is formed, the first transistor layer including a first transistor, a first conductive structure, a second conductive structure, and a third conductive structure; the first transistor including a first oxide structure; the first conductive structure connecting a first portion of the first oxide structure, forming a first terminal of the first transistor at the first portion; the second conductive structure connecting a second portion of the first oxide structure, forming a second terminal of the first transistor at the second portion; and a first channel being formed within the first oxide structure between the first terminal and the second terminal; the third conductive structure including a portion formed on the first channel, serving as a first driving terminal of the first transistor, and having a first dielectric layer between the first oxide structure.

[0112] At step S172, a second transistor layer is formed, including a second transistor; the second transistor including a third terminal, a fourth terminal, and a second driving terminal, a second channel being formed between the third terminal and the fourth terminal, the second driving terminal being formed on the second channel and having a second dielectric layer between the second channel.

[0113] At step S173, a capacitor layer is formed, including a capacitor; the capacitor including a first terminal structure and a second terminal structure, the first terminal structure and the second terminal structure having a third dielectric layer therebetween; the first terminal, the second driving terminal, and the first terminal structure being electrically connected.

[0114] The method can be performed in the above order, or in a different order, for example, sequentially in other orders, or partially or wholly synchronously.

[0115] Some embodiments of the present disclosure can further provide a storage and calculation device (or processing device) including a storage circuit and a control circuit as in any of the above embodiments, the control circuit being configured to control the working state of the storage circuit.

[0116] Some embodiments of the present disclosure can also provide an electronic device. For example, FIG. 18 shows a schematic diagram of an electronic device according to an example embodiment of the present disclosure. The electronic device 1800 can include a storage and computing device 1810 for processing data of the electronic device 1800. The electronic device 1800 can also include an input / output device 1820 for receiving input from a user or outputting the processing result. The present disclosure does not limit the type of input and output. For example, the input can include voice input, text input, image input, or video input, etc. The output can include text output, voice output, image output, or video output, etc. The electronic device 1800 can also include a processor 1830, which can process the data provided to the storage and computing device 1810 or process the output data of the storage and computing device 1810. The output of the input / output device 1820 can be based on the output of the processor 1830 or the output of the storage and computing device 1810.

[0117] The present disclosure does not limit the type of electronic device. For example, according to some embodiments, the electronic device 1800 can include a wearable device. The wearable device can include, for example, but not limited to, a head-mounted device (e.g., a helmet or a hat, etc.), a device wearable on the ear (e.g., an earphone), a device wearable on the wrist (e.g., a watch), a device wearable on other parts of the body (e.g., an electronic necklace, a medical monitoring device, or glasses, etc.), etc. According to some embodiments, the electronic device 1800 can include a portable terminal. For example, the electronic device 1800 can include, but not limited to, a mobile phone, a general computing device (e.g., a laptop computer, or a tablet computer, etc.), a personal digital assistant, etc. According to some embodiments, the electronic device 1800 can include other types of terminal devices, such as a personal computer, an in-vehicle computer or in-vehicle computing platform, or a smart home electronic product, etc. According to some embodiments, the electronic device 1800 can also include a server or the like.

[0118] In the above embodiments, the description of different embodiments focuses on different aspects, and the parts not described or recorded in detail in a certain embodiment can refer to the related description of other embodiments. Moreover, the different embodiments above can be freely combined as needed. Moreover, as technology evolves, the elements described in the present disclosure can be replaced by equivalent elements that appear after the present disclosure.

Claims

1. A semiconductor device, comprising: a first transistor layer comprising a first transistor, a first conductive structure, a second conductive structure and a third conductive structure, wherein the first transistor comprises a first oxide structure, the first conductive structure connects a first portion of the first oxide structure, forms a first terminal of the first transistor at the first portion, the second conductive structure connects a second portion of the first oxide structure, forms a second terminal of the first transistor at the second portion, and a first channel is formed within the first oxide structure between the first terminal and the second terminal, the third conductive structure comprises a portion formed on the first channel, is used as a first driving terminal of the first transistor, and has a first dielectric layer between the first oxide structure; a second transistor layer comprising a second transistor, the second transistor comprises a third terminal, a fourth terminal and a second driving terminal, a second channel is formed between the third terminal and the fourth terminal, the second driving terminal is formed on the second channel and has a second dielectric layer between the second channel; and a capacitor layer comprising a capacitor, the capacitor comprises a first terminal structure and a second terminal structure, the first terminal structure and the second terminal structure have a third dielectric layer therebetween, wherein the first terminal, the second driving terminal and the first terminal structure are electrically connected. 2.The semiconductor device of claim 1, wherein the first conductive structure and the second conductive structure are located in a same conductive layer or in different conductive layers. 3.The semiconductor device of claim 2, wherein the second conductive structure is located in a first conductive layer, the third conductive structure comprises a portion located in a second conductive layer; the first conductive layer extends along a first direction and connects second terminals of a plurality of first transistors arranged along the first direction in the first transistor layer; and the second conductive layer extends along a second direction and connects first driving terminals of a plurality of first transistors arranged along the second direction in the first transistor layer. 4.The semiconductor device of claim 3, wherein the first direction and the second direction cross in a same projection direction. 5.The semiconductor device of any one of claims 1-4, wherein the capacitor layer is located between the first transistor layer and the second transistor layer. 6.The semiconductor device of claim 5, wherein the first conductive structure and the first terminal structure are formed in a same conductive layer. 7.The semiconductor device of claim 5 or 6, wherein a second oxide structure is located between the first portion of the first oxide structure and the first terminal structure of the capacitor. 8.The semiconductor device of any one of claims 5-7, wherein a third oxide structure is located between the second portion of the first oxide structure and the second conductive structure. 9.The semiconductor device of any one of claims 1-8, wherein the first transistor layer comprises: a first opening formed on the first conductive structure, and the second conductive structure is connected to a sidewall of the first opening. ​ ​ ​ ​ ​ ​ The first oxide structure includes a portion formed in the first opening, the first portion is located at a bottom of the first opening, the second portion is located at a sidewall of the first opening, and is connected with the second conductive structure.

10. The semiconductor device of any one of claims 1-8, wherein, The first transistor layer includes: a first opening, the first oxide structure includes a portion formed in the first opening, a third conductive structure is formed at an outer sidewall of the first opening, the first conductive structure and the second conductive structure are respectively formed at two ends of the first opening.

11. The semiconductor device of any one of claims 1-10, the second transistor layer comprising the second transistor, a fourth conductive structure, a fifth conductive structure, and a sixth conductive structure, wherein, The second transistor includes a fourth oxide structure, a fourth conductive structure connects a third portion of the fourth oxide structure, the third terminal is formed at the third portion, a fifth conductive structure connects a fourth portion of the fourth oxide structure, the fourth terminal is formed at the fourth portion, and a second channel is formed between the third terminal and the fourth terminal in the fourth oxide structure, a sixth conductive structure includes a portion formed on the second channel, is used as a second driving terminal of the second transistor, and has a second dielectric layer between the fourth oxide structure.

12. The semiconductor device according to any one of Claims 1-10, wherein The second transistor includes a silicon transistor.

13. The semiconductor device according to any one of Claims 1-12, further comprising: a third conductive layer extending in a third direction, connecting third terminals of a plurality of second transistors arranged in the third direction in the second transistor layer; a fourth conductive layer extending in a fourth direction, connecting fourth terminals of a plurality of second transistors arranged in the fourth direction in the second transistor layer, wherein the third direction and the fourth direction cross in a same projection direction.

14. The semiconductor device according to Claim 13, the second transistor layer including a first group of second transistors and a second group of second transistors arranged in the fourth direction adjacent to each other, the fourth conductive layer connecting the fourth terminals of the second transistors of the first group and the second group.

15. The semiconductor device according to Claim 13, the second transistor layer including a second transistor set including second transistors arranged in the third direction adjacent to each other and sharing the third terminals, the third conductive layer connecting the third terminals of the second transistors of the second transistor set.

16. A method of manufacturing a semiconductor device, comprising: forming a first transistor layer, the first transistor layer comprising a first transistor, a first conductive structure, a second conductive structure and a third conductive structure, wherein the first transistor comprises a first oxide structure, the first conductive structure connects a first part of the first oxide structure, forms a first terminal of the first transistor at the first part, the second conductive structure connects a second part of the first oxide structure, forms a second terminal of the first transistor at the second part, and a first channel is formed between the first terminal and the second terminal in the first oxide structure, and the third conductive structure comprises a part formed on the first channel, is used as a first driving terminal of the first transistor, and has a first dielectric layer between the first oxide structure; forming a second transistor layer, comprising a second transistor, the second transistor comprising a third terminal, a fourth terminal and a second driving terminal, a second channel is formed between the third terminal and the fourth terminal, the second driving terminal is formed on the second channel, and a second dielectric layer is between the second channel and the second driving terminal; forming a capacitor layer, comprising a capacitor, the capacitor comprising a first end structure and a second end structure, the first end structure and the second end structure having a third dielectric layer therebetween, wherein the first terminal, the second driving terminal and the first end structure are electrically connected.

17. A memory and computing device, comprising: a memory circuit comprising the semiconductor device of any one of claims 1-15; a control circuit configured to control the working state of the memory circuit.

18. An electronic device comprising the memory and computing device of claim 17.

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