High-speed high-voltage fully differential power amplifier for beam deflection driver

Abstract

The present disclosure provides a deflector driver for driving a deflector of a charged particle inspection apparatus. The deflector driver may include a fully differential amplifier configured to generate a fully differential output having an absolute value greater than 100 V. Wherein the fully differential output may enable the plurality of deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection apparatus based on the fully differential output.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Application 63 / 530,241, filed August 1, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments provided herein generally relate to inspection equipment, and more specifically to a beam manipulation system for inspection equipment. Background Technology

[0003] In the manufacturing process of integrated circuits (ICs), incomplete or completed circuit components are inspected to ensure they are manufactured according to design and free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes (such as scanning electron microscopy (SEM)) can be employed. As the physical dimensions of IC components continue to shrink, the accuracy and yield of defect detection become increasingly important. However, the image resolution and throughput of inspection tools struggle to keep pace with the ever-shrinking feature sizes of IC components. The accuracy, resolution, and throughput of such inspection tools may be limited by the lack of deflector drive mechanisms that meet industry-expected standards. Summary of the Invention

[0004] Some embodiments provide a charged particle inspection apparatus. The apparatus may include a charged particle beam source configured to generate a primary charged particle beam for sample scanning; a deflector driver including a fully differential amplifier configured to generate a fully differential output with an absolute value greater than 100V; and a plurality of deflector electrodes coupled to the fully differential output and configured to influence the charged particle beam based on the fully differential output.

[0005] Some embodiments provide a deflector driver for driving a deflector in a charged particle inspection apparatus. The deflector driver may include a fully differential amplifier configured to generate a fully differential output with an absolute value greater than 100V. The fully differential output enables multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection apparatus based on the fully differential output.

[0006] Some embodiments provide a method for operating a deflector driver for driving a deflector in a charged particle inspection apparatus. The method may include: generating a fully differential output with an absolute value greater than 100V via a fully differential amplifier included in the deflector driver; measuring a common-mode voltage of the fully differential output of the fully differential amplifier via a common-mode control circuit included in the deflector driver; providing the difference between the common-mode voltage and a reference voltage to the fully differential amplifier via the common-mode control circuit; and adjusting the fully differential output of the differential amplifier based on the difference. The adjusted fully differential output enables multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection apparatus based on the fully differential output. The fully differential amplifier and the common-mode control circuit can be integrated into a single integrated circuit (IC) chip.

[0007] Other advantages of the embodiments of this disclosure will become apparent from the following description taken in conjunction with the accompanying drawings, in which certain embodiments of the invention are illustrated by way of description and example. Attached Figure Description

[0008] The above and other aspects of this disclosure will become more apparent from the description of exemplary embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 This is a schematic diagram illustrating an exemplary charged particle beam inspection system consistent with embodiments of the present disclosure.

[0010] Figure 2A This is a schematic diagram illustrating an exemplary multi-beam tool consistent with embodiments of this disclosure, the tool may be... Figure 1 This is part of an exemplary charged particle beam inspection system.

[0011] Figure 2B This is a schematic diagram illustrating an exemplary single-beam tool consistent with embodiments of the present disclosure, the tool may be... Figure 1 This is part of an exemplary charged particle beam inspection system.

[0012] Figure 3A This is a diagram illustrating an exemplary configuration of a scan deflection system consistent with embodiments of the present disclosure.

[0013] Figure 3B This is a schematic diagram of the deflection of a charged particle beam consistent with embodiments of this disclosure.

[0014] Figure 3C This is a diagram illustrating the configuration of an exemplary deflection element consistent with embodiments of this disclosure.

[0015] Figure 4 This is a schematic diagram illustrating an exemplary configuration of a deflection control unit associated with a charged particle beam deflector, consistent with embodiments of this disclosure.

[0016] Figure 5 This is a diagram illustrating the driver system architecture of a pseudo-differential amplifier utilizing dual single-ended power amplifiers.

[0017] Figure 6 This is a diagram showing the circuit configuration of a single-ended power amplifier.

[0018] Figure 7 This is a diagram illustrating an exemplary driver system architecture with a fully differential power amplifier consistent with embodiments of this disclosure.

[0019] Figure 8 This is a diagram illustrating an exemplary fully differential power amplifier circuit configuration and common-mode control circuit consistent with embodiments of this disclosure.

[0020] Figure 9 This is a flowchart illustrating an exemplary method for operating a deflector driver with a fully differential power amplifier, consistent with embodiments of this disclosure. Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the drawings, wherein the same numerals in different drawings denote the same or similar elements unless otherwise stated. The implementations set forth in the following description of exemplary embodiments do not represent all implementations. Rather, they are merely examples of apparatuses and methods consistent with aspects of the disclosed embodiments described in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, this disclosure is not limited thereto. Other types of charged particle beams (e.g., including protons, ions, muons, or any other charged particles) can be similarly applied. Furthermore, other imaging systems, such as optical imaging, photon detection, X-ray detection, ion detection, etc., can be used.

[0022] Electronic devices consist of circuits formed on a semiconductor material called a substrate. Semiconductor materials can include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium. Many circuits can be formed together on the same silicon wafer and are called integrated circuits (ICs). The size of these circuits has drastically decreased, allowing more circuitry to be mounted on the substrate. For example, an IC chip in a smartphone can be as small as a thumb but may contain over 2 billion transistors, each less than 1 / 1000th the size of a human hair.

[0023] Manufacturing these ICs from extremely small structures or components is a complex, time-consuming, and expensive process, typically involving hundreds of individual steps. Even an error in one step can lead to a defective IC that renders it unusable. Therefore, one goal of the manufacturing process is to avoid such defects in order to maximize the number of functional ICs manufactured in the process, i.e., to improve the overall yield of the process.

[0024] A component of improving yield is monitoring the chip manufacturing process to ensure that a sufficient number of functional integrated circuits are produced. One method for monitoring this process is to inspect the chip circuit structure at various stages of its formation. This inspection can be performed using a scanning charged particle microscope (“SCPM”). For example, SCPM could be a scanning electron microscope (SEM). SCPM can be used to image these extremely small structures; in effect, it can take “photographs” of the wafer’s structure. This image can be used to determine whether the structure has been correctly formed in the correct location. If there are defects in the structure, the process can be adjusted to make the defects less likely to recur.

[0025] As the physical dimensions of IC components continue to shrink, the accuracy and yield of defect detection become increasingly important. Furthermore, with the increasing global demand for computing power, the need to increase IC manufacturing or inspection speed is also growing. However, improving IC inspection speed can present technical challenges in maintaining high defect detection accuracy. The accuracy, resolution, and throughput of IC inspection may be limited by the lack of drive mechanisms for deflectors that meet industry-required standards. Currently, deflector driver systems with differential drive capability are being used to achieve better signal-to-noise ratio (SNR). Specifically, when transmitting signals within a single PCB or between PCBs, electromagnetic impedance (EMI) can couple to each signal, and this EMI coupling can cause additional noise problems. By transmitting signals differentially, the EMI typically coupled to two differential signals can be canceled. The industry needs a deflector driver system with differential drive capability, with the following specifications.

[0026] Deflection driver systems are expected to operate at higher speeds, with power bandwidths greater than 1 MHz, to meet industry demands for scan rates, such as 1.2 gigabits per second. Increasing the bandwidth of deflection driver systems presents a challenge because the bandwidth of the power amplifier, a key component of the system, is limited by a trade-off between scan speed and stability. Higher power amplifier bandwidth allows for higher scan speeds, which can also improve system yield. However, at the same gain-bandwidth product (GBW), increasing circuit bandwidth causes the power amplifier to operate in a lower phase margin region, leading to reduced circuit stability and consequently lower image resolution. Therefore, it is desirable to design power amplifiers with higher bandwidths or GBWs to achieve higher throughput while maintaining sufficient circuit stability. It is also desirable for power amplifiers to be designed with unity-gain stability and a phase margin greater than 60 degrees to provide sufficient design flexibility for the deflection driver system. However, increasing the bandwidth of the power amplifier can introduce more noise into the system, thus reducing signal quality and image resolution. Therefore, there is a need in the art to provide increased power bandwidth without sacrificing signal quality, for example, by maintaining low noise levels.

[0027] Higher voltage outputs are desired in deflection driver systems to achieve faster scan rates. There is a trade-off between output voltage level and signal-to-noise ratio (SNR). Higher voltage levels in the deflection drive signal reduce SNR because the noise floor is amplified along with the drive signal. Lower voltage levels can be considered to improve SNR. However, lower voltage drive signals may not be able to deflect the beam across the entire inspection range. Furthermore, lower voltage drive signals may not achieve the required inspection sensitivity at the edges of the inspection area. To increase the inspection area and improve edge sensitivity when using lower voltage drive signals, a deflector with higher sensitivity can be used to compensate for the reduction in electric field strength, thus ensuring the desired electric field strength level is achieved at lower voltages. The sensitivity of the deflector can often be increased by designing a bulkier or longer deflector, which ultimately leads to reduced image resolution, especially at the edges of the inspection area. Therefore, there is a need in the art to provide deflection driver systems with higher voltages without sacrificing signal quality. In this disclosure, a higher voltage level can refer to a voltage level greater than 100V, which can support industry scan rate requirements, such as 1.2 gigabits per second, without sacrificing signal quality, for example, by maintaining a low noise level.

[0028] Higher slew rates, such as greater than 500V / µs, are also expected for deflection driver systems to achieve desired scan throughput. As scan rates continue to increase, higher slew rates become increasingly important for reducing scan overhead. Furthermore, by utilizing dynamic links, the output wiring of deflection driver systems may be longer in future products, making higher slew rates even more crucial for increasing throughput. When the slew rate is greater than 500V / µs, excessive overhead caused by longer wiring can be avoided, thereby improving throughput.

[0029] It is also expected that the noise level of the deflection driver system will be kept below 2.5 nV / sqrt (Hz). The noise specifications of traditional deflection driver systems (e.g., 3 nV / sqrt (Hz)) have historically met industry noise standards. However, with the emergence of new products utilizing smaller pixel sizes, the demand for deflection driver systems with lower noise levels is constantly increasing.

[0030] Because conventional fully differential amplifiers cannot meet the aforementioned design criteria, pseudo-differential power amplifiers, constructed from dual single-ended power amplifiers, are used in conventional deflection driver systems. However, pseudo-differential power amplifiers consist of multiple discrete power amplifiers, such as two single-ended power amplifiers, each integrated into its own IC chip. Therefore, even with the selection of components with the highest practical precision and extensively optimized printed circuit board (PCB) designs, component mismatch between the two independent amplifiers is unavoidable. This component mismatch limits the common-mode rejection ratio (CMRR), resulting in higher noise levels and consequently lower image resolution. As mentioned above, conventional deflection driver systems utilizing pseudo-differential power amplifiers exhibit high noise levels, at least in part due to the low CMRR caused by component mismatch between the two single-ended power amplifiers. Therefore, while conventional deflection driver systems including pseudo-differential power amplifiers can drive high-voltage signals, they cannot meet the noise standards required for next-generation systems, such as less than 2.5 nV / sqrt(Hz).

[0031] According to some embodiments of this disclosure, a deflector driver system can be provided that utilizes a fully differential power amplifier instead of a pseudo-differential power amplifier. According to some embodiments of this disclosure, the deflector driver system can drive higher voltage deflector drive signals that meet the above-described standards at high speed. According to some embodiments of this disclosure, a differential power amplifier is provided, configured to generate a fully differential output with an absolute value greater than 100V. According to some embodiments of this disclosure, a deflector driver system with an improved common-mode rejection ratio can be provided. According to some embodiments of this disclosure, the differential power amplifier can be fully integrated with common-mode feedback circuitry into a single IC chip, which improves scan speed and throughput to meet the above-described standards. According to some embodiments of this disclosure, the fully differential power amplifier can be integrated into a single IC chip, which reduces noise originating from component mismatch. According to some embodiments of this disclosure, a deflector driver system including a fully differential power amplifier and multiple digital-to-analog converters (DACs) can be mounted on a single PCB board, which saves PCB area and improves PCB design efficiency. According to some embodiments of this disclosure, a deflector driver system with high-speed, low-noise, high-voltage, and high-slew rate differential drive capability can be provided.

[0032] For clarity, the relative dimensions of components in the accompanying drawings may be exaggerated. In the following description of the drawings, the same or similar reference numerals refer to the same or similar components or entities, and differences from individual embodiments are described only. Other objects and advantages of this disclosure can be achieved by the elements and combinations set forth in the embodiments discussed herein. However, embodiments of this disclosure are not necessarily required to achieve such exemplary objects or advantages, and some embodiments may not achieve any of the stated objects or advantages.

[0033] Without limiting the scope of this disclosure, some embodiments can be described in the context of providing scanning deflection systems and methods in systems utilizing electron beams (“e-beams”). Some scanning deflection systems can use an electric field to influence a charged particle beam. However, this disclosure is not limited thereto. Other types of charged particle beams can be applied similarly. For example, systems and methods can be applied to optical, photonic, X-ray, and ion beams. Deflection can be used to scan the beam on a surface, such as a cathode ray tube (CRT), a lithography machine, a scanning charged particle microscope (SCPM), or other analytical instruments. While some embodiments are discussed with reference to deflection systems that use an electric field to influence the beam, deflection can also be achieved using a magnetic field.

[0034] As used herein, unless otherwise specified, the term "or" covers all possible combinations unless impractical. For example, if a component is specified to include either A or B, then unless otherwise specified or impractical, the component may include A, or B, or A and B. As a second example, if a component is specified to include A, B, or C, then unless otherwise specified or impractical, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C. Expressions such as "at least one" do not necessarily modify the entire list below, nor do they necessarily modify every member of the list; therefore, "at least one of A, B, and C" should be understood to include only one of A, only one of B, only one of C, or any combination of A, B, and C. The phrase "one of A and B" or "any one of A and B" should be interpreted in the broadest sense to include either one of A or one of B.

[0035] Figure 1 An exemplary electron beam inspection (EBI) system 100 consistent with embodiments of this disclosure is shown. The EBI system 100 can be used for imaging. Figure 1 As shown, the EBI system 100 includes a main chamber 101, a loading / locking chamber 102, a beam tool 104, and an Equipment Front-End Module (EFEM) 106. The beam tool 104 is located within the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include one or more additional loading ports. The first loading port 106a and the second loading port 106b receive a front-opening wafer transfer cassette (FOUP), which contains wafers (e.g., semiconductor wafers or wafers made of other materials) or samples to be inspected (wafers and samples can be used interchangeably). A “lot” refers to multiple wafers that can be loaded and processed as a batch.

[0036] One or more robotic arms (not shown) in EFEM 106 can transport the wafer to loading / locking chamber 102. Loading / locking chamber 102 is connected to a loading / locking vacuum pump system (not shown), which removes gas molecules within loading / locking chamber 102 to achieve a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transport the wafer from loading / locking chamber 102 to main chamber 101. Main chamber 101 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules within main chamber 101 to achieve a second pressure below the first pressure. After reaching the second pressure, the wafer is inspected by a beam tool 104. Beam tool 104 can be a single-beam system or a multi-beam system.

[0037] Controller 109 is electrically connected to clamping tool 104. Controller 109 may be a computer configured to perform various controls of EBI system 100. Although controller 109 is... Figure 1 The controller 109 is shown outside the structure that includes the main chamber 101, the loading / locking chamber 102 and the EFEM 106, but it should be understood that the controller 109 may be part of the structure.

[0038] In some embodiments, controller 109 may include one or more processors (not shown). A processor may be a general-purpose or specific electronic device capable of manipulating or processing information. For example, a processor may include any number of central processing units (or “CPU”), graphics processing units (or “GPUs”), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable controller arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), application-specific integrated circuits (ASICs), and any combination of any type of circuitry capable of data processing. A processor may also be a virtual processor, comprising one or more processors distributed across multiple machines or devices coupled via a network.

[0039] In some embodiments, controller 109 may also include one or more memories (not shown). The memory can be a general-purpose or specific electronic device capable of storing processor-accessible code and data (e.g., via a bus). For example, the memory may include any number of random access memory (RAM), read-only memory (ROM), optical discs, magnetic disks, hard disks, solid-state drives, flash drives, secure digital cards (SD cards), memory sticks, compact flash (CF) cards, or any combination of any type of storage device. The code and data may include an operating system (OS) and one or more applications (or “apps”) for a specific task. The memory may also be virtual memory, which includes one or more memories distributed across multiple machines or devices coupled via a network.

[0040] Figure 2A A schematic diagram of an exemplary multi-beam tool 104A (also referred to herein as device 104A) and an image processing system 290 consistent with embodiments of the present disclosure is shown, which can be configured for use in EBI system 100 ( Figure 1 ).

[0041] The beam tool 104A includes a charged particle source 202, a bore 204, a condenser lens 206, a primary charged particle beam 210 emitted from the charged particle source 2020, a source conversion unit 212, multiple beamlets 214, 216, and 218 of the primary charged particle beam 210, a main projection optics system 220, a motorized wafer stage 280, a wafer holder 282, multiple secondary charged particle beams 236, 238, and 240, an auxiliary optics system 242, and a charged particle detection device 244. The main projection optics system 220 may include a beam splitter 222, a deflection scanning unit 226, and an objective lens 228. The charged particle detection device 244 may include detection sub-regions 246, 248, and 250.

[0042] The charged particle source 202, the aperture 204, the condenser lens 206, the source conversion unit 212, the beam splitter 222, the deflection scanning unit 226, and the objective lens 228 can be aligned with the main optical axis 260 of the device 104A. The auxiliary optical system 242 and the charged particle detection device 244 can be aligned with the auxiliary optical axis 252 of the device 104A.

[0043] Charged particle source 202 can emit one or more charged particles, such as electrons, protons, ions, muons, or any other charged particles. In some embodiments, charged particle source 202 can be an electron source. For example, charged particle source 202 can include a cathode, extractor, or anode, wherein primary electrons can be emitted from the cathode and extracted or accelerated to form a primary charged particle beam 210 (in this case, a primary electron beam) having a crossover point (virtual or real) 208. For ease of explanation and without ambiguity, electrons are used as examples in some descriptions herein. However, it should be noted that any charged particle can be used in any embodiment of this disclosure, and is not limited to electrons. The primary charged particle beam 210 can be visualized as being emitted from the crossover point 208. The aperture 204 can block peripheral charged particles of the primary charged particle beam 210 to reduce the Coulomb effect. The Coulomb effect can lead to an increase in the size of the detection point.

[0044] Source conversion unit 212 may include an imaging element array and a beam confinement aperture array. The imaging element array may include a micro-deflector or microlens array. The imaging element array can form multiple parallel images (virtual or real) at intersection 208 with multiple beam waves 214, 216, and 218 of the primary charged particle beam 210. The beam confinement aperture array can confine the multiple beam waves 214, 216, and 218. Although Figure 2AThree beams 214, 216, and 218 are shown, but embodiments of this disclosure are not limited thereto. For example, in some embodiments, device 104A may be configured to generate a first number of beams. In some embodiments, the first number of beams may be in the range of 1 to 1000. In some embodiments, the first number of beams may be in the range of 200 to 500. In an exemplary embodiment, device 104A may generate 400 beams.

[0045] The condenser lens 206 can focus the primary charged particle beam 210. The currents of the beam waves 214, 216, and 218 downstream of the source conversion unit 212 can be changed by adjusting the focusing capability of the condenser lens 206 or by changing the radial dimensions of the corresponding beam-limiting apertures in the beam-limiting aperture array. The objective lens 228 can focus the beam waves 214, 216, and 218 onto the wafer 230 for imaging, and can form multiple detection points 270, 272, and 274 on the surface of the wafer 230.

[0046] Beam splitter 222 can be a Wien filter type beam splitter that generates electrostatic dipole fields and magnetic dipole fields. In some embodiments, if an electrostatic dipole field is applied, the force exerted by the electrostatic dipole field on the charged particles (e.g., electrons) of beam waves 214, 216, and 218 on the charged particles can be substantially equal in magnitude and opposite in direction to the force exerted by the magnetic dipole field on the charged particles. Therefore, beam waves 214, 216, and 218 can pass directly through beam splitter 222 with zero deflection. However, the total dispersion of beam waves 214, 216, and 218 generated by beam splitter 222 can also be non-zero. Beam splitter 222 can separate secondary charged particle beams 236, 238, and 240 from beam waves 214, 216, and 218, and direct secondary charged particle beams 236, 238, and 240 toward auxiliary optical system 242.

[0047] Deflection scanning unit 226 can deflect beams 214, 216, and 218 to scan detection points 270, 272, and 274 on the surface region of wafer 230. In response to the incident beams 214, 216, and 218 at detection points 270, 272, and 274, secondary charged particle beams 236, 238, and 240 can be emitted from wafer 230. Secondary charged particle beams 236, 238, and 240 can include charged particles (e.g., electrons) with an energy distribution. For example, secondary charged particle beams 236, 238, and 240 can be secondary electron beams comprising secondary electrons (energy ≤ 50 eV) and backscattered electrons (energy between 50 eV and the landing energy of beams 214, 216, and 218). The auxiliary optical system 242 can focus the secondary charged particle beams 236, 238, and 240 onto the detection sub-regions 246, 248, and 250 of the charged particle detection device 244. The detection sub-regions 246, 248, and 250 can be configured to detect the corresponding secondary charged particle beams 236, 238, and 240 and generate corresponding signals (e.g., voltage, current, etc.) for reconstructing an inspection image of the structure on or under the surface region of the wafer 230.

[0048] The generated signals can represent the intensity of the secondary charged particle beams 236, 238, and 240, and can be provided to an image processing system 290 that communicates with the charged particle detection device 244, the main projection optics system 220, and the motorized wafer stage 280. The movement speed of the motorized wafer stage 280 can be synchronized and coordinated with the beam deflection controlled by the deflection scanning unit 226, so that the movement of the scanning probe points (e.g., scanning probe points 270, 272, and 274) can orderly cover the region of interest on the wafer 230. The parameters of this synchronization and coordination can be adjusted to accommodate different materials of the wafer 230. For example, different materials of the wafer 230 may have different resistivity and capacitance characteristics, which may result in different signal sensitivities to the movement of the scanning probe points.

[0049] The intensities of the secondary charged particle beams 236, 238, and 240 can vary depending on the external or internal structure of the wafer 230, and thus can indicate whether the wafer 230 contains defects. Furthermore, as described above, beams 214, 216, and 218 can be projected onto different locations on the top surface of the wafer 230, or different sides of a local structure of the wafer 230, to generate secondary charged particle beams 236, 238, and 240 with varying intensities. Therefore, by mapping the intensities of the secondary charged particle beams 236, 238, and 240 to regions of the wafer 230, the image processing system 290 can reconstruct an image reflecting the characteristics of the internal or external structure of the wafer 230.

[0050] In some embodiments, the image processing system 290 may include an image acquirer 292, a storage device 294, and a controller 296. The image acquirer 292 may include one or more processors. For example, the image acquirer 292 may include a computer, server, mainframe, terminal, personal computer, any type of mobile computing device, or a combination thereof. The image acquirer 292 may be communicatively coupled to the charged particle detection device 244 of the beam tool 104A via a medium such as an electrical conductor, fiber optic cable, portable storage medium, IR, Bluetooth, Internet, wireless network, wireless radio, or a combination thereof. In some embodiments, the image acquirer 292 may receive signals from the charged particle detection device 244 and may construct an image. Thus, the image acquirer 292 may acquire an inspection image of the wafer 230. The image acquirer 292 may also perform various post-processing functions, such as generating contours, overlaying indicators on the acquired image, etc. The image acquirer 292 may be configured to perform brightness and contrast adjustments on the acquired image. In some embodiments, the storage device 294 may be a storage medium such as a hard disk, flash memory, cloud storage, random access memory (RAM), other types of computer-readable storage, etc. Storage device 294 can be coupled to image acquirer 292 and can be used to save scanned raw image data as raw images and post-processed images. Image acquirer 292 and storage device 294 can be connected to controller 296. In some embodiments, image acquirer 292, storage device 294 and controller 296 can be integrated together as a single control unit.

[0051] In some embodiments, the image acquirer 292 may acquire one or more inspection images of the wafer based on imaging signals received from the charged particle detection device 244. The imaging signals may correspond to a scanning operation for performing charged particle imaging. The acquired image may be a single image comprising multiple imaging regions. The single image may be stored in the storage device 294. The single image may be an original image that can be divided into multiple regions. Each region may include an imaging region containing features of the wafer 230. The acquired images may include multiple images of a single imaging region of the wafer 230 sampled multiple times over a time series. The multiple images may be stored in the storage device 294. In some embodiments, the image processing system 290 may be configured to perform image processing steps on multiple images of the same location on the wafer 230.

[0052] In some embodiments, the image processing system 290 may include measurement circuitry (e.g., an analog-to-digital converter) to acquire the distribution of detected secondary charged particles (e.g., secondary electrons). The charged particle distribution data collected during the detection time window, combined with corresponding scan path data of the beams 214, 216, and 218 incident on the wafer surface, can be used to reconstruct an image of the inspected wafer structure. The reconstructed image can be used to reveal various features of the internal or external structure of the wafer 230, and thus can be used to reveal any defects that may exist in the wafer.

[0053] In some embodiments, the charged particles can be electrons. When electrons from the primary charged particle beam 210 are projected onto the surface of the wafer 230 (e.g., detection points 270, 272, and 274), the electrons of the primary charged particle beam 210 can penetrate the surface of the wafer 230 to a certain depth to interact with the particles of the wafer 230. Some electrons from the primary charged particle beam 210 can elastically interact with the material of the wafer 230 (e.g., in the form of elastic scattering or collision) and can be reflected or bounced off the surface of the wafer 230. Elastic interactions conserve the total kinetic energy of the interacting objects (e.g., electrons from the primary charged particle beam 210), where the kinetic energy of the interacting objects is not converted into other forms of energy (e.g., heat, electromagnetic energy, etc.). Such reflected electrons generated by elastic interactions can be called backscattered electrons (BSE). Some electrons from the primary charged particle beam 210 can inelastically interact with the material of the wafer 230 (e.g., in the form of inelastic scattering or collision). Inelastic interactions do not preserve the total kinetic energy of the interacting objects; some or all of the kinetic energy is converted into other forms of energy. For example, through inelastic interaction forces, the kinetic energy of some electrons in the primary charged particle beam 210 may lead to electron excitation and transitions between material atoms. This inelastic interaction can also generate electrons emitted from the surface of wafer 230, which can be called secondary electrons (SEs). The throughput or emission rate of BSEs and SEs depends, for example, on the material being examined and the landing energy of the electrons in the primary charged particle beam 210 on the material surface. The energy of the electrons in the primary charged particle beam 210 can be partly determined by its accelerating voltage (e.g., Figure 2A The accelerating voltage between the anode and cathode of the charged particle source 202 is imparted. The number of BSE and SE can be more or less (or even the same) than the injected electrons of the primary charged particle beam 210.

[0054] Now refer to Figure 2B Another example of a charged particle beam device is discussed. Beam tool 104B (also referred to herein as device 104B) can be an example of beam tool 104 and can be similar to... Figure 2AThe device 104A is shown as a beam tool. However, unlike device 104A, device 104B can be a single-beam tool, which uses only one primary electron beam to scan one location on the wafer at a time.

[0055] like Figure 2B As shown, device 104B includes a wafer holder 136 supported by a motorized stage 134 for holding a wafer 150 to be inspected. Beam tool 104B includes an electron emitter that may include a cathode 103, an anode 121, and a bore 122. Beam tool 104B also includes a beam limiting aperture 125, a condenser lens 126, a post aperture 135, an objective assembly 132, and a detector 144. In some embodiments, objective assembly 132 may be a modified SORIL lens, which includes a pole piece 132a, a control electrode 132b, a deflector unit 132c, and an excitation coil 132d. During inspection or imaging, an electron beam 161 emitted from the tip of cathode 103 can be accelerated by the voltage of anode 121, passes through bore 122, beam limiting aperture 125, and condenser lens 126, and is focused by the modified SORIL lens onto a detection point 170, impacting the surface of wafer 150. The probe point 170 can be scanned across the surface of the wafer 150 by a deflector (such as deflector unit 132c or other deflectors in a SORIL lens). Secondary or scattering particles, such as secondary electrons emitted from the wafer surface or scattered primary electrons, can be collected by the detector 144 to determine the intensity of the beam and to reconstruct an image of the region of interest on the wafer 150.

[0056] An image processing system 199 may also be provided, comprising an image acquirer 120, a storage device 130, and a controller 109. The image acquirer 120 may include one or more processors. For example, the image acquirer 120 may include a computer, server, mainframe, terminal, personal computer, any type of mobile computing device, or a combination thereof. The image acquirer 120 may be connected to the detector 144 of the beam tool 104B via a medium such as an electrical conductor, fiber optic cable, portable storage medium, IR, Bluetooth, Internet, wireless network, wireless radio, or a combination thereof. The image acquirer 120 may receive signals from the detector 144 and may construct an image. Therefore, the image acquirer 120 may acquire an image of the wafer 150. The image acquirer 120 may also perform various post-processing functions, such as image averaging, contour generation, overlaying indicators on the acquired image, etc. The image acquirer 120 may be configured to perform adjustments such as brightness and contrast of the acquired image. The storage device 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage device, or other types of computer-readable storage. Storage device 130 may be coupled to image acquirer 120 and may be used to save scanned raw image data as raw images and post-processed images. Image acquirer 120 and storage device 130 may be connected to controller 109. In some embodiments, image acquirer 120, storage device 130 and controller 109 may be integrated together as an electronic control unit.

[0057] In some embodiments, the image acquirer 120 may acquire one or more images of a sample based on imaging signals received from the detector 144. The imaging signals may correspond to a scanning operation for imaging charged particles. The acquired image may be a single image comprising multiple imaging regions, which may contain various features of the wafer 150. The single image may be stored in the storage device 130. Imaging may be performed based on imaging frames.

[0058] The concentrator and illumination optics of an electron beam tool may include or be supplemented with an electromagnetic quadrupole electron lens. For example, such as Figure 2B As shown, the electron beam tool 104B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used to control the electron beam. For example, the first quadrupole lens 148 may be controlled to adjust the beam current, and the second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0059] Figure 2B A charged particle beam device is shown that can use a single primary beam, which can generate secondary electrons through interaction with a wafer 150. A detector 144 can be positioned along the optical axis 105, as shown... Figure 2BIn the illustrated embodiment, the primary electron beam can be configured to travel along the optical axis 105. Therefore, the detector 144 can include a hole at its center so that the primary electron beam can pass through to reach the wafer 150. Figure 2B An example of a detector 144 with an opening at its center is shown. However, some embodiments may use a detector positioned off-axis relative to the optical axis along which the primary electron beam travels. For example, as discussed above. Figure 2B The illustrated embodiment may provide a beam splitter 222 to direct the secondary electron beam to an off-axis detector. The beam splitter 222 may be configured to direct the secondary electron beam toward the electron detection device 244, such as... Figure 2A As shown.

[0060] Images generated by SCPM can be used for defect inspection. For example, a generated image used to capture a test device area of ​​a wafer can be compared with a reference image used to capture the same test device area. The reference image can be predetermined (e.g., by simulation) and does not include known defects. If the difference between the generated image and the reference image exceeds a tolerance level, a potential defect can be identified. As another example, SCPM can scan multiple areas of a wafer, each including identically designed test device areas, and generate multiple images capturing these manufactured test device areas. These multiple images can be compared with each other. If the differences between the multiple images exceed a tolerance level, a potential defect can be identified.

[0061] Now for reference Figure 3A This illustrates a configuration of the deflector and objective lens assembly consistent with embodiments of this disclosure. For example... Figure 3A As shown, deflectors 309-1 and 309-2 can be disposed within the magnetic field of the magnetic objective lens assembly 310, wherein deflectors 309-2 and 309-1 can be disposed within the deflection scanning unit (e.g., Figure 2A It can be implemented in the deflection scanning unit 226, or it can be used as a deflector unit (e.g., Figure 2B The deflector unit 132c is used for implementation. Deflectors 309-1 and 309-2 can be configured to dynamically deflect the electron beam to scan a desired region on the surface of sample 308. The dynamic deflection of the electron beam may cause the desired region or region of interest to be iteratively scanned, for example in a raster scan mode, to generate a secondary electron beam for sample inspection (e.g., Figure 2A (236, 238, and 240). Deflectors 309-1 or 309-2 can be configured to deflect the electron beam in the X-axis or Y-axis direction. As used herein, the X-axis and Y-axis form Cartesian coordinates of an arbitrary reference frame, where the electron beam can propagate along the Z-axis or principal optical axis 304. Figure 2A , Figure 2B or Figure 3AIn the view, the X-axis refers to the horizontal axis or transverse axis that extends along the width of the paper, and the Y-axis refers to the vertical axis that extends inside and outside the plane of the paper.

[0062] Now for reference Figure 3B This illustrates a representation of a charged particle beam passing through a deflector, consistent with embodiments of the present disclosure. In some embodiments, the charged particle beam passes through the region between a pair of electrodes 335 and 345 of the deflector (as will be discussed later). Figure 3C Electrodes e2 and e4 in the middle may be deflected. Figure 3B As shown, the charged particle beam 320 can travel along axis 350. Axis 350 can be aligned with the Z-axis of the charged particle beam system. Electrodes 335 and 345 can be positioned on either side of axis 350. A voltage can be applied to electrodes 335 and 345. An electric field can be formed between the electrodes, with its component substantially perpendicular to the direction of travel of the charged particle beam 320. As the charged particle beam 320 travels through the generated electric field, it may be affected by the electric field. For example, its trajectory may change. A deflection scanning unit can use a deflector to deflect the beam in order to scan the beam across a region on the sample.

[0063] Now for reference Figure 3C This is a diagram showing the configuration of the electrodes of a deflector consistent with embodiments of the present disclosure. Figure 3C A multi-pole structure with four electrodes e1-e4 is shown, which can be configured to operate in different ways based on the voltage applied to each electrode. Deflector (e.g., Figure 3A The deflector (309-1 or 309-2) can be formed using electrodes e1-e4. In some embodiments, a deflection voltage can be formed between opposing electrode pairs (e.g., an electrode pair formed by electrodes e2 and e4; or an electrode pair formed by electrodes e1 and e3). Multiple pairs of electrodes can be combined to allow deflection in a two-dimensional plane. For example, a first pair of electrodes (e.g., electrodes e2 and e4) can be operated to deflect the beam in the X direction, and a second pair of electrodes (e.g., electrodes e1 and e3) can be operated to deflect the beam in the Y direction. The deflector can be located in the objective region of the SEM system. The deflector can be used to dynamically guide the beam to a desired location on the sample surface. In some embodiments, multiple beams can be guided to multiple locations on the sample surface.

[0064] like Figure 3A As shown, the deflection scanning unit may include two deflectors 309-1 and 309-2, which are stacked in the z-direction and configured to cooperate with each other to precisely manipulate the beam. Because in this configuration, even a small error in one or two deflectors can cause the beam trajectory to deviate further from the expected trajectory, accurate and precise manipulation of the deflectors is even more critical. Although the deflection scanning unit (e.g., Figure 2AThe deflection scanning unit 226) or deflector unit (e.g., Figure 2B The deflector unit 132c is shown as comprising two deflectors 309-1 and 309-2, each having four electrodes e1-e4. However, it should be noted that any number of deflectors having any number of electrodes can be used in the embodiments of this disclosure, and is not limited to any other type. Figures 3A-3C The configuration shown. It should also be recognized that any pair of electrodes can be controlled to deflect the beam in any direction other than the X or Y direction.

[0065] Now for reference Figure 4 This illustrates an exemplary configuration of a deflection control unit 400 associated with charged particle beam deflectors (e.g., primary electron beam deflectors 309-1 and 309-2) consistent with embodiments of this disclosure. As shown, each primary electron beam deflector can be electronically driven by a corresponding driver system. For example, the deflection control unit 400 may include a driver system 425-1 associated with primary electron beam deflector 309-1 and a driver system 425-2 associated with primary electron beam deflector 309-2. Figure 4 As shown, deflector 309-1 can be implemented as having four electrodes 401-404, and deflector 309-2 can be implemented as having four electrodes 405-408.

[0066] like Figure 4 As shown, the deflection control unit 400 may further include a scan control unit 450. The scan control unit 450 may be configured to generate deflection signals 430-1 to 430-4, which are configured to be applied to primary electron beam deflectors 309-1 and 309-2. Deflection signals 430-1 to 430-4 may include voltage / current signals applied to one or more corresponding electrodes of the primary electron beam deflector(s). Although Figure 4 The deflection control unit 400 shown includes a single scan control unit 450 configured to generate and provide deflection signals for multiple driver systems (e.g., 425-1 and 425-2), but it should be understood that any number of scan control units 450 may be used in embodiments of this disclosure, such as a separate scan control unit for each driver system.

[0067] In some embodiments, the scan control unit 450 can generate multiple deflection signals corresponding to the multiple electrodes 401 to 408 of the deflectors 309-1 and 309-2. For example... Figure 4As shown, the scan control unit 450 can generate deflection signals 430-1 to 430-4 for manipulating electrodes 401-408 of deflectors 309-1 and 309-2. In some embodiments, the driver system (e.g., driver system 425-01 or 425-2) may include multiple DACs for converting digital deflection signals (e.g., deflection signals 430-1 to 430-4) into analog deflection signals when the deflection signals 430-1 to 430-4 are digital signals. In some embodiments, the driver system (e.g., driver system 425-1 or 425-2) may also include one or more power amplifiers configured to generate drive signals (e.g., drive signals 431 to 438) corresponding to the deflection signals (e.g., deflection signals 430-1 to 430-4). It should be understood that, although not shown, the driver system (e.g., driver system 425-1 or 425-2) may include other components and circuitry, such as a variable gain amplifier, power supply, timing circuitry, etc., to appropriately manipulate along the principal optical axis (e.g., Figure 3A The primary electron beam travels along the main optical axis 304. In some embodiments, the driver system 425-1 or 425-2 may further include circuitry for calibration, offset and gain adjustment, scan pattern generation, or diagnostics, which will not be described in this disclosure for simplicity. In some embodiments, a pair of electrodes may be controlled to deflect the beam in a predetermined direction. For example, a first pair of electrodes 402 and 404 may be controlled to deflect the beam in the X direction, and a second pair of electrodes 401 and 403 may be controlled to deflect the beam in the Y direction. To deflect the beam in the X direction, drive signals 432 and 434 (e.g., +V) having the same absolute value and opposite polarity can be used. X and -V X A drive signal 431 and 433 (e.g., +V) with the same absolute value and opposite polarity can be applied to the first pair of electrodes 402 and 404. Similarly, to deflect the beam in the Y direction, drive signals 431 and 433 with the same absolute value and opposite polarity can be applied. Y and -V Y The beam is applied to the second pair of electrodes 401 and 403. It should be understood that other electrode pairs (e.g., the third pair of electrodes 406 and 408 and the fourth pair of electrodes 405 and 407) can be controlled in a similar manner to deflect the beam in a certain direction.

[0068] Now for reference Figure 5 This illustrates a deflector driver system architecture with a pseudo-differential amplifier utilizing dual single-ended power amplifiers. In some embodiments, the driver system 500 may be Figure 4 The driver system 425-1 or 425-2 is used to drive deflector electrodes, such as deflector electrodes 401-408. The driver system 500 can be configured to receive deflection signals and generate high-voltage drive signals for the deflector electrodes. Figure 5 As shown, the driver system 500 may include a pattern generator 510 and a deflection driver 520.

[0069] In some embodiments, the deflection pattern generator 510 may include one or more digital-to-analog converters (DACs) that convert one or more digital deflection signals into one or more analog deflection signals. Figure 5 The deflection pattern generator 510 is shown to include two DACs, 511-1 and 511-2. (See diagram.) Figure 5 As shown, the first DAC 511-1 is configured to receive a first digital deflection signal 501-1 and generate differential analog deflection signals 502-1 and 502-2. The first differential analog deflection signal 502-1 and the second differential analog deflection signal 502-2 may have the same absolute value but opposite polarities, such as +S and -S. In some embodiments, the first digital deflection signal 501-1 may be a signal used to manipulate the beam in a specific direction (e.g., the X direction). The first differential analog deflection signal 502-1 and the second differential analog deflection signal 502-2 may each have a value of +S. X and -S X Similarly, such as Figure 5 As shown, the second DAC 511-2 is configured to receive the second digital deflection signal 501-2 and generate differential analog deflection signals 502-3 and 502-4. The second digital deflection signal 501-2 can be a signal used to manipulate the beam in different directions (e.g., the Y direction). The third differential analog deflection signal 502-3 and the fourth differential analog deflection signal 502-4 can each have a value of +S. Y and -S Y .

[0070] like Figure 5 As shown, the pattern generator 510 may also include other components and circuitry, such as various amplifiers. For example, the pattern generator 510 may include transimpedance amplifiers 512-1 to 512-4 for converting the impedance of analog deflection signals 502-1 to 502-4. In some embodiments, after the transimpedance amplifiers 512-1 to 512-4 convert the impedance, for example, from current to voltage, the analog deflection signals 502-1 to 502-4 may be +V respectively. X -V X +V Y and -V Y In the form of. For example... Figure 5 As shown, the pattern generator 510 may further include an additional amplifier 513 configured to amplify the deflection signal. Amplifier 513 may be configured to correct the common-mode voltage of the deflection signal to be transmitted to the deflection driver 520. Figure 5As shown, amplifier 513 can be a fully differential amplifier that receives differential inputs and has differential outputs. By using a fully differential amplifier, EMI coupling problems along the transmission path can be reduced. In some embodiments, some deflection signals can be superimposed before being provided as inputs to amplifier 513. In some embodiments, positive deflection signals can be superimposed and provided as one differential input to amplifier 513, and negative deflection signals can be superimposed and provided as the other differential input to amplifier 513. Figure 5 In the middle, the first analog deflection signal 502-1 (+V X ) and the third analog deflection signal 502-3 (+V Y The signals are superimposed to form the first superimposed signal 503-1 (+V). X and +V Y The sum of these signals is provided as the first differential input of amplifier 513. Similarly, the second analog deflection signal 502-2 (-V X ) and the fourth analog deflection signal 502-4 (-V Y The signals are superimposed to form a second superimposed signal 503-2 (-V). X and -V Y (the sum of ), and is provided as the second differential input of amplifier 513.

[0071] like Figure 5 As shown, after the deflection signals 502-1 to 502-4 are impedance-converted, superimposed, or amplified by the pattern generator 510, the deflection signals 502-1 to 502-4 can be provided to the deflection driver 520. In some embodiments, the deflection driver 520 may include a pseudo-differential power amplifier 515 configured to generate different high-voltage drive signals. Figure 5 As shown, the pseudo-differential power amplifier 515 can be implemented using two separate single-ended power amplifiers 515-1 and 515-2. Figure 5 In this configuration, the first single-ended power amplifier 515-1 can be configured to receive the first superimposed signal 503-1 (e.g., +V). X and +V Y The sum of (and output the first superimposed drive signal 504-1, for example, as +V) OX and +V OY The sum of . Similarly, the second single-ended power amplifier 515-2 can be configured to receive the second superimposed signal 503-2 (e.g., -V X and -V Y The sum of (and outputs a second superimposed drive signal 504-2, for example, as -V) OX and -V OYThe sum of. In some embodiments, when the inputs to the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 are differential signals with the same absolute value but opposite polarities, the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 can be configured to generate differential output signals with the same absolute value but opposite polarities. Figure 5 In this context, because the inputs of the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 are differential signals with the same absolute value but opposite polarities (V... X and V Y (the sum of the two amplifiers), therefore the first single-ended amplifier 515-1 and the second single-ended power amplifier 515-2 can operate like a single differential amplifier generating a differential output signal. In this respect, in this disclosure, the first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 are collectively referred to as pseudo-differential amplifiers.

[0072] In some embodiments, the output of the deflection driver 520 can be segmented before being applied to the corresponding electrode because these outputs are superimposed output signals. For example, the first superimposed drive signal 504-1 can be used to generate two drive signals +V before being applied to the corresponding electrode. OX and +V OY For example, applied to Figure 3C electrode e2 or Figure 4 The drive signal +V of electrode 402 OX and applied to Figure 3C electrode e1 or Figure 4 The drive signal +V of electrode 401 OY Similarly, the second superimposed drive signal 504-2 can be used to generate two drive signals -V before being applied to the corresponding electrode. OX and -V OY For example, applied to Figure 3C electrode e4 or Figure 4 The drive signal -V of electrode 404 OX and applied to Figure 3C electrode e3 or Figure 4 The drive signal -V of electrode 403 OY .like Figure 5 As shown, the deflection driver 520 may also include another differential amplifier 514 for eliminating or minimizing common-mode noise injected along the path from the pattern generator 510 to the pseudo-differential power amplifier 515.

[0073] While the driver system 500 has been shown to be configured to generate drive signals for manipulating the beam in both the X and Y directions, it should be understood that the driver system 500 can be configured to generate drive signals for manipulating the beam in only one direction. For example, the driver system 500 can be configured to generate drive signals for manipulating the beam in the X direction. In these implementations, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified before being input into power amplifiers 515-1 and 515-2 by comparing the coordinates of the wafer on the wafer stage with the coordinates of the deflector electrodes. For example, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified to generate differential signals representing the actual deflection control signal in the X direction. In some embodiments, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified based on the coordinates of the wafer on the wafer stage, the coordinates of the deflector electrodes, and the rotation angle between the wafer coordinates and the deflector electrode coordinates. In these implementations, the outputs of power amplifiers 515-1 and 515-2 can be differential drive signals for electrodes that are controlled to deflect the beam in the X direction, for example... Figure 3C The first pair of electrodes e2 and e4 or Figure 4 The first pair of electrodes 402 and 404. Similarly, in some embodiments, an additional driver system, similar to driver system 500, can be used to generate drive signals to manipulate the beam in the Y direction. In these implementations, the output of the power amplifier of the additional driver system can be a differential drive signal for electrodes that are controlled to deflect the beam in the Y direction, for example... Figure 3C The second pair of electrodes e1 and e3 or Figure 4 The second pair of electrodes, 401 and 403.

[0074] Now for reference Figure 6 This illustrates a single-ended power amplifier circuit configuration. The single-ended power amplifier 600 can be... Figure 5 The first single-ended power amplifier 515-1 and the second single-ended power amplifier 515-2 are both possible. The single-ended power amplifier 600 may include an input stage 610, a bias stage 620, a gain stage 630, and an output stage 640. The bias stage 620 provides current to the single-ended power amplifier 600 to drive all the transistors included in the single-ended power amplifier 600. The current from the bias stage 620 is passed to the input stage 610. In the input stage 610, a first input signal 601-1 and a second input signal 601-2 are input to the input stage 610. Figure 6As shown, input stage 610 can be implemented using various transistors such as Q1, Q2, Q6, Q7, Q10A, Q10B, and Q13, and is configured to measure the differential signal between two input signals 601-1 and 601-2, and pass the differential signal to gain stage 630. In gain stage 630, the differential signal can be amplified with a predetermined gain. In some embodiments, the differential signal can be amplified to a high voltage greater than 100V in gain stage 630. In some embodiments, a high voltage greater than 100V can be achieved by utilizing multiple cascaded transistors operating at lower voltages. Although Figure 6 Not shown, but gain stage 630 may also include phase compensation capacitors to prevent internal oscillations. The amplified differential signal proceeds to output stage 640, which acts as a buffer to prevent the characteristics of the single-ended power amplifier 600 from varying based on load effects (e.g., resistance connected to the output terminals). High current can be provided in output stage 640 to improve the slew rate of the power amplifier. Figure 6 In the output stage 640, a current limiter is also included, comprising transistors Q12 and Q17, to protect the circuitry from high current while increasing the slew rate through the use of high current. For example... Figure 6 As shown, power supply +V S and -V S It is supplied to a single-ended power amplifier circuit, and a single output signal 603 is obtained from the output terminal OUT. The single-ended power amplifier 600 can be integrated into an IC chip.

[0075] Refer again Figure 5The driver system 500 is implemented using a first single-ended power amplifier 515-1 and a second single-ended power amplifier 515-2, each of which constitutes an IC chip. Even with the selection of components with the highest practical precision and extensively optimized PCB design, using individual IC chips inevitably leads to component mismatch. Component mismatch further limits the common-mode rejection ratio (CMRR), resulting in higher noise levels and lower image resolution, and further limits signal linearity, leading to higher image distortion. Multi-chip implementation also leads to increased design complexity and additional circuit conditioning operations, which limits mass production. Multi-chip implementation is also affected by lower design integrity between the two individual chips, and this design integrity makes it difficult to troubleshoot problems caused by mismatch between the two chips. Furthermore, the driver system 500 using pseudo-differential power amplifiers suffers from high noise levels, at least in part due to the low CMRR caused by component mismatch between the two single-ended power amplifiers. Furthermore, because the two IC chips occupy limited space on the PCB, the deflection driver 520 is mounted on a separate PCB from the pattern generator 510, which includes multiple DACs 511-1 and 511-2. This necessitates the installation of additional components (e.g., amplifiers 513 and 514) on the PCB. The longer signal transmission distance caused by using two separate PCBs can also introduce additional noise into the system and thus worsen the noise problem of the driver system 500. Therefore, the driver system 500 does not meet the noise standards required for current and next-generation systems, such as less than 2.5 nV / sqrt(Hz).

[0076] Now for reference Figure 7 This illustrates a driver system architecture with a fully differential power amplifier consistent with embodiments of this disclosure. In some embodiments, the driver system 700 may be... Figure 4 The driver system 700 is configured to receive a deflection signal and generate a high-voltage fully differential drive signal. According to some embodiments of this disclosure, the driver system 700 may include a pattern generator 710 and a deflection driver 720.

[0077] According to some embodiments of this disclosure, pattern generator 710 may include one or more DACs (e.g., DACs 511-1 and 511-2) for converting (one or more) digital deflection signals into (one or more) analog deflection signals. In some embodiments, pattern generator 710 may also include transimpedance amplifiers 512-1 to 512-4 for converting the impedance of analog deflection signals 502-1 to 502-4. As indicated by the same reference numerals, Figure 7The pattern generator 710's DACs 511-1 and 511-2, as well as transimpedance amplifiers 512-1 to 512-4, can be connected with... Figure 5 The pattern generator 510 in the diagram contains DACs 511-1 and 511-2, as well as transresistance amplifiers 512-11 to 512-4, which are the same as or similar. Therefore, for simplicity, details about... Figure 7 The operation and function of the pattern generator 710, DACs 511-1 and 511-2, and transimpedance amplifiers 512-1 to 512-4 are described in an overlapping manner.

[0078] According to some embodiments, the deflection driver 720 may include a fully differential power amplifier 715 configured to receive differential inputs and generate high-voltage differential outputs. For example... Figure 7 As shown, the differential power amplifier 715 can be configured to receive a first superimposed signal 503-1 (e.g., +V). X and +V Y The sum of the two superimposed signals 503-2 (e.g., -V) X and -V Y The sum of the values ​​of the inputs is used as the differential input. In some embodiments, the differential power amplifier 715 can also be configured to output a first superimposed drive signal 704-1 (e.g., +V). OX and +V OY The sum of the two superimposed driving signals 704-2 (e.g., -V) OX and -V OY The sum of these values ​​is used as the difference output. For example... Figure 7 As shown, since the deflection driver 720 is located on the same PCB 701 adjacent to the pattern generator 710, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be provided to the differential power amplifier 715 without the need for an additional low-voltage fully differential amplifier. Furthermore, because the deflection driver 720 is positioned near the generator 710, common-mode noise injected along the path between the deflection driver 720 and the pattern generator 710 can be minimized or reduced.

[0079] In some embodiments, the output of the deflection driver 720 can be segmented before being applied to the corresponding electrode because these outputs are superimposed output signals. For example, the first superimposed drive signal 704-1 can be used to generate two drive signals +V before being applied to the corresponding electrode. OX and +V OY For example, applied to Figure 3C electrode e2 or Figure 4 The drive signal +V of electrode 402 OX and applied to Figure 3B electrode e1 or Figure 4 The driving signal +V of electrode 401 in the middleOY Similarly, the second superimposed drive signal 704-2 can be used to generate two drive signals -V before being applied to the corresponding electrode. OX and -V OY For example, applied to Figure 3C electrode e4 or Figure 4 The drive signal -V of electrode 404 OX and applied to Figure 3C electrode e3 or Figure 4 The drive signal -V of electrode 403 OY .

[0080] Although the driver system 700 has been shown to be configured to generate drive signals for manipulating the beam in both the X and Y directions, it should be understood that the driver system 700 can be configured to generate drive signals for manipulating the beam in only one direction. For example, the driver system 700 can be configured to generate drive signals for manipulating the beam in the X direction. In these implementations, the coordinates of the wafer on the wafer stage can be modified before inputting the first superimposed signal 503-1 and the second superimposed signal 503-2 into the differential power amplifier 715 by comparing the coordinates of the wafer on the wafer stage with the coordinates of the deflector electrodes. For example, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified to generate differential signals representing the actual deflection control signals in the X direction. In some embodiments, the first superimposed signal 503-1 and the second superimposed signal 503-2 can be modified based on the coordinates of the wafer on the wafer stage, the coordinates of the deflector electrodes, and the rotation angle between the wafer coordinates and the deflector electrode coordinates. In these implementations, the output of the differential power amplifier 715 can be a differential drive signal for electrodes controlled to deflect the beam in the X direction, for example... Figure 3C The first pair of electrodes e2 and e4 or Figure 4 The first pair of electrodes 402 and 404. Similarly, in some embodiments, an additional driver system, similar to driver system 700, can be used to generate drive signals to manipulate the beam in the Y direction. In these implementations, the output of the differential power amplifier of the additional driver system can be a differential drive signal for electrodes that are controlled to deflect the beam in the Y direction, for example... Figure 3C The second pair of electrodes e1 and e3 or Figure 4 The second pair of electrodes, 401 and 403.

[0081] Now for reference Figure 8 This illustrates a fully differential power amplifier circuit configuration consistent with embodiments of the present disclosure. In some embodiments, the differential power amplifier circuit 715 may be included in... Figure 7The deflection driver 720 contains a fully differential power amplifier circuit 715. According to some embodiments of this disclosure, the differential power amplifier 715 may include an input stage 610, two bias stages 620 and 820, two gain stages 630 and 830, and two output stages 640 and 840. Similar to... Figure 6 600 single-ended power amplifier Figure 8 The input stage 610, first bias stage 620, first gain stage 630, and first output stage 640 can be configured to generate a first output 603-1 of differential outputs 603-1 and 603-2 in response to differential input signals 601-1 and 601-2. For example, Figure 8 The input stage 610, first bias stage 620, first gain stage 630, and first output stage 640 can be configured to generate a positive output +V by amplifying the differential signal between two input signals 601-1 and 601-2 input to the input stage 610. O Similarly, Figure 8 The input stage 610, the second bias stage 820, the second gain stage 830, and the second output stage 840 can be configured to generate a second output 603-2 of differential outputs 603-1 and 603-2 in response to differential input signals 601-1 and 601-2. For example, Figure 8 The input stage 610, the second bias stage 820, the second gain stage 830, and the second output stage 840 can be configured to generate a negative output -V by amplifying the differential signal between the two input signals 601-1 and 601-2 input to the input stage 610. O As indicated by the same reference numerals in the accompanying drawings, Figure 8 The input stage 610, first bias stage 620, first gain stage 630, and first output stage 640 can be connected with Figure 6 The input stage 610, bias stage 620, gain stage 630, and output stage 640 are the same or similar. Furthermore, as... Figure 6 and Figure 8 As shown, Figure 8 The second bias stage 820, second gain stage 830, and second output stage 840 of the differential power amplifier 715 can be implemented by mirroring and modifying the first bias stage 620, first gain stage 630, and first output stage 640, so that the second bias stage 820, second gain stage 830, and second output stage 840 generate a second output 603-2 with the same absolute value but opposite polarity as the first output signal 603-1. Therefore, as referenced... Figure 6 The two differential outputs 603-1 and 603-2 can be high-voltage differential signals that meet industry requirements (such as greater than 100V).

[0082] According to some embodiments of this disclosure, the differential power amplifier 715 may further include a common-mode control circuit 810. According to some embodiments, the common-mode control circuit 810 may include an error amplifier 811. In some embodiments, the error amplifier 811 may be configured to compare the common-mode voltages of the differential outputs 603-1 and 603-2 with a reference voltage V. REF Compare. For example... Figure 8 As shown, the error amplifier 811 is coupled to differential outputs 603-1 and 603-2 and is configured to receive the common-mode voltages of the two differential outputs 603-1 and 603-2 as feedback inputs via a first input terminal 812. In some embodiments, the common-mode control circuit 810 may further include two resistors 814 and 815. Figure 8 In this configuration, a first resistor 814 is coupled between the first input terminal 812 and the first output terminal +OUT of the error amplifier 811, and a second resistor 815 is coupled between the first output terminal 812 and the second output terminal -OUT of the error amplifier 811. In some embodiments, the first resistor 814 and the second resistor 815 may have the same resistance value, allowing the measurement of the common-mode voltage, which is the median of the two differential output signals 603-1 and 603-2, and its input as a feedback input at the first input terminal 812. Figure 8 As shown, the error amplifier 811 can be configured to receive a reference voltage V via the second input terminal 813. REF As a reference input. According to some embodiments of this disclosure, the error amplifier 811 is configured to compare the feedback input and the reference input, and output the difference 816 between the feedback input and the reference input. Figure 8 As shown, difference 816 is provided back to differential power amplifier 715 to regulate output signals 603-1 and 603-2, thereby canceling out difference 816. For example, output signals 603-1 and 603-2 can be adjusted according to difference 816 such that the common-mode voltage of the two output signals 603-1 and 603-2 can be equal to the reference voltage V. REF In some embodiments, the reference voltage V REF It can be set to the value 0V. For example... Figure 8 As shown, the difference 816 can be provided back to the first gain stage 630 to regulate the first output signal 603-1, and back to the second gain stage 830 to regulate the second output signal 603-2. In some embodiments, when a non-zero value as the difference 816 is provided to the gain stages 630 and 830, the output signals 603-1 and 603-2 can be regulated to cancel the difference. In some embodiments, the common-mode control circuit 810 is a closed-loop feedback circuit and is configured to automatically adjust the output.

[0083] According to some embodiments of this disclosure, the fully differential power amplifier 715 can be manufactured using high-voltage semiconductor manufacturing processes that support voltages greater than 100V. In some embodiments, the fully differential power amplifier 715 can be manufactured using semiconductor materials capable of withstanding high voltages, such as gallium nitride, silicon carbide, etc. In some embodiments, the fully differential power amplifier 715 can be manufactured without utilizing complementary metal-oxide-semiconductor (CMOS), which is typically used for low-voltage devices. In some embodiments, the fully differential power amplifier 715 operating at voltages greater than 100V can be implemented by utilizing multiple cascaded transistors, each operating at a lower voltage. According to some embodiments of this disclosure, the fully differential power amplifier 715 can be integrated into a single IC chip without component mismatch issues between the two separate components. Therefore, the fully differential power amplifier 715 can exhibit improved common-mode rejection ratio (CMSS) without needing to address component mismatch issues. Because the fully differential power amplifier 715 is a true differential amplifier, not a pseudo-differential amplifier, the fully differential amplifier 715 with better component matching can improve linearity, thereby reducing image distortion. In the fully differential power amplifier 715, even-order distortion terms can be eliminated using the fully differential output. (See figure...) Figure 8 As shown, since the fully differential power amplifier 715 is implemented with two differential outputs using a common input stage (e.g., input stage 610), the area occupied by the fully differential amplifier 715 can be reduced compared to two single-ended power amplifiers. Therefore, the fully differential power amplifier 715 can be integrated into a single IC chip, which can be mounted on the same PCB as the pattern generator 710, preventing the need for additional components (such as...) Figure 5 Additional amplifiers 513 and 514 must be included in the driver system 700. This reduction in components and signal transmission distance on the driver system 700 can also be attributed to a reduction in system noise. According to some embodiments of this disclosure, the driver system 700 can meet the noise standards required by current and next-generation systems, such as less than 2.5 nV / sqrt (Hz), while meeting the high-voltage drive signal requirements such as high voltage (greater than 100V), high speed (power bandwidth greater than 1MHz), and slew rate (greater than 500V / µs). If the drive signal is kept below 100V, industry scan rate requirements (e.g., 1.2 gigabits per second) may not be achievable without sacrificing signal quality. For example, 1.2 gigabits per second can be achieved by using a deflector with higher sensitivity when using a drive signal below 100V, which ultimately leads to a decrease in image resolution. Therefore, in this disclosure, a higher voltage level can refer to a voltage level greater than 100V, which can support industry scan rate requirements, such as 1.2 gigabits per second, without sacrificing signal quality.

[0084] Furthermore, according to some embodiments of this disclosure, the driver system 700 can provide greater design integrity and increased circuit component versatility, thereby simplifying PCB design and facilitating future RACK-based deflection driver designs. According to some embodiments of this disclosure, the increased circuit component versatility results in a smaller circuit size required to deliver higher voltages than conventional systems. According to some embodiments of this disclosure, the driver system 700 can provide lower power consumption, leading to simplified thermal design and also helping to achieve higher slew rates. According to some embodiments of this disclosure, the driver system 700 can provide simplified circuit conditioning strategies, thereby improving mass production capabilities. According to some embodiments of this disclosure, the common-mode control circuitry 800 is also integrated into the same IC chip as the fully differential amplifier, which can improve the slew rate compared to implementations with feedback loops in the PCB area.

[0085] Figure 9 This is a flowchart illustrating an exemplary method for operating a deflector driver with a fully differential power amplifier, consistent with embodiments of this disclosure. The steps of method 900 can be performed by a deflector driver system, for example, including a fully differential power amplifier 715. Figure 7 The drive system 700. It should be understood that the method 900 shown can be modified to change the order of the steps and include additional steps.

[0086] In step S910, a fully differential output is generated by a fully differential power amplifier 715. In some embodiments, the fully differential output may have an absolute value greater than 100V. In step S920, the common-mode voltage of the differential output of the differential amplifier is measured by a common-mode control circuit 810. In step S930, the difference between the common-mode voltage and a reference voltage is provided back to the differential amplifier. In some embodiments, this difference may be provided to the gain stage of the differential amplifier. In step S940, the differential output may be adjusted based on this difference, thereby eliminating the difference. In some embodiments, the adjusted fully differential output may be applied to multiple deflector electrodes to influence the charged particle beam of the charged particle inspection device based on the fully differential output.

[0087] A non-transitory computer-readable medium may be provided to store instructions for use by a controller (e.g., Figure 1The processor of controller 109 performs image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, condenser lens adjustment, activation of charged particle sources, beam deflection, and method 900, etc. Common forms of non-transitory media include floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, optical disc read-only memory (CD-ROM), any other optical data storage media, any physical media with a perforated pattern, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), FLASH-EPROM or any other flash memory, non-volatile random access memory (NVRAM), caches, registers, any other memory chips or cartridges, and their networked versions.

[0088] The embodiments may be further described using the following terms: 1. A charged particle inspection device, comprising: A charged particle beam source is configured to generate a primary charged particle beam for sample scanning; The deflector driver includes a fully differential amplifier configured to generate a fully differential output with an absolute value greater than 100V; and Multiple deflector electrodes are coupled to the fully differential output and configured to influence the charged particle beam based on the fully differential output. 2. The device according to Clause 1, wherein the differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V. 3. The device according to clause 1 or 2, wherein the deflector driver further comprises: Multiple digital-to-analog converters (DACs) are used to generate input differential signals for the fully differential amplifier. The plurality of DACs and the fully differential amplifier are mounted on a single printed circuit board. 4. The device according to any one of clauses 1 to 3, wherein the deflector driver further comprises: A common-mode control circuit is configured to measure the common-mode voltage of the fully differential output of the fully differential amplifier and provide the difference between the common-mode voltage and a reference voltage to the fully differential amplifier, such that the fully differential output of the differential amplifier is adjusted based on the difference. The fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip. 5. The device according to any one of clauses 1 to 4, wherein the fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz. 6. The device according to any one of clauses 1 to 5, wherein the fully differential amplifier is configured to operate at a slew rate greater than 500 V / µs. 7. The device according to any one of clauses 1 to 6, wherein the fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt (Hz). 8. A deflector driver for driving a deflector in a charged particle inspection device, the deflector driver comprising: The fully differential amplifier is configured to generate a fully differential output with an absolute value greater than 100V. The fully differential output enables the multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output. 9. The deflector driver according to Clause 8, wherein the fully differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V. 10. The deflector driver according to clause 8 or 9, wherein the deflector driver further comprises: Multiple digital-to-analog converters (DACs) are used to generate input differential signals for the fully differential amplifier. The plurality of DACs and the fully differential amplifier are mounted on a single printed circuit board. 11. The deflector driver according to any one of clauses 8 to 10, wherein the deflector driver further comprises: A common-mode control circuit is configured to measure the common-mode voltage of the fully differential output of the fully differential amplifier and provide the difference between the common-mode voltage and a reference voltage to the fully differential amplifier, such that the fully differential output of the fully differential amplifier is adjusted based on the difference. The fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip. 12. The deflector driver according to any one of clauses 8 to 11, wherein the fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz. 13. The deflector driver according to any one of clauses 8 to 12, wherein the fully differential amplifier is configured to operate at a slew rate greater than 500 V / µs. 14. The deflector driver according to any one of clauses 8 to 13, wherein the fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt (Hz). 15. A method of operating a deflector driver for driving a deflector in a charged particle inspection device, the method comprising: The deflector driver generates a fully differential output with an absolute value greater than 100V through a fully differential amplifier. The common-mode voltage of the fully differential output of the fully differential amplifier is measured by the common-mode control circuit included in the deflector driver; The difference between the common-mode voltage and the reference voltage is provided to the fully differential amplifier via the common-mode control circuit; and The fully differential output of the differential amplifier is adjusted based on the difference, wherein the adjusted fully differential output enables the plurality of deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output, and The fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip. 16. The method described pursuant to Clause 15 further comprises: The input differential signal is generated for the fully differential amplifier by utilizing multiple digital-to-analog converters (DACs) included in the deflector driver. The plurality of DACs and the fully differential amplifier are mounted on a single printed circuit board. 17. The method according to Clause 15 or 16, wherein the fully differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V. 18. The method according to any one of Clauses 15 to 17, wherein the fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz. 19. The method according to any one of Clauses 15 to 18, wherein the fully differential amplifier is configured to operate at a slew rate greater than 500 V / µs. 20. The method according to any one of clauses 15 to 19, wherein the fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt (Hz). 21. A deflector driver assembly, comprising: A fully differential amplifier is configured to generate a fully differential output with an absolute value greater than 100V; and A common-mode control circuit is configured to measure the common-mode voltage of the fully differential output of the fully differential amplifier and provide the difference between the common-mode voltage and a reference voltage to the fully differential amplifier. The fully differential amplifier is further configured to adjust its fully differential output based on the difference, the adjusted fully differential output enabling multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output. The fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip. 22. The deflector driver assembly according to clause 21, further comprising: Multiple digital-to-analog converters (DACs) are configured to generate input differential signals for the fully differential amplifier. The plurality of DACs and the fully differential amplifier are mounted on a single printed circuit board. 23. The deflector driver assembly according to clause 21 or 22, wherein the fully differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V. 24. The deflector driver assembly according to any one of clauses 21 to 23, wherein the fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz. 25. The deflector driver assembly according to any one of clauses 21 to 24, wherein the fully differential amplifier is configured to operate at a slew rate greater than 500 V / µs. 26. The deflector driver assembly according to any one of clauses 21 to 25, wherein the fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt (Hz).

[0089] The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in the diagrams may represent certain arithmetic or logical operations that can be implemented using hardware such as electronic circuits. A block may also represent a code module, segment, or portion comprising one or more executable instructions for implementing a specified logical function. It should be understood that in some alternative implementations, the functions indicated in the blocks may not appear in the order shown in the figures. For example, depending on the function involved, two blocks shown consecutively may be executed or implemented substantially simultaneously, or the two blocks may sometimes be executed in reverse order. Some blocks may also be omitted. It should also be understood that each block in the block diagram, and combinations of blocks, can be implemented by a system based on dedicated hardware that performs the specified function or action, or by a combination of dedicated hardware and computer instructions.

[0090] It should be understood that the embodiments of this disclosure are not limited to the exact constructions described above and shown in the accompanying drawings, but various modifications and changes can be made without departing from its scope. This disclosure has been described in conjunction with various embodiments, and other embodiments of the invention will become apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

Claims

1. A charged particle inspection device, comprising: A charged particle beam source is configured to generate a primary charged particle beam for sample scanning; Deflector driver, including a fully differential amplifier configured to generate a fully differential output with an absolute value greater than 100V; as well as Multiple deflector electrodes are coupled to the fully differential output and configured to influence the charged particle beam based on the fully differential output.

2. The device of claim 1, wherein the differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V.

3. The device of claim 1, wherein the deflector driver further comprises: Multiple digital-to-analog converters (DACs) are used to generate input differential signals for the fully differential amplifier. The plurality of DACs and the fully differential amplifier are mounted on a single printed circuit board.

4. The device of claim 1, wherein the deflector driver further comprises: A common-mode control circuit is configured to measure the common-mode voltage of the fully differential output of the fully differential amplifier and provide the difference between the common-mode voltage and a reference voltage to the fully differential amplifier, such that the fully differential output of the differential amplifier is adjusted based on the difference. The fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

5. The device of claim 1, wherein the fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz.

6. The device of claim 1, wherein the fully differential amplifier is configured to operate at a slew rate greater than 500 V / µs.

7. The device of claim 1, wherein the fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt (Hz).

8. A deflector driver for driving a deflector in a charged particle inspection device, the deflector driver comprising: The fully differential amplifier is configured to generate a fully differential output with an absolute value greater than 100V. The fully differential output enables the multiple deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output.

9. The deflector driver of claim 8, wherein the fully differential amplifier is manufactured using a high-voltage semiconductor manufacturing process that supports voltage levels greater than 100V.

10. The deflector driver of claim 8, wherein the deflector driver further comprises: Multiple digital-to-analog converters (DACs) are used to generate input differential signals for the fully differential amplifier. The plurality of DACs and the fully differential amplifier are mounted on a single printed circuit board.

11. The deflector driver of claim 8, wherein the deflector driver further comprises: A common-mode control circuit is configured to measure the common-mode voltage of the fully differential output of the fully differential amplifier and provide the difference between the common-mode voltage and a reference voltage to the fully differential amplifier, such that the fully differential output of the fully differential amplifier is adjusted based on the difference. The fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

12. The deflector driver of claim 8, wherein the fully differential amplifier is configured to operate with a power bandwidth greater than 1 MHz.

13. The deflector driver of claim 8, wherein the fully differential amplifier is configured to operate at a slew rate greater than 500 V / µs.

14. The deflector driver of claim 8, wherein the fully differential amplifier is configured to operate at a noise level of less than 2.5 nV / sqrt (Hz).

15. A method of operating a deflector driver for driving a deflector in a charged particle inspection device, the method comprising: The deflector driver generates a fully differential output with an absolute value greater than 100V through a fully differential amplifier. The common-mode voltage of the fully differential output of the fully differential amplifier is measured by the common-mode control circuit included in the deflector driver; The difference between the common-mode voltage and the reference voltage is provided to the fully differential amplifier through the common-mode control circuit. as well as The fully differential output of the differential amplifier is adjusted based on the difference, wherein the adjusted fully differential output enables the plurality of deflector electrodes of the deflector to influence the charged particle beam of the charged particle inspection device based on the fully differential output, and The fully differential amplifier and the common-mode control circuit are integrated into a single integrated circuit (IC) chip.

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