Display panel, preparation method thereof and display device

Abstract

The display panel comprises a substrate and a plurality of light-emitting devices, and the light-emitting devices are located on the same side of the substrate. The plurality of light-emitting devices comprise a first light-emitting device and a second light-emitting device, the first light-emitting device emits first color light, and the second light-emitting device emits second color light; the first light-emitting device comprises a first electrode, a first hole transport layer, a first light-emitting layer, a first electron transport layer and a second electrode which are arranged in a stacked mode in the first direction perpendicular to the substrate and away from the substrate. The second light-emitting device comprises a third electrode, a second electron transport layer, a second light-emitting layer, a second hole transport layer and a fourth electrode which are stacked; in the first direction, the size between the first light-emitting device and the substrate is approximately equal to the size between the second light-emitting device and the substrate.

Description

Display panel, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel, a preparation method thereof and a display device. BACKGROUND

[0002] Quantum dot light emitting diodes (QLED) using quantum dots (QDs) as light emitting centers have become a potential next generation light emitting device due to the characteristics of size-adjustable light emission, narrow half-peak width, high photoluminescence efficiency and thermal stability of QDs.

[0003] SUMMARY

[0004] In one aspect, a display panel is provided, which includes a substrate and a plurality of light emitting devices located on the same side of the substrate, the plurality of light emitting devices including a first light emitting device configured to emit first color light and a second light emitting device configured to emit second color light, wherein, along a first direction perpendicular to the substrate and away from the substrate, the first light emitting device includes a first electrode, a first hole transport layer, a first light emitting layer, a first electron transport layer and a second electrode stacked, and the second light emitting device includes a third electrode, a second electron transport layer, a second light emitting layer, a second hole transport layer and a fourth electrode stacked, and in the first direction, a size between the first light emitting device and the substrate is substantially equal to a size between the second light emitting device and the substrate.

[0005] In some embodiments, the plurality of light emitting devices further includes a third light emitting device configured to emit third color light, wherein a film layer structure of the third light emitting device is the same as any one of the first light emitting device and the second light emitting device, the third light emitting device includes a fifth electrode, a third electron transport layer, a third light emitting layer, a third hole transport layer and a sixth electrode, and in the first direction, a size between the third light emitting device and the substrate is substantially equal to a size between the first light emitting device and the substrate.

[0006] In some embodiments, the film layer structure of the third light emitting device is the same as that of the first light emitting device, the third electron transport layer and the first electron transport layer are arranged in the same layer; along the first direction, the size between the first electron transport layer and the substrate is substantially equal to the size between the third electron transport layer and the substrate; the size between the second electron transport layer and the substrate is smaller than the size between the first electron transport layer and the substrate. Or, the film layer structure of the third light emitting device is the same as that of the second light emitting device, the third electron transport layer and the second electron transport layer are arranged in the same layer; along the first direction, the size between the second electron transport layer and the substrate is substantially equal to the size between the third electron transport layer and the substrate; the size between the first electron transport layer and the substrate is greater than the size between the second electron transport layer and the substrate.

[0007] In some embodiments, the first electron transport layer, the second electron transport layer and the third electron transport layer are arranged in the same layer.

[0008] In some embodiments, the material of the first electron transport layer, the material of the second electron transport layer and the material of the third electron transport layer are the same, and the material of the first electron transport layer, the material of the second electron transport layer and the material of the third electron transport layer are selected from at least one of zinc oxide, tin oxide, titanium oxide, gallium oxide, aluminum oxide, zinc gallium oxide, zinc tin oxide, zinc titanium oxide, zinc aluminum oxide, tin gallium oxide and zinc tin gallium oxide.

[0009] In some embodiments, the film layer structure of the third light emitting device is the same as that of the first light emitting device, the third hole transport layer and the first hole transport layer are arranged in the same layer; along the first direction, the size between the first hole transport layer and the substrate is substantially equal to the size between the third hole transport layer and the substrate; the size between the second hole transport layer and the substrate is greater than the size between the first hole transport layer and the substrate. Or, the film layer structure of the third light emitting device is the same as that of the second light emitting device, the third hole transport layer and the second hole transport layer are arranged in the same layer; along the first direction, the size between the second hole transport layer and the substrate is substantially equal to the size between the third hole transport layer and the substrate; the size between the first hole transport layer and the substrate is smaller than the size between the second hole transport layer and the substrate.

[0010] In some embodiments, the first hole transport layer, the second hole transport layer and the third hole transport layer are arranged in the same layer.

[0011] In some embodiments, the first light-emitting device further comprises a first hole injection layer between the first electrode and the first hole transport layer; the second light-emitting device further comprises a second hole injection layer between the second light-emitting layer and the fourth electrode; and the third light-emitting device further comprises a third hole injection layer between the third light-emitting layer and the sixth electrode.

[0012] In some embodiments, the third light-emitting device has the same film layer structure as the first light-emitting device, and the third hole injection layer and the first hole injection layer are disposed in the same layer; along the first direction, the size between the first hole injection layer and the substrate is substantially equal to the size between the third hole injection layer and the substrate; and the size between the second hole injection layer and the substrate is greater than the size between the first hole injection layer and the substrate. Or, the third light-emitting device has the same film layer structure as the second light-emitting device, and the third hole injection layer and the second hole injection layer are disposed in the same layer; along the first direction, the size between the second hole injection layer and the substrate is substantially equal to the size between the third hole injection layer and the substrate; and the size between the first hole injection layer and the substrate is less than the size between the second hole injection layer and the substrate.

[0013] In some embodiments, the first light-emitting device further comprises a first hole injection layer between the first electrode and the first hole transport layer; the second light-emitting device further comprises a second hole injection layer between the second light-emitting layer and the fourth electrode; and the third light-emitting device further comprises a third hole injection layer between the third light-emitting layer and the sixth electrode; wherein the first hole injection layer, the second hole injection layer, and the third hole injection layer are disposed in the same layer.

[0014] In some embodiments, the material of the first hole injection layer, the material of the second hole injection layer, and the material of the third hole injection layer are the same, and the material of the first hole injection layer, the material of the second hole injection layer, and the material of the third hole injection layer are selected from at least one of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid), 4,4',4"-tris[2-naphthylphenylamino]triphenylamine, 4,4',4"-tris(N-3-methylphenyl-N-phenylamino)triphenylamine, molybdenum trioxide, copper phthalocyanine, tungsten oxide, nickel oxide, and vanadium oxide.

[0015] In some embodiments, the display panel further comprises: a pixel defining layer, the pixel defining layer is provided with a plurality of openings, the plurality of light emitting devices are arranged in one-to-one correspondence in the plurality of openings; wherein the pixel defining layer comprises: a main body part and an auxiliary part located on the side of the main body part away from the substrate; the material of the main body part comprises: a first organic material, and the material of the auxiliary part comprises: at least one of an inorganic material and a second organic material.

[0016] In some embodiments, the first light emitting device comprises: a first hole injection layer, the second light emitting device comprises: a second hole injection layer; the third light emitting device comprises: a third hole injection layer; wherein the material of the auxiliary part is the same as the material of at least one of the first hole injection layer, the first hole transport layer, the first electron transport layer, the second hole injection layer, the second hole transport layer, the second electron transport layer, the third hole injection layer, the third hole transport layer and the third electron transport layer.

[0017] In some embodiments, the second electrode, the fourth electrode and the sixth electrode are connected.

[0018] In some embodiments, the film layer structure of the third light emitting device is the same as that of the second light emitting device, the fourth electrode and the sixth electrode are connected, and the fourth electrode and the sixth electrode are both spaced apart from the second electrode. Or, the film layer structure of the third light emitting device is the same as that of the first light emitting device, the second electrode and the sixth electrode are connected, and the second electrode and the sixth electrode are both spaced apart from the fourth electrode.

[0019] In some embodiments, in the case where the film layer structure of the third light emitting device is the same as that of the second light emitting device, the fourth electrode and the sixth electrode are arranged in the same layer and are arranged in different layers from the second electrode. Or, in the case where the film layer structure of the third light emitting device is the same as that of the first light emitting device, the second electrode and the sixth electrode are arranged in the same layer and are arranged in different layers from the fourth electrode.

[0020] In some embodiments, in the case where the film layer structure of the third light emitting device is the same as that of the second light emitting device, in the orthographic projection onto the substrate, the film layer in which the second electrode is located covers the film layers in which the fourth electrode and the sixth electrode are located. Or, in the case where the film layer structure of the third light emitting device is the same as that of the first light emitting device, in the orthographic projection onto the substrate, the film layer in which the fourth electrode is located covers the film layers in which the second electrode and the sixth electrode are located.

[0021] In some embodiments, the second electrode, the fourth electrode and the sixth electrode are arranged in the same layer.

[0022] In some embodiments, when the third light emitting device has the same film layer structure as the second light emitting device, the fourth electrode and the sixth electrode are arranged alternately along a second direction, and a plurality of the second electrodes are arranged along the second direction; and the rows in which the fourth electrode and the sixth electrode are arranged are arranged alternately along a third direction with the rows in which a plurality of the second electrodes are arranged. Or, when the third light emitting device has the same film layer structure as the first light emitting device, the second electrode and the sixth electrode are arranged alternately along a second direction, and a plurality of the fourth electrodes are arranged along the second direction; and the rows in which the second electrode and the sixth electrode are arranged are arranged alternately along a third direction with the rows in which a plurality of the fourth electrodes are arranged. Wherein, the second direction and the third direction are parallel to the plane in which the substrate is arranged, and the second direction and the third direction intersect. In some embodiments, the display panel further comprises: a first pixel circuit and a second pixel circuit, the first pixel circuit is configured to be electrically connected with the first light emitting device, the first pixel circuit is used to drive the first light emitting device to emit first color light, the second pixel circuit is configured to be electrically connected with the second light emitting device, the second pixel circuit is used to drive the second light emitting device to emit second color light; wherein, the first light emitting device is located on the side of the first pixel circuit away from the substrate, and the second light emitting device is located on the side of the second pixel circuit away from the substrate.

[0023] In some embodiments, the first pixel circuit comprises: a first drive transistor, a gate of the first drive transistor is electrically connected with a first node, a source of the first drive transistor is electrically connected with a first voltage signal terminal, and a drain of the first drive transistor is electrically connected with a first electrode of the first light emitting device; a second electrode of the first light emitting device is electrically connected with a second voltage signal terminal; the voltage of the first voltage signal terminal is higher than the voltage of the second voltage signal terminal.

[0024] In some embodiments, the first drive transistor is a P-type transistor.

[0025] In some embodiments, the second pixel circuit comprises: a second drive transistor, a gate of the second drive transistor is electrically connected with a second node, a source of the second drive transistor is electrically connected with a third voltage signal terminal, and a drain of the second drive transistor is electrically connected with a third electrode of the second light emitting device; a fourth electrode of the second light emitting device is electrically connected with a fourth voltage signal terminal; the voltage of the third voltage signal terminal is less than the voltage of the fourth voltage signal terminal.

[0026] In some embodiments, the second drive transistor is an N-type transistor.

[0027] In some embodiments, in the case that the display panel comprises a third light-emitting device, the display panel further comprises: a third pixel circuit configured to be electrically connected with the third light-emitting device, the third pixel circuit being configured to drive the third light-emitting device to emit light of a third color; and the third light-emitting device is located on a side of the third pixel circuit away from the substrate.

[0028] In some embodiments, the film layer structure of the third light-emitting device is the same as the film layer structure of the first light-emitting device, and the third pixel circuit comprises: a third drive transistor, a gate of the third drive transistor being electrically connected with a third node, a source of the third drive transistor being electrically connected with a first voltage signal terminal, and a drain of the third drive transistor being electrically connected with a fifth electrode of the third light-emitting device, and a sixth electrode of the third light-emitting device being electrically connected with a second voltage signal terminal. Or, the film layer structure of the third light-emitting device is the same as the film layer structure of the second light-emitting device, and the third pixel circuit comprises: a fourth drive transistor, a gate of the fourth drive transistor being electrically connected with a seventh node, a source of the fourth drive transistor being electrically connected with a third voltage signal terminal, and a drain of the fourth drive transistor being electrically connected with the fifth electrode of the third light-emitting device, and the sixth electrode of the third light-emitting device being electrically connected with a fourth voltage signal terminal.

[0029] In some embodiments, the third drive transistor is a P-type transistor; and / or, the fourth drive transistor is an N-type transistor.

[0030] In another aspect, a method for manufacturing a display panel is provided, the method comprising: providing a substrate; forming a first electrode and a third electrode on the same side of the substrate; forming, on a side of the first electrode away from the substrate, a first hole transport layer, a first light-emitting layer, a first electron transport layer, and a second electrode in sequence to obtain a first light-emitting device configured to emit light of a first color; forming, on a side of the third electrode away from the substrate, a second electron transport layer, a second light-emitting layer, a second hole transport layer, and a fourth electrode in sequence to obtain a second light-emitting device configured to emit light of a second color, thereby forming a display panel; and wherein, along a first direction perpendicular to the substrate and away from the substrate, a dimension between the first light-emitting device and the substrate is substantially equal to a dimension between the second light-emitting device and the substrate.

[0031] In yet another aspect, a display device is provided, the display device comprising: the display panel according to any one of the above embodiments; and the display device further comprising: a driving chip configured to drive the display panel to display. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0033] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0034] FIG. 2 is a structural diagram of a display panel according to some embodiments;

[0035] FIG. 3 is another structural diagram of a display panel according to some embodiments;

[0036] FIG. 4A is yet another structural diagram of a display panel according to some embodiments;

[0037] FIG. 4B is yet another structural diagram of a display panel according to some embodiments;

[0038] FIG. 5 is yet another structural diagram of a display panel according to some embodiments;

[0039] FIG. 6 is a structural diagram of a top electrode and a bottom electrode of a display panel according to some embodiments;

[0040] FIG. 7 is another structural diagram of a top electrode and a bottom electrode of a display panel according to some embodiments;

[0041] FIG. 8 is yet another structural diagram of a display panel according to some embodiments;

[0042] FIG. 9 is yet another structural diagram of a top electrode and a bottom electrode of a display panel according to some embodiments;

[0043] FIG. 10 is yet another structural diagram of a display panel according to some embodiments;

[0044] FIG. 11 is yet another structural diagram of a top electrode and a bottom electrode of a display panel according to some embodiments;

[0045] FIG. 12 is yet another structural diagram of a top electrode and a bottom electrode of a display panel according to some embodiments;

[0046] FIG. 13 is a structural diagram of a first pixel circuit according to some embodiments;

[0047] FIG. 14 is another structural diagram of a display device according to some embodiments;

[0048] FIG. 15 is a timing diagram of a pixel circuit according to some embodiments;

[0049] FIG. 16 is a structure diagram of a second pixel circuit according to some embodiments;

[0050] FIG. 17 is another structure diagram of a second pixel circuit according to some embodiments;

[0051] FIG. 18 is yet another structure diagram of a display panel according to some embodiments;

[0052] FIG. 19 is another structure diagram of a first pixel circuit according to some embodiments;

[0053] FIG. 20 is yet another structure diagram of a second pixel circuit according to some embodiments;

[0054] FIG. 21 is yet another structure diagram of a second pixel circuit according to some embodiments;

[0055] FIG. 22 is yet another structure diagram of a first pixel circuit according to some embodiments;

[0056] FIG. 23 is another timing diagram of a pixel circuit according to some embodiments;

[0057] FIGS. 24-26 are driving flow diagrams of a first pixel circuit according to some embodiments;

[0058] FIG. 27 is an equivalent circuit diagram of a first pixel circuit from a first reset transistor, a capacitor to a fourth node according to some embodiments;

[0059] FIG. 28 is an equivalent circuit diagram of a first pixel circuit from a first reset transistor, a capacitor, a first driving transistor to a sixth node according to some embodiments;

[0060] FIG. 29 is a driving flow diagram of a first pixel circuit according to some embodiments;

[0061] FIG. 30 is a structure diagram of a first compensation circuit according to some embodiments;

[0062] FIG. 31 is a structure diagram of a second compensation circuit according to some embodiments;

[0063] FIG. 32 is a structure diagram of a third pixel circuit according to some embodiments;

[0064] FIG. 33 is another structure diagram of a third pixel circuit according to some embodiments;

[0065] FIG. 34 is a flow diagram of a method for manufacturing a display panel according to some embodiments;

[0066] FIG. 35 is another flow diagram of a method for manufacturing a display panel according to some embodiments;

[0067] FIGS. 36-42 are structural diagrams of respective steps of a preparation method of a display panel according to some embodiments;

[0068] FIG. 43 is another flowchart of a preparation method of a display panel according to some embodiments;

[0069] FIGS. 44-49 are another structural diagrams of respective steps of a preparation method of a display panel according to some embodiments. DETAILED DESCRIPTION

[0070] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0071] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, are used in an open, inclusive sense, that is, as “including, but not limited to”. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to indicate a particular feature, structure, material, or characteristic that is included in at least one embodiment of the present disclosure. The illustrative representations of the above terms do not necessarily indicate a same embodiment or example. In addition, a particular feature, structure, material or characteristic can be included in any suitable manner in any one or more embodiments or examples.

[0072] Hereinafter, the terms “first” and “second” are used only for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of “a plurality of” is two or more, unless otherwise specified.

[0073] In describing some embodiments, "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either physical or electrical contact with each other, even at a distance. As will be apparent, "a" or "an" can be used herein to refer to one or more than one (i.e., to "one or more") of the referenced material or object. The disclosure presented herein is not intended to be limited to the particular embodiments described.

[0074] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0075] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0076] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the recited value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0077] As used herein, "parallel," "perpendicular," and "equal" include the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable deviation range of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable deviation range of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable deviation range of, for example, less than or equal to 5% of either of the two quantities being compared.

[0078] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0079] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have jagged edges. Thus, the regions illustrated in the figures are schematic and not drawn to scale. The same should be understood with regard to angles, etc. as illustrated in the figures.

[0080] As shown in FIG. 1, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays both motion (e.g., video) and fixed (e.g., still image) and both text and images. More specifically, embodiments are contemplated to be implemented in or in connection with a variety of electronic devices, such as (but not limited to) mobile telephones (e.g., cell phones), wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projections, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like. The display device 1000 is schematically depicted in FIG. 1 as a mobile telephone.

[0081] Exemplarily, the display device 1000 can be an electroluminescent display device or a photoluminescent display device. In the case that the display device 1000 is an electroluminescent display device, the electroluminescent display device can be an organic electroluminescent display device (OLED) or a quantum dot electroluminescent display device (QLED). In the case that the display device 1000 is a photoluminescent display device, the photoluminescent display device can be a quantum dot photoluminescent display device. Hereinafter, some embodiments of the present disclosure are schematically described by taking the display device 1000 as a QLED display device as an example, but the embodiments of the present disclosure include but are not limited to this, and any other display device can also be considered as long as the same technical idea is applied.

[0082] Please continue to refer to FIG. 1, the display device 1000 described above comprises a display panel 100.

[0083] In some embodiments, as shown in FIG. 2, the display panel 100 comprises a substrate 20, and a pixel defining layer 50 and a plurality of light emitting devices 10 located on one side of the substrate 20. The pixel defining layer 50 has a plurality of openings K, and the plurality of light emitting devices 10 can be arranged one-to-one with the plurality of openings K.

[0084] For example, the plurality of light emitting devices 10 comprises a first light emitting device 101, a second light emitting device 102, and a third light emitting device 103. The first light emitting device 101 is configured to emit one of red light, green light, and blue light, the second light emitting device 102 is configured to emit another of red light, green light, and blue light, and the third light emitting device 103 is configured to emit the last one of red light, green light, and blue light, so as to realize full-color display of the display panel 100.

[0085] In some examples, in order to facilitate the preparation of the display panel 100, the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 are simultaneously upright light emitting devices, or the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 are simultaneously inverted light emitting devices.

[0086] As shown in FIG. 2, taking the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 as upright light emitting devices as an example. The first light emitting device 101 comprises a first electrode 11, a first hole transport layer 14, a first light emitting layer 13, a first electron transport layer 15, and a second electrode 12, which are arranged in a stack along a first direction Y perpendicular to the substrate 20 and away from the substrate 20; the second light emitting device 102 comprises a third electrode 21, a second hole transport layer 24, a second light emitting layer 23, a second electron transport layer 25, and a fourth electrode 22, which are arranged in a stack along the first direction Y perpendicular to the substrate 20 and away from the substrate 20; and the third light emitting device 103 comprises a fifth electrode 31, a third hole transport layer 34, a third light emitting layer 33, a third electron transport layer 35, and a sixth electrode 32, which are arranged in a stack along the first direction Y perpendicular to the substrate 20 and away from the substrate 20.

[0087] The first electrode 11, the third electrode 21, and the fifth electrode 31 are anodes, and the second electrode 12, the fourth electrode 22, and the sixth electrode 32 are cathodes. The first electrode 11, the third electrode 21, and the fifth electrode 31 can be referred to as bottom electrodes 202, and the second electrode 12, the fourth electrode 22, and the sixth electrode 32 can be referred to as top electrodes 203.

[0088] However, the inventors found that the performance (e.g., including luminous efficiency and lifetime) of the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103 is not the same when the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103 are in the structure of the upright light emitting device or the inverted light emitting device.

[0089] Therefore, when the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103 are in the structure of the upright light emitting device or the inverted light emitting device, the performance of the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103 cannot be optimal at the same time, thereby affecting the performance of the display panel 100.

[0090] In some examples, as shown in FIG. 2, in order to facilitate the preparation of the functional layer, for example, the functional layer includes the first hole transport layer 14, the second hole transport layer 24, the third hole transport layer 34, the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35, the first hole transport layer 14, the second hole transport layer 24 and the third hole transport layer 34 are arranged in the same layer, and the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35 are arranged in the same layer.

[0091] In the present disclosure, the "A and B arranged in the same layer" means that A and B are formed at the same time by the same patterning process. That is, the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35 are formed at the same time by the same patterning process, so that the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35 have the same material and the same thickness.

[0092] However, in order to optimize the performance of the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103, the functional layer of each of the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103 is not the same.

[0093] Therefore, when the functional layer of the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103 is the same, the performance of the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103 cannot be optimal at the same time, thereby affecting the performance of the display panel 100.

[0094] Based on this, as shown in FIG. 3, the display panel 100 provided by the embodiments of the present disclosure includes a substrate 20 and a plurality of light emitting devices 10 located on the same side of the substrate 20, and the plurality of light emitting devices 10 include a first light emitting device 101 configured to emit first color light and a second light emitting device 102 configured to emit second color light.

[0095] For example, the substrate 20 can be an inorganic material, an organic material, a silicon wafer, a composite material layer, or the like. The inorganic material can be glass, metal, or the like; and the organic material can be polycarbonate, polymethyl methacrylate, polyethylene terephthalate, polyethylene naphthalate, polyamide, polyether sulfone, or a combination thereof, or the like.

[0096] For example, the first color light is one of red light, green light, and blue light, and the second color light is another one of the red light, the green light, and the blue light.

[0097] In some embodiments, as shown in FIG. 3, the first light emitting device 101 includes a first electrode 11, a first hole transport layer 14, a first light emitting layer 13, a first electron transport layer 15, and a second electrode 12 stacked along a first direction Y perpendicular to the substrate 20 and away from the substrate 20. The first electrode 11 is an anode, and the second electrode 12 is a cathode.

[0098] It should be noted that the "stacked" can include sequential stacking, or can only represent a relative position relationship, and there can be other film layers between different film layers.

[0099] For example, the first light emitting device 101 further includes a first hole injection layer 16 located between the first electrode 11 and the first hole transport layer 14.

[0100] For example, the second light emitting device 102 includes a third electrode 21, a second electron transport layer 25, a second light emitting layer 23, a second hole transport layer 24, and a fourth electrode 22 stacked along a first direction Y perpendicular to the substrate 20 and away from the substrate 20. The third electrode 21 is a cathode, and the fourth electrode 22 is an anode.

[0101] For example, the second light emitting device 102 further includes a second hole injection layer 26 located between the second hole transport layer 24 and the fourth electrode 22.

[0102] That is, the first light emitting device 101 is a light emitting device with a normal structure (referred to as a normal light emitting device), and the second light emitting device 102 is a light emitting device with an inverted structure (referred to as an inverted light emitting device).

[0103] The display panel 100 of the embodiments of the present disclosure includes both the upright light emitting device and the inverted light emitting device, so that the light emitting device 10 emitting different color light can have higher light emitting efficiency and longer service life in the state corresponding to the structure of the light emitting device 10 emitting different color light having higher light emitting efficiency and longer service life. In addition, the functional layer of the upright light emitting device and the inverted light emitting device can be arranged respectively, so that the functional layer and the light emitting layer (including the first light emitting layer 13, the second light emitting layer 23 and the third light emitting layer 33) of the light emitting device 10 have better energy level matching, which is conducive to the transmission of carriers (electrons and holes), and can improve the light emitting efficiency and the service life of each light emitting device 10, so as to improve the display effect and the service life of the display panel 100.

[0104] For example, the material of the light emitting layer includes quantum dot material, for example, the quantum dot material includes at least one of CdS, CdSe, ZnSe, ZnTeSe, InP, PbS, CsPbCl3, CsPbBr3, CsPbI3, CdS / ZnS, CdSe / ZnS, ZnSe, ZnSeTe, InP / ZnS, PbS / ZnS, CsPbCl3 / ZnS, CsPbBr3 / ZnS, CsPbI3 / ZnS, CdS / ZnSeS / ZnS, CdSe / ZnSeS / ZnS, ZnSe / ZnSeS / ZnS, ZnSeTe / ZnSeS / ZnS, InP / ZnS, PbS / ZnS, CsPbCl3 / ZnS, CsPbBr3 / ZnS and CsPbI3 / ZnS, and the embodiments of the present disclosure are not limited thereto.

[0105] It should be noted that in the embodiments of the present disclosure, the circular quantum dot is only an example of the shape of the quantum dot, and is not a limitation on the shape of the quantum dot. The shape of the quantum dot includes a spherical shape, an ellipsoidal shape, a polyhedral shape, a rod shape, a cross shape and a ring shape, etc.

[0106] In some examples, as shown in FIG. 3, in the first direction Y, the size D1 between the first light emitting device 101 and the substrate 20 is substantially equal to the size D2 between the second light emitting device 102 and the substrate 20, i.e. d1≈d2.

[0107] It can also be understood that the first light emitting device 101 and the second light emitting device 102 are located on the same plane.

[0108] Exemplarily, the substrate 20 and the plurality of light emitting devices 10 are provided with a pixel circuit layer 60, the pixel circuit layer 60 comprising a plurality of pixel circuits 61 for driving the light emitting devices 10 to emit light. That is, the first light emitting device 101 and the second light emitting device 102 are both located on the same plane away from the substrate 20 on the side of the pixel circuit layer 60, which is conducive to the preparation of the first light emitting device 101 and the second light emitting device 102. For details, refer to the description of the preparation method of the display panel, which will not be described here.

[0109] Exemplarily, the size D1 of the first light emitting device 101 and the substrate 20 in the first direction Y can be the distance between the first electrode 11 and the substrate 20 in the first direction Y. The size D2 of the second light emitting device 102 and the substrate 20 in the first direction Y can be the distance between the third electrode 21 and the substrate 20 in the first direction Y.

[0110] In some embodiments, as shown in FIG. 3, the plurality of light emitting devices 10 further comprises a third light emitting device 103 configured to emit third color light; the film layer structure of the third light emitting device 103 is the same as that of any one of the first light emitting device 101 and the second light emitting device 102, and the third light emitting device 103 comprises a fifth electrode 31, a third electron transport layer 35, a third light emitting layer 33, a third hole transport layer 34 and a sixth electrode 32.

[0111] Exemplarily, the third light emitting device 103 further comprises a third hole injection layer 36 located between the third hole transport layer 34 and the sixth electrode 32.

[0112] That is, the third light emitting device 103 is any one of an upright light emitting device and an inverted light emitting device. For example, when the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101, the third light emitting device 103 comprises the fifth electrode 31, the third hole transport layer 34, the third light emitting layer 33, the third electron transport layer 35 and the sixth electrode 32 stacked along the first direction Y. For example, when the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102, the third light emitting device 103 comprises the fifth electrode 31, the third electron transport layer 35, the third light emitting layer 33, the third hole transport layer 34 and the sixth electrode 32 stacked along the first direction Y.

[0113] Exemplarily, the first color light is one of red light, green light and blue light, the second color light is another one of red light, green light and blue light, and the third color light is the last one of red light, green light and blue light. The arrangement of the plurality of light emitting devices 10 comprising the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103 can realize full-color display of the display panel 100.

[0114] Since the third light emitting device 103 can be any one of a normal light emitting device and an inverted light emitting device, the third light emitting device 103 can be arranged according to a structure corresponding to a case where the third light emitting device 103 has a higher light emitting efficiency and a longer service life, so as to improve the display effect and the service life of the display panel 100.

[0115] In some examples, as shown in FIG. 3, in the first direction Y, the size D3 between the third light emitting device 103 and the substrate 20 is substantially equal to the size D1 between the first light emitting device 101 and the substrate 20, i.e., D1≈D3.

[0116] For example, the size D3 of the third light emitting device 103 and the substrate 20 in the first direction Y can be the distance between the fifth electrode 31 and the substrate 20 in the first direction Y.

[0117] As described above with respect to the size D1 between the first light emitting device 101 and the substrate 20 and the size D2 between the second light emitting device 102 and the substrate 20 in the first direction Y being substantially equal, in the first direction Y, the size D3 between the third light emitting device 103 and the substrate 20, the size D1 between the first light emitting device 101 and the substrate 20, and the size D2 between the second light emitting device 102 and the substrate 20 are substantially equal, i.e., D1≈D2≈D3.

[0118] It can also be understood that the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 are located on the same plane. That is, the plurality of light emitting devices 10 are located on the same plane on the side of the pixel circuit layer 60 away from the substrate 20, so as to facilitate the preparation of the plurality of light emitting devices 10. For specific content, refer to the description of the preparation method of the display panel, which will not be described here.

[0119] In some embodiments, as shown in FIG. 3, the third light emitting device 103 is an inverted light emitting device, and the third light emitting device 103 includes a fifth electrode 31, a third electron transport layer 35, a third light emitting layer 33, a third hole transport layer 34, a third hole injection layer, and a sixth electrode 32 arranged in a stack in the first direction Y. The fifth electrode 31 is a cathode, and the sixth electrode 32 is an anode.

[0120] In some examples, as shown in FIG. 4A, the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102, and the third electron transport layer 35 and the second electron transport layer 25 are arranged in the same layer; along the first direction Y, the size D6 between the second electron transport layer 25 and the substrate 20 is substantially equal to the size D7 between the third electron transport layer 35 and the substrate 20, i.e. D6≈D7; the size D8 between the first electron transport layer 15 and the substrate 20 is greater than the size D6 between the second electron transport layer 25 and the substrate 20, i.e. D8>D6.

[0121] In some examples, as shown in FIG. 4B, the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101, and the third electron transport layer 35 and the first electron transport layer 15 are arranged in the same layer; along the first direction Y, the size D8 between the first electron transport layer 15 and the substrate 20 is substantially equal to the size D7 between the third electron transport layer 35 and the substrate 20, i.e. D8≈D7; the size D6 between the second electron transport layer 25 and the substrate 20 is less than the size D8 between the first electron transport layer 15 and the substrate 20, i.e. D8>D6.

[0122] In some examples, as shown in FIG. 3, the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35 are arranged in the same layer. That is, the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35 are formed simultaneously by the same patterning process.

[0123] For example, when preparing the display panel 100 as shown in FIG. 3, after forming the first light emitting layer 13 of the first light emitting device 101, the first electron transport layer 15 is formed, and the second electron transport layer 25 and the third electron transport layer 35 are formed simultaneously when forming the first electron transport layer 15. In this way, the preparation of the plurality of light emitting devices 10 including the upright light emitting device and the inverted light emitting device can be realized, and the preparation process of the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35 can be simplified. For specific content, refer to the description of the preparation method of the display panel, which will not be described here.

[0124] In some examples, as shown in FIG. 3, the material of the first electron transport layer 15, the material of the second electron transport layer 25 and the material of the third electron transport layer 35 are the same, and the material of the first electron transport layer 15, the material of the second electron transport layer 25 and the material of the third electron transport layer 35 are selected from at least one of zinc oxide, tin oxide, titanium oxide, gallium oxide, aluminum oxide, zinc gallium oxide, zinc tin oxide, zinc titanium oxide, zinc aluminum oxide, tin gallium oxide and zinc tin gallium oxide, and the embodiments of the present disclosure are not limited thereto.

[0125] For example, the material of the first electron transport layer 15, the material of the second electron transport layer 25, and the material of the third electron transport layer 35 are selected from at least one of nano-particle type zinc oxide, sol-gel type zinc oxide, and a second ligand material coordinated on the nano-particle type zinc oxide or the sol-gel type zinc oxide. The nano-zinc oxide can be metal-doped nano-zinc oxide.

[0126] For example, the metal-doped nano-zinc oxide includes zinc oxide (ZnO) doped with at least one of magnesium (Mg), aluminum (Al), zirconium (Zr), and yttrium (Y). The second ligand material includes, for example, an organic material such as acetamide.

[0127] For example, the thickness of the first electron transport layer 15, the second electron transport layer 25, and the third electron transport layer 35 ranges from 10 nm to 150 nm. For example, the thickness of the first electron transport layer 15, the second electron transport layer 25, and the third electron transport layer 35 is 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm, without being limited thereto.

[0128] In some embodiments, as shown in FIG. 4A, the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102, and the third hole transport layer 34 and the second hole transport layer 24 are arranged in the same layer. Along the first direction Y, the size D9 between the second hole transport layer 24 and the substrate 20 is substantially equal to the size D10 between the third hole transport layer 34 and the substrate 20, i.e., D9≈D10. The size D11 between the first hole transport layer 14 and the substrate 20 is smaller than the size D9 between the second hole transport layer 24 and the substrate 20, i.e., D11<D9.

[0129] In some embodiments, as shown in FIG. 4B, the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101, and the third hole transport layer 34 and the first hole transport layer 14 are arranged in the same layer. Along the first direction Y, the size D11 between the first hole transport layer 14 and the substrate 20 is substantially equal to the size D10 between the third hole transport layer 34 and the substrate 20, i.e., D11≈D10. The size D9 between the second hole transport layer 24 and the substrate 20 is greater than the size D11 between the first hole transport layer 14 and the substrate 20, i.e., D9>D11.

[0130] In some examples, the first hole transport layer 14, the second hole transport layer 24, and the third hole transport layer 34 are formed simultaneously through the same patterning process.

[0131] For example, the first hole transport layer 14, the second hole transport layer 24, and the third hole transport layer 34 are arranged in the same layer.

[0132] For example, the material of the first hole transport layer 14, the material of the second hole transport layer 24, and the material of the third hole transport layer 34 are the same, and are selected from any one of the materials containing at least one of a carbazole group, a carbazole derivative group, a triphenylamine group, and a triphenylamine derivative group. For example, the material of the first hole transport layer 14, the material of the second hole transport layer 24, and the material of the third hole transport layer 34 include at least one of poly[(9,9-dioctylfluorene-2,7-diyl)-alt-(4,4'-N-(4-n-butyl)phenyl)-diphenylamine)] (TFB) and polyvinylcarbazole (PVK) or poly[bis(4-phenyl)(4-butylphenyl)amine] (Poly-TPD), and the like.

[0133] For example, the material of the first hole transport layer 14, the material of the second hole transport layer 24, and the material of the third hole transport layer 34 are selected from an aromatic amine compound, an organic cation material, an inorganic material doped organic material, an inorganic metal oxide, or a high molecular polymer.

[0134] The aromatic amine compound includes at least one of N,N'-diaryl-N,N'-diphenylphenylamine (NPD) and N,N,N',N'-tetraphenylphenylamine (TPD). The material of the organic cation material includes poly(3,4-ethylenedioxythiophene) (PEDOT) and its derivatives, and the like. The inorganic material doped organic material includes some inorganic materials (such as metal phthalocyanine compounds, metal complexes, and the like). The inorganic metal oxide includes nickel oxide (NiO), copper oxide (CuO), tungsten trioxide (WO3), molybdenum trioxide (MoO3), and the like. The high molecular polymer includes Poly-TPD, TFB, PF8Cz, PVK, polytriazylamine (PTAA), or Spiro-OMe TAD, and the like.

[0135] For example, the thickness of the first hole transport layer 14, the second hole transport layer 24, and the third hole transport layer 34 ranges from 5 nm to 60 nm. For example, the thickness of the first hole transport layer 14, the second hole transport layer 24, and the third hole transport layer 34 is 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, or 60 nm, and the like, which is not limited herein.

[0136] In some embodiments, as shown in FIG. 4A, the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102, and the third hole injection layer 36 and the second hole injection layer 26 are arranged in the same layer; along the first direction Y, the size D12 between the second hole injection layer 26 and the substrate 20 is substantially equal to the size D13 between the third hole injection layer 36 and the substrate 20, i.e. D12≈D13; and the size D14 between the first hole injection layer 16 and the substrate 20 is smaller than the size D12 between the second hole injection layer 26 and the substrate 20, i.e. D14<D12.

[0137] In some embodiments, as shown in FIG. 4B, the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101, and the third hole injection layer 36 and the first hole injection layer 16 are arranged in the same layer; along the first direction Y, the size D14 between the first hole injection layer 16 and the substrate 20 is substantially equal to the size D13 between the third hole injection layer 36 and the substrate 20, i.e. D14≈D13; and the size D12 between the second hole injection layer 26 and the substrate 20 is larger than the size D14 between the first hole injection layer 16 and the substrate 20, i.e. D12>D14.

[0138] In some embodiments, as shown in FIG. 4A, the first hole injection layer 16, the second hole injection layer 26 and the third hole injection layer 36 are arranged in the same layer. That is, the first hole injection layer 16, the second hole injection layer 26 and the third hole injection layer 36 are formed simultaneously through the same patterning process.

[0139] For example, in the preparation of the display panel 100 as shown in FIG. 4A, after the second hole transport layer 24 of the second light emitting device 102 and the third hole transport layer 34 of the third light emitting device 103 are formed, the second hole injection layer 26 and the third hole injection layer 36 are formed. In the formation of the second hole injection layer 26 and the third hole injection layer 36, the first hole injection layer 16 is also formed. In this way, the preparation of the multiple light emitting devices 10 including the upright light emitting device and the inverted light emitting device can be realized, and the preparation process of the first hole injection layer 16, the second hole injection layer 26 and the third hole injection layer 36 can be simplified. For details, refer to the description of the preparation method of the display panel, which will not be described here.

[0140] In some embodiments, as shown in FIG. 4A, the material of the first hole injection layer 16, the material of the second hole injection layer 26 and the material of the third hole injection layer 36 are the same, and the material of the first hole injection layer 16, the material of the second hole injection layer 26 and the material of the third hole injection layer 36 are selected from at least one of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid), 4,4',4"-tris[2-naphthylphenylamino]triphenylamine, 4,4',4"-tris(N-3-methylphenyl-N-phenylamino)triphenylamine, molybdenum trioxide, copper phthalocyanine, tungsten oxide, nickel oxide and vanadium oxide.

[0141] Exemplarily, the thickness of the first hole injection layer 16, the second hole injection layer 26 and the third hole injection layer 36 ranges from 3 nm to 60 nm. For example, the thickness of the first hole injection layer 16, the second hole injection layer 26 and the third hole injection layer 36 is 3 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm or 60 nm, etc., which is not limited herein.

[0142] In some embodiments, as shown in FIG. 3 and FIG. 4A, the display panel 100 further comprises a pixel defining layer 50, the pixel defining layer 50 has a plurality of openings K, and the plurality of light emitting devices 10 are arranged in the plurality of openings K one by one, the pixel defining layer 50 comprises a main body part 51 and an auxiliary part 52 located on the side of the main body part 51 away from the substrate 20, the material of the main body part 51 comprises a first organic material, and the material of the auxiliary part 52 comprises at least one of an inorganic material and a second organic material.

[0143] Exemplarily, the first organic material can be polyimide, the inorganic material can be one of zinc oxide nanoparticles and zinc oxide sol-gel, and the second organic material can be at least one of tetracyanoquinodimethane, trinitrofluorenone, (8-hydroxyquinoline)aluminum, oxadiazole, triazole, naphthalimide, chrysoidine, C60 and its derivatives, poly(9,9-dioctylfluorene-co-N-(4-butylphenyl)diphenylamine), polyvinylcarbazole, poly 3,4-ethylenedioxythiophene and polystyrene sulfonate.

[0144] Exemplarily, the material of the auxiliary part 52 is the same as the material of at least one of the functional layers of the light emitting device 10, and the functional layers of the light emitting device 10 comprise the first hole injection layer 16, the first hole transport layer 14, the first electron transport layer 15, the second hole injection layer 26, the second hole transport layer 24, the second electron transport layer 25, the third hole injection layer 36, the third hole transport layer 35 and the third electron transport layer 36. The functional layers of the light emitting device 10 can further comprise a hole blocking layer, an electron injection layer and an electron blocking layer. For example, the auxiliary part 52 is formed synchronously when the functional layers of the light emitting device 10 are formed. The formation of the auxiliary part 52 can be referred to the introduction of the preparation method of the display panel, which is not described herein.

[0145] As introduced above about the structure of the first light emitting device 101, the second light emitting device 102 and the third light emitting device 103, the first light emitting device 101 includes the second electrode 12, the second light emitting device 102 includes the fourth electrode 22, and the third light emitting device 103 includes the sixth electrode 32. Exemplarily, the material of the second electrode 12, the fourth electrode 22 and the sixth electrode 32 can be inorganic material, for example, the material of the second electrode 12, the fourth electrode 22 and the sixth electrode 32 can be at least one of indium tin oxide, indium zinc oxide and indium tin zinc oxide. For example, the second electrode 12, the fourth electrode 22 and the sixth electrode 32 can be formed by a deposition process.

[0146] By setting the pixel defining layer 50 to include the main body part 51 and the auxiliary part 52 located on the side of the main body part 51 away from the substrate 20, and the material of the auxiliary part 52 including at least one of inorganic material and second organic material, when the material of the part of the auxiliary part 52 farthest away from the substrate 20 is inorganic material, and the second electrode 12, the fourth electrode 22 and the sixth electrode 32 are formed by a deposition process, the material of the auxiliary part 52 and the material of the electrode (including the second electrode 12, the fourth electrode 22 and the sixth electrode 32) are both inorganic material, which is conducive to the deposition of electrode material on the surface of the auxiliary part 52, helps to form an electrode with good continuity, so that the surface flatness of the electrode is better, so that the surface of the display panel 100 is more flat, which is conducive to improving the light output effect of the display panel 100.

[0147] In some examples, as shown in FIG. 3, the auxiliary part 52 includes a single layer of film. The auxiliary part 52 is arranged in the same layer as the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35. The material of the auxiliary part 52 is the same as the material of the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35, for example, the material of the auxiliary part 52 is zinc oxide nanoparticles, at this time, the material of the auxiliary part 52 is inorganic material, which is conducive to the deposition of electrode material on the surface of the auxiliary part 52, helps to form an electrode with good continuity, so that the surface flatness of the electrode is better, so that the surface of the display panel 100 is more flat, which is conducive to improving the light output effect of the display panel 100.

[0148] In some examples, as shown in FIG. 4A, the auxiliary part 52 includes multiple layers of film. The auxiliary part 52 includes a first layer 521, a second layer 522 and a third layer 523 arranged in layers along the first direction Y perpendicular to the substrate 20 and away from the substrate 20.

[0149] Exemplarily, the first layer 521 is arranged in the same layer as the first hole injection layer 16, the second layer 522 is arranged in the same layer as the first hole transport layer 14, and the third layer 523 is arranged in the same layer as the first electron transport layer 15.

[0150] In some examples, as shown in FIG. 5, in the orthographic projection of the substrate 20, the auxiliary part 52 between the two adjacent light emitting devices 10 can cover the main part 51 between the two adjacent light emitting devices 10.

[0151] For example, in the second direction X as shown in FIG. 5, the size D4 of the auxiliary part 52 between the two adjacent light emitting devices 10 is less than or equal to the size D5 of the main part 51 between the two adjacent light emitting devices 10.

[0152] For example, the auxiliary part 52 between the two adjacent light emitting devices 10 can be located at the edge of the main part 51 between the two adjacent light emitting devices 10. Or, the auxiliary part 52 between the two adjacent light emitting devices 10 can be located at the middle of the main part 51 between the two adjacent light emitting devices 10. The auxiliary part 52 can be arranged at one part of the main part 51 away from the substrate 20, and the auxiliary part 52 can not be arranged at another part of the main part 51 away from the substrate 20.

[0153] In some embodiments, as shown in FIG. 3 and FIG. 6, the second electrode 12, the fourth electrode 22 and the sixth electrode 32 are connected.

[0154] For example, as shown in FIG. 3 and FIG. 6, the second electrode 12, the fourth electrode 22 and the sixth electrode 32 are common electrodes arranged in an integral layer. That is, the second electrode 12, the fourth electrode 22 and the sixth electrode 32 are arranged in the same layer.

[0155] When the second electrode 12, the fourth electrode 22 and the sixth electrode 32 are connected, the second electrode 12, the fourth electrode 22 and the sixth electrode 32 transmit the same voltage signal (for example, the signal is referred to as the first voltage signal), at this time, the voltage signal transmitted through the first electrode 11 is higher than the first voltage signal, so as to form an electric field between the first electrode 11 and the second electrode 12 of the first light emitting device 101 (the upright light emitting device), so that the first light emitting device 101 emits light; the voltage signal transmitted through the third electrode 21 is lower than the first voltage signal, so as to form an electric field between the third electrode 21 and the fourth electrode 22 of the second light emitting device 102 (the inverted light emitting device), so that the second light emitting device 102 emits light; the voltage signal transmitted through the fifth electrode 31 is lower than the first voltage signal, so as to form an electric field between the fifth electrode 31 and the sixth electrode 32 of the third light emitting device 103 (for example, the third light emitting device 103 is taken as the inverted light emitting device), so that the third light emitting device 103 emits light.

[0156] In some embodiments, as shown in FIG. 7 and FIG. 8, for example, the third light emitting device 103 is taken as the inverted light emitting device, the fourth electrode 22 and the sixth electrode 32 are connected, and the fourth electrode 22 and the sixth electrode 32 are both spaced apart from the second electrode 12.

[0157] For example, as shown in FIGS. 7 and 8, the second light emitting device 102 and the third light emitting device 103 are inverted light emitting devices, and the fourth electrode 22 of the second light emitting device 102 and the sixth electrode 32 of the third light emitting device 103 are connected. The first light emitting device 101 is a normal light emitting device, and the second electrode 12 of the first light emitting device 101 is an independent structure, that is, not connected with the fourth electrode 22, and the second electrode 12 of the first light emitting device 101 is not connected with the sixth electrode 32.

[0158] At this time, the fourth electrode 22 and the sixth electrode 32 can transmit the same voltage signal, and the voltage signal transmitted by the second electrode 12 can be different from the voltage signal transmitted by the fourth electrode 22 (or the sixth electrode 32). Alternatively, the voltage signal transmitted by the second electrode 12 can be the same as the voltage signal transmitted by the fourth electrode 22 (or the sixth electrode 32). By connecting the fourth electrode 22 and the sixth electrode 32, and spacing the fourth electrode 22 and the sixth electrode 32 from the second electrode 12, the transmission of the electrode voltage signal of the normal light emitting device and the inverted light emitting device can be more flexible, and the electrode voltage can be set according to the structure of the light emitting device 10, so that the light emitting device 10 has higher light emitting efficiency and service life.

[0159] In some embodiments, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101 as an example, that is, the third light emitting device 103 and the first light emitting device 101 are both normal light emitting devices, the second electrode 12 is connected with the sixth electrode 32, and the second electrode 12 and the sixth electrode 32 are both spaced from the fourth electrode 22.

[0160] In some examples, as shown in FIGS. 10 and 11, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102 as an example, that is, the third light emitting device 103 and the second light emitting device 102 are both inverted light emitting devices, the fourth electrode 22 and the sixth electrode 32 are disposed in the same layer, and are disposed in different layers from the second electrode 12.

[0161] For example, as shown in FIG. 10, the fourth electrode 22 and the sixth electrode 32 are connected and located in the same conductive layer, the second electrode 12 is an entire layer of conductive layer, and an insulating layer 63 is disposed between the conductive layer where the fourth electrode 22 and the sixth electrode 32 are located and the conductive layer where the second electrode 12 is located.

[0162] In some examples, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101 as an example, that is, the third light emitting device 103 and the first light emitting device 101 are both normal light emitting devices, the second electrode 12 and the sixth electrode 32 are disposed in the same layer, and are disposed in different layers from the fourth electrode 22. In some examples, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101 as an example, that is, the third light emitting device 103 and the first light emitting device 101 are both normal light emitting devices, the second electrode 12 and the sixth electrode 32 are disposed in the same layer, and are disposed in different layers from the fourth electrode 22.

[0163] In some examples, as shown in FIGS. 10-12, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102 as an example, in the orthographic projection onto the substrate 20, the film layer where the second electrode 12 is located covers the film layers where the fourth electrode 22 and the sixth electrode 32 are located.

[0164] For example, as shown in FIG. 10, the film layer where the second electrode 12 is located is located on the side of the conductive layers where the fourth electrode 22 and the sixth electrode 32 are located away from the substrate 20.

[0165] For example, the second electrode 12 can be provided in an integral layer to form a structure in which the film layer where the second electrode 12 is located covers the film layers where the fourth electrode 22 and the sixth electrode 32 are located in the orthographic projection onto the substrate 20, which facilitates the preparation of the second electrode 12 and simplifies the manufacturing process of the display panel 100.

[0166] In some embodiments, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101 as an example, in the orthographic projection onto the substrate 20, the film layer where the fourth electrode 22 is located covers the film layers where the second electrode 12 and the sixth electrode 32 are located.

[0167] In some embodiments, as shown in FIGS. 9 and 12, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102 as an example, the fourth electrode 22 and the sixth electrode 32 are alternately arranged along the second direction X, and a plurality of second electrodes 12 are arranged along the second direction X; and the rows where the fourth electrode 22 and the sixth electrode 32 are located and the rows where the plurality of second electrodes 12 are located are alternately arranged along the third direction Z. The second direction X and the third direction Z are parallel to the plane where the substrate 20 is located, and the second direction X and the third direction Z intersect.

[0168] For example, the second direction X and the third direction Z are perpendicular.

[0169] For example, as shown in FIGS. 9 and 12, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102 as an example, the plurality of light emitting devices 10 are divided into a plurality of first pixel rows 111 and a plurality of second pixel rows 112, each of the plurality of first pixel rows 111 includes the second light emitting device 102 and the third light emitting device 103 alternately arranged along the second direction X, the plurality of second pixel rows includes a plurality of first light emitting devices 101 arranged along the second direction X; and the first pixel rows 111 and the second pixel rows 112 are alternately arranged along the third direction Z.

[0170] For example, the second light emitting device 102 and the third light emitting device 103 adjacent to each other in the first pixel row 111 form a pixel S with the first light emitting device 101 in the second pixel row 112. The display panel 100 includes a plurality of pixels S arranged in an array to realize full-color display of the display panel 100.

[0171] That is, in a pixel S, the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 are arranged in a triangular shape.

[0172] In some embodiments, taking the case that the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101 as an example, the second electrode 12 and the sixth electrode 32 are arranged alternately along the second direction X, and the plurality of fourth electrodes 22 are arranged along the second direction X; and the rows where the second electrode 12 and the sixth electrode 32 are located and the rows where the plurality of fourth electrodes 22 are located are arranged alternately along the third direction Z.

[0173] In another example, as shown in FIG. 11, the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 are arranged alternately along the second direction X, and the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 arranged in sequence form a pixel S.

[0174] As shown in FIGS. 11 and 12, in each pixel S, the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 are arranged in different manners to make the display panel 100 have different display effects.

[0175] In some examples, as shown in FIG. 9, in a pixel S, the first light emitting device 101, the second light emitting device 102, and the third light emitting device 103 are arranged in a triangular shape, and taking the case that the third light emitting device 103 is an inverted light emitting device as an example, the fourth electrode 22 and the sixth electrode 32 are connected. The fourth electrode 22 and the sixth electrode 32 are arranged in the same layer and are arranged in different layers from the second electrode 12. In the orthographic projection onto the substrate 20, the second electrode 12 does not overlap with the fourth electrode 22 and the sixth electrode 32. For example, in the region where the plurality of pixels S are arranged in an array, the conductive layer where the fourth electrode 22 and the sixth electrode 32 are located and the conductive layer where the second electrode 12 is located are arranged alternately along the third direction Z.

[0176] In some embodiments, as shown in FIGS. 3 and 4A, the display panel 100 further includes an encapsulation layer 401 located on the side of the top electrode 203 away from the substrate 20. The encapsulation layer 401 is used to protect the display panel 100 from water and oxygen.

[0177] In some embodiments, as shown in FIG. 3, the display panel 100 further comprises: a first pixel circuit 611 and a second pixel circuit 612, the first pixel circuit 611 is configured to be electrically connected with the first light emitting device 101, the first pixel circuit 611 is used to drive the first light emitting device 101 to emit first color light, the second pixel circuit 612 is configured to be electrically connected with the second light emitting device 102, the second pixel circuit 612 is used to drive the second light emitting device 102 to emit second color light. Wherein, the first light emitting device 101 is located at the side of the first pixel circuit 611 away from the substrate 20, and the second light emitting device 102 is located at the side of the second pixel circuit 612 away from the substrate 20.

[0178] For example, as shown in FIG. 3, a pixel circuit layer 60 is arranged between the substrate 20 and the plurality of light emitting devices 10, the pixel circuit layer 60 comprises a plurality of pixel circuits 61, and the plurality of pixel circuits 61 comprises: the first pixel circuit 611 and the second pixel circuit 612.

[0179] By arranging the display panel 100 to comprise the first pixel circuit 611 and the second pixel circuit 612, the first pixel circuit 611 is used to drive the first light emitting device 101 (normal light emitting device) to emit light, and the second pixel circuit 612 is used to drive the second light emitting device 102 (inverted light emitting device) to emit light. That is, in one display panel 100, the normal light emitting device and the inverted light emitting device are arranged at the same time, so as to realize the respective driving of the normal light emitting device and the inverted light emitting device in the case of optimizing the light emitting efficiency and the service life of the light emitting device 10 emitting different color light.

[0180] By arranging the first light emitting device 101 at the side of the first pixel circuit 611 away from the substrate 20 and the second light emitting device 102 at the side of the second pixel circuit 612 away from the substrate 20, the normal light emitting device and the inverted light emitting device are arranged on the same plane at the side of the pixel circuit layer 60 away from the substrate 20, which is beneficial to the preparation of the light emitting device 10.

[0181] In some examples, as shown in FIG. 13 and FIG. 14, the first pixel circuit 611 comprises: a first drive transistor T31, a gate g1 of the first drive transistor T31 is electrically connected with a first node O1, a source s1 of the first drive transistor T31 is electrically connected with a first voltage signal terminal Q1, a drain d1 of the first drive transistor T31 is electrically connected with a first electrode 11 of the first light emitting device 101, a second electrode 12 of the first light emitting device 101 is electrically connected with a second voltage signal terminal Q2, and the voltage of the first voltage signal terminal Q1 is higher than the voltage of the second voltage signal terminal Q2, that is, V Q1 >V Q2 .

[0182] For example, the first drive transistor T31 is a P-type transistor.

[0183] Exemplarily, the first voltage signal terminal Q1 is electrically connected with the first power signal line VDD1, and the first voltage signal terminal Q1 is configured to receive a first power voltage signal transmitted by the first power signal line VDD1. The second voltage signal terminal Q2 is electrically connected with the first reference voltage line VSS1, and the second voltage signal terminal Q2 is configured to receive a first reference voltage signal transmitted by the first reference voltage line VSS1. The first power voltage signal is greater than the first reference voltage signal.

[0184] Exemplarily, the first power signal line VDD1 and the first reference voltage line VSS1 of the display panel 100 are connected with the driving chip 70, and the driving chip 70 is configured to provide the first power voltage signal to the first power signal line VDD1, and the driving chip 70 is configured to provide the first reference voltage signal to the first reference voltage line VSS1.

[0185] The first pixel circuit 611 in some embodiments of the present disclosure can be a 7T1C, 8T1C or 9T1C circuit, where T represents a transistor, the number in front of T represents the number of transistors, C represents a capacitor, and the number in front of C represents the number of capacitors. Exemplarily, 7T1C represents 7 transistors and 1 capacitor.

[0186] In some embodiments, the structure of the first pixel circuit 611 based on FIG. 13 is introduced, and the first pixel circuit 611 is a 7T1C pixel driving circuit. The first pixel circuit 611 includes a first reset transistor T6, a compensation transistor T4, a first driving transistor T31, a data writing transistor T2, a first light emitting control transistor T1, a second light emitting control transistor T5 and a second reset transistor T7.

[0187] Exemplarily, as shown in FIG. 13, the first reset transistor T6 includes a gate, a first electrode and a second electrode, the gate of the first reset transistor T6 is electrically connected with the first reset signal line RST1, the first electrode of the first reset transistor T6 is electrically connected with the first initialization signal line Vint1, and the second electrode of the first reset transistor T6 is electrically connected with the first node O1. The first reset transistor T6 is configured to reset the gate g1 of the first driving transistor T31 in response to the reset signal received at the first reset signal line RST1.

[0188] Exemplarily, as shown in FIG. 13, the compensation transistor T4 includes a gate, a first electrode and a second electrode, the gate of the compensation transistor T4 is electrically connected with the first scan signal line Gat1, the first electrode of the compensation transistor T4 is electrically connected with the fourth node O4, and the second electrode of the compensation transistor T4 is electrically connected with the first node O1. The compensation transistor T4 is configured to reset or threshold compensate the first driving transistor T31 in response to the scan signal received at the first scan signal line Gat1.

[0189] For example, as shown in FIG. 13, the first drive transistor T31 includes a gate g1, a source s1 and a drain d1, the gate g1 of the first drive transistor T31 is electrically connected with the first node O1, the source s1 of the first drive transistor T31 is electrically connected with the fifth node O5, and the drain d1 of the first drive transistor T31 is electrically connected with the fourth node O4. The first drive transistor T31 is configured to generate a drive current signal.

[0190] For example, as shown in FIG. 13, the data write transistor T2 includes a gate, a first pole and a second pole, the gate of the data write transistor T2 is electrically connected with the second scan signal line Gat2, the first pole of the data write transistor T2 is electrically connected with the data signal line Data, and the second pole of the data write transistor T2 is electrically connected with the fifth node O5. The data write transistor T2 is configured to transmit a data signal received at the data signal line Data to the first drive transistor T31 in response to a scan signal received at the second scan signal line Gat2.

[0191] For example, as shown in FIG. 13, the first light-emitting control transistor T1 includes a gate, a first pole and a second pole, the gate of the first light-emitting control transistor T1 is electrically connected with the first light-emitting control signal line EM1, the first pole of the first light-emitting control transistor T1 is electrically connected with the first power signal line VDD1, and the second pole of the first light-emitting control transistor T1 is electrically connected with the fifth node O5. The first light-emitting control transistor T1 is configured to transmit a power signal received at the first power signal line VDD1 to the first drive transistor T31 in response to a light-emitting control signal received at the first light-emitting control signal line EM1.

[0192] For example, as shown in FIG. 13, the second light-emitting control transistor T5 includes a gate, a first pole and a second pole, the gate of the second light-emitting control transistor T5 is electrically connected with the first light-emitting control signal line EM1, the first pole of the second light-emitting control transistor T5 is electrically connected with the fourth node O4, and the second pole of the second light-emitting control transistor T5 is electrically connected with the sixth node O6. The second light-emitting control transistor T5 is configured to transmit a drive current signal to the first light-emitting device 101 for driving the first light-emitting device 101 to emit light in response to a light-emitting control signal received at the first light-emitting control signal line EM1.

[0193] Exemplarily, as shown in FIG. 13, the second reset transistor T7 includes a gate, a first pole and a second pole, the gate of the second reset transistor T7 is electrically connected with the second reset signal line RST2, the first pole of the second reset transistor T7 is electrically connected with the second initialization signal line Vint2, and the second pole of the second reset transistor T7 is electrically connected with the sixth node O6. The second reset transistor T7 is configured to transmit the initialization signal received at the second initialization signal line Vint2 to the first light emitting device 101 to reset the first light emitting device 101 in response to the reset signal received at the second reset signal line RST2.

[0194] Exemplarily, the anode of the first light emitting device 101 is electrically connected with the sixth node O6, and the cathode of the first light emitting device 101 is electrically connected with the first reference voltage line VSS1.

[0195] Exemplarily, as shown in FIG. 13, the first pixel circuit 611 further includes a capacitor Cst including a first pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 of the capacitor Cst is electrically connected with the first node O1, and the second pole plate Cst2 of the capacitor Cst is electrically connected with the first power supply signal line VDD1.

[0196] It should be noted that in the circuit provided by the embodiments of the present disclosure, the nodes are not actual components, but are convergence points of relevant electrical connections in the circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram.

[0197] The first pole of the transistor in the present disclosure is one of the source and the drain of the transistor, and the second pole is the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain of the transistor can be indistinguishable in structure, that is, the first pole and the second pole of the transistor in the embodiments of the present disclosure can be indistinguishable in structure. Exemplarily, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source, and the second pole of the transistor is the drain; and exemplarily, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain, and the second pole of the transistor is the source.

[0198] It should be noted that the first driving transistor T31 is a P-type transistor, and the conduction condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than the threshold voltage of the P-type transistor, that is, the gate voltage of the P-type transistor is less than the sum of the source voltage and the threshold voltage of the P-type transistor, and the threshold voltage of the P-type transistor is negative. The conduction condition of the N-type transistor is that the gate-source voltage difference is greater than the threshold voltage of the N-type transistor, that is, the gate voltage of the N-type transistor is greater than the sum of the source voltage and the threshold voltage of the N-type transistor, and the threshold voltage of the N-type transistor is positive.

[0199] In some embodiments, the transistors in the first pixel circuit 611 can be at least one of oxide thin film transistors (oxide TFTs), low temperature poly-silicon (LTPS) thin film transistors, low temperature poly-silicon oxide (LTPO), and complementary metal oxide semiconductor (CMOS) transistors.

[0200] For example, the compensation transistor T4 and the first reset transistor T6 can be oxide thin film transistors and N-type transistors, i.e., high-level on. The first drive transistor T31, the data write transistor T2, the first light-emitting control transistor T1, the second light-emitting control transistor T5, and the second reset transistor T7 are all P-type transistors of low temperature poly-silicon thin film transistors, i.e., low-level on. The use of oxide thin film transistors for the compensation transistor T4 can effectively prevent leakage at the fourth node O4, and the use of oxide thin film transistors for the first reset transistor T6 can effectively prevent leakage at the first node O1.

[0201] It should be noted that the above examples of the first reset transistor T6, the compensation transistor T4, the first drive transistor T31, the data write transistor T2, the first light-emitting control transistor T1, the second light-emitting control transistor T5, and the second reset transistor T7 are not limitations on the types of transistors.

[0202] In some embodiments, the timing diagram of the first pixel circuit 611 as shown in FIG. 13 is as shown in FIG. 15. The timing includes three stages, an initialization stage t1, a data write and Vth compensation stage t2, and a light-emitting stage t3.

[0203] In the initialization stage t1, the first reset signal line RST1, the first light-emitting control signal line EM1, and the second scan signal line Gat2 are high, the second reset signal line RST2 and the first scan signal line Gat1 are low, the first reset transistor T6 and the second reset transistor T7 are on, the first light-emitting control transistor T1 and the second light-emitting control transistor T5 are off, the voltage of the first initialization signal line Vint1 is written to the first node O1 through the first reset transistor T6 to initialize the first drive transistor T31, and the voltage of the second initialization signal line Vint2 is written to the anode of the first light-emitting device 101 through the second reset transistor T7 to reset the first light-emitting device 101.

[0204] In the data writing and Vth compensation stage t2, the first reset signal line RST1 is at low level, and the signal transmitted by the first initialization signal line Vint1 is off. The first scan signal line Gat1 is at high level, the second scan signal line Gat2 is at low level, and the data signal at the data signal line Data is written into the first node O1 through the data writing transistor T2, the first driving transistor T31 and the compensation transistor T4, so as to compensate the Vth of the first driving transistor T31.

[0205] In the light emitting stage t3, the first scan signal line Gat1 is at low level, the second scan signal line Gat2 is at high level, and the first light emitting control signal line EM1 is at low level, so that the compensation transistor T4 is off, and the first light emitting control transistor T1 and the second light emitting control transistor T5 are on to enter the light emitting stage t3.

[0206] In the light emitting stage t3, the current provided by the first driving transistor T31 is:

[0207] Wherein, Vdata represents the voltage transmitted by the data signal line Data, VDD1 represents the voltage transmitted by the first power signal line VDD1, C ox represents the capacitance of the capacitor Cst, μ is a constant, and W and L are parameters related to the structure of the first driving transistor T31 (the width and length of the channel region of the first driving transistor T31). The circuit realizes the compensation of the Vth of the first driving transistor T31.

[0208] In some embodiments, as shown in FIG. 14 and FIG. 16, the second pixel circuit 612 comprises: a second driving transistor T32, a gate g2 of the second driving transistor T32 is electrically connected with the second node O2, a source s2 of the second driving transistor T32 is electrically connected with a third voltage signal terminal Q3, a drain d2 of the second driving transistor T32 is electrically connected with a third electrode 21 of the second light emitting device 102, and a fourth electrode 22 of the second light emitting device 102 is electrically connected with a fourth voltage signal terminal Q4. The voltage of the third voltage signal terminal Q3 is less than the voltage of the fourth voltage signal terminal Q4, that is, V Q3 <V Q4 .

[0209] For example, the second driving transistor T32 is an N-type transistor.

[0210] For example, the third voltage signal terminal Q3 is electrically connected with a second reference voltage line VSS2, and the third voltage signal terminal Q3 is used to receive a second reference voltage signal transmitted by the second reference voltage line VSS2. The fourth voltage signal terminal Q4 is electrically connected with a second power signal line VDD2, and the fourth voltage signal terminal Q4 is used to receive a second power voltage signal transmitted by the second power signal line VDD2. Wherein, the second power voltage signal is greater than the second reference voltage signal.

[0211] For example, the voltage of the fourth voltage signal terminal Q4 can be equal to the voltage of the first voltage signal terminal Q1, i.e., V Q1 = V Q4 The voltage of the third voltage signal terminal Q3 can be equal to the voltage of the second voltage signal terminal Q2, i.e., V Q3 = V Q2 At this time, the second power voltage signal transmitted by the second power signal line VDD2 is equal to the first power voltage signal transmitted by the first power signal line VDD1, and the second reference voltage signal transmitted by the second reference voltage line VSS2 is equal to the first reference voltage signal transmitted by the first reference voltage line VSS1.

[0212] By virtue of the arrangement that the second pixel circuit 612 comprises the second driving transistor T32, and the gate g2 of the second driving transistor T32 is electrically connected with the second node O2, the source s2 of the second driving transistor T32 is electrically connected with the third voltage signal terminal Q3, and the drain d2 of the second driving transistor T32 is electrically connected with the third electrode 21 of the second light emitting device 102, the stability of the light emitted by the second light emitting device 102 is facilitated, and specific reasons are as follows.

[0213] In some embodiments, the second pixel circuit 612 in some embodiments of the present disclosure can be a 7T1C, 8T1C or 9T1C circuit.

[0214] In some embodiments, the structure of the second pixel circuit 612 based on FIG. 16 is introduced, and the second pixel circuit 612 is a 7T1C pixel driving circuit. The second pixel circuit 612 comprises a first reset transistor T6, a compensation transistor T4, a second driving transistor T32, a data writing transistor T2, a first light emitting control transistor T1, a second light emitting control transistor T5 and a second reset transistor T7.

[0215] It should be noted that the first pixel circuit 611 and the second pixel circuit 612 are both exemplarily described as 7T1C, and for the transistors and nodes with the same name in the first pixel circuit 611 and the second pixel circuit 612, the connection arrangement mode should be understood based on the pixel circuit 61 in which the transistors and nodes are located.

[0216] For example, as shown in FIG. 16, the first reset transistor T6 comprises a gate, a first pole and a second pole, the gate of the first reset transistor T6 is electrically connected with the first reset signal line RST1, the first pole of the first reset transistor T6 is electrically connected with the first initialization signal line Vint1, and the second pole of the first reset transistor T6 is electrically connected with the second node O2. The first reset transistor T6 is configured to reset the gate g2 of the second driving transistor T32 in response to the reset signal received at the first reset signal line RST1.

[0217] Exemplarily, as shown in FIG. 16, the compensation transistor T4 includes a gate, a first pole and a second pole, the gate of the compensation transistor T4 is electrically connected with the first scan signal line Gat1, the first pole of the compensation transistor T4 is electrically connected with the fourth node O4, and the second pole of the compensation transistor T4 is electrically connected with the second node O2. The compensation transistor T4 is configured to reset or threshold compensate the second drive transistor T32 in response to the scan signal received at the first scan signal line Gat1.

[0218] Exemplarily, as shown in FIG. 16, the second drive transistor T32 includes a gate g2, a source s2 and a drain d2, the gate g2 of the second drive transistor T32 is electrically connected with the second node O2, the source s2 of the second drive transistor T32 is electrically connected with the fifth node O5, and the drain d2 of the second drive transistor T32 is electrically connected with the fourth node O4. The second drive transistor T32 is configured to generate a drive current signal.

[0219] Exemplarily, as shown in FIG. 16, the data write transistor T2 includes a gate, a first pole and a second pole, the gate of the data write transistor T2 is electrically connected with the first scan signal line Gat1, the first pole of the data write transistor T2 is electrically connected with the data signal line Data, and the second pole of the data write transistor T2 is electrically connected with the fifth node O5. The data write transistor T2 is configured to transmit the data signal received at the data signal line Data to the second drive transistor T32 in response to the scan signal received at the first scan signal line Gat1.

[0220] Exemplarily, as shown in FIG. 16, the first light emitting control transistor T1 includes a gate, a first pole and a second pole, the gate of the first light emitting control transistor T1 is electrically connected with the second light emitting control signal line EM2, the first pole of the first light emitting control transistor T1 is electrically connected with the second reference voltage line VSS2, and the second pole of the first light emitting control transistor T1 is electrically connected with the fifth node O5. The first light emitting control transistor T1 is configured to transmit the second reference voltage signal received at the second reference voltage line VSS2 to the second drive transistor T32 in response to the light emitting control signal received at the second light emitting control signal line EM2.

[0221] Exemplarily, as shown in FIG. 16, the second light-emitting control transistor T5 includes a gate, a first pole and a second pole, the gate of the second light-emitting control transistor T5 is electrically connected with the second light-emitting control signal line EM2, the first pole of the second light-emitting control transistor T5 is electrically connected with the fourth node O4, and the second pole of the second light-emitting control transistor T5 is electrically connected with the sixth node O6. The second light-emitting control transistor T5 is configured to transmit a driving current signal to the second light-emitting device 102 for driving the second light-emitting device 102 to emit light in response to a light-emitting control signal received at the second light-emitting control signal line EM2.

[0222] Exemplarily, as shown in FIG. 16, the second reset transistor T7 includes a gate, a first pole and a second pole, the gate of the second reset transistor T7 is electrically connected with the first reset signal line RST1, the first pole of the second reset transistor T7 is electrically connected with the second initialization signal line Vint2, and the second pole of the second reset transistor T7 is electrically connected with the sixth node O6. The second reset transistor T7 is configured to transmit an initial signal received at the second initialization signal line Vint2 to the second light-emitting device 102 to reset the second light-emitting device 102 in response to a reset signal received at the second reset signal line RST2.

[0223] Exemplarily, the cathode of the second light-emitting device 102 is electrically connected with the sixth node O6, and the anode of the second light-emitting device 102 is electrically connected with the second power supply signal line VDD2.

[0224] Exemplarily, as shown in FIG. 16, the second pixel circuit 612 further includes a capacitor Cst including a first pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 of the capacitor Cst is electrically connected with the second node O2, and the second pole plate Cst2 of the capacitor Cst is electrically connected with the second reference voltage line VSS2.

[0225] In some embodiments, the transistors in the second pixel circuit 612 can be at least one of oxide thin film transistors, low-temperature polysilicon thin film transistors and complementary metal oxide semiconductor transistors.

[0226] Exemplarily, the first reset transistor T6, the compensation transistor T4, the second driving transistor T32, the data writing transistor T2, the first light-emitting control transistor T1, the second light-emitting control transistor T5 and the second reset transistor T7 of the second pixel circuit 612 are all oxide thin film transistors and are N-type transistors, i.e., high-level transistors.

[0227] It should be noted that the examples of the first reset transistor T6, compensation transistor T4, second drive transistor T32, data write transistor T2, first light-emitting control transistor T1, second light-emitting control transistor T5, and second reset transistor T7 are not intended to limit the types of transistors.

[0228] In some embodiments, the timing diagram of the second pixel circuit 612 shown in FIG16 is shown in FIG15. The timing includes three stages: initialization stage t1, data writing and Vth compensation stage t2, and light emission stage t3.

[0229] During the initialization phase t1, the first reset signal line RST1 is at a high level, the first scan signal line Gat1 and the second light emission control signal line EM2 are at a low level. The voltage of the first initialization signal line Vint1 is written to the second node O2 through the first reset transistor T6, thereby initializing the second driving transistor T32. The voltage of the second initialization signal line Vint2 is written to the cathode of the second light-emitting device 102 through the second reset transistor T7, thereby resetting the second light-emitting device 102.

[0230] During the data writing and Vth compensation phase t2, the first reset signal line RST1 is low, and the signal transmitted by the first initialization signal line Vint1 is turned off. The first scan signal line Gat1 is high, and the data signal at the data signal line Data is written to the second node O2 through the data writing transistor T2, the second driving transistor T32, and the compensation transistor T4, compensating for the Vth of the second driving transistor T32.

[0231] During the light-emitting stage t3, the first scan signal line Gat1 is at a low level, the second light-emitting control signal line EM2 is at a high level, the compensation transistor T4 is turned off, and the first light-emitting control transistor T1 and the second light-emitting control transistor T5 are turned on to enter the light-emitting stage t3.

[0232] During the light-emitting phase t3, the current supplied by the second driving transistor T32 is:

[0233] Where Vdata represents the voltage transmitted on the data signal line Data, VSS2 represents the voltage transmitted on the second reference voltage line VSS2, and C ox The capacitance Cst represents the capacitance of the capacitor, μ is a constant, and W and L are parameters related to the structure of the second driving transistor T32 (width and length of the channel region of the second driving transistor T32). This circuit realizes the compensation of Vth of the second driving transistor T32 and the VSS voltage is relatively stable, so that the current I driving the second light-emitting device 102 to emit light is relatively stable, which is beneficial to the stability of the emitted light of the second light-emitting device 102.

[0234] In some embodiments, a structure based on the first pixel circuit 610 shown in FIG. 16 is introduced, which is a 6T1C pixel driving circuit. The first pixel circuit 610 includes a first reset transistor T6, a compensation transistor T4, a data writing transistor T2, a first light-emitting control transistor T1, and a second light-emitting control transistor T5.

[0235] The first reset transistor T6, the compensation transistor T4, the data writing transistor T2, the first light-emitting control transistor T1, and the second light-emitting control transistor T5 are all P-type transistors, which are turned on at a low level. It should be noted that the above examples of the first reset transistor T6, the compensation transistor T4, the data writing transistor T2, the first light-emitting control transistor T1, and the second light-emitting control transistor T5 are not a limitation on the type of transistors.

[0236] For example, as shown in FIG. 16, the first reset transistor T6 includes a gate, a first electrode, and a second electrode. The gate of the first reset transistor T6 is electrically connected to a second reset signal line RST2. The first electrode of the first reset transistor T6 is electrically connected to a first initialization signal line Vint1. The second electrode of the first reset transistor T6 is electrically connected to a second node O2. The first reset transistor T6 is configured to reset the gate g3 of the driving transistor T3 in response to a reset signal received at the second reset signal line RST2.

[0237] For example, as shown in FIG. 16, the compensation transistor T4 includes a gate, a first electrode, and a second electrode. The gate of the compensation transistor T4 is electrically connected to a second scan signal line Gat2. The first electrode of the compensation transistor T4 is electrically connected to a fourth node O4. The second electrode of the compensation transistor T4 is electrically connected to the second node O2. The compensation transistor T4 is configured to reset or threshold compensate the driving transistor T3 in response to a scan signal received at the second scan signal line Gat2.

[0238] For example, as shown in FIG. 16, the data writing transistor T2 includes a gate g1, a source s1, and a drain d1. The gate g1 of the data writing transistor T2 is electrically connected to the second node O2. The source s1 of the data writing transistor T2 is electrically connected to a fifth node O5. The drain d1 of the data writing transistor T2 is electrically connected to the fourth node O4. The data writing transistor T2 is configured to write a data signal.

[0239] Exemplarily, as shown in FIG. 17, the data writing transistor T2 includes a gate, a first pole and a second pole, the gate of the data writing transistor T2 is electrically connected with the second scan signal line Gat2, the first pole of the data writing transistor T2 is electrically connected with the data signal line Data, and the second pole of the data writing transistor T2 is electrically connected with the fifth node O5. The data writing transistor T2 is configured to transmit the data signal received at the data signal line Data to the driving transistor T3 in response to the scan signal received at the second scan signal line Gat2.

[0240] Exemplarily, as shown in FIG. 17, the first light emitting control transistor T1 includes a gate, a first pole and a second pole, the gate of the first light emitting control transistor T1 is electrically connected with the first light emitting control signal line EM1, the first pole of the first light emitting control transistor T1 is electrically connected with the second reference voltage line VSS2, and the second pole of the first light emitting control transistor T1 is electrically connected with the fourth node O4. The first light emitting control transistor T1 is configured to transmit the second reference voltage signal received at the second reference voltage line VSS2 to the second driving transistor T32 in response to the light emitting control signal received at the first light emitting control signal line EM1.

[0241] Exemplarily, as shown in FIG. 17, the second light emitting control transistor T5 includes a gate, a first pole and a second pole, the gate of the second light emitting control transistor T5 is electrically connected with the first light emitting control signal line EM1, the first pole of the second light emitting control transistor T5 is electrically connected with the fifth node O5, and the second pole of the second light emitting control transistor T5 is electrically connected with the sixth node O6. The second light emitting control transistor T5 is configured to transmit the driving current signal to the second light emitting device 102 for driving the second light emitting device 102 to emit light in response to the light emitting control signal received at the first light emitting control signal line EM1.

[0242] Exemplarily, as shown in FIG. 17, the second reset transistor T7 includes a gate, a first pole and a second pole, the gate of the second reset transistor T7 is electrically connected with the second reset signal line RST2, the first pole of the second reset transistor T7 is electrically connected with the second initialization signal line Vint2, and the second pole of the second reset transistor T7 is electrically connected with the sixth node O6. The second reset transistor T7 is configured to transmit the initial signal received at the second initialization signal line Vint2 to the second light emitting device 102 for resetting the second light emitting device 102 in response to the reset signal received at the second reset signal line RST2.

[0243] Exemplarily, the cathode of the second light emitting device 102 is electrically connected with the sixth node O6, and the anode of the second light emitting device 102 is electrically connected with the second power signal line VDD2.

[0244] As shown in FIG. 17, the second pixel circuit 612 further includes a capacitor Cst including a first plate Cst1 and a second plate Cst2, the first plate Cst1 of the capacitor Cst being electrically connected to the second node O2, and the second plate Cst2 of the capacitor Cst being electrically connected to the second reference voltage line VSS2.

[0245] In some embodiments, the transistors in the second pixel circuit 612 can be at least one of an oxide thin film transistor (oxide TFT), a low temperature poly-silicon (LTPS) thin film transistor, a low temperature poly-silicon oxide (LTPO), and a complementary metal oxide semiconductor (CMOS) transistor.

[0246] In some embodiments, the timing diagram of the second pixel circuit 612 as shown in FIG. 17 is as shown in FIG. 15. The timing includes three stages, an initialization stage t1, a data writing and Vth compensation stage t2, and a light emitting stage t3.

[0247] In the initialization stage t1, the second reset signal line RST2 is at a low level, the second scan signal line Gat2 and the first light emitting control signal line EM1 are at a high level, and the voltage of the first initialization signal line Vint1 is written to the second node O2 through the first reset transistor T6 to initialize the second driving transistor T32. The voltage of the second initialization signal line Vint2 is written to the cathode of the second light emitting device 102 through the second reset transistor T7 to reset the second light emitting device 102.

[0248] In the data writing and Vth compensation stage t2, the second reset signal line RST2 is at a high level, and the signal transmitted by the first initialization signal line Vint1 is turned off. The second scan signal line Gat2 is at a high level, and the data signal at the data signal line Data is written to the second node O2 through the data writing transistor T2, the second driving transistor T32, and the compensation transistor T4 to compensate the Vth of the second driving transistor T32.

[0249] In the light emitting stage t3, the second scan signal line Gat2 is at a high level, and the first light emitting control signal line EM1 is at a low level, and the compensation transistor T4 is turned off. The first light emitting control transistor T1 and the second light emitting control transistor T5 are turned on to enter the light emitting stage t3.

[0250] In the light emitting stage t3, the current provided by the driving transistor T3 is:

[0251] Wherein, Vdata represents the voltage transmitted by the data signal line Data, although the circuit realizes the compensation of Vth of the second driving transistor T32. However, V S The potential is not a fixed potential, unstable, susceptible to the resistance of the light emitting device 10 and other factors, V S The potential is not fixed, which will cause the current I driving the second light emitting device 102 to emit light to be unstable, which will reduce the stability of the light emitted by the second light emitting device 102.

[0252] In some embodiments, the first reset transistor T6 and the compensation transistor T4 of the second pixel circuit 612 can be N-type transistors, which are turned on at high level. The second driving transistor T32, the data writing transistor T2, the first light emitting control transistor T1, the second light emitting control transistor T5 and the second reset transistor T7 can be P-type transistors, which are turned on at low level. Since the second driving transistor T32 is a P-type transistor, it will reduce the stability of the light emitted by the second light emitting device 102, and the specific reasons are introduced in the content of the second pixel circuit 612 shown in FIG. 17, which will not be described here.

[0253] In some examples, based on the above introduction of the first pixel circuit 611 including the first driving transistor T31 and the second pixel circuit 612 including the second driving transistor T32, as shown in FIG. 18, in the case that the display panel 100 includes normal light emitting devices and inverted light emitting devices, the process of realizing the driving of the normal light emitting devices and the inverted light emitting devices can be as follows.

[0254] As shown in FIG. 14 and FIG. 18, the scan signal line Gat in each pixel S is divided into two groups, the scan signal line Gat includes: a first scan signal line Gat1 and a second scan signal line Gat2, the first pixel circuit 611 of the normal light emitting device and the second pixel circuit 612 of the inverted light emitting device are respectively switched controlled by different scan signal lines Gat. For example, the first scan signal line Gat1 switches controls the first pixel circuit 611, and the second scan signal line Gat2 switches controls the second pixel circuit 612.

[0255] The first electrode 11 of the first light emitting device 101 (normal light emitting device) is connected with the first power signal line VDD1, and the second electrode 12 of the first light emitting device 101 (normal light emitting device) is connected with the first reference voltage line VSS1. A voltage difference between the first power signal line VDD1 and the first reference voltage line VSS1 forms an electric field between the first electrode 11 and the second electrode 12, so as to drive the first light emitting device 101 (normal light emitting device) to emit light.

[0256] The third electrode 21 of the second light emitting device 102 (inverted light emitting device) is connected with the second reference voltage line VSS2, and the fourth electrode 22 of the second light emitting device 102 (inverted light emitting device) is connected with the second power signal line VDD2. A voltage difference between the second reference voltage line VSS2 and the second power signal line VDD2 forms an electric field between the third electrode 21 and the fourth electrode 22 to drive the second light emitting device 102 (inverted light emitting device) to emit light.

[0257] The first pixel circuit 611 and the second pixel circuit 612 are introduced as an exemplary structure of another 7T1C pixel driving circuit.

[0258] In some embodiments, the structure of the first pixel circuit 611 shown in FIG. 19 is introduced. The first pixel circuit 611 includes a first reset transistor T6, a compensation transistor T4, a first drive transistor T31, a data writing transistor T2, a first light emitting control transistor T1, a second light emitting control transistor T5, and a second reset transistor T7.

[0259] The first reset transistor T6, the compensation transistor T4, the first drive transistor T31, the data writing transistor T2, the first light emitting control transistor T1, the second light emitting control transistor T5, and the second reset transistor T7 are all P-type transistors and are turned on at a low level. It should be noted that the above examples of the first reset transistor T6, the compensation transistor T4, the first drive transistor T31, the data writing transistor T2, the first light emitting control transistor T1, the second light emitting control transistor T5, and the second reset transistor T7 are not a limitation on the type of transistor.

[0260] For example, as shown in FIG. 19, the first reset transistor T6 includes a gate, a first electrode, and a second electrode. The gate of the first reset transistor T6 is electrically connected with the second reset signal line RST2. The first electrode of the first reset transistor T6 is electrically connected with the reference signal line Vref. The second electrode of the first reset transistor T6 is electrically connected with the eighth node O8. The first reset transistor T6 is configured to reset the eighth node O8 in response to a reset signal received at the second reset signal line RST2.

[0261] For example, as shown in FIG. 19, the compensation transistor T4 includes a gate, a first electrode, and a second electrode. The gate of the compensation transistor T4 is electrically connected with the second scan signal line Gat2. The first electrode of the compensation transistor T4 is electrically connected with the tenth node O10. The second electrode of the compensation transistor T4 is electrically connected with the first node O1. The compensation transistor T4 is configured to reset or threshold compensate the first drive transistor T31 in response to a scan signal received at the second scan signal line Gat2.

[0262] Exemplarily, as shown in FIG. 19, the first driving transistor T31 includes a gate g1, a source s1 and a drain d1, the gate g1 of the first driving transistor T31 is electrically connected with the first node O1, the gate g1 of the first driving transistor T31 is electrically connected with the first power supply signal line VDD1, and the drain d1 of the first driving transistor T31 is electrically connected with the tenth node O10. The first driving transistor T31 is configured to generate a driving current signal.

[0263] Exemplarily, as shown in FIG. 19, the data writing transistor T2 includes a gate, a first pole and a second pole, the gate of the data writing transistor T2 is electrically connected with the second scan signal line Gat2, the first pole of the data writing transistor T2 is electrically connected with the data signal line Data, and the second pole of the data writing transistor T2 is electrically connected with the eighth node O8. The data writing transistor T2 is configured to transmit a data signal received at the data signal line Data to the eighth node O8 in response to a scan signal received at the second scan signal line Gat2.

[0264] Exemplarily, as shown in FIG. 19, the first light emitting control transistor T1 includes a gate, a first pole and a second pole, the gate of the first light emitting control transistor T1 is electrically connected with the first light emitting control signal line EM1, the first pole of the first light emitting control transistor T1 is electrically connected with the reference signal line Vref, and the second pole of the first light emitting control transistor T1 is electrically connected with the eighth node O8. The first light emitting control transistor T1 is configured to transmit a reference signal received at the reference signal line Vref to the eighth node O8 in response to a light emitting control signal received at the first light emitting control signal line EM1.

[0265] Exemplarily, as shown in FIG. 19, the second light emitting control transistor T5 includes a gate, a first pole and a second pole, the gate of the second light emitting control transistor T5 is electrically connected with the first light emitting control signal line EM1, the first pole of the second light emitting control transistor T5 is electrically connected with the tenth node O10, and the second pole of the second light emitting control transistor T5 is electrically connected with the anode of the first light emitting device 101. The second light emitting control transistor T5 is configured to transmit a driving current signal to the first light emitting device 101 for driving the first light emitting device 101 to emit light in response to a light emitting control signal received at the first light emitting control signal line EM1.

[0266] Exemplarily, as shown in FIG. 19, the second reset transistor T7 includes a gate, a first pole and a second pole, the gate of the second reset transistor T7 is electrically connected with the second reset signal line RST2, the first pole of the second reset transistor T7 is electrically connected with the first initialization signal line Vint1, and the second pole of the second reset transistor T7 is electrically connected with the first node O1. The second reset transistor T7 is configured to transmit the initial signal received at the first initialization signal line Vint1 to the first node O1 in response to the reset signal received at the second reset signal line RST2, so as to reset the gate g1 of the first driving transistor T31.

[0267] Exemplarily, the cathode of the first light emitting device 101 is electrically connected with the first reference voltage line VSS1.

[0268] Exemplarily, as shown in FIG. 19, the first pixel circuit 611 further includes a capacitor Cst, the capacitor Cst includes a first pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 of the capacitor Cst is electrically connected with the first node O1, and the second pole plate Cst2 of the capacitor Cst is electrically connected with the eighth node O8.

[0269] In some embodiments, the transistor in the first pixel circuit 611 can be at least one of an oxide thin film transistor (oxide TFT), a low temperature poly-silicon (LTPS) thin film transistor, a low temperature poly-silicon oxide (LTPO), and a complementary metal oxide semiconductor (CMOS) transistor.

[0270] In some embodiments, the timing diagram of the first pixel circuit 611 as shown in FIG. 19 is as shown in FIG. 15. The timing diagram includes three stages, an initialization stage t1, a data writing and Vth compensation stage t2, and a light emitting stage t3.

[0271] In the initialization stage t1, the second reset signal line RST2 is at a low level, the second scan signal line Gat2 and the first light emitting control signal line EM1 are at a high level, the reference signal of the reference signal line Vref is written to the eighth node O8 through the first reset transistor T6 to initialize the second pole plate Cst2 of the capacitor Cst, and the voltage of the first initialization signal line Vint1 is written to the first node O1 through the second reset transistor T7 to reset the gate g1 of the first driving transistor T31.

[0272] In the data writing and Vth compensation stage t2, the second reset signal line RST2 is at high level, and the signal transmitted by the reference signal line Vref is closed. The second scan signal line Gat2 is at low level, the data writing transistor T2, the first driving transistor T31 and the compensation transistor T4 are turned on, and the data signal at the data signal line Data is written into the eighth node O8 through the data writing transistor T2, and the Vth of the first driving transistor T31 is compensated according to the electrode coupling effect of the capacitor Cst.

[0273] In the light emitting stage t3, the second scan signal line Gat2 is at high level, the first light emitting control signal line EM1 is at low level, the compensation transistor T4 is closed, the first light emitting control transistor T1 is opened, the reference signal of the reference signal line Vref is written into the eighth node O8, and the second light emitting control transistor T5 is opened to enter the light emitting stage t3.

[0274] In some embodiments, a structure based on the second pixel circuit 612 shown in FIG. 20 is introduced, and the second pixel circuit 612 is a 7T1C pixel driving circuit. The second pixel circuit 612 includes a first reset transistor T6, a compensation transistor T4, a second driving transistor T32, a data writing transistor T2, a first light emitting control transistor T1, a second light emitting control transistor T5 and a second reset transistor T7.

[0275] Among them, the first reset transistor T6, the compensation transistor T4, the second driving transistor T32, the data writing transistor T2, the first light emitting control transistor T1, the second light emitting control transistor T5 and the second reset transistor T7 are all N-type transistors and are turned on at high level. It should be noted that the above-mentioned examples of the first reset transistor T6, the compensation transistor T4, the second driving transistor T32, the data writing transistor T2, the first light emitting control transistor T1, the second light emitting control transistor T5 and the second reset transistor T7 are not a limitation on the type of transistor.

[0276] For example, as shown in FIG. 20, the first reset transistor T6 includes a gate, a first pole and a second pole, the gate of the first reset transistor T6 is electrically connected with the first reset signal line RST1, the first pole of the first reset transistor T6 is electrically connected with the reference signal line Vref, and the second pole of the first reset transistor T6 is electrically connected with the eighth node O8. The first reset transistor T6 is configured to reset the eighth node O8 in response to the reset signal received at the first reset signal line RST1.

[0277] Exemplarily, as shown in FIG. 20, the compensation transistor T4 includes a gate, a first pole and a second pole, the gate of the compensation transistor T4 is electrically connected with the first scan signal line Gat1, the first pole of the compensation transistor T4 is electrically connected with the tenth node O10, and the second pole of the compensation transistor T4 is electrically connected with the second node O2. The compensation transistor T4 is configured to reset or threshold compensate the second driving transistor T32 in response to the scan signal received at the first scan signal line Gat1.

[0278] Exemplarily, as shown in FIG. 20, the second driving transistor T32 includes a gate g2, a source s2 and a drain d2, the gate g2 of the second driving transistor T32 is electrically connected with the second node O2, the source s2 of the second driving transistor T32 is electrically connected with the second reference voltage line VSS2, and the drain d2 of the second driving transistor T32 is electrically connected with the tenth node O10. The second driving transistor T32 is configured to generate a driving current signal.

[0279] Exemplarily, as shown in FIG. 20, the data writing transistor T2 includes a gate, a first pole and a second pole, the gate of the data writing transistor T2 is electrically connected with the first scan signal line Gat1, the first pole of the data writing transistor T2 is electrically connected with the data signal line Data, and the second pole of the data writing transistor T2 is electrically connected with the eighth node O8. The data writing transistor T2 is configured to transmit the data signal received at the data signal line Data to the eighth node O8 in response to the scan signal received at the first scan signal line Gat1.

[0280] Exemplarily, as shown in FIG. 20, the first light emitting control transistor T1 includes a gate, a first pole and a second pole, the gate of the first light emitting control transistor T1 is electrically connected with the second light emitting control signal line EM2, the first pole of the first light emitting control transistor T1 is electrically connected with the reference signal line Vref, and the second pole of the first light emitting control transistor T1 is electrically connected with the eighth node O8. The first light emitting control transistor T1 is configured to transmit the reference signal received at the reference signal line Vref to the eighth node O8 in response to the light emitting control signal received at the second light emitting control signal line EM2.

[0281] Exemplarily, as shown in FIG. 20, the second light emitting control transistor T5 includes a gate, a first pole and a second pole, the gate of the second light emitting control transistor T5 is electrically connected with the second light emitting control signal line EM2, the first pole of the second light emitting control transistor T5 is electrically connected with the tenth node O10, and the second pole of the second light emitting control transistor T5 is electrically connected with the cathode of the second light emitting device 102. The second light emitting control transistor T5 is configured to transmit the driving current signal to the second light emitting device 102 for driving the second light emitting device 102 to emit light in response to the light emitting control signal received at the second light emitting control signal line EM2.

[0282] For example, as shown in FIG. 20, the second reset transistor T7 includes a gate, a first pole and a second pole, the gate of the second reset transistor T7 is electrically connected with the first reset signal line RST1, the first pole of the second reset transistor T7 is electrically connected with the first initialization signal line Vint1, and the second pole of the second reset transistor T7 is electrically connected with the second node O2. The second reset transistor T7 is configured to transmit the initial signal received at the first initialization signal line Vint1 to the second node O2 in response to the reset signal received at the first reset signal line RST1, so as to reset the gate g2 of the second driving transistor T32.

[0283] For example, the anode of the second light emitting device 102 is electrically connected with the second power signal line VDD2.

[0284] For example, as shown in FIG. 20, the second pixel circuit 612 further includes a capacitor Cst, the capacitor Cst includes a first pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 of the capacitor Cst is electrically connected with the second node O2, and the second pole plate Cst2 of the capacitor Cst is electrically connected with the eighth node O8.

[0285] In some embodiments, the transistor in the second pixel circuit 612 can be at least one of an oxide thin film transistor (oxide TFT), a low temperature poly-silicon (LTPS) thin film transistor, a low temperature poly-silicon oxide (LTPO), and a complementary metal oxide semiconductor (CMOS) transistor.

[0286] In some embodiments, the timing diagram of the second pixel circuit 612 as shown in FIG. 20 is as shown in FIG. 15. The timing includes three stages, an initialization stage t1, a data writing and Vth compensation stage t2, and a light emitting stage t3.

[0287] In the initialization stage t1, the first reset signal line RST1 is at a high level, the first scan signal line Gat1 and the second light emitting control signal line EM2 are at a low level, the reference signal of the reference signal line Vref is written to the eighth node O8 through the first reset transistor T6 to initialize the second pole plate Cst2 of the capacitor Cst, and the voltage of the first initialization signal line Vint1 is written to the second node O2 through the second reset transistor T7 to reset the gate g2 of the second driving transistor T32.

[0288] Data write-in and Vth compensation stage t2, the first reset signal line RST1 is low, the signal transmitted by the reference signal line Vref is off. The first scan signal line Gat1 is high, the data write-in transistor T2, the second driving transistor T32 and the compensation transistor T4 are turned on, the data signal at the data signal line Data is written into the eighth node O8 through the data write-in transistor T2, and the Vth of the compensation second driving transistor T32 is compensated according to the electrode coupling effect of the capacitor Cst.

[0289] Light-emitting stage t3, the first scan signal line Gat1 is low, the second light-emitting control signal line EM2 is high, the compensation transistor T4 is off, the first light-emitting control transistor T1 is on, the reference signal of the reference signal line Vref is written into the eighth node O8, and the second light-emitting control transistor T5 is on to enter the light-emitting stage t3.

[0290] The following introduces another exemplary structure of a second pixel circuit 612 of 7T1C.

[0291] In some embodiments, a structure based on the second pixel circuit 612 shown in FIG. 21 is introduced. The second pixel circuit 612 includes a first reset transistor T6, a compensation transistor T4, a second driving transistor T32, a data write-in transistor T2, a first light-emitting control transistor T1, a second light-emitting control transistor T5 and a second reset transistor T7.

[0292] Among them, the first reset transistor T6, the compensation transistor T4, the second driving transistor T32, the data write-in transistor T2, the first light-emitting control transistor T1, the second light-emitting control transistor T5 and the second reset transistor T7 are all P-type transistors, and low level is turned on. It should be noted that the above examples of the first reset transistor T6, the compensation transistor T4, the second driving transistor T32, the data write-in transistor T2, the first light-emitting control transistor T1, the second light-emitting control transistor T5 and the second reset transistor T7 are not limited to the type of transistor.

[0293] For example, as shown in FIG. 21, regarding the first reset transistor T6, the compensation transistor T4, the data write-in transistor T2, the first light-emitting control transistor T1, the second reset transistor T7 and the capacitor Cst, reference can be made to the introduction in the first pixel circuit 611 shown in FIG. 19, which will not be repeated here. The second driving transistor T32 and the second light-emitting control transistor T5 are introduced as follows.

[0294] Exemplarily, as shown in FIG. 21, the second driving transistor T32 includes a gate g2, a source s2 and a drain d2, the gate g2 of the second driving transistor T32 is electrically connected with the second node O2, the source s2 of the second driving transistor T32 is electrically connected with the eleventh node O11, the drain d2 of the second driving transistor T32 is electrically connected with the tenth node O10, and the tenth node O10 is electrically connected with the second reference voltage line VSS2. The second driving transistor T32 is configured to generate a driving current signal.

[0295] Exemplarily, as shown in FIG. 21, the second light emitting control transistor T5 includes a gate, a first pole and a second pole, the gate of the second light emitting control transistor T5 is electrically connected with the first light emitting control signal line EM1, the first pole of the second light emitting control transistor T5 is electrically connected with the eleventh node O11, and the second pole of the second light emitting control transistor T5 is electrically connected with the cathode of the first light emitting device 101. The second light emitting control transistor T5 is configured to transmit the driving current signal to the second light emitting device 102 for driving the second light emitting device 102 to emit light in response to the light emitting control signal received at the first light emitting control signal line EM1.

[0296] Exemplarily, the anode of the second light emitting device 102 is electrically connected with the second power signal line VDD2.

[0297] In some embodiments, the timing diagram of the second pixel circuit 612 as shown in FIG. 21 is as shown in FIG. 15. The timing diagram includes three stages, an initialization stage t1, a data writing and Vth compensation stage t2 and a light emitting stage t3. For the introduction of the timing of the second pixel circuit 612 as shown in FIG. 21, reference can be made to the introduction of the timing of the first pixel circuit 611 as shown in FIG. 19, which will not be repeated here.

[0298] The following introduces an exemplary structure of the first pixel circuit 611 as another 7T1C pixel driving circuit.

[0299] In some embodiments, as shown in FIG. 22, the first pixel circuit 611 includes a first reset transistor T6, a compensation transistor T4, a first driving transistor T31, a data writing transistor T2, a first light emitting control transistor T1, a second light emitting control transistor T5 and a seventh transistor T70.

[0300] Exemplarily, as shown in FIG. 22, the first reset transistor T6 includes a gate, a first pole and a second pole, the gate of the first reset transistor T6 is electrically connected with the first reset signal line RST1, the first pole of the first reset transistor T6 is electrically connected with the first initialization signal line Vint1, and the second pole of the first reset transistor T6 is electrically connected with the sixth node O6. The first reset transistor T6 is configured to reset the anode of the first light emitting device 101 in response to the reset signal received at the first reset signal line RST1.

[0301] Exemplarily, as shown in FIG. 22, the compensation transistor T4 includes a gate, a first pole and a second pole, the gate of the compensation transistor T4 is electrically connected with the first scan signal line Gat1, the first pole of the compensation transistor T4 is electrically connected with the fifth node O5, and the second pole of the compensation transistor T4 is electrically connected with the first node O1. The compensation transistor T4 is configured to reset or threshold compensate the first drive transistor T31 in response to the scan signal received at the first scan signal line Gat1.

[0302] Exemplarily, as shown in FIG. 22, the first drive transistor T31 includes a gate g1, a source s1 and a drain d1, the gate g1 of the first drive transistor T31 is electrically connected with the first node O1, the source s1 of the first drive transistor T31 is electrically connected with the fourth node O4, and the drain d1 of the first drive transistor T31 is electrically connected with the fifth node O5. The first drive transistor T31 is configured to generate a drive current signal.

[0303] Exemplarily, as shown in FIG. 22, the data write transistor T2 includes a gate, a first pole and a second pole, the gate of the data write transistor T2 is electrically connected with the first scan signal line Gat1, the first pole of the data write transistor T2 is electrically connected with the data signal line Data, and the second pole of the data write transistor T2 is electrically connected with the fourth node O4. The data write transistor T2 is configured to transmit the data signal received at the data signal line Data to the first drive transistor T31 in response to the scan signal received at the first scan signal line Gat1.

[0304] Exemplarily, as shown in FIG. 22, the first light emitting control transistor T1 includes a gate, a first pole and a second pole, the gate of the first light emitting control transistor T1 is electrically connected with the second light emitting control signal line EM2, the first pole of the first light emitting control transistor T1 is electrically connected with the first power signal line VDD1, and the second pole of the first light emitting control transistor T1 is electrically connected with the fifth node O5. The first light emitting control transistor T1 is configured to transmit the power signal received at the first power signal line VDD1 to the first drive transistor T31 in response to the light emitting control signal received at the second light emitting control signal line EM2.

[0305] Exemplarily, as shown in FIG. 22, the second light emitting control transistor T5 includes a gate, a first pole and a second pole, the gate of the second light emitting control transistor T5 is electrically connected with the second light emitting control signal line EM2, the first pole of the second light emitting control transistor T5 is electrically connected with the fourth node O4, and the second pole of the second light emitting control transistor T5 is electrically connected with the sixth node O6. The second light emitting control transistor T5 is configured to transmit a driving current signal to the first light emitting device 101 for driving the first light emitting device 101 to emit light in response to a light emitting control signal received at the second light emitting control signal line EM2.

[0306] Exemplarily, as shown in FIG. 22, the seventh transistor T70 includes a gate, a first pole and a second pole, the gate of the seventh transistor T70 is electrically connected with the second scan signal line Gat2, the first pole of the seventh transistor T70 is electrically connected with the first node O1, and the second pole of the seventh transistor T70 is electrically connected with the first power supply signal line VDD1. The seventh transistor T70 is configured to transmit a first power supply voltage signal received at the first power supply signal line VDD1 to the first node O1 in response to a scan signal received at the second scan signal line Gat2.

[0307] Exemplarily, the anode of the first light emitting device 101 is electrically connected with the sixth node O6, and the cathode of the first light emitting device 101 is electrically connected with the first reference voltage line VSS1.

[0308] Exemplarily, as shown in FIG. 22, the first pixel circuit 611 further includes a capacitor Cst including a first pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 of the capacitor Cst is electrically connected with the first node O1, and the second pole plate Cst2 of the capacitor Cst is electrically connected with the sixth node O6.

[0309] Exemplarily, the transistors in the first pixel circuit 611 can be oxide thin film transistors and N-type transistors, i.e., high-level on.

[0310] In some embodiments, the timing diagram of the first pixel circuit 611 as shown in FIG. 22 is as shown in FIG. 23. The timing diagram includes three stages, an initialization stage t1, a data writing and Vth compensation stage t2, and a light emitting stage t3, wherein the light emitting stage t3 includes a first light emitting stage t31 and a second light emitting stage t32.

[0311] In the initialization stage t1, as shown in FIG. 24, the first reset signal line RST1 and the second scan signal line Gat2 are high, the second emission control signal line EM2 and the first scan signal line Gat1 are low, the first reset transistor T6 and the seventh transistor T70 are turned on, and the voltage of the first initialization signal line Vint1 is written into the anode of the first light emitting device 101 through the first reset transistor T6 to reset the first light emitting device 101. At this time, the voltage of the sixth node O6 is the voltage Vinit transmitted by the first initialization signal line Vint1. The voltage of the first power supply signal line VDD1 is written into the first node O1 through the seventh transistor T70, and at this time, the voltage of the first node O1 is the first power voltage.

[0312] In the data writing and Vth compensation stage t2, as shown in FIG. 25, the first reset signal line RST1 remains high, the first scan signal line Gat1 is high, the second scan signal line Gat2 and the second emission control signal line EM2 are low, and the data signal at the data signal line Data is written into the first node O1 through the data writing transistor T2, the first drive transistor T31 and the compensation transistor T4 to compensate the Vth of the first drive transistor T31. At this time, the voltage of the first node O1 is the sum of the voltage Vdata transmitted by the data signal line Data and the Vth of the first drive transistor T31, i.e. Vdata+Vth. The voltage of the sixth node O6 remains unchanged as the holding voltage Vinit.

[0313] In the first light emitting stage t31, as shown in FIG. 26, the first reset signal line RST1 remains high, the second emission control signal line EM2 is high, and the first scan signal line Gat1 and the second scan signal line Gat2 are low. The first light emitting control transistor T1 and the second light emitting control transistor T5 are turned on, and the first light emitting device 101 is turned on. At this time, the voltage of the sixth node O6 remains unchanged as the holding voltage Vinit, and the voltage of the first node O1 is Vdata+Vth+△V G .

[0314] wherein,

[0315] FIG. 27 is an equivalent circuit diagram of the first pixel circuit 611 from the first reset transistor T6, the capacitor Cst to the fourth node O4, and FIG. 28 is an equivalent circuit diagram of the first pixel circuit 611 from the first reset transistor T6, the capacitor Cst, the first drive transistor T31 to the sixth node O6, C gsMd represents the parasitic capacitance of the first drive transistor T31, and Cst represents the capacitance of the capacitor Cst. Vinit represents the voltage transmitted by the first initialization signal line Vint1, and Vdata represents the voltage transmitted by the data signal line Data.

[0316] In the second light emitting stage t32, the first reset signal line RST1, the first scan signal line Gat1 and the second scan signal line Gat2 are at low level, the second light emitting control signal line EM2 is at high level, and the signal transmitted by the first initialization signal line Vint1 is off. At this time, the voltage of the first node O1 is Vdata+Vth+△V G +(V OLED -Vinit). The voltage of the sixth node O6 is V OLED .

[0317] In the second light emitting stage t32, the current provided by the first drive transistor T31 is:

[0318] The circuit realizes compensation of Vth of the first drive transistor T31.

[0319] In the above embodiment, in the case where the display panel 100 includes the upright light emitting device and the inverted light emitting device, for example, the first light emitting device 101 is the upright light emitting device and the second light emitting device 102 is the inverted light emitting device, by the setting of the first pixel circuit 611 and the second pixel circuit 612, the upright light emitting device and the inverted light emitting device can be driven to emit light.

[0320] In some embodiments, as shown in FIG. 30 and FIG. 31, by the setting of the external compensation circuit 66, the upright light emitting device and the inverted light emitting device can be driven to emit light. The external compensation circuit 66 includes: a first compensation circuit 661 and a second compensation circuit 662.

[0321] In some examples, as shown in FIG. 30, the first compensation circuit 661 includes: a first transistor T10, a second transistor T20 and a third transistor T30.

[0322] For example, the first transistor T10, the second transistor T20 and the third transistor T30 are N-type transistors, and are turned on at low level.

[0323] For example, as shown in FIG. 30, the first transistor T10 includes: a gate, a first pole and a second pole, the gate of the first transistor T10 is electrically connected with the first scan signal line Gat1, the first pole of the first transistor T10 is electrically connected with the data signal line Data, and the second pole of the first transistor T10 is electrically connected with the gate g4 of the second transistor T20. The first transistor T10 is configured to transmit the data signal received at the data signal line Data to the gate g4 of the second transistor T20 in response to the scan signal received at the first scan signal line Gat1.

[0324] Exemplarily, as shown in FIG. 30, the second transistor T20 includes a gate g5, a source s5 and a drain d5, the source s5 of the second transistor T20 is electrically connected with the anode of the first light emitting device 101, and the drain d5 of the second transistor T20 is electrically connected with the first power signal line VDD1. The second transistor T20 is configured to generate a driving current signal.

[0325] Exemplarily, as shown in FIG. 30, the third transistor T30 includes a gate, a first pole and a second pole, the gate of the third transistor T30 is electrically connected with the second scan signal line Gat2, the first pole of the third transistor T30 is electrically connected with the sensing signal line Sense, and the second pole of the third transistor T30 is electrically connected with the source s5 of the second transistor T20. The third transistor T30 is configured to transmit the sensing signal received at the sensing signal line Sense to the source s5 of the second transistor T20 in response to the scan signal received at the second scan signal line Gat2.

[0326] Exemplarily, as shown in FIG. 30, the first compensation circuit 661 further includes a capacitor Cst including a first pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 of the capacitor Cst is electrically connected with the gate g4 of the second transistor T20, and the second pole plate Cst2 of the capacitor Cst is electrically connected with the source s5 of the second transistor T20.

[0327] Exemplarily, as shown in FIG. 30, the cathode of the first light emitting device 101 is electrically connected with the first reference voltage line VSS1.

[0328] In some examples, as shown in FIG. 31, the second compensation circuit 662 includes the first transistor T10, the second transistor T20 and the third transistor T30.

[0329] Exemplarily, the first transistor T10, the second transistor T20 and the third transistor T30 are N-type transistors and are low-level on.

[0330] Exemplarily, as shown in FIG. 31, the first transistor T10 includes a gate, a first pole and a second pole, the gate of the first transistor T10 is electrically connected with the first scan signal line Gat1, the first pole of the first transistor T10 is electrically connected with the data signal line Data, and the second pole of the first transistor T10 is electrically connected with the gate g4 of the second transistor T20. The first transistor T10 is configured to transmit the data signal received at the data signal line Data to the gate g4 of the second transistor T20 in response to the scan signal received at the first scan signal line Gat1.

[0331] Exemplarily, as shown in FIG. 31, the second transistor T20 includes a gate g5, a source s5 and a drain d5, the source s5 of the second transistor T20 is electrically connected with the second reference voltage line VSS2, and the drain d5 of the second transistor T20 is electrically connected with the cathode of the second light emitting device 102. The second transistor T20 is configured to generate a driving current signal.

[0332] Exemplarily, as shown in FIG. 31, the third transistor T30 includes a gate, a first pole and a second pole, the gate of the third transistor T30 is electrically connected with the second scan signal line Gat2, the first pole of the third transistor T30 is electrically connected with the sensing signal line Sense, and the second pole of the third transistor T30 is electrically connected with the drain d5 of the second transistor T20. The third transistor T30 is configured to transmit the sensing signal received at the sensing signal line Sense to the drain d5 of the second transistor T20 in response to the scan signal received at the second scan signal line Gat2.

[0333] Exemplarily, as shown in FIG. 31, the second compensation circuit 662 further includes a capacitor Cst including a first pole plate Cst1 and a second pole plate Cst2, the first pole plate Cst1 of the capacitor Cst is electrically connected with the gate g4 of the second transistor T20, and the second pole plate Cst2 of the capacitor Cst is electrically connected with the drain d5 of the second transistor T20.

[0334] Exemplarily, as shown in FIG. 31, the anode of the first light emitting device 101 is electrically connected with the second power signal line VDD2.

[0335] In the above embodiment, through the setting of the first compensation circuit 661 and the second compensation circuit 662, external compensation is achieved to drive the normally-on light emitting device and the inverted light emitting device to emit light.

[0336] In some embodiments, as shown in FIG. 3, in the case that the display panel 100 includes a third light emitting device 103, the display panel 100 further includes a third pixel circuit 613 configured to be electrically connected with the third light emitting device 103, the third pixel circuit 613 being used for driving the third light emitting device 103 to emit light of a third color, and the third light emitting device 103 is located on a side of the third pixel circuit 613 away from the substrate 20.

[0337] Exemplarily, as shown in FIG. 3, a pixel circuit layer 60 is arranged between the substrate 20 and the plurality of light emitting devices 10, and the pixel circuit layer 60 includes a plurality of pixel circuits 61, the plurality of pixel circuits 61 including the first pixel circuit 611, the second pixel circuit 612 and the third pixel circuit 613.

[0338] By disposing the first light emitting device 101 on the side of the first pixel circuit 611 away from the substrate 20, the second light emitting device 102 on the side of the second pixel circuit 612 away from the substrate 20, and the third light emitting device 103 on the side of the third pixel circuit 613 away from the substrate 20, the upright light emitting device and the inverted light emitting device are disposed on the same plane on the side of the pixel circuit layer 60 away from the substrate 20, which is beneficial to the preparation of the light emitting device 10.

[0339] In some embodiments, as shown in FIG. 3 and FIG. 32, the film layer structure of the third light emitting device 103 is the same as that of the first light emitting device 101, that is, the third light emitting device 103 and the first light emitting device 101 are upright light emitting devices, and the third pixel circuit 613 includes: a third drive transistor T33, a gate g3 of the third drive transistor T33 is electrically connected with a third node O3, a source s1 of the third drive transistor T33 is electrically connected with a first voltage signal terminal Q1, a drain d3 of the third drive transistor T33 is electrically connected with a fifth electrode 31 of the third light emitting device 103, and a sixth electrode 32 of the third light emitting device 103 is electrically connected with a second voltage signal terminal Q2.

[0340] For example, the third drive transistor T33 is a P-type transistor.

[0341] The third pixel circuit 613 in some embodiments of the present disclosure can be a 7T1C, 8T1C or 9T1C circuit. In this embodiment, since the third light emitting device 103 and the first light emitting device 101 are both upright light emitting devices, the third pixel circuit 613 is used to drive the third light emitting device 103 to emit light, and the first pixel circuit 611 is used to drive the first light emitting device 101 to emit light, therefore, the third pixel circuit 613 can be understood by referring to the above description of the first pixel circuit 611, which will not be repeated here.

[0342] In some embodiments, as shown in FIG. 14 and FIG. 33, the film layer structure of the third light emitting device 103 is the same as that of the second light emitting device 102, that is, the third light emitting device 103 and the second light emitting device 102 are inverted light emitting devices, and the third pixel circuit 613 includes: a fourth drive transistor T34, a gate g4 of the fourth drive transistor T34 is electrically connected with a seventh node O7, a source s4 of the fourth drive transistor T34 is electrically connected with a third voltage signal terminal Q3, a drain d4 of the fourth drive transistor T34 is electrically connected with the fifth electrode 31 of the third light emitting device 103, and a sixth electrode 32 of the third light emitting device 103 is electrically connected with a fourth voltage signal terminal Q4.

[0343] For example, the fourth drive transistor T34 is an N-type transistor.

[0344] In this embodiment, since the third light emitting device 103 and the second light emitting device 102 are both inverted light emitting devices, the third pixel circuit 613 is configured to drive the third light emitting device 103 to emit light, and the second pixel circuit 612 is configured to drive the second light emitting device 102 to emit light. Therefore, the third pixel circuit 613 can be understood with reference to the above description of the second pixel circuit 612, and details are not repeated here.

[0345] By the first pixel circuit 611, the second pixel circuit 612 and the third pixel circuit 613, the normally-on light emitting device and the inverted light emitting device of the display panel 100 are driven to emit light, and full-color display of the display panel 100 is achieved.

[0346] Embodiments of the present disclosure also provide a method for manufacturing a display panel, as shown in FIGS. 34, 36-42, the method comprising steps R1-R4.

[0347] R1, providing a substrate 20.

[0348] R2, forming a first electrode 11 and a third electrode 21 on the same side of the substrate.

[0349] R3, sequentially forming a first hole transport layer 14, a first light emitting layer 13, a first electron transport layer 15 and a second electrode 12 on the side of the first electrode 11 away from the substrate 20 to obtain a first light emitting device 101, the first light emitting device 101 being configured to emit a first color.

[0350] R4, sequentially forming a second electron transport layer 25, a second light emitting layer 23, a second hole transport layer 24 and a fourth electrode 22 on the side of the third electrode 21 away from the substrate 20 to obtain a second light emitting device 102, the second light emitting device 102 being configured to emit a second color light, and forming a display panel 100.

[0351] Wherein, along a first direction Y perpendicular to the substrate 20 and away from the substrate 20, a dimension D1 between the first light emitting device 101 and the substrate 20 is substantially equal to a dimension D2 between the second light emitting device 102 and the substrate 20.

[0352] According to the above steps, the following specific embodiments of the method for manufacturing a display panel are provided.

[0353] In some examples, as shown in FIG. 35, the method comprises steps M1-M7.

[0354] M1, as shown in FIG. 36, providing a substrate 20.

[0355] Exemplarily, the substrate 20 can be an inorganic material, an organic material, a silicon wafer, a composite material layer, or the like. Exemplarily, the inorganic material can be glass, metal, or the like; and the organic material can be polycarbonate, polymethyl methacrylate, polyethylene terephthalate, polyethylene naphthalate, polyamide, polyether sulfone, or a combination thereof, or the like.

[0356] Exemplarily, as shown in FIG. 36, one side of the substrate 20 can be provided with a pixel circuit layer 60, and the pixel circuit layer 60 includes a plurality of pixel circuits 61, for example, the pixel circuits 61 include a first pixel circuit 611, a second pixel circuit 612, and a third pixel circuit 613.

[0357] M2, as shown in FIG. 36, a main body part 51 of the pixel defining layer 50 is formed on one side of the substrate 20, and the main body part 51 is provided with a plurality of openings K.

[0358] Exemplarily, the material of the pixel defining layer 50 can be polyimide.

[0359] M3, as shown in FIG. 36, the first electrode 11, the third electrode 21, and the fifth electrode 31 are formed, and the first electrode 11, the third electrode 21, and the fifth electrode 31 are one-to-one correspondingly arranged in the plurality of openings K.

[0360] Exemplarily, a plurality of bottom electrodes 202 are formed by a patterning process, and the plurality of bottom electrodes 202 are one-to-one correspondingly arranged in the plurality of openings K, and the plurality of bottom electrodes 202 include the first electrode 11, the third electrode 21, and the fifth electrode 31.

[0361] It should be noted that the "patterning process" of the embodiments of the present disclosure includes deposition, coating photoresist, mask exposure, development, etching, stripping photoresist, and the like for metal materials, inorganic materials, or transparent conductive materials, and includes coating organic materials, mask exposure, and development, and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating, and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited by the embodiments of the present disclosure.

[0362] Through this step, the first electrode 11, the third electrode 21, and the fifth electrode 31 can be formed synchronously on the same horizontal plane, which facilitates the preparation of the first electrode 11, the third electrode 21, and the fifth electrode 31, and the distance between the first electrode 11 and the substrate 20 in the first direction Y, the distance between the third electrode 21 and the substrate 20 in the first direction Y, and the distance between the fifth electrode 31 and the substrate 20 in the first direction Y are substantially equal.

[0363] M4, as shown in FIGS. 36-38, the first light-emitting layer 13 is formed on the side of the first electrode 11 away from the substrate 20.

[0364] Exemplarily, the material of the first light-emitting layer 13 and the material of the second light-emitting layer 23 and the material of the third light-emitting layer 33 comprise quantum dot materials. For example, the quantum dot materials comprise at least one of CdS, CdSe, ZnSe, ZnTeSe, InP, PbS, CsPbCl3, CsPbBr3, CsPbI3, CdS / ZnS, CdSe / ZnS, ZnSe, ZnSeTe, InP / ZnS, PbS / ZnS, CsPbCl3 / ZnS, CsPbBr3 / ZnS, CsPbI3 / ZnS, CdS / ZnSeS / ZnS, CdSe / ZnSeS / ZnS, ZnSe / ZnSeS / ZnS, ZnSeTe / ZnSeS / ZnS, InP / ZnS, PbS / ZnS, CsPbCl3 / ZnS, CsPbBr3 / ZnS and CsPbI3 / ZnS.

[0365] Exemplarily, the specific step of forming the first light-emitting layer 13 on the side of the first electrode 11 away from the substrate 20 comprises M41-M47.

[0366] M41, as shown in FIG. 36, a photoresist layer 80 is formed on the side of the bottom electrode 202 away from the substrate 20.

[0367] Exemplarily, the material of the photoresist layer 80 is a positive photoresist. The positive photoresist refers to a substance that is insoluble in some solvents, but becomes soluble after being exposed to light.

[0368] M42, as shown in FIG. 36, the photoresist layer 80 is exposed using a mask plate 90, and the photoresist layer 80 is formed into an exposed area photoresist 80b and a non-exposed area photoresist 80a.

[0369] Exemplarily, as shown in FIG. 3 and FIG. 36, the area where the exposed area photoresist 80b is located comprises an area where the first light-emitting device 101 is pre-formed.

[0370] Exemplarily, the mask plate 90 comprises a light-blocking area 90a and a plurality of openings 90b. The light-blocking area 90a blocks light from passing through, corresponding to the non-exposed area photoresist 80a in the photoresist layer 80. The plurality of openings 90b do not block light, corresponding to the exposed area photoresist 80b in the photoresist layer 80. After exposure, the photoresist layer 80 forms the non-exposed area photoresist 80a and the exposed area photoresist 80b corresponding to the positions of the light-blocking area 90a and the openings 90b of the mask plate 90.

[0371] M43, as shown in FIG. 36 and FIG. 37, the photoresist layer 80 is developed, and the exposed area photoresist 80b is removed.

[0372] Exemplarily, the photoresist layer 80 is developed by using a developing solution, the photoresist 80b in the exposed area is removed, and the photoresist 80a in the non-exposed area is reserved. The bottom electrode 202 exposed after the photoresist 80b in the exposed area is removed is the first electrode 11.

[0373] M44, as shown in FIG. 37, an initial first light-emitting layer 130 is formed on the side of the first electrode 11 away from the substrate 20.

[0374] Exemplarily, before the initial first light-emitting layer 130 is formed, an initial first hole injection layer 160 and an initial first hole transport layer 140 are also formed. For example, the initial first hole injection layer 160 is formed on the side of the first electrode 11 away from the substrate 20 by a deposition process, the initial first hole transport layer 140 is formed on the side of the initial first hole injection layer 160 away from the substrate 20, and the initial first light-emitting layer 130 is formed on the side of the initial first hole transport layer 140 away from the substrate 20.

[0375] M45, as shown in FIG. 37, the initial first light-emitting layer 130 is exposed, and an exposed-area first light-emitting layer 130A and a non-exposed-area first light-emitting layer 130B are formed.

[0376] Exemplarily, the initial first light-emitting layer 130 is exposed by using a mask plate, and the exposed-area first light-emitting layer 130A and the non-exposed-area first light-emitting layer 130B are formed.

[0377] M46, as shown in FIG. 38, the initial first light-emitting layer 130 is developed, the non-exposed-area first light-emitting layer 130B is removed, and the exposed-area first light-emitting layer 130A forms the first light-emitting layer 13.

[0378] Exemplarily, the initial first light-emitting layer 130 is developed by using a developing solution, the non-exposed-area first light-emitting layer 130B is removed, and the exposed-area first light-emitting layer 130A is reserved.

[0379] Exemplarily, due to the influence of the performance of the developing solution, etc., part of the non-exposed-area first light-emitting layer 130B is not removed.

[0380] M47, as shown in FIG. 38, the whole surface is exposed, the photoresist layer 80 and the film layer on the side of the photoresist layer 80 away from the substrate 20 are removed.

[0381] Exemplarily, the part of the initial first hole injection layer 160 on the side of the photoresist layer 80 away from the substrate 20 and the part of the initial first hole transport layer 140 on the side of the photoresist layer 80 away from the substrate 20 are removed. The part of the initial first hole injection layer 160 on the side of the first electrode 11 away from the substrate 20 forms the first hole injection layer 16, and the part of the initial first hole transport layer 140 on the side of the first electrode 11 away from the substrate 20 forms the first hole transport layer 14.

[0382] Exemplarily, the first light-emitting layer 130A is formed as the first light-emitting layer 13.

[0383] Through the steps M41-M47, the first light-emitting layer 13 is formed on the side of the first electrode 11 away from the substrate 20, and the first hole injection layer 16 and the first hole transport layer 14 are formed between the first light-emitting layer 13 and the first electrode 11.

[0384] M5, as shown in FIG. 38, a first film layer 150 is formed, which includes: the first electron transport layer 15 on the side of the first light-emitting layer 13 away from the substrate 20, the second electron transport layer 25 on the side of the third electrode 21 away from the substrate 20, the third electron transport layer 35 on the side of the fifth electrode 31 away from the substrate 20, and at least part of the auxiliary part 52 of the pixel defining layer 50 on the side of the main body part 51 away from the substrate 20.

[0385] Exemplarily, the first film layer 150 is formed through a deposition process.

[0386] In this step, the first electron transport layer 15, the second electron transport layer 25, and the third electron transport layer 35 are formed synchronously, and at least part of the auxiliary part 52 of the pixel defining layer 50 is formed synchronously. The auxiliary part 52 can include other film layers in addition to the part of the first film layer 150, for example, other functional layers in addition to the first electron transport layer 15, the second electron transport layer 25, and the third electron transport layer 35.

[0387] M6, as shown in FIG. 39, a second light-emitting layer 23 is formed on the side of the second electron transport layer 25 away from the substrate 20.

[0388] Exemplarily, the step of forming the second light-emitting layer 23 on the side of the second electron transport layer 25 away from the substrate 20 includes: M61-M63.

[0389] M61, as shown in FIG. 39, an initial second light-emitting layer 230 is formed on the side of the second electron transport layer 25 away from the substrate 20.

[0390] Exemplarily, the initial second light-emitting layer 230 is formed through a deposition process.

[0391] M62, as shown in FIG. 39, the initial second light-emitting layer 230 is exposed, forming an exposed area second light-emitting layer 230A and a non-exposed area second light-emitting layer 230B.

[0392] Exemplarily, the initial second light-emitting layer 230 is exposed through a mask plate, forming the exposed area second light-emitting layer 230A and the non-exposed area second light-emitting layer 230B.

[0393] M63, as shown in Fig. 39, developing the initial second light-emitting layer 230, removing the non-exposed area second light-emitting layer 230B, and forming the second light-emitting layer 23 from the exposed area second light-emitting layer 230A.

[0394] For example, the initial second light-emitting layer 230 is developed by using a developing solution, the non-exposed area second light-emitting layer 230B is removed, and the second light-emitting layer 23 is formed from the exposed area second light-emitting layer 230A.

[0395] For example, the non-exposed area second light-emitting layer 230B can be removed completely by using a developing solution with strong developing effect. For example, the developing solution is a weak alkaline solution, including a solution of tetramethylammonium hydroxide, tetrabutylammonium hydroxide, or potassium hydroxide. For example, the developing solution is a weak acid solution, including a solution of dilute hydrochloric acid or dilute nitric acid. For example, the developing solution is an organic system, which can be a mixed solution of at least one of n-octane, heptane, toluene, chlorobenzene, and propylene glycol methyl ether acetate, and at least one of oleylamine and oleic acid.

[0396] M7, as shown in Fig. 40, forming the third light-emitting layer 33 on the side of the third electron transport layer 35 away from the substrate 20, and forming the display panel 100.

[0397] For example, the step of forming the third light-emitting layer 33 on the side of the third electron transport layer 35 away from the substrate 20 includes M71-M73.

[0398] M71, as shown in Fig. 40, forming an initial third light-emitting layer 330 on the side of the third electron transport layer 35 away from the substrate 20.

[0399] For example, the initial third light-emitting layer 330 is formed by using a deposition process.

[0400] M72, as shown in Fig. 40, exposing the initial third light-emitting layer 330 to form the exposed area third light-emitting layer 330A and the non-exposed area third light-emitting layer 330B.

[0401] For example, the initial third light-emitting layer 330 is exposed by using a mask to form the exposed area third light-emitting layer 330A and the non-exposed area third light-emitting layer 330B.

[0402] M73, as shown in Fig. 40, developing the initial third light-emitting layer 330, removing the non-exposed area third light-emitting layer 330B, and forming the third light-emitting layer 33 from the exposed area third light-emitting layer 330A.

[0403] For example, the initial third light-emitting layer 330 is developed by using a developing solution, the non-exposed area third light-emitting layer 330B is removed, and the third light-emitting layer 33 is formed from the exposed area third light-emitting layer 330A.

[0404] Exemplarily, as shown in FIGS. 41 and 42, the step of forming the display panel 100 further comprises: M74.

[0405] M74, as shown in FIGS. 41 and 42, the second hole transport layer 24 and the second hole injection layer 26 are formed on the side of the second light-emitting layer 23 away from the substrate 20, and the third hole transport layer 34 and the third hole injection layer 36 are formed on the side of the third light-emitting layer 33 away from the substrate 20.

[0406] Exemplarily, as shown in FIG. 41, the second hole transport layer 24, the second hole injection layer 26, the third hole transport layer 34 and the third hole injection layer 36 are formed by using a printing process, for example, a current fluid printing process.

[0407] Exemplarily, as shown in FIG. 42, the second hole transport layer 24, the second hole injection layer 26, the third hole transport layer 34 and the third hole injection layer 36 are formed by using a patterning process. Meanwhile, the second layer 522 and the third layer 523 of the auxiliary part 52 are formed, the first layer 521 of the auxiliary part 52 is arranged in the same layer as the first electron transport layer 15, the second electron transport layer 25 and the third electron transport layer 35, the second layer 522 of the auxiliary part 52 is arranged in the same layer as the second hole transport layer 24 and the third hole transport layer 34, and the third layer 523 of the auxiliary part 52 is arranged in the same layer as the second hole injection layer 26 and the third hole injection layer 36.

[0408] In this step, the auxiliary part 52 of the pixel defining layer 50 is formed at the same time as the functional layers of the light-emitting device 10 are formed.

[0409] Exemplarily, as shown in FIG. 3, the step of forming the display panel 100 further comprises: forming the top electrode 203 and forming the encapsulation layer 401 on the side of the top electrode 203 away from the substrate 20, the top electrode 203 being the second electrode 12, the fourth electrode 22 and the sixth electrode 32.

[0410] The display panel 100 comprising: the first light-emitting device 101, the second light-emitting device 102 and the third light-emitting device 103 is prepared through the above steps M1-M7. In this method, the first light-emitting device 101 is formed first, and then the second light-emitting device 102 and the third light-emitting device 103 are formed. Among them, the first light-emitting device 101 is a normal light-emitting device, and the second light-emitting device 102 and the third light-emitting device 103 are inverted light-emitting devices.

[0411] Embodiments of the present disclosure further provide another method for preparing a display panel, as shown in FIG. 43, which comprises steps: N1-N7.

[0412] N1, as shown in FIG. 44, the substrate 20 is provided.

[0413] N2. As shown in FIG. 44, a main body part 51 of the pixel defining layer 50 is formed on one side of the substrate 20, and the main body part 51 is provided with a plurality of openings K.

[0414] N3. As shown in FIG. 44, the first electrode 11, the third electrode 21 and the fifth electrode 31 are formed, and the first electrode 11, the third electrode 21 and the fifth electrode 31 are arranged one by one in the plurality of openings K.

[0415] The content of step N1 is described with reference to step M1, the content of step N2 is described with reference to step M2, and the content of step N3 is described with reference to step M3, which will not be repeated here.

[0416] N4. As shown in FIGS. 44-46, the second light emitting layer 23 is formed on the side of the third electrode 21 away from the substrate 20.

[0417] For example, before forming the second light emitting layer 23, the method further comprises: forming a second electron transport layer 25 on the side of the third electrode 21 away from the substrate 20, and forming a third electron transport layer 35 on the side of the fifth electrode 31 away from the substrate 20.

[0418] For example, the steps of forming the second electron transport layer 25, the third electron transport layer 35 and the second light emitting layer 23 comprise N41-N47.

[0419] N41. As shown in FIG. 44, a photoresist layer 80 is formed on the side of the bottom electrode 202 away from the substrate 20.

[0420] N42. As shown in FIG. 44, the photoresist layer 80 is exposed using a mask plate 90, and the photoresist layer 80 is formed into an exposed area photoresist 80b and a non-exposed area photoresist 80a.

[0421] As shown in FIG. 4A and FIG. 44, the area where the exposed area photoresist 80b is located includes the area where the second light emitting device 102 and the third light emitting device 103 are to be formed.

[0422] N43. As shown in FIGS. 44 and 45, the photoresist layer 80 is developed, and the exposed area photoresist 80b is removed.

[0423] For example, the third electrode 21 and the fifth electrode 31 exposed after the exposed area photoresist 80b is removed.

[0424] N44. As shown in FIG. 45, a third film layer 153 is formed on the side of the third electrode 21 and the fifth electrode 31 away from the substrate 20, wherein the part of the third film layer 153 on the side of the third electrode 21 away from the substrate 20 forms the second electron transport layer 25, and the part of the third film layer 153 on the side of the fifth electrode 31 away from the substrate 20 forms the third electron transport layer 35.

[0425] That is, the second electron transport layer 25 and the third electron transport layer 35 can employ the same material.

[0426] N45, as shown in FIG. 45, an initial second light emitting layer 230 is formed on the side of the third film layer 153 away from the substrate 20.

[0427] N46, as shown in FIG. 46, the initial second light emitting layer 230 is exposed to form an exposed area second light emitting layer 230A and a non-exposed area second light emitting layer 230B.

[0428] N47, as shown in FIG. 46, the initial second light emitting layer 230 is developed to remove the non-exposed area second light emitting layer 230B, and the exposed area second light emitting layer 230A forms the second light emitting layer 23.

[0429] The second electron transport layer 25, the third electron transport layer 35 and the second light emitting layer 23 are formed through the above steps N41-N47.

[0430] N5, as shown in FIG. 46 and FIG. 47, a third light emitting layer 33 is formed on the side of the fifth electrode 31 away from the substrate 20.

[0431] It can be understood that after the third electron transport layer 35 is formed on the side of the fifth electrode 31 away from the substrate 20, the third light emitting layer 33 is located on the side of the third electron transport layer 35 away from the substrate 20.

[0432] Exemplarily, the step of forming the third light emitting layer 33 includes N51-N53.

[0433] N51, as shown in FIG. 46, an initial third light emitting layer 330 is formed on the side of the third electron transport layer 35 away from the substrate 20.

[0434] N52, as shown in FIG. 47, the initial third light emitting layer 330 is exposed to form an exposed area third light emitting layer 330A and a non-exposed area third light emitting layer 330B.

[0435] N53, as shown in FIG. 47, the initial third light emitting layer 330 is developed to remove the non-exposed area third light emitting layer 330B, and the exposed area third light emitting layer 330A forms the third light emitting layer 33.

[0436] N6, as shown in FIG. 47 and FIG. 48, a second film layer 152 is formed, and the second film layer 152 includes: the first hole injection layer 16 located on the side of the first electrode 11 away from the substrate 20, the second hole injection layer 26 located on the side of the second light emitting layer 23 away from the substrate 20, the third hole injection layer 36 located on the side of the third light emitting layer 33 away from the substrate 20, and at least part of the auxiliary part 52 of the pixel defining layer 50 located on the side of the main part 51 away from the substrate 20.

[0437] Exemplarily, before forming the second film layer 152, further comprising: forming a second hole transport layer 24 on the side of the second light emitting layer 23 away from the substrate 20 and a third hole transport layer 34 on the side of the third light emitting layer 33 away from the substrate 20.

[0438] Exemplarily, the steps of forming the second hole transport layer 24, the third hole transport layer 34 and the second film layer 152 comprise: N61-N64.

[0439] N61, as shown in FIG. 47, forming a fourth film layer 154 on the side of the second light emitting layer 23 and the third light emitting layer 33 away from the substrate 20, the fourth film layer 154 forms the second hole transport layer 24 on the side of the second light emitting layer 23 away from the substrate 20, and the fourth film layer 154 forms the third hole transport layer 34 on the side of the third light emitting layer 33 away from the substrate 20.

[0440] N62, as shown in FIG. 4A and FIG. 48, exposing the photoresist layer 80.

[0441] N63, as shown in FIG. 48, developing the photoresist layer 80, removing the photoresist layer 80 and the third film layer 153 and the fourth film layer 154 on the side of the photoresist layer 80 away from the substrate 20.

[0442] N64, as shown in FIG. 48, forming the second film layer 152 on the side of the fourth film layer 154 away from the substrate 20.

[0443] The second film layer 152 comprises: the first hole injection layer 16, the second hole injection layer 26 and the third hole injection layer 36, that is, the first hole injection layer 16, the second hole injection layer 26 and the third hole injection layer 36 are arranged in the same layer.

[0444] The second film layer 152 forms at least part of the auxiliary part 52 on the side of the main part 51 away from the substrate 20.

[0445] Therefore, in the embodiment of the present disclosure, the material of the auxiliary part 52 is the same as the material of at least one of the functional layers of the light emitting device 10.

[0446] N7, as shown in FIG. 49, forming the first light emitting layer 13 on the side of the first hole injection layer 16 away from the substrate 20, forming the display panel 100.

[0447] The steps of forming the first light emitting layer 13 can refer to the introduction of the content of step M4, which will not be described here.

[0448] Exemplarily, before forming the first light emitting layer 13, further comprising: forming a first hole transport layer 14 on the side of the first hole injection layer 16 away from the substrate 20.

[0449] Exemplarily, as shown in FIG. 4A and FIG. 49, after the first light-emitting layer 13 is formed, the method further comprises: forming a first electron transport layer 15 on the side of the first light-emitting layer 13 away from the substrate 20, and forming a top electrode 203 and an encapsulation layer 401.

[0450] Exemplarily, after the second film layer 152 is formed in step N6, the fourth electrode 22 and the sixth electrode 32 can be formed first, the fourth electrode 22 has a protective effect on the film layer between the fourth electrode 22 and the substrate 20, and the sixth electrode 32 has a protective effect on the film layer between the sixth electrode 32 and the substrate 20.

[0451] The display panel 100 is prepared through the above steps N1-N7, and the display panel 100 comprises: the first light-emitting device 101, the second light-emitting device 102, and the third light-emitting device 103. In the method, the second light-emitting device 102 and the third light-emitting device 103 are formed first, and then the first light-emitting device 101 is formed. Among them, the first light-emitting device 101 is a normal light-emitting device, and the second light-emitting device 102 and the third light-emitting device 103 are inverted light-emitting devices.

[0452] Through the above steps M1-M7 or steps N1-N7, the display panel 100 comprising the normal light-emitting device and the inverted light-emitting device can be formed, and the plurality of light-emitting devices 10 are located in the same plane, which facilitates the preparation of the display panel 100 comprising the light-emitting devices 10 of different types of structures.

[0453] As shown in FIG. 1 and FIG. 14, some embodiments of the present disclosure provide a display device 1000, which comprises: the display panel 100 as described in any of the above embodiments, and the display device 1000 further comprises: a driving chip 70, which is used to drive the display panel 100 to display.

[0454] The display device may, for example, be a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, a wearable display device, etc. The specific form of the display device is not specially limited in the embodiments of the present disclosure. The display device 1000 comprises the display panel 100 provided in any of the above embodiments. Therefore, the display device 1000 provided in the embodiments of the present disclosure has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be described here.

[0455] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed in the present disclosure, which shall be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: Substrate; Multiple light-emitting devices are located on the same side of the substrate; The plurality of light-emitting devices include: a first light-emitting device and a second light-emitting device, wherein the first light-emitting device is configured to emit light of a first color and the second light-emitting device is configured to emit light of a second color; Wherein, along a first direction perpendicular to the substrate and away from the substrate, the first light-emitting device includes a first electrode, a first hole transport layer, a first light-emitting layer, a first electron transport layer, and a second electrode stacked together; the second light-emitting device includes a third electrode, a second electron transport layer, a second light-emitting layer, a second hole transport layer, and a fourth electrode stacked together; in the first direction, the dimension between the first light-emitting device and the substrate is approximately equal to the dimension between the second light-emitting device and the substrate.

2. The display panel according to claim 1, wherein, The plurality of light-emitting devices further includes: a third light-emitting device, the third light-emitting device being configured to emit a third color light; The film structure of the third light-emitting device is the same as that of either the first light-emitting device or the second light-emitting device. The third light-emitting device includes a fifth electrode, a third electron transport layer, a third light-emitting layer, a third hole transport layer, and a sixth electrode. In the first direction, the dimension between the third light-emitting device and the substrate is approximately equal to the dimension between the first light-emitting device and the substrate.

3. The display panel according to claim 2, wherein, The film structure of the third light-emitting device is the same as that of the first light-emitting device, and the third electron transport layer and the first electron transport layer are disposed in the same layer. Along the first direction, the dimension between the first electron transport layer and the substrate is approximately equal to the dimension between the third electron transport layer and the substrate; the dimension between the second electron transport layer and the substrate is smaller than the dimension between the first electron transport layer and the substrate; or, The film structure of the third light-emitting device is the same as that of the second light-emitting device, and the third electron transport layer and the second electron transport layer are disposed in the same layer. Along the first direction, the dimension between the second electron transport layer and the substrate is approximately equal to the dimension between the third electron transport layer and the substrate; the dimension between the first electron transport layer and the substrate is greater than the dimension between the second electron transport layer and the substrate.

4. The display panel according to claim 2, wherein, The first electron transport layer, the second electron transport layer, and the third electron transport layer are disposed in the same layer.

5. The display panel according to claim 4, wherein, The materials of the first electron transport layer, the second electron transport layer, and the third electron transport layer are the same, and the materials of the first electron transport layer, the second electron transport layer, and the third electron transport layer are selected from at least one of zinc oxide, tin oxide, titanium oxide, gallium oxide, aluminum oxide, zinc gallium oxide, zinc tin oxide, zinc titanium oxide, zinc aluminum oxide, tin gallium oxide, and zinc tin gallium oxide.

6. The display panel according to claim 2, wherein, The film structure of the third light-emitting device is the same as that of the first light-emitting device, and the third hole transmission... The transport layer and the first hole transport layer are configured on the same layer. Along the first direction, the dimension between the first hole transport layer and the substrate is approximately equal to the dimension between the third hole transport layer and the substrate; the dimension between the second hole transport layer and the substrate is larger than the dimension between the first hole transport layer and the substrate; or, The film structure of the third light-emitting device is the same as that of the second light-emitting device, and the third hole transport layer and the second hole transport layer are disposed in the same layer. Along the first direction, the dimension between the second hole transport layer and the substrate is approximately equal to the dimension between the third hole transport layer and the substrate; The dimension between the first hole transport layer and the substrate is smaller than the dimension between the second hole transport layer and the substrate.

7. The display panel according to claim 2, wherein, The first hole transport layer, the second hole transport layer, and the third hole transport layer are configured on the same layer.

8. The display panel according to claim 2, wherein, The first light-emitting device further includes: a first hole injection layer, the first hole injection layer being located between the first electrode and the first hole transport layer; the second light-emitting device further includes: a second hole injection layer, the second hole injection layer being located between the second light-emitting layer and the fourth electrode; the third light-emitting device further includes: a third hole injection layer, the third hole injection layer being located between the third light-emitting layer and the sixth electrode; Wherein, the film structure of the third light-emitting device is the same as that of the first light-emitting device, and the third hole injection layer and the first hole injection layer are disposed in the same layer; along the first direction, the dimension between the first hole injection layer and the substrate is approximately equal to the dimension between the third hole injection layer and the substrate; the dimension between the second hole injection layer and the substrate is larger than the dimension between the first hole injection layer and the substrate; or, The film structure of the third light-emitting device is the same as that of the second light-emitting device, and the third hole injection layer and the second hole injection layer are disposed in the same layer; along the first direction, the dimension between the second hole injection layer and the substrate is approximately equal to the dimension between the third hole injection layer and the substrate; the dimension between the first hole injection layer and the substrate is smaller than the dimension between the second hole injection layer and the substrate.

9. The display panel according to claim 2, wherein, The first light-emitting device further includes: a first hole injection layer; the second light-emitting device further includes: a second hole injection layer; the third light-emitting device further includes: a third hole injection layer; The first hole injection layer, the second hole injection layer, and the third hole injection layer are disposed in the same layer.

10. The display panel according to claim 9, wherein, The materials of the first hole injection layer, the second hole injection layer, and the third hole injection layer are the same, and the materials of the first hole injection layer, the second hole injection layer, and the third hole injection layer are selected from at least one of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid), 4,4',4”-tris[2-naphthylphenylamino]triphenylamine, 4,4',4”-tris(N-3-methylphenyl-N-phenylamino)triphenylamine, molybdenum trioxide, copper phthalocyanine, tungsten oxide, nickel oxide, and vanadium oxide.

11. The display panel according to any one of claims 2 to 10, further comprising: A pixel defining layer is provided with multiple openings, and multiple light-emitting devices are disposed in the multiple openings one by one; The pixel defining layer includes a main body portion and an auxiliary portion located on the side of the main body portion away from the substrate; the material of the main body portion includes a first organic material, and the material of the auxiliary portion includes at least one of an inorganic material and a second organic material.

12. The display panel according to claim 11, wherein, The first light-emitting device includes a first hole injection layer; the second light-emitting device includes a second hole injection layer; and the third light-emitting device includes a third hole injection layer. The auxiliary part is made of the same material as at least one of the first hole injection layer, the first hole transport layer, the first electron transport layer, the second hole injection layer, the second hole transport layer, the second electron transport layer, the third hole injection layer, the third hole transport layer, and the third electron transport layer.

13. The display panel according to any one of claims 2 to 12, wherein, The second electrode, the fourth electrode, and the sixth electrode are connected together.

14. The display panel according to any one of claims 2 to 12, wherein, The third light-emitting device has the same film structure as the second light-emitting device; the fourth electrode and the sixth electrode are connected, and both the fourth electrode and the sixth electrode are spaced apart from the second electrode; or, The film structure of the third light-emitting device is the same as that of the first light-emitting device. The second electrode is connected to the sixth electrode, and both the second electrode and the sixth electrode are spaced apart from the fourth electrode.

15. The display panel according to claim 14, wherein, When the third light-emitting device and the second light-emitting device have the same film structure, the fourth electrode is disposed in the same layer as the sixth electrode and in a different layer from the second electrode; or, When the film structure of the third light-emitting device is the same as that of the first light-emitting device, the second electrode and the sixth electrode are disposed in the same layer, and the second electrode and the fourth electrode are disposed in a different layer.

16. The display panel according to claim 15, wherein, When the film structure of the third light-emitting device is the same as that of the second light-emitting device, in the orthogonal projection onto the substrate, the film layer containing the second electrode covers the film layers containing the fourth electrode and the sixth electrode. or, When the film structure of the third light-emitting device is the same as that of the first light-emitting device, in the orthogonal projection onto the substrate, the film layer containing the fourth electrode covers the film layers containing the second electrode and the sixth electrode.

17. The display panel according to claim 13 or 14, wherein, The second electrode, the fourth electrode, and the sixth electrode are disposed in the same layer.

18. The display panel according to any one of claims 14 to 17, wherein, When the film structure of the third light-emitting device is the same as that of the second light-emitting device, the fourth electrode and the sixth electrode are arranged alternately along the second direction, and a plurality of the second electrodes are arranged along the second direction; and the rows containing the fourth electrode and the sixth electrode are alternately arranged with the rows containing the plurality of the second electrodes along the third direction; or, When the third light-emitting device has the same film structure as the first light-emitting device, the second electrode and the sixth electrode are arranged alternately along the second direction, and a plurality of fourth electrodes are arranged along the second direction; and the second electrode The row containing the sixth electrode and the rows containing multiple fourth electrodes are alternately arranged along the third direction; Wherein, the second direction and the third direction are parallel to the plane where the substrate is located, and the second direction and the third direction intersect.

19. The display panel according to any one of claims 1 to 18, further comprising: A first pixel circuit and a second pixel circuit, wherein the first pixel circuit is configured to be electrically connected to the first light-emitting device and is used to drive the first light-emitting device to emit light of a first color, and the second pixel circuit is configured to be electrically connected to the second light-emitting device and is used to drive the second light-emitting device to emit light of a second color. The first light-emitting device is located on the side of the first pixel circuit away from the substrate, and the second light-emitting device is located on the side of the second pixel circuit away from the substrate.

20. The display panel according to claim 19, wherein, The first pixel circuit includes: a first driving transistor, the gate of the first driving transistor being electrically connected to a first node, the source of the first driving transistor being electrically connected to a first voltage signal terminal, the drain of the first driving transistor being electrically connected to a first electrode of the first light-emitting device, and a second electrode of the first light-emitting device being electrically connected to a second voltage signal terminal, wherein the voltage of the first voltage signal terminal is higher than the voltage of the second voltage signal terminal.

21. The display panel according to claim 20, wherein, The first driving transistor is a P-type transistor.

22. The display panel according to any one of claims 19 to 21, wherein, The second pixel circuit includes: a second driving transistor, the gate of the second driving transistor being electrically connected to a second node, the source of the second driving transistor being electrically connected to a third voltage signal terminal, the drain of the second driving transistor being electrically connected to a third electrode of the second light-emitting device, and a fourth electrode of the second light-emitting device being electrically connected to a fourth voltage signal terminal; the voltage of the third voltage signal terminal is less than the voltage of the fourth voltage signal terminal.

23. The display panel according to claim 22, wherein, The second driving transistor is an N-type transistor.

24. The display panel according to any one of claims 19 to 23, wherein, When the display panel includes a third light-emitting device, the display panel further includes a third pixel circuit, the third pixel circuit being configured to be electrically connected to the third light-emitting device, the third pixel circuit being used to drive the third light-emitting device to emit a third color light; The third light-emitting device is located on the side of the third pixel circuit away from the substrate.

25. The display panel according to claim 24, wherein, The film structure of the third light-emitting device is the same as that of the first light-emitting device. The third pixel circuit includes: a third driving transistor, the gate of which is electrically connected to a third node, the source of which is electrically connected to a first voltage signal terminal, the drain of which is electrically connected to a fifth electrode of the third light-emitting device, and a sixth electrode of which is electrically connected to a second voltage signal terminal; or, The film structure of the third light-emitting device is the same as that of the second light-emitting device. The third pixel circuit includes: a fourth driving transistor, the gate of which is electrically connected to the seventh node, the source of which is electrically connected to the third voltage signal terminal, and the drain of which is connected to the third light-emitting device. The fifth electrode of the third light-emitting device is electrically connected, and the sixth electrode of the third light-emitting device is electrically connected to the fourth voltage signal terminal.

26. The display panel according to claim 25, wherein, The third driving transistor is a P-type transistor; and / or, the fourth driving transistor is an N-type transistor.

27. A method for manufacturing a display panel, comprising: Provide substrate; A first electrode and a third electrode are formed on the same side of the substrate; A first hole transport layer, a first light-emitting layer, a first electron transport layer, and a second electrode are sequentially formed on the side of the first electrode away from the substrate to obtain a first light-emitting device, wherein the first light-emitting device is configured to emit a first color. A second electron transport layer, a second light-emitting layer, a second hole transport layer, and a fourth electrode are sequentially formed on the side of the third electrode away from the substrate to obtain a second light-emitting device. The second light-emitting device is configured to emit a second color light to form a display panel. The dimension between the first light-emitting device and the substrate is approximately equal to the dimension between the second light-emitting device and the substrate along a first direction perpendicular to and away from the substrate.

28. A display device, comprising: The display panel as described in any one of claims 1 to 26; A driver chip is used to drive the display panel to display.

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