Reference voltage source circuit and electronic device

Abstract

The invention discloses a reference voltage source circuit and an electronic device. The circuit comprises a pre-voltage-stabilizing module, a starting module and a band-gap reference module. The pre-voltage-stabilizing module is used for carrying out pre-voltage-stabilizing processing on the input voltage. The starting module provides starting current based on the pre-stabilized voltage output by the pre-stabilized voltage module. And the band-gap reference module is used for receiving the pre-stabilized voltage, establishing working bias according to the starting current and outputting a plurality of reference voltages with different voltage values. The Brokaw band-gap reference circuit solves the problems that a traditional Brokaw band-gap reference circuit is single in output voltage and the design complexity is increased due to the fact that an operational amplifier is used.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a reference voltage source circuit and electronic device. Background Technology

[0002] A reference voltage source is an important component in analog integrated circuits. Its function is to generate a stable reference voltage that is virtually unaffected by power supply voltage, temperature, and process technology. It is widely used in chips such as analog-to-digital converters (ADCs), low-dropout linear regulators (LDOs), and sensors. The basic operating principle of a bandgap reference circuit is based on the base-emitter voltage VN of an NPN transistor. BE The negative temperature coefficient and thermal voltage V T The positive temperature coefficients are mutually compensated to obtain a reference voltage with zero temperature coefficient.

[0003] The traditional Brokaw bandgap reference circuit generates a temperature-independent reference voltage by connecting the bases of two NPN transistors of unequal area and utilizing the virtual short characteristic of an operational amplifier (op-amp) to equalize the current in the two transistor branches. While the traditional Brokaw bandgap reference circuit can generate a stable reference voltage of approximately 1.24V, it has several drawbacks: firstly, it can only achieve a single-channel reference voltage output with a fixed output voltage, failing to meet the needs of multiple reference voltages in different applications; secondly, the use of an op-amp increases the complexity of the circuit design and also affects power consumption. Summary of the Invention

[0004] The purpose of this application is to provide a reference voltage source circuit and electronic device to solve the problems of traditional Brokaw bandgap reference circuits, which can only achieve single-channel reference voltage output with a fixed output voltage and increase circuit design complexity by using operational amplifiers.

[0005] To achieve the above objectives, this application adopts the following technical solution.

[0006] According to a first aspect of this application, embodiments of this application provide a reference voltage source circuit, the circuit comprising: The pre-regulator module is used to pre-regulate the input voltage. A startup module, coupled to the pre-regulator module, is used to provide a startup current based on the pre-regulated voltage output by the pre-regulator module; A bandgap reference module, coupled to the pre-regulator module and the startup module, is used to receive the pre-regulator voltage, establish a working bias based on the startup current, and output multiple reference voltages with different voltage values. The bandgap reference module includes a bandgap MOS transistor, a resistor divider network, and a first unit that are coupled to each other. The bandgap MOS transistor is used to form a feedback loop, the first unit is used to generate an output voltage, and the resistor divider network is used to form multiple output terminals to divide the output voltage and output reference voltages with different voltage values.

[0007] According to a second aspect of this application, embodiments of this application provide an electronic device that includes any of the reference voltage source circuits described in this application.

[0008] This application provides a reference voltage source circuit and electronic device. By employing a bandgap MOSFET, a first transistor, a second transistor, and multiple mirrored MOSFETs to form a loop in the bandgap reference module, and creating multiple output terminals at the source of the bandgap MOSFET through a resistor divider network, it achieves the generation of multiple reference voltage outputs with different voltage values ​​without using an operational amplifier. This not only simplifies the circuit and reduces design complexity but also ensures loop stability by ensuring that the negative feedback loop gain is greater than the positive feedback loop gain. Furthermore, the pre-regulator module of this application is based on Zener diodes and source followers for a wide range of voltage regulation. The input voltage is pre-regulated to improve the power supply rejection ratio of the reference voltage source. The startup module of this application provides startup current to the bandgap reference module when the power supply is turned on by detecting the output voltage status, which enables the circuit to get rid of the degenerate bias point and start reliably. After the circuit is working normally, it automatically shuts down to avoid additional power consumption. Thus, the circuit can operate stably in a wide input voltage range of 10V to 25V and output three reference voltages of about 1.24V, 2.4V and 3.3V to meet the needs of multiple reference voltages in different application scenarios. It has the characteristics of multiple output voltages, good circuit stability and high power supply rejection ratio. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is the circuit schematic of a traditional Brokaw bandgap reference circuit.

[0011] Figure 2 This is a circuit diagram of a reference voltage source circuit in one embodiment of this application.

[0012] Figure 3 This is a schematic diagram of the temperature characteristics simulation results of a reference voltage source circuit in one embodiment of this application.

[0013] Figure 4 This is a schematic diagram of the transient characteristic simulation results of a reference voltage source circuit in one embodiment of this application.

[0014] Figure 5 This is a schematic diagram of the loop stability simulation results of the reference voltage source circuit in one embodiment of this application.

[0015] Figure 6 This is a schematic diagram of the electronic device architecture in one embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] like Figure 1 The conventional Brokaw bandgap reference circuit shown includes two NPN transistors Q1 and Q2 with unequal areas (area ratio Q2:Q1 = 8:1), resistors R1, R2, and R3, and an operational amplifier serving as the error amplifier EA. The collectors of Q1 and Q2 are coupled to the power supply VDD through resistors R4 and R3, respectively, and are also coupled to the two input terminals (VDD, R4, and R3) of the operational amplifier. Y and V X The emitter of Q1 is grounded through resistor R1, and the emitter of Q2 is grounded through a series connection of resistor R2 and resistor R1; the output V of the operational amplifier... REF Feedback is given to the bases of Q1 and Q2. Based on the PN junction characteristics of bipolar junction transistors, when two transistors of different areas operate at the same current, the voltage difference ΔV between their base and emitter... BE =V T ln(n) increases linearly with temperature, exhibiting a positive temperature coefficient, where n is the area ratio (n=8), V T This is the thermal voltage. The virtual short characteristic of the operational amplifier makes V... X =V Y Based on the circuit connection, V can be obtained. BE1 =V BE2 +IR2, i.e., ΔV BE =IR2, thus determining the branch current I=ΔV BE / R2. Based on the virtual short characteristic of the op-amp and the symmetry design of the circuit, the current flowing through the two branches of Q1 and Q2 is the same, and the current flowing through R1 is I1 = 2I. From the analysis of the Q2 branch, the output voltage V can be obtained. REF =V BE2 +ΔV BE+2IR1=V BE2 +(1+2R1 / R2)ΔV BE .

[0018] To achieve a zero temperature coefficient, V needs to be... BE2 The negative temperature coefficient (approximately -1.5 mV / K) and (1+2R1 / R2)ΔV BE The positive temperature coefficient is compensated for. At room temperature T=300K, V BE2 ≈800mV, thermal voltage V T =kT / q≈26mV (temperature coefficient is +0.087mV / K), where k is the Boltzmann constant (1.38×10⁻⁶). -23 J / K), T is the absolute temperature, and q is the electron charge (1.6 × 10⁻⁶). -19 C). Due to ΔV BE =V T ln(n), whose temperature coefficient is ln(n)·(0.087mV / K), therefore, (1+2R1 / R2)ΔV BE The temperature coefficient is (1+2R1 / R2)ln(n)·(0.087mV / K). Let the absolute values ​​of the negative and positive temperature coefficients be equal, i.e., ((1+2R1 / R2)ln(n))·(0.087mV / K)=1.5mV / K, then (1+2R1 / R2)ln(n)≈17.2. Taking n=8 (ln(8)≈2.08), the resistance ratio can be determined as 1+2R1 / R2≈8.3, finally obtaining the reference voltage with zero temperature coefficient as V. REF =V BE2 +17.2V T ≈1.24V.

[0019] The researchers in this application discovered the following limitations of the traditional Brokaw bandgap reference circuit: First, it requires the use of an operational amplifier. This is because the virtual short characteristic of the op-amp is needed to ensure that the collector voltages of the two transistor branches are equal, thereby guaranteeing that the currents in the two branches are the same. This is a prerequisite for achieving temperature compensation. If the op-amp is removed, other methods are needed to establish a stable bias circuit and feedback loop. Second, the traditional Brokaw bandgap reference circuit outputs a fixed reference voltage of approximately 1.24V at only one node, which satisfies V BE2 The negative temperature coefficient and (1+2R1 / R2)ΔV BE To achieve full compensation of the positive temperature coefficient, the circuit needs to be improved if multiple outputs with different voltage values ​​are to be realized.

[0020] In view of the above, this application proposes a reference voltage source circuit, which includes a pre-regulation module, a startup module, and a bandgap reference module. The pre-regulation module pre-regulates the input voltage using a Zener diode and a source follower, providing pre-regulation over a wide input voltage range and improving the power supply rejection ratio of the entire circuit. The startup module includes multiple startup MOSFETs and an inverter, used to detect the voltage state at the output terminal when the power supply is turned on and provide a startup current to the bandgap reference module, enabling the circuit to escape the degenerate bias point and start reliably. It automatically shuts down after the circuit is operating normally to avoid additional power consumption. The bandgap reference module receives the pre-regulated voltage and establishes an operating bias based on the startup current, outputting reference voltages of different values. Further, the bandgap reference module includes mutually coupled bandgap MOSFETs, a resistor divider network, and a first unit; the bandgap MOSFETs form a feedback loop, the first unit generates the output voltage, and the resistor divider network forms multiple output terminals to divide the output voltage and output reference voltages of different values. Furthermore, the first transistor, second transistor, mirror MOSFET, resistors in the voltage divider network, and bandgap MOSFET in the first unit form a feedback loop. This feedback loop includes both negative and positive feedback loops. The loop gain of the negative feedback loop is greater than that of the positive feedback loop, thus ensuring loop stability. Additionally, the startup module provides a startup path to the loop by coupling to the source of the mirror MOSFET, the source of the bandgap MOSFET, and the base of the second transistor. Furthermore, the voltage divider network of the bandgap reference module is connected in series between the source of the bandgap MOSFET and ground. The first output of this voltage divider network has a low temperature coefficient characteristic. The second and third outputs (i.e., the source node of the bandgap MOSFET) are obtained from the first output through voltage division. Therefore, all three outputs have the same low temperature coefficient characteristic, thus achieving multi-channel reference voltage output without operational amplifiers.

[0021] See Figure 2 As shown, the reference voltage source circuit 1 in this embodiment may include a pre-stabilization module 10, a startup module 20, and a bandgap reference module 30.

[0022] The pre-regulator module 10 pre-regulates the input voltage VIN to obtain a pre-regulated output voltage, providing a stable power supply for the subsequent startup module 20 and bandgap reference module 30. The startup module 20, coupled to the pre-regulator module 10, provides a startup current to the bandgap reference module 30 by detecting the output voltage state when the power is on, enabling the circuit to overcome degenerate bias and start reliably. The bandgap reference module 30, coupled to the pre-regulator module 10 and the startup module 20, receives the pre-regulated voltage and establishes an operating bias based on the startup current, outputting reference voltages of different values. The bandgap reference module 30 may include a bandgap MOSFET M16, a resistor divider network, and a first unit, all coupled to each other. The bandgap MOSFET M16 forms a feedback loop, the first unit generates an output voltage (VREF), and the resistor divider network forms multiple output terminals to divide the output voltage and output reference voltages of different values. The bandgap reference module 30 can generate a reference voltage with a low temperature coefficient and form multiple output terminals through a resistor voltage divider network to output reference voltages of different values.

[0023] In this embodiment, the input voltage VIN ranges from 10V to 25V. The pre-regulator module 10 stabilizes this input voltage to approximately 5.3V. The bandgap reference module 30 includes multiple output terminals: a first output terminal VREF, a second output terminal V2D4, and a third output terminal V3D3. The first output terminal VREF outputs a reference voltage of approximately 1.24V, the second output terminal V2D4 outputs a reference voltage of approximately 2.4V, and the third output terminal V3D3 outputs a reference voltage of approximately 3.3V. All three output voltages exhibit low temperature coefficient characteristics and maintain good stability within a temperature range of -40℃ to 125℃.

[0024] The following will provide a more detailed explanation of the specific circuits and working principles of each module.

[0025] See Figure 2 The pre-regulator module 10 may include a Zener diode D1 and a Zener MOSFET M1. The Zener MOSFET M1 serves as a source follower.

[0026] In this embodiment, the pre-stabilized voltage module 10 may further include a first resistor R1, a first capacitor C1, and a second capacitor C2.

[0027] In this configuration, the cathode of Zener diode D1 is coupled to one end of the first resistor R1, while its anode is grounded. The other end of the first resistor R1 is coupled to the input voltage VIN. Zener MOSFET M1 is a DMOS transistor; its gate is coupled to the cathode of Zener diode D1, its source serves as the pre-regulated output terminal, and its drain is coupled to the input voltage VIN. The first capacitor C1 is coupled between the gate of Zener MOSFET M1 and ground, and the second capacitor C2 is coupled between the source of Zener MOSFET M1 and ground.

[0028] In this embodiment, Zener diode D1 utilizes its voltage regulation characteristics to stabilize the gate voltage of Zener MOSFET M1 at the Zener voltage value. When the input voltage VIN varies within the range of 10V to 25V, the first resistor R1 provides operating current to Zener diode D1. Zener diode D1 operates in the reverse breakdown region, and its cathode voltage remains relatively stable. This voltage serves as the gate voltage of Zener MOSFET M1. Zener MOSFET M1 operates in source follower mode, and its source voltage follows the gate voltage. Therefore, the source of the Zener MOSFET can obtain a stable output voltage of approximately 5.3V. The first capacitor C1 is used to filter out high-frequency noise at the gate node, and the second capacitor C2 is used to filter out ripple at the pre-regulated output terminal, improving the stability of the pre-regulated output.

[0029] In this embodiment, the Zener diode D1's stability characteristics are unaffected by input voltage variations, enabling it to provide a stable reference voltage for subsequent circuits. The source follower has low output impedance, providing sufficient drive capability. Furthermore, the pre-regulation module 10 improves the power supply rejection ratio (PSRR) of the reference voltage source circuit 1, allowing the subsequent bandgap reference module 30 to operate stably over a wide input voltage range.

[0030] In other embodiments, the Zener diode D1 in the pre-regulator module 10 can be replaced with other devices with voltage regulation characteristics. The Zener MOSFET M1 can be a DMOS transistor, an LDMOS transistor, or other types of power MOSFETs, as long as it can realize the source follower function and provide sufficient driving capability.

[0031] Continue reading Figure 2 In this embodiment, the startup module 20 may include multiple startup MOSFETs and an inverter INV, used to control the startup process by detecting the output voltage status when the power supply is powered on. The startup module 20 may include a first startup MOSFET M2, a second startup MOSFET M3, a third startup MOSFET M4, and an eighth startup MOSFET M9.

[0032] In some embodiments, the input terminal of inverter INV is coupled to a resistor divider network, and the output terminal of inverter INV is coupled to the gate of the third startup MOSFET M4; the gate and drain of the first startup MOSFET M2 and the gate of the second startup MOSFET M3 are coupled to each other, and the source of the first startup MOSFET M2 and the source of the second startup MOSFET M3 are both coupled to the pre-regulated output terminal of the pre-regulated module 10; the drain of the first startup MOSFET M2 is coupled to the drain of the third startup MOSFET M4; the drains of the second startup MOSFET M3 and the third startup MOSFET M4 are both coupled to ground; the source of the eighth startup MOSFET M9 is coupled to ground, the drain of the eighth startup MOSFET M9 is coupled to the first unit, and the gate of the eighth startup MOSFET M9 is coupled to the drain of the second startup MOSFET M3.

[0033] In some embodiments, the startup module 20 may further include a second resistor R2, which is coupled between the source and ground of the eighth startup MOSFET M9.

[0034] In some embodiments, the plurality of startup MOSFETs may further include: a fourth startup MOSFET M5, a fifth startup MOSFET M6, a sixth startup MOSFET M7, and a seventh startup MOSFET M8. The drain and gate of the fourth startup MOSFET M5 are coupled to the source of the third startup MOSFET M4, and the drain of the fourth startup MOSFET M4 is coupled to the drain of the sixth startup MOSFET M7; the drain of the fifth startup MOSFET M6 is coupled to the drain of the second startup MOSFET M3, the gate of the fifth startup MOSFET M6 is coupled to the first cell, and the source of the fifth startup MOSFET M6 is coupled to the drain of the seventh startup MOSFET M8; the gate of the sixth startup MOSFET M7 is coupled to the source of the fourth startup MOSFET M5, and the source of the sixth startup MOSFET M7 is grounded; the gate of the seventh startup MOSFET M8 is coupled to the source of the fifth startup MOSFET M6, and the source of the seventh startup MOSFET M8 is grounded.

[0035] Specifically, in Figure 2In the illustrated embodiment, the input terminal of the inverter INV is coupled to the third output terminal V3D3, and the output terminal is coupled to the gate of the third startup MOSFET M4. The gate and drain of the first startup MOSFET M2 and the gate of the second startup MOSFET M3 are mutually coupled. The sources of the first startup MOSFET M2 and the second startup MOSFET M3 are both coupled to the pre-regulated output terminal of the pre-regulated module 10. The drain of the first startup MOSFET M2 is coupled to the drain of the third startup MOSFET M4. The drain of the second startup MOSFET M3 is coupled to the gate of the eighth startup MOSFET M9 and the drain of the fifth startup MOSFET M6. The drain and gate of the fourth startup MOSFET M5 are coupled to the source of the third startup MOSFET M4. The drain and gate of the sixth startup MOSFET M7 are coupled to the source of the fourth startup MOSFET M5, and the source of the sixth startup MOSFET M7 is grounded. The drain and gate of the seventh startup MOSFET M8 are coupled to the source of the fifth startup MOSFET M6, and the source of the seventh startup MOSFET M8 is grounded. The drain of the fifth startup MOSFET M6 is coupled to the gate of the eighth startup MOSFET M9, and the gate of the fifth startup MOSFET M6 is coupled to the base of the second transistor Q2. The source of the eighth startup MOSFET M9 is coupled to one end of the second resistor R2, and its drain is coupled to the gates of the third mirror MOSFET M12 and the fourth mirror MOSFET M13, the drain of the third mirror MOSFET M12, and the drain of the fifth mirror MOSFET M14. The other end of the second resistor R2 is grounded.

[0036] Since conventional bandgap reference circuits may have a degenerate bias point, i.e., all transistors are in the off state and no current flows through the circuit, the circuit will enter the degenerate bias point after power-on and will not be able to start up and enter normal operation. Therefore, this application provides a startup module 20 to provide a startup path. When the power supply is initially turned on and the circuit has not yet started, the voltage of the third output terminal V3D3 is 0V, the input terminal of the inverter INV is low level, and the output terminal is high level. This high level is applied to the gate of the third startup MOSFET M4, and the third startup MOSFET M4 is turned on. The first startup MOSFET M2 and the second startup MOSFET M3 are current mirrors. When the third startup MOSFET M4 is turned on, a current path is formed through the first startup MOSFET M2 and the third startup MOSFET M4. The second startup MOSFET M3 mirrors the current of the first startup MOSFET M2, so it provides charging current to the gate of the eighth startup MOSFET M9 through the second startup MOSFET M3. At this time, the gate of the fifth startup MOSFET M6 is coupled to the base of the first transistor Q1 and the second transistor Q2. Since the circuit has not yet started, the base voltages of Q1 and Q2 have not yet been established, and the gate voltage of the fifth startup MOSFET M6 is 0V. Therefore, the fifth startup MOSFET M6 is in the off state and cannot affect the gate of the eighth startup MOSFET M9 through its drain. As the pre-regulated output voltage stabilizes and the charging current provided by the second startup MOSFET M3 increases, the gate voltage of the eighth startup MOSFET M9 gradually rises. When the gate-source voltage of the eighth startup MOSFET M9 (V... GS When the voltage exceeds its threshold voltage, the eighth startup MOSFET M9 turns on, and the drain voltage of the eighth startup MOSFET M9 (i.e., the gate voltage of the third mirror MOSFET M12 and the fourth mirror MOSFET M13) is pulled low, causing the bandgap reference module 30 to start working. After the bandgap reference module 30 starts working, the first output terminal VREF gradually builds up a voltage of about 1.24V, and through the resistor voltage divider network, the third output terminal V3D3 gradually builds up a voltage of about 3.3V. At this time, the input terminal of the inverter INV becomes high level, the output terminal becomes low level, and the third startup MOSFET M4 turns off. Since the gate of the fifth startup MOSFET M6 is coupled to the base of the first transistor Q1 and the second transistor Q2, and the bases of the first transistor Q1 and the second transistor Q2 are coupled to the first output terminal VREF, when the base voltages of the first transistor Q1 and the second transistor Q2 rise to approximately 1.24V, the fifth startup MOSFET M6 turns on, pulling the gate voltage of the eighth startup MOSFET M9 down to near ground potential, thus turning off the eighth startup MOSFET M9. At this time, both the third startup MOSFET M4 and the eighth startup MOSFET M9 are in the off state. The startup module 20 completes the startup task, the startup path is completely disconnected, and startup power consumption is no longer consumed. The entire circuit will maintain a stable operating state through the feedback loop of the bandgap reference module 30.

[0037] This application enables the circuit to start from the degenerate bias point through the aforementioned startup module 20, and automatically disconnects the startup path after startup is completed to stop consuming startup power. Furthermore, it implements simple and reliable startup control logic by detecting the voltage state of the third output terminal V3D3 and using an inverter.

[0038] In other embodiments, the specific number and connection method of the startup MOS transistors in the startup module 20 can be adjusted as needed, as long as they can provide startup current when the power is turned on and automatically shut down after the circuit is working normally.

[0039] Continue reading Figure 2 In this embodiment, the bandgap reference module 30 is coupled to the pre-regulator module 10 and the startup module 20 to generate a low temperature coefficient reference voltage and achieve multiple outputs through a resistor divider network. The first unit of the bandgap reference module 30 may include a first transistor Q1, a second transistor Q2, and multiple mirrored MOSFETs.

[0040] In some embodiments, the plurality of mirrored MOSFETs may include a first mirrored MOSFET M10, a second mirrored MOSFET M11, a third mirrored MOSFET M12, a fourth mirrored MOSFET M13, a fifth mirrored MOSFET M14, and a sixth mirrored MOSFET M15. The plurality of resistors may include a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The resistor divider network includes the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 connected in series. The sources of the first mirrored MOSFET M10 and the second mirrored MOSFET M11 are both coupled to the pre-regulated output terminal of the pre-regulated module 10, and their drains are respectively coupled to the sources of the third mirrored MOSFET M12 and the fourth mirrored MOSFET M13. The gate and drain of the first mirrored MOSFET M10 are coupled together, and the gate of the second mirrored MOSFET M11 is coupled to the gate of the first mirrored MOSFET M11. The gate and drain of the third mirror MOSFET M12 are coupled. The gate of the fourth mirror MOSFET M13 is coupled to the gate of the third mirror MOSFET M12. The drain of the third mirror MOSFET M12 is coupled to the drain of the fifth mirror MOSFET M14. The drain of the fourth mirror MOSFET M13 is coupled to the drain of the sixth mirror MOSFET M15. The base of the first transistor Q1 is coupled to the base of the second transistor Q2. The collector of the first transistor Q1 is coupled to the source of the sixth mirror MOSFET M15. The collector of the second transistor Q2 is coupled to the source of the fifth mirror MOSFET M14. The emitters of the first transistor Q1 and the second transistor Q2 are coupled to ground. The gate and drain of the sixth mirror MOSFET M15 are coupled. The drain of the bandgap MOSFET M16 is coupled to the pre-regulated output terminal of the pre-regulated module 10, the gate is coupled to the drain of the fourth mirror MOSFET M13, and the source is coupled to the resistor divider network.

[0041] In some embodiments, the bandgap reference module 30 may further include a third resistor R3 and a compensation capacitor C3. The compensation capacitor C3 is coupled between the source of the bandgap MOSFET M16 and ground. The third resistor R3 is coupled between the base of the first transistor Q1 and the base of the second transistor Q2.

[0042] In some embodiments, the bandgap reference module 30 may further include a fourth resistor R4 and a fifth resistor R5. One end of the fourth resistor R4 is coupled to the emitter of the first transistor Q1 and one end of the fifth resistor R5, and the other end of the fourth resistor R4 is coupled to the emitter of the second transistor Q2; the other end of the fifth resistor R5 is grounded.

[0043] In some embodiments, the resistor divider network may include a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. One end of the sixth resistor R6 is coupled to the source of the bandgap MOSFET M16 and serves as the third output terminal of the bandgap reference module 30. The other end of the sixth resistor R6 is coupled to one end of the seventh resistor R7 and serves as the second output terminal of the bandgap reference module 30. The other end of the seventh resistor R7 is coupled to one end of the eighth resistor R8 and serves as the first output terminal of the bandgap reference module 30. The other end of the eighth resistor R8 is grounded. The other end of the seventh resistor R7 is also coupled to the base of the first transistor Q1.

[0044] Furthermore, the feedback loop can include a negative feedback loop and a positive feedback loop. The negative feedback loop is formed by the bandgap MOSFET M16, the sixth resistor R6, the seventh resistor R7, the first transistor Q1, and the sixth mirror MOSFET M15. The positive feedback loop is formed by the bandgap MOSFET M16, the sixth resistor R6, the seventh resistor R7, the third resistor R3, the second transistor Q2, the fifth mirror MOSFET M14, the third mirror MOSFET M12, and the fourth mirror MOSFET M13. The loop gain of the negative feedback loop is greater than the loop gain of the positive feedback loop.

[0045] Specifically, in Figure 2 In the illustrated embodiment, the sources of the first mirror MOSFET M10 and the second mirror MOSFET M11 are coupled to the pre-regulated output terminal of the pre-regulated module 10, and their drains are coupled to the sources of the third mirror MOSFET M12 and the fourth mirror MOSFET M13, respectively. The gate and drain of the first mirror MOSFET M10 are coupled, and the gate of the second mirror MOSFET M11 is coupled to the gate of the first mirror MOSFET M10.

[0046] In this embodiment, the gate and drain of the third mirror MOSFET M12 are coupled together, and the gate of the fourth mirror MOSFET M13 is coupled to the gate of the third mirror MOSFET M12. The drain of the third mirror MOSFET M12 is coupled to the drains of the fifth mirror MOSFET M14 and the eighth startup MOSFET M9. The drain of the fourth mirror MOSFET M13 is coupled to the drain and gate of the sixth mirror MOSFET M15 and the gate of the bandgap MOSFET M16. The gate of the fifth mirror MOSFET M14 is coupled to the gate of the sixth mirror MOSFET M15, its source is coupled to the collector of the second transistor Q2, and its drain is coupled to the drain of the eighth startup MOSFET M9, the drain of the third mirror MOSFET M12, and its gate. The gate of the sixth mirror MOSFET M15 is coupled to its drain, and the sixth mirror MOSFET M15 and the fifth mirror MOSFET M14 are current mirrors. The source of the sixth mirror MOSFET M15 is coupled to the collector of the first transistor Q1, and the drain is coupled to the gate of the bandgap MOSFET M16 and the drain of the fourth mirror MOSFET M13.

[0047] In this embodiment, the drain of the bandgap MOSFET M16 is coupled to the pre-regulated output terminal of the pre-regulated module 10, the gate is coupled to the drain of the fourth mirror MOSFET M13, the drain of the sixth mirror MOSFET M15, and the gate, and the source is coupled to one end of the resistor divider network and the compensation capacitor C3. The base of the first transistor Q1 is coupled to one end of the third resistor R3, and the base of the second transistor Q2 is coupled to the other end of the third resistor R3. The collector of the first transistor Q1 is coupled to the source of the sixth mirror MOSFET M15, and the emitter is coupled to one end of the fourth resistor R4 and one end of the fifth resistor R5. The collector of the second transistor Q2 is coupled to the source of the fifth mirror MOSFET M14, and the emitter is coupled to the other end of the fourth resistor R4. The other end of the fifth resistor R5 is grounded and coupled to the other end of the compensation capacitor C3 and the eighth resistor R8.

[0048] In this embodiment, the compensation capacitor C3 is coupled between the source of the bandgap MOSFET M16 and ground for loop compensation. In this embodiment, the capacitance of the compensation capacitor C3 is 8pF, which is determined based on a comprehensive consideration of layout area, response speed, and loop stability.

[0049] In this embodiment, the resistor divider network includes a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8 connected in series. This resistor divider network is coupled to the source of the bandgap MOSFET M16. The first output terminal VREF is coupled to the node between the seventh resistor R7 and the eighth resistor R8. The second output terminal V2D4 is coupled to the node between the sixth resistor R6 and the seventh resistor R7. The third output terminal V3D3 is coupled to the node between the source of the bandgap MOSFET M16 and the sixth resistor R6, and is also coupled to one end of the compensation capacitor C3. In this embodiment, the resistance of the sixth resistor R6 is 22kΩ, the resistance of the seventh resistor R7 is 28kΩ, and the resistance of the eighth resistor R8 is 30kΩ. Based on the above resistor ratios, the first output terminal VREF outputs a reference voltage of approximately 1.24V, the second output terminal V2D4 outputs a reference voltage of approximately 2.4V, and the third output terminal V3D3 outputs a reference voltage of approximately 3.3V.

[0050] The bandgap reference module 30 of this application is based on the temperature compensation concept of the traditional Brokaw bandgap reference circuit, but adopts an op-amp-free structure. It establishes bias through a current mirror and ensures that the branch currents are equal, forming a negative feedback loop and a positive feedback loop to ensure the stability of the output voltage.

[0051] In this embodiment, the first mirror MOSFET M10, the second mirror MOSFET M11, the third mirror MOSFET M12, and the fourth mirror MOSFET M13 form a common-source, common-gate current mirror. The drain voltage of M13 controls the conduction level of the bandgap MOSFET M16. The fifth mirror MOSFET M14 and the sixth mirror MOSFET M15 also constitute current mirrors, providing collector currents for the second transistor Q2 and the first transistor Q1, respectively, ensuring that the collector currents of Q1 and Q2 are equal, thereby satisfying the temperature compensation condition.

[0052] As mentioned earlier, to ensure layout matching, the emitter area ratio of the first transistor Q1 and the second transistor Q2 is set to 1:8. The base coupling of the first transistor Q1 and the second transistor Q2 has almost the same base voltage; the base-emitter voltage of the second transistor Q2 is defined as V. BE2 The base-emitter voltage of the first transistor Q1 is V. BE1 Under the condition of equal collector current, the different emitter areas result in different current densities. According to semiconductor theory, the base-emitter voltage difference ΔV between two transistors with an area ratio of n is... BE =V T ln(n), where n=8, V T This is the thermal voltage. According to the circuit connections, the emitter of the second transistor Q2 is grounded through the fourth resistor R4 and the fifth resistor R5 connected in series, while the emitter of the first transistor Q1 is grounded through the fifth resistor R5. The voltage difference between the emitter of the second transistor Q2 and the emitter of the first transistor Q1 is ΔV. BE The current flowing through the fourth resistor R4 is I = ΔV. BE / R4=V T ln(8) / R4, the current continues to flow through the fifth resistor R5, and at the same time the emitter current of the first transistor Q1 also flows through R5. Therefore, the sum of the emitter currents of the first transistor Q1 and the second transistor Q2 flowing through the fifth resistor R5 is equal to the sum of the emitter currents of the second transistor Q1 and the first transistor Q2 flowing through the fifth resistor R5.

[0053] In this embodiment, temperature compensation is achieved at the first output terminal VREF of the resistor divider network through the configuration of resistors R4 and R5. The voltage at the first output terminal VREF can be expressed as V. REF =V BE2 +(1+2R4 / R5)ΔV BE =V BE2 +αΔV BE α is determined by the ratio of resistors R4 and R5. BE2 It has a negative temperature coefficient of approximately -1.5 mV / K, ΔV BE =V T ln(8) has a positive temperature coefficient, where V TThe temperature coefficient of kT / q is +0.087 mV / K. By properly configuring the resistance ratio, αΔV... BE The positive temperature coefficient and V BE2 The negative temperature coefficients cancel each other out, thus giving the first output terminal VREF a zero temperature coefficient characteristic and outputting a reference voltage of approximately 1.24V, which is the same as the output voltage of a traditional Brokaw bandgap reference circuit, satisfying the theoretical value of silicon bandgap voltage.

[0054] In this embodiment, this application implements multiple reference voltage outputs through a resistor divider network. The voltage divider network includes a sixth resistor R6 (22kΩ), a seventh resistor R7 (28kΩ), and an eighth resistor R8 (30kΩ) connected in series, coupled between the source of the bandgap MOSFET M16 and ground. The first output terminal VREF is coupled to the node between the seventh resistor R7 and the eighth resistor R8, the second output terminal V2R2 is coupled to the node between the sixth resistor R6 and the seventh resistor R7, and the third output terminal V3D3 is coupled to the node between the sixth resistor and the source of M16. Based on the first output terminal VREF, which has a zero temperature coefficient, the other two output voltages can be obtained through the resistor divider relationship. The voltage of the second output terminal V2D4 is V2D4 = (VREF / R8)·(R7+R8). Since R7+R8 = 58kΩ and R8 = 30kΩ, V2D4 ≈ 2.4V. The voltage at the third output terminal V3D3 is V3D3 = (VREF / R8)·(R6+R7+R8). Since R6+R7+R8 = 80kΩ, V3D3 is approximately 3.3V.

[0055] Furthermore, since the second output terminal V2D4 and the third output terminal V3D3 are both obtained through resistor voltage division based on the first output terminal VREF, which has a low temperature coefficient, the three output voltages have the same low temperature coefficient characteristics. Within a temperature range of -40℃ to 125℃, all three output voltages maintain good stability, meeting the requirements of various application scenarios for multiple reference voltages.

[0056] In this embodiment, the bandgap MOSFET M16, the sixth resistor R6, the seventh resistor R7, the first transistor Q1, and the sixth mirror MOSFET M15 constitute a negative feedback loop. When the gate voltage of the bandgap MOSFET M16 increases, M16 acts as a source follower, thus increasing the source voltage of M16. Consequently, the base voltage of the first transistor Q1 increases, and the collector voltage of Q1 decreases, meaning the source voltage of the sixth mirror MOSFET M15 decreases. Since the sixth mirror MOSFET M15 uses a diode connection, its drain voltage decreases, which reduces the gate-source voltage of the bandgap MOSFET M16, weakening its conduction capability. This suppresses further increases in the source voltage of the bandgap MOSFET M16, forming negative feedback.

[0057] In this embodiment, the bandgap MOSFET M16, the sixth resistor R6, the seventh resistor R7, the third resistor R3, the second transistor Q2, the fifth mirror MOSFET M14, the third mirror MOSFET M12, and the fourth mirror MOSFET M13 form a positive feedback loop. When the gate voltage of the bandgap MOSFET M16 increases, M16 acts as a source follower, thus increasing the source voltage of M16. Consequently, the base voltage of the second transistor Q2 also increases, and the base and collector voltages of Q2 are in opposite phase (i.e., changing in opposite directions), causing the collector voltage of Q2 to decrease. Since the fifth mirror MOSFET M14 has no effect on the feedback polarity in this loop, the drain voltage of the third mirror MOSFET M12 decreases, which in turn decreases the gate voltage of the fourth mirror MOSFET M13. Because M13 is a PMOS transistor, its conduction capability is enhanced, increasing the drain voltage of M13. This, in turn, increases the gate-source voltage of M16, enhancing its conduction capability and further increasing the source voltage of M16, thus forming positive feedback.

[0058] To ensure circuit stability, the loop gain of the negative feedback loop needs to be greater than that of the positive feedback loop. In this embodiment, the gate nodes of the third mirror MOSFET M12 and the fourth mirror MOSFET M13 are high-impedance nodes. This high-impedance characteristic makes it easier for the negative feedback loop to meet the condition that its gain is greater than that of the positive feedback loop. The compensation capacitor C3 is placed between the source of the bandgap MOSFET M16 and ground. This 8pF capacitor is used to adjust the phase margin of the loop. By adjusting the position of the poles in the loop, the frequency characteristics of the loop are improved, achieving a phase margin of approximately 60 degrees, thereby ensuring stable operation of the circuit under different process angles and temperature conditions.

[0059] In other embodiments, the number of current mirrors and their configuration in the bandgap reference module 30 can be adjusted to meet different performance requirements and process conditions. Furthermore, the position of the compensation capacitor C3 can also be adjusted to ensure loop stability.

[0060] The following will further describe the process of the circuit from power-on to stable operation.

[0061] When the input voltage VIN rises from 0V, the pre-regulator module 10 starts to work. When VIN reaches the breakdown voltage of Zener diode D1 plus a certain margin, D1 enters the reverse breakdown region. Through the source follower action of Zener MOSFET M1, the source of M1 generates a pre-regulated output voltage of approximately 5.3V.

[0062] In the initial stage of circuit startup, since the bandgap reference module 30 has not yet established its operating current, the voltages at the first output terminal VREF, the second output terminal V2D4, and the third output terminal V3D3 are all 0V. At this time, the input terminal of the inverter INV (coupled to the third output terminal V3D3) is at a low level, and the output terminal is at a high level, causing the third startup MOSFET M4 to conduct. The first startup MOSFET M2 and the second startup MOSFET M3 form a current mirror. When the third startup MOSFET M4 conducts, a current path is formed from the pre-regulated output terminal through the first startup MOSFET M2, the third startup MOSFET M4, the fourth startup MOSFET M5, and the sixth startup MOSFET M7. M3 mirrors the current flowing through M2 and provides charging current to the gate of the eighth startup MOSFET M9. As the pre-regulated output voltage stabilizes, the gate voltage of the eighth startup MOSFET M9 gradually increases. When the gate-source voltage of M9 exceeds its threshold voltage, M9 turns on, pulling down the gate voltages of the third mirror MOSFET M12 and the fourth mirror MOSFET M13, causing M12 and M13 to turn on and start the operation of the bandgap reference module 30. Since M12 and M13 are current mirrors, current begins to flow through M13. The drain of M13 is coupled to the drain and gate of M15 (M15 is connected by a diode), and M14 and M15 are also current mirrors. Therefore, current begins to flow through the branches of the first transistor Q1 and the second transistor Q2. Simultaneously, the drain of M13 is coupled to the gate of the bandgap MOSFET M16, causing the gate voltage of M16 to increase. When the gate-source voltage of M16 (V...)... GS When the voltage exceeds its threshold voltage, M16 begins to work normally.

[0063] During startup, the first mirror MOSFET M10 and the second mirror MOSFET M11 provide current from the pre-regulated output terminal. Through the current mirror effect, the currents in the two branches are made equal, and the circuit gradually enters a stable operating point. At this time, the first output terminal VREF stabilizes at approximately 1.24V, the second output terminal V2D4 stabilizes at approximately 2.4V, and the third output terminal V3D3 stabilizes at approximately 3.3V. When the voltage at the third output terminal V3D3 rises to approximately 3.3V, the input terminal of the inverter INV becomes high and the output terminal becomes low, causing the third startup MOSFET M4 to turn off. Since the base voltages of Q1 and Q2 are already approximately 1.24V, the fifth startup MOSFET M6 is turned on, pulling down the gate voltage of the eighth startup MOSFET M9, causing M9 to turn off. At this point, the startup module 20 completely exits and no longer consumes power.

[0064] Subsequently, the circuit maintains stable operation relying on the negative and positive feedback loops of the bandgap reference module 30. Since the gain of the negative feedback loop is greater than that of the positive feedback loop, the circuit of this application can maintain balance at a stable operating point. Even if external conditions such as temperature or power supply voltage change, the circuit can automatically adjust through the feedback mechanism to maintain a stable output voltage.

[0065] See Figures 3 to 5 As shown, the reference voltage source circuit 1 of this application exhibits good performance in terms of temperature characteristics, power supply rejection ratio, and loop stability.

[0066] Regarding temperature characteristics, the circuit of this application was simulated and verified using circuit simulation tools at 27℃ and TT process corner. For example... Figure 3 The simulation results show that, within a temperature range of -40℃ to 125℃, the first output terminal VREF, the second output terminal V2D4, and the third output terminal V3D3 all exhibit low temperature coefficient characteristics. The temperature coefficients of the three output voltages are essentially the same because all three outputs are obtained through resistor voltage division based on the same reference node that meets the temperature compensation conditions. Compared to the traditional Brokaw bandgap reference circuit, which can only achieve one reference voltage output with a fixed output voltage of 1.24V, this application achieves multiple outputs and meets the needs of different application scenarios.

[0067] Regarding power supply rejection ratio (PSRR), this application improves the PSRR of the output voltage of the reference voltage source circuit 1 by designing a pre-regulator module 10. Specifically, a wide-range input voltage from 10V to 25V is stabilized to approximately 5.3V using a Zener diode D1 and a source follower. Figure 4 The simulation results show that the three output voltages remain stable as the input voltage changes from 10V to 25V, enabling the circuit of this application to be used in application scenarios with a wide input voltage range.

[0068] Regarding loop stability, this application ensures output voltage stability through a loop formed by a bandgap MOSFET M16, a first transistor Q1, a second transistor Q2, and multiple mirror MOSFETs, where both negative and positive feedback loops exist simultaneously. To guarantee circuit stability, the gate nodes of the third mirror MOSFET M12 and the fourth mirror MOSFET M13 are high-impedance nodes, making it easier for the negative feedback loop to satisfy the condition that its gain is greater than that of the positive feedback loop. Furthermore, to adjust the loop's phase margin, a compensation capacitor C3 is placed between the source of the bandgap MOSFET M16 and ground, with a capacitance value of 8pF. This capacitance value is determined based on a comprehensive consideration of layout area, response speed, and phase margin. Figure 5The simulation results show that the phase margin of the loop is 59 degrees (approximately 60 degrees) at the tt process angle, ensuring that the circuit can work stably under various process angles and temperature conditions.

[0069] In terms of power consumption and layout area, this application adopts an op-amp-less structure, eliminating the operational amplifiers and their required bias and compensation circuits found in traditional Brokaw bandgap reference circuits, thus reducing the number of transistors and layout area. Furthermore, the startup module 20 automatically shuts down after completing the startup task, consuming no additional power.

[0070] It should be noted that the terms "bandgap MOSFET," "mirror MOSFET," "zener MOSFET," and "startup MOSFET" used in this article essentially all refer to MOSFETs (including PMOS and NMOS transistors). The above naming convention is intended to differentiate MOSFETs based on their position or function in the circuit, facilitating description and understanding, and is not intended to impose any special limitations on the devices themselves.

[0071] The reference voltage source circuit 1 described in this application solves the problems of traditional Brokaw bandgap reference circuits, which can only achieve single-channel reference voltage output with a fixed output voltage and increase circuit design complexity by using operational amplifiers. Furthermore, it achieves the following technical effects: The loop formed by the bandgap MOSFET, the first transistor, the second transistor, and multiple MOSFETs ensures output voltage stability. The negative feedback loop gain is greater than the positive feedback loop gain, guaranteeing loop stability, thus simplifying circuit design, reducing complexity, and decreasing layout area and power consumption. The source-coupled resistor voltage divider network of the bandgap MOSFET forms the first, second, and third output terminals, respectively outputting reference voltages of approximately 1.24V, 2.4V, and 3.3V, achieving multi-channel reference voltage output. Since the three outputs are based on a single low-temperature... The nodes with low temperature coefficient characteristics are obtained through resistor voltage division. They all have the same low temperature coefficient characteristics, thus meeting the requirements of multiple reference voltages in different application scenarios. The pre-regulation module, based on Zener diodes and source followers, pre-regulates a wide range of input voltages from 10V to 25V, improving the power supply rejection ratio of the reference voltage source and enabling the circuit to operate stably in application scenarios with large input voltage fluctuations. The startup module detects the output voltage status and provides startup current to the bandgap reference module when the power supply is turned on, enabling the circuit to break free from the degenerate bias point and start up. It automatically shuts down after startup to avoid additional power consumption. The circuit maintains good temperature stability in a temperature range of -40℃ to 125℃. The temperature coefficients of the three output voltages are low, and the loop phase margin is about 60 degrees, thus ensuring stable operation of the circuit under various process angles and temperature conditions.

[0072] It should be noted that the reference voltage source circuit 1 provided in this application can be widely used in various integrated circuits and electronic systems that require a stable reference voltage. For example, in analog-to-digital converters (ADCs), the multi-output reference voltage source can provide reference voltages for different voltage domains or multiple channels. Since the three outputs have the same temperature characteristics, consistency between channels can be guaranteed, improving conversion accuracy. As another example, in low-dropout linear regulators (LDOs) and power management chips, the reference voltage source of this application has low temperature drift and high power supply rejection ratio characteristics, enabling stable operation over a wide input voltage range (10V to 25V) and a wide temperature range. It is suitable for applications such as automotive electronics and industrial control, and the multiple outputs can provide the required reference voltages for different functional modules. Furthermore, in sensor interface circuits, the reference voltage source has low temperature drift characteristics in the range of -40℃ to 125℃, and the multiple outputs can provide reference voltages for sensor excitation and signal conditioning circuits.

[0073] This application also provides an electronic device, see reference. Figure 6 The electronic device 100 includes the reference voltage source circuit 1 described in any of the above embodiments. The electronic device 100 may be in the form of an integrated circuit chip, integrating the reference voltage source circuit 1 with other functional circuits on the same chip. For example, the reference voltage source circuit 1 may be integrated with an ADC to form an ADC chip, or with an LDO to form a power management chip, or with a sensor signal processing circuit to form a sensor chip.

[0074] The aforementioned electronic device 100 can also be an independent reference voltage source chip, serving as a general-purpose reference voltage source product for use in other systems. Because the reference voltage source circuit 1 of this application has characteristics such as multiple outputs, a wide input voltage range, and low temperature drift, the electronic device 100 using this reference voltage source circuit 1 can be widely applied in various electronic systems requiring high-precision reference voltages.

[0075] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0076] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A reference voltage source circuit, characterized by comprising: The application relates to a bandgap reference module, comprising: a pre-stabilization module for pre-stabilizing an input voltage; a starting module coupled to the pre-stabilization module for providing a starting current based on a pre-stabilized voltage output by the pre-stabilization module; a bandgap reference module coupled to the pre-stabilization module and the starting module for receiving the pre-stabilized voltage and establishing a working bias according to the starting current, and outputting reference voltages of multiple different voltage values; wherein the bandgap reference module comprises a bandgap MOS transistor, a resistance voltage dividing network and a first unit, the bandgap MOS transistor is used for forming a feedback loop, the first unit is used for generating an output voltage, and the resistance voltage dividing network is used for forming multiple output terminals to output reference voltages of different voltage values after dividing the output voltage.

2. The reference voltage source circuit of claim 1, wherein, The pre-stabilization module comprises a Zener diode, a stabilizing MOS transistor, a first resistor, a first capacitor and a second capacitor. The gate of the stabilizing MOS transistor is coupled to the cathode of the Zener diode, the source thereof is used as a pre-stabilization output terminal, and the drain thereof is coupled to an input voltage; the first capacitor is coupled between the gate of the stabilizing MOS transistor and the ground; the second capacitor is coupled between the source of the stabilizing MOS transistor and the ground; the cathode of the Zener diode is coupled to one end of the first resistor, and the anode thereof is grounded; and the other end of the first resistor is coupled to the input voltage.

3. The reference voltage source circuit of claim 1, wherein, The starting module comprises multiple starting MOS transistors and an inverter. The multiple starting MOS transistors comprise a first starting MOS transistor, a second starting MOS transistor, a third starting MOS transistor and an eighth starting MOS transistor. The input terminal of the inverter is coupled to the resistance voltage dividing network, and the output terminal of the inverter is coupled to the gate of the third starting MOS transistor. The gate and the drain of the first starting MOS transistor are coupled to the gate of the second starting MOS transistor, the source of the first starting MOS transistor and the source of the second starting MOS transistor are both coupled to the pre-stabilization output terminal of the pre-stabilization module, the drain of the first starting MOS transistor is coupled to the drain of the third starting MOS transistor, and the drain of the second starting MOS transistor and the drain of the third starting MOS transistor are both coupled to the ground terminal. The source of the eighth starting MOS transistor is coupled to the ground terminal, the drain of the eighth starting MOS transistor is coupled to the first unit, and the gate of the eighth starting MOS transistor is coupled to the drain of the second starting MOS transistor.

4. The reference voltage source circuit of claim 3, wherein, The starting module further comprises a second resistor coupled between the source of the eighth starting MOS transistor and the ground terminal.

5. The reference voltage source circuit of claim 3, wherein, The multiple starting MOS transistors further comprise a fourth starting MOS transistor, a fifth starting MOS transistor, a sixth starting MOS transistor and a seventh starting MOS transistor. The drain and the gate of the fourth starting MOS transistor are coupled to the source of the third starting MOS transistor, and the drain of the fourth starting MOS transistor is coupled to the drain of the sixth starting MOS transistor. The drain of the fifth starting MOS transistor is coupled to the drain of the second starting MOS transistor, the gate of the fifth starting MOS transistor is coupled to the first unit, and the source of the fifth starting MOS transistor is coupled to the drain of the seventh starting MOS transistor. A gate of the sixth start-up MOS transistor is coupled to a source of the fourth start-up MOS transistor, and a source of the sixth start-up MOS transistor is grounded. A gate of the seventh start-up MOS transistor is coupled to a source of the fifth start-up MOS transistor, and a source of the seventh start-up MOS transistor is grounded.

6. The reference voltage source circuit of claim 1, wherein, The first unit comprises: a first triode, a second triode and a plurality of mirror MOS transistors; the mirror MOS transistors comprise: a first mirror MOS transistor, a second mirror MOS transistor, a third mirror MOS transistor, a fourth mirror MOS transistor, a fifth mirror MOS transistor and a sixth mirror MOS transistor; sources of the first mirror MOS transistor and the second mirror MOS transistor are both coupled to a pre-stabilization output end of the pre-stabilization module, and drains thereof are coupled to sources of the third mirror MOS transistor and the fourth mirror MOS transistor respectively; a gate of the first mirror MOS transistor is coupled to a drain thereof, and a gate of the second mirror MOS transistor is coupled to a gate of the first mirror MOS transistor; a gate of the third mirror MOS transistor is coupled to a drain thereof, a gate of the fourth mirror MOS transistor is coupled to a gate of the third mirror MOS transistor, a drain of the third mirror MOS transistor is coupled to a drain of the fifth mirror MOS transistor, and a drain of the fourth mirror MOS transistor is coupled to a drain of the sixth mirror MOS transistor; a base of the first triode is coupled to a base of the second triode, a collector of the first triode is coupled to a source of the sixth mirror MOS transistor, a collector of the second triode is coupled to a source of the fifth mirror MOS transistor, and an emitter of the first triode and an emitter of the second triode are coupled to a ground end; a gate of the sixth mirror MOS transistor is coupled to a drain thereof; a drain of the bandgap MOS transistor is coupled to the pre-stabilization output end of the pre-stabilization module, a gate thereof is coupled to a drain of the fourth mirror MOS transistor, and a source thereof is coupled to the resistance voltage dividing network.

7. The reference voltage source circuit of claim 6, wherein, The bandgap reference module further comprises a third resistance and a compensation capacitor; the compensation capacitor is coupled between the source of the bandgap MOS transistor and the ground end; the third resistance is coupled between the base of the first triode and the base of the second triode.

8. The reference voltage source circuit of claim 7, wherein, The bandgap reference module further comprises a fourth resistance and a fifth resistance; one end of the fourth resistance is coupled to the emitter of the first triode and one end of the fifth resistance, and the other end of the fourth resistance is coupled to the emitter of the second triode; the other end of the fifth resistance is coupled to the ground end.

9. The reference voltage source circuit of claim 7, wherein, The resistance voltage dividing network comprises a sixth resistance, a seventh resistance and an eighth resistance; one end of the sixth resistance is coupled to the source of the bandgap MOS transistor and serves as a third output end of the bandgap reference module, the other end of the sixth resistance is coupled to one end of the seventh resistance and serves as a second output end of the bandgap reference module, the other end of the seventh resistance is coupled to one end of the eighth resistance and serves as a first output end of the bandgap reference module, the other end of the eighth resistance is coupled to the ground end, and the other end of the seventh resistance is further coupled to the base of the first triode; the feedback loop comprises a negative feedback loop and a positive feedback loop; The band gap MOS transistor, the sixth resistor, the seventh resistor, the first triode and the sixth mirror MOS transistor constitute a negative feedback loop; The band gap MOS transistor, the sixth resistor, the seventh resistor, the third resistor, the second triode, the fifth mirror MOS transistor, the third mirror MOS transistor and the fourth mirror MOS transistor constitute a positive feedback loop; The loop gain of the negative feedback loop is greater than the loop gain of the positive feedback loop.

10. An electronic device, characterized by The reference voltage source circuit comprises the reference voltage source circuit of any one of claims 1 to 9.

Images