Method and device for managing register

Abstract

The invention relates to the field of computers, in particular to a register management method and device. In the prior art, an assembly line register is reused for temporarily storing data, then a data transmission mechanism of a processor is used for transmitting the temporarily stored data to subsequent instructions on an assembly line for use, and due to the fact that the number of the instructions entering the assembly line is limited, the method is only suitable for the instructions with the short life cycle, and the application scene is limited. The first indication information indicates the first life cycle of the register associated with the first instruction set, the first life cycle is shorter than the second life cycle determined by hardware, the processor can be prompted to release the register in advance, and therefore the use efficiency of register resources is improved. The first indication information indicates the life cycle of the non-pipeline register, so that the technology provided by the invention not only can optimize the register resource used by the instruction with the shorter life cycle, but also can optimize the register resource used by the instruction with the longer life cycle.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically to a method and apparatus for managing registers. Background Technology

[0002] A register is a storage device, usually integrated into the processor, used to store instructions or data that the processor needs to access quickly, such as parameters and return values ​​during function scheduling, as well as intermediate calculation results.

[0003] Registers are typically faster to read and write than cache, memory, and disk. However, processor register resources are limited, and increasing the number of registers not only increases cost but also negatively impacts processor power consumption and size. Therefore, it is necessary to optimize register usage.

[0004] One approach to register usage utilizes the compiler's program analysis capabilities to identify short-lived instructions in the program. These instructions are marked with information that instructs the hardware not to allocate registers to them, but instead to reuse pipeline registers to temporarily store data. The processor's data forwarding mechanism then transfers the temporarily stored data to subsequent instructions in the pipeline. However, because the number of instructions entering the pipeline is limited, this method is only suitable for short-lived instructions, limiting its application scenarios. Summary of the Invention

[0005] The embodiments of this application provide a method and apparatus for managing registers, which can optimize register resources used by instructions with short lifecycles as well as those used by instructions with long lifecycles.

[0006] In a first aspect, embodiments of this application provide a method for managing registers. The execution subject of this method may be a processor or an electronic device containing a processor. The following description uses a processor as an example. The method includes: obtaining first indication information, the first indication information indicating a first lifetime of a register associated with a first instruction set, the first lifetime being less than a second lifetime, the second lifetime being the lifetime of the register associated with the first instruction set determined by the processor, the processor being used to process the first instruction set; processing the first instruction set; and releasing the register associated with the first instruction set according to the first indication information, wherein the actual lifetime of the register associated with the first instruction set is less than or equal to the first lifetime.

[0007] From a program perspective, the lifetime of a register is the time from when it is allocated to the last time its value is read. For the processor, since it lacks the ability to read program data, the processor determines the lifetime of a register as the time from its allocation to its release. This difference in understanding of register lifetimes between software and hardware leads to wasted register resources. In this embodiment, the first indication information is information that the processor can read, such as information carried by instructions or metadata. By indicating a shorter lifetime—that is, the first lifetime of the register associated with the first instruction set—the processor can release the register earlier, allowing it to be used by other instructions, thereby improving the efficiency of register resource utilization. Because the first indication information indicates the lifetime of a non-pipelined register, this embodiment can optimize register resources used by instructions with short lifetimes as well as those with long lifetimes.

[0008] In an optional implementation of the first aspect, the first lifetime is equal to the processing time of the first instruction set, and releasing the register associated with the first instruction set according to the first indication information includes: releasing the register associated with the first instruction set when the processing of the last instruction of the first instruction set is completed according to the first indication information, wherein the last instruction is the instruction in the first instruction set that is processed last.

[0009] When the first instruction set is completed, its processing result will be read by other instructions or stored in a cache or other medium. The registers associated with the first instruction set no longer need to store its processing result. Therefore, the first lifetime indicated by the first indication information can be equal to the processing time of the first instruction set, instructing the processor to release the registers associated with the first instruction set when the last instruction of the first instruction set is processed. Compared to schemes where the first lifetime is longer than the processing time of the first instruction set, this embodiment can release the registers associated with the first instruction set as quickly as possible, improving the efficiency of register resource utilization.

[0010] In an optional implementation of the first aspect, the first indication information is carried in the first instruction, the first indication information including the first information cell, the first information cell indicating the first instruction set.

[0011] In this embodiment, the first indication information exists in the form of an instruction. The instruction carrying the first indication information can be flexibly inserted into the set of instructions to be processed, thereby expanding the applicable scenarios of the above method.

[0012] In an optional implementation of the first aspect, the first information element includes: an identifier of a last instruction, and / or an identifier of a start instruction, wherein the last instruction is an instruction in the first instruction set that is processed last, and the start instruction is an instruction in the first instruction set that is processed first.

[0013] The first instruction set is indicated by the identifiers of the end instruction and / or the start instruction. The first instruction information does not need to carry the number of instructions in the first instruction set, thus reducing the resource overhead of the first instruction information. In addition, when the first information cell includes the identifiers of the end instruction and the start instruction, the insertion position of the first instruction information only needs to be before the end instruction of the first instruction set, making the insertion position of the first instruction information more flexible.

[0014] In an alternative implementation of the first aspect, the first information cell includes the number of instructions in the first instruction set.

[0015] In this embodiment, the first instruction information does not need to carry the identifiers of the end instruction and / or start instruction of the first instruction set, thus reducing the resource overhead of the first instruction information.

[0016] In an optional implementation of the first aspect, the first indication information is carried in metadata. The first indication information includes an identifier of the end instruction, or the first indication information includes an identifier of the start instruction and an identifier of the end instruction. The start instruction is the instruction that is first in the processing order of the first instruction set, and the end instruction is the instruction that is last in the processing order of the first instruction set.

[0017] In this embodiment, the first instruction information exists in the form of metadata. Compared with instructions, metadata contains richer information. For example, metadata can contain some source code level information, thereby providing richer management methods for the registers associated with the first instruction set.

[0018] In an alternative implementation of the first aspect, the first indication information includes a second information element indicating a register in the register associated with the first instruction set that needs to be freed.

[0019] After the first instruction set is processed, its associated registers may need to be released, or only a portion of them may need to be released. Based on the second cell, the processor can release those registers that need to be released, thus enabling more precise register management.

[0020] In an optional implementation of the first aspect, the first instruction set is an instruction set of a first program, and the first program further includes a second instruction set, wherein the program function corresponding to the first instruction set is different from the program function corresponding to the second instruction set.

[0021] The instructions of a program can be divided into multiple instruction sets based on the program's function. For multiple instructions that implement a program function (such as selecting the maximum value from the results of multiple numerical operations and storing the maximum value in memory), the intermediate results generated after these instructions are executed are generally not passed to subsequent instructions. Therefore, when dividing instruction sets, multiple instructions that implement the same program function can be divided into one instruction set. After the instruction set is executed, its associated registers can be released, which can reduce the number of times registers are released, thereby reducing the power consumption overhead caused by operating registers.

[0022] In an alternative implementation of the first aspect, the number of instructions in the first instruction set is positively correlated with the number of processor registers.

[0023] If the processor has a large number of registers, the number of instructions in the first instruction set can be set to a larger value; if the processor has a small number of registers, the number of instructions in the first instruction set can be set to a smaller value. This satisfies the instruction requirements while reducing the power consumption overhead of operating on registers.

[0024] In an optional implementation of the first aspect, before obtaining the first indication information, the method further includes: running a first program, the first program being a program corresponding to a first instruction set; and providing feedback on the running result, the running result indicating the use of registers during the running of the first program, the running result being used to determine the first indication information.

[0025] In this embodiment, by running the first program, the processor can determine the register resource requirements of the first program during actual operation. If some running nodes (e.g., a certain instruction, the time of executing a certain instruction, a certain segment of instructions, or the time of executing a certain segment of instructions) have a large demand for register resources, the processor can feed back these running nodes as running results to the software layer so that the software layer can optimize the register resources during the running process of the first program in a targeted manner.

[0026] Secondly, embodiments of this application provide an apparatus for managing registers. The apparatus may include a processing unit and an input unit for performing any of the methods described in the first aspect and its optional embodiments.

[0027] Thirdly, embodiments of this application provide an apparatus for managing registers, which may be an electronic device or a chip applied to an electronic device. The apparatus may include a processor for performing any of the methods described in the first aspect and its optional embodiments.

[0028] Optionally, when the device is an electronic device, the processor may be, for example, a central processing unit (CPU), a system-on-chip (SoC), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a microcontroller unit (MCU), a programmable logic device (PLD), or other logic devices; when the device is a chip, the processor may be, for example, a core, which may include a control unit and an execution unit, such as an arithmetic logic unit (ALU).

[0029] Optionally, the device may also include a communication interface, which may be an input / output interface, pins, or circuits, etc.

[0030] Optionally, the device may further include a memory for storing algorithms (e.g., logic operations embedded in a circuit), and the processor executes the algorithms stored in the memory to cause the device to perform any of the methods described in the first aspect and its optional embodiments. The memory may be logic circuitry, etc. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a program compilation method provided by an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of a program execution method provided in an embodiment of this application;

[0033] Figure 3 This is a schematic diagram of an instruction format provided by an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of an assembly line provided in an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of a register lifecycle provided by an embodiment of this application;

[0036] Figure 6 This is a schematic diagram illustrating a method for managing registers provided in an embodiment of this application;

[0037] Figure 7 This is a schematic diagram illustrating a method for releasing a register associated with a first instruction set, provided in an embodiment of this application.

[0038] Figure 8 This is a schematic diagram illustrating another method for releasing a register associated with a first instruction set, provided by an embodiment of this application;

[0039] Figure 9 This is a schematic diagram illustrating another method for releasing a register associated with a first instruction set, provided in an embodiment of this application;

[0040] Figure 10 This is a schematic diagram illustrating another method for releasing a register associated with a first instruction set, provided in an embodiment of this application;

[0041] Figure 11 This is a schematic diagram of a first instruction message provided in an embodiment of this application;

[0042] Figure 12 This is a schematic diagram of another first instruction information provided in an embodiment of this application;

[0043] Figure 13 This is a schematic diagram of another type of first instruction information provided in an embodiment of this application;

[0044] Figure 14 This is a schematic diagram of another type of first instruction information provided in an embodiment of this application;

[0045] Figure 15 This is a schematic diagram of another type of first instruction information provided in an embodiment of this application;

[0046] Figure 16 This is a schematic diagram of another type of first instruction information provided in an embodiment of this application;

[0047] Figure 17 This is a schematic diagram of another type of first instruction information provided in an embodiment of this application;

[0048] Figure 18 This is a schematic diagram illustrating another method for managing registers provided in an embodiment of this application;

[0049] Figure 19 This is a schematic diagram of a register management device provided in an embodiment of this application;

[0050] Figure 20 This is a schematic diagram of another register management device provided in an embodiment of this application;

[0051] Figure 21This is a schematic diagram of another device for managing registers provided in an embodiment of this application. Detailed Implementation

[0052] To facilitate understanding of the technical solution of this application, a brief introduction to some terms and concepts involved in this application will be given first. It should be noted that the descriptions of these terms and concepts are illustrative rather than limiting.

[0053] 1. Computer system.

[0054] A computer system comprises a hardware layer, an operating system layer running on top of the hardware layer, and an application layer running on top of the operating system layer. The hardware layer includes hardware such as processing units, memory, and memory control units. An operating system is any one or more software systems that implement business processing through processes; for example, the Linux operating system. operating system, operating system, operating system, Operating system or Operating system. The application layer includes applications (APPs) such as browsers, address books, word processing software, and instant messaging software. Optionally, the computer system applicable to this application may be wearable devices such as smartwatches, handheld devices such as smartphones, terminal devices such as personal computers, or network devices such as servers; this application does not limit this.

[0055] In the embodiments of this application, a program is a collection of ordered instructions (or code), data, and their organization to implement a relatively independent function. Programs typically employ a modular design, meaning they can be broken down into multiple smaller functional modules. A program contains at least one function, which is a code segment that implements a functional module; therefore, a function can be considered the basic unit of program functional modularity.

[0056] 2. Program compilation.

[0057] Programs are usually written in high-level languages ​​and cannot be directly executed by the processor. Therefore, it is necessary to convert the high-level language code used to write the program into low-level language code that can be read by the machine.

[0058] Figure 1 This is a schematic diagram of a program compilation method provided by an embodiment of this application.

[0059] A compiler can compile source code to produce an executable file; a processor can recognize the executable file and implement the functions described in the source code based on the executable file. The source code is, for example, a program written in a high-level language such as C, and the executable file is, for example, binary machine code. The compilation process is the process of using a compiler to generate an executable file from the source code.

[0060] Optionally, the compilation process can be divided into six stages: lexical analysis, syntax analysis, semantic analysis, intermediate code generation, code optimization, and executable file generation. A brief introduction to these six stages follows.

[0061] (1) Lexical Analysis: Input source code, scan and decompose the string that constitutes the source code, and identify individual word symbols. Word symbols are the basic syntactic units of a programming language, such as keywords (or reserved words), identifiers, constants, operators, and separators (such as punctuation marks, parentheses, etc.). The word symbols output by the lexical analyzer are usually output in the form of tuples, that is, the word category and the value of the word itself.

[0062] (2) Syntax Analysis: Based on lexical analysis, the sequence of word symbols is decomposed into various grammatical units, such as "expressions," "statements," and "programs," according to the grammatical rules of the language. The syntax analyzer determines whether the entire input string constitutes a grammatically correct program. If the source code has no grammatical errors, a syntax tree can be correctly constructed after syntax analysis.

[0063] (3) Semantic analysis: Analyze the meaning of each syntactic structure, check whether the source code contains static semantic errors, and collect type information for use in the subsequent intermediate code generation stage. A major task of semantic analysis is to perform type analysis and checking.

[0064] (4) Intermediate code generation: Intermediate code is generated based on the output of semantic analysis. Intermediate code is an internal representation of the source code, also known as intermediate representation (IR). The purpose of intermediate representation is to make the code structure logically simpler and clearer, so that code optimization is easier to achieve.

[0065] (5) Code optimization: This involves processing the intermediate code generated earlier to produce more efficient code in the final stage. Optimization is generally based on the analysis of the program's control flow and data flow, and is independent of the specific machine. The principles underlying optimization are the program's equivalent transformation rules, such as the extraction of common subexpressions, loop optimization, and the removal of useless code.

[0066] (6) Generate executable file: Transform the intermediate code into low-level language code for a specific machine (e.g., binary machine code). This stage is closely related to the specific machine.

[0067] Typically, lexical analysis, syntax analysis, semantic analysis, and executable generation are mandatory, while intermediate code generation and code optimization are optional.

[0068] 3. Program execution.

[0069] During program execution, the operating system loads the program into memory, and then the processor processes the instructions in the program sequentially according to a certain order, thereby realizing the execution of the program.

[0070] like Figure 2 As shown, the areas occupied by a program loaded into memory include the code segment and the data segment. The code segment and the data segment are parts of the executable file generated by the program compilation. The code segment is used to store instructions and metadata, while the data segment is used to store constant data and initialized global variables.

[0071] An instruction is a command that can be recognized and executed by a processor. Optionally, an instruction includes two types of information: the opcode and the address code.

[0072] Figure 3 This is a schematic diagram of an instruction format provided by an embodiment of this application.

[0073] The opcode represents the operation to be performed by the instruction, such as addition, subtraction, multiplication, division, memory access, or branching. Its length depends on the number of instructions in the instruction set. For example, if the opcode occupies 7 bits, the machine can contain a maximum of 128 (i.e., 2^32) instructions. 7 ) instructions.

[0074] An address code is used to indicate the address of an operand, where the operand is the data to be processed by the operation indicated by the opcode. An address code can be an immediate value, a memory address, a register name, an input / output (I / O) port number, or a formal address. An instruction can include one or more address codes. For example, if the address code is a register name, the processor can use that address code to locate the corresponding register and fetch the operand from it.

[0075] Metadata is a type of data that describes data. Metadata can be used to describe instruction attributes; for example, it can describe a set of instructions and the registers associated with those instructions.

[0076] Back Figure 2The processor includes a control unit, a storage unit, and a processing unit, which are connected via a bus. Figure 2 (Connections not shown). The control unit includes a program counter and an instruction register. The program counter stores the address of the next instruction to be executed in memory, while the instruction register stores the instruction to be executed. The storage unit typically includes multiple registers, such as general-purpose registers and floating-point registers. These registers are typically used to store data needed during instruction execution. The arithmetic logic unit (ALU) processes the data according to the currently executing instruction.

[0077] Based on the above structure, the program operates as follows: Under the action of timing pulses, the control unit sends the instruction address (i.e., the address of the instruction in memory) from the program counter to the address bus, and then reads the instruction at this address into the instruction register for decoding. For data needed during instruction execution, the control unit sends the corresponding operand address to the address bus and reads the data into a temporary storage unit based on that operand address. Finally, the arithmetic unit processes the data in the storage unit based on the currently executed instruction. The arithmetic unit can write output data into the temporary storage unit, and some output data is eventually written into memory.

[0078] In general, the processor fetches instructions and corresponding data from memory one by one, and performs calculations on the data according to the opcode in the instruction until the program is completed.

[0079] Processors can process instructions using pipeline technology, which refers to dividing the processing of an instruction into multiple steps, each completed by a dedicated circuit. The processing flow formed by the processor executing these multiple steps can be called a pipeline.

[0080] Optionally, such as Figure 4 As shown, a production line includes the following steps:

[0081] I. Instruction fetch (IF).

[0082] Instruction fetching, also known as instruction loading, is the process of retrieving an instruction from memory into the instruction register. The program counter indicates the location in memory of the next instruction to be executed. Once an instruction is fetched, the program counter automatically increments according to the instruction's length, ensuring that the program counter always points to the address of the next instruction to be fetched.

[0083] II. Instruction Decoding (ID).

[0084] After the instruction is fetched, the processor enters the instruction decoding stage. During this stage, the processor's instruction decoder breaks down and interprets the fetched instruction according to a predetermined instruction format, identifying the instruction type and the method for obtaining operands.

[0085] III. Execute (execute, EXE).

[0086] After the instruction fetch and decode stages, the processor enters the execution stage. The task of the execution stage is to complete the various operations specified by the instruction to achieve its function. Therefore, different units of the processor are connected to perform the required operations. For example, if the processor needs to perform an addition operation, the ALU in the arithmetic logic unit (ALU) will be connected to a set of input registers and a set of output registers. The input registers provide the values ​​to be added, and the output registers provide storage space for the result.

[0087] IV. Memory access (MEM).

[0088] During instruction execution, the processor may need to access memory to read operands, depending on the instruction's requirements. In this case, the processor enters the memory access phase. The task of the memory access phase is to obtain the memory address of the operand based on the instruction's address code and read the operand from memory for computation.

[0089] V. Writeback (WB).

[0090] As the final stage, the write-back stage's task is to "write back" the output data from the execution stage to some kind of storage structure. For example, output data is usually written to the processor's internal registers for quick access by subsequent instructions; in some cases, output data may also be written to relatively slower but cheaper and larger memory.

[0091] After the output data is written back, the processor can then fetch the address of the next instruction from the program counter and begin a new cycle. Optionally, a multi-stage pipeline can be used to improve processor efficiency.

[0092] It should be noted that, Figure 4 This is an example, not a limitation. For instance, each step in a pipeline may be completed within one timing pulse or within multiple timing pulses. Furthermore, a pipeline may include more or fewer steps; for example, a pipeline may also include register reallocation.

[0093] 4. Registers.

[0094] A register is a storage device, usually integrated into the processor, used to store information that the processor needs to access quickly.

[0095] Different registers have different functions, and registers can be classified into the following categories according to their functions.

[0096] Data registers: Used to store operands, intermediate results, and final data. Data registers typically include multiple bytes of storage space to support operations on various data types.

[0097] Address register: Used to store memory addresses or peripheral device addresses. When the processor needs to access memory or a peripheral device, it first stores the target address in the address register and then performs the corresponding read / write operation.

[0098] The status register stores processor status information, such as parity bits and interrupt flags. This status information is crucial for the processor's control logic and exception handling. The processor uses the value of the status register to determine whether to execute an interrupt operation, perform exception handling, etc.

[0099] Instruction Register: Used to store the currently executing instruction. After the processor reads an instruction from memory, it stores it in the instruction register, then decodes and executes it.

[0100] Special registers: In addition to the basic registers mentioned above, there are some special registers, such as floating-point registers and vector registers, which are used to support specific data types and operations.

[0101] Processors can allocate, reallocate, and free registers. Allocation refers to assigning a register to an instruction to write data; the data in that register can then be read by one or more instructions. Reallocation refers to assigning a register to an instruction to write data, and then assigning that register to another instruction to write data. Once a register is allocated, its state can be changed by freeing it; a freed register can then be allocated to other instructions to write data.

[0102] Some registers can be allocated, while others cannot. For example, data registers can be allocated, but the program counter cannot. In embodiments of this application, registers that can be allocated are referred to as general-purpose registers, and registers that cannot be allocated are referred to as non-general-purpose registers.

[0103] Once a register is allocated, it acquires a lifetime. For the processor, a register's lifetime is the time from when it is allocated until it is freed or reallocated. However, for a program, a register's lifetime has a different meaning.

[0104] Figure 5This is a schematic diagram of a register lifecycle provided by an embodiment of this application.

[0105] R1 through R4 represent four registers. After compilation, the program generates six instructions, numbered 1 through 6, with the following meanings:

[0106] Instruction 1 operates as "R1 = .", which means reading data from memory (e.g., data 1) and writing it to R1;

[0107] Instruction 2 operates as "R2 = .", which means reading data from memory (e.g., data 2) and writing it to R2;

[0108] Instruction 3 means “R4 = R1 + R2”, which means performing an addition operation on data 1 and data 2 and writing the result of the addition operation into R4;

[0109] Instruction 4 operates on the condition "R3 = R4", meaning that the data in R4 will be moved to R3.

[0110] Instruction 5 operates as "R2 = R3 + R2", which means performing an addition operation on the data in R3 and the data in R2, and writing the result of the addition operation into R2;

[0111] Instruction 6 operates as "R1 = R2", which means moving the data in R2 to R1.

[0112] R1 is allocated when instruction 1 is executed. When instruction 3 is executed, data 1 in R1 is read. Since subsequent instructions no longer use data 1, R1 can be released. Subsequently, when instruction 6 is executed, R1 is allocated again, and the processor writes the data from R2 into R1.

[0113] R2 is allocated when instruction 2 is executed. When instruction 3 is executed, data 2 in R2 is read. Since instruction 5 still needs to use the data in R2, R2 cannot be released when instruction 3 is executed. When instruction 5 is executed, data 2 in R2 is read again. Since subsequent instructions no longer use data 2, R2 can be released.

[0114] R4 is allocated when instruction 3 is executed. When instruction 4 is executed, the data in R4 is moved to R3. Since subsequent instructions no longer use the data in R4, R4 can be released.

[0115] R3 is allocated when instruction 4 is executed. When instruction 5 is executed, the data in R3 is read. Since subsequent instructions no longer use data 3, R3 can be released.

[0116] At the software level, a program is aware of its own complete logic, thereby determining the logical relationships between various instructions. Therefore, the register lifetime that the program sees is the period during which the register is actually used.

[0117] For the program, the lifecycle of R1 is the execution period of instruction 1 to instruction 2, and the execution period of instruction 6; the lifecycle of R2 is the execution period of instruction 2 to instruction 5; the lifecycle of R4 is the execution period of instruction 3; and the lifecycle of R3 is the execution period of instruction 4.

[0118] At the hardware level, the processor fetches instructions 1 through 6 one by one, and cannot determine the logical relationships between the instructions. For example, when the processor is processing instruction 3, instruction 5 has not yet been fetched, and it cannot determine whether the data in R2 will be used by subsequent instructions. Therefore, the register lifetime seen by the processor is not the actual time period during which the register is used.

[0119] For the processor, R1 is allocated when instruction 1 is executed, reallocated when instruction 6 is executed, and released only when the program finishes running. Therefore, the lifetime of R1 starts from the execution of instruction 1 and continues until the program finishes running. R2 is allocated when instruction 2 is executed, reallocated when instruction 5 is executed, and released only when the program finishes running. Therefore, the lifetime of R2 starts from the execution of instruction 2 and continues until the program finishes running. R4 is allocated when instruction 3 is executed, and released only when the program finishes running. Therefore, the lifetime of R4 starts from the execution of instruction 3 and continues until the program finishes running. R3 is allocated when instruction 4 is executed, and released only when the program finishes running. Therefore, the lifetime of R3 starts from the execution of instruction 4 and continues until the program finishes running.

[0120] The register lifetimes seen by the program differ from those seen by the processor, making it impossible to optimize register resources at the software level. As a result, the processor needs more registers to meet computational demands, thereby increasing the processor's cost and power consumption.

[0121] The following describes a method for managing registers provided by embodiments of this application. The execution subject of this method can be a processor or an electronic device containing a processor. The processor can be a core, CPU, SoC, GPU, ASIC, FPGA, MCU, PLD, or other logic device, such as discrete component gate circuits. Embodiments of this application do not limit the specific type of processor.

[0122] The electronic device containing the processor can be a terminal or a server. The terminal can be a mobile phone, tablet computer, smart printer, smart home device, wearable device, vehicle, charging station, airplane, ship, robot, or robotic arm, etc. The server can be a rack-mount server, tower server, blade server, or platform server, etc. The embodiments of this application do not limit the specific technologies or device forms used in the terminal and server.

[0123] The following description uses a processor as an example. Figure 6 As shown, method 600 includes:

[0124] S610, Obtain first instruction information. The first instruction information indicates the first lifetime of the register associated with the first instruction set. The first lifetime is shorter than the second lifetime. The second lifetime is the lifetime of the register associated with the first instruction set determined by the processor. The processor uses this information to process the first instruction set.

[0125] The first instruction information exists in the form of machine code that the processor can recognize. Otherwise, the embodiments of this application do not limit the form of the first instruction information. Optionally, the first instruction information may be information carried in instructions or metadata. The first instruction information will be described in detail below after the description of the register operation flow.

[0126] Optionally, before obtaining the first instruction information, the processor may run the program to which the first instruction set belongs, i.e., the first program, once or multiple times. During the execution of the first program, the processor records the usage of registers and provides feedback on the execution result during or after the execution of the first program. The execution result indicates the usage of registers during the execution of the first program and is used by the software layer to determine the first instruction information.

[0127] For example, if the execution results indicate that some execution nodes of the first program have a high demand for register resources, then the software layer (e.g., the compiler) can insert instructions containing first indication information at these execution nodes to instruct the processor to release some registers to meet the needs of the first program. Here, an execution node can be an instruction, the time when an instruction is executed, a block of instructions, the time when a block of instructions is executed, or other parameters that can reflect the use of registers during the execution of the first program.

[0128] The first instruction set includes one or more instructions. The embodiments of this application do not limit the number and type of instructions in the first instruction set.

[0129] Optionally, the instruction set can be partitioned based on program functionality and / or the number of registers.

[0130] For example, when a program's function is to "select the maximum value from the results of multiple numerical operations and store that maximum value in memory," the corresponding instructions will read multiple values ​​from multiple registers, perform calculations based on these values, obtain intermediate result 1 and intermediate result 2, then compare intermediate result 1 and intermediate result 2, and store the larger value in memory. Before these instructions have finished executing, intermediate result 1 and intermediate result 2 still need to be used. If all registers associated with these instructions are released before their completion, intermediate result 1 and intermediate result 2 will need to be moved to other registers. Therefore, when partitioning instruction sets, multiple instructions implementing the same program function can be grouped into one instruction set. The associated registers can be released only after the instruction set has finished executing, reducing the number of register releases and thus reducing the power consumption overhead from register operations.

[0131] like Figure 5 As shown, both instructions 3 and 5 use the data in R2 as input for computation. Therefore, instructions 3 and 5 can be considered to perform the same program function. If instructions 3 and 5 are divided into two instruction sets, the data in R2, after being read by instruction 3, would need to be moved to another register to await reading by instruction 5, so that the processor can release R2. However, the execution times of instructions 5 and 3 are not far apart, and frequent register operations would incur additional power consumption overhead. Therefore, instructions 3 and 5 can be divided into a single instruction set.

[0132] When dividing the instruction set based on the number of registers, the number of instructions in the first instruction set can be set to a value that is positively correlated with the number of processor registers.

[0133] For example, if the processor has a large number of registers, the number of instructions in the first instruction set can be set to a larger value to avoid the extra power consumption caused by frequent register operations; if the processor has a small number of registers, the number of instructions in the first instruction set can be set to a smaller value to release the registers associated with the current instruction set as soon as possible to meet the needs of subsequent instructions.

[0134] The register associated with the first instruction set can be one or more. Here, "register" refers to a general-purpose register, that is, a register that can be allocated and freed by the processor. Apart from this, the embodiments of this application do not limit the number or type of registers associated with the first instruction set.

[0135] The first lifecycle can be the lifecycle determined by the compiler based on the compilation results of the program.

[0136] For example, the first instruction set is Figure 5The instructions 1 through 6 are shown. The registers associated with the first instruction set are R1 through R4. After analyzing the operations of instructions 1 through 6, the compiler determines the logical relationship between each instruction. Based on this logical relationship, the first lifetime of each register can be determined. Specifically, the first lifetime of R1 is the execution period of instructions 1 through 6; the first lifetime of R2 is the execution period of instructions 2 through 6; the first lifetime of R4 is the execution period of instructions 3 through 6; and the first lifetime of R3 is the execution period of instructions 4 through 6.

[0137] The first life cycle can also be determined manually through other analysis tools. The embodiments of this application do not limit the specific method for determining the first life cycle.

[0138] The second lifecycle is the lifecycle determined by the processor without relying on the first instruction information.

[0139] Still with Figure 5 For example, the first instruction set consists of instructions 1 to 6, and the registers associated with the first instruction set are R1 to R4. Without relying on the first instruction information, the processor's second lifetime is determined from the moment the registers are allocated until the program finishes execution. Specifically, the second lifetime of R1 is the period from the start of instruction 1 execution to the program's completion; the second lifetime of R2 is the period from the start of instruction 2 execution to the program's completion; the second lifetime of R4 is the period from the start of instruction 3 execution to the program's completion; and the second lifetime of R3 is the period from the start of instruction 4 execution to the program's completion.

[0140] The processor may acquire the first instruction set after acquiring the first instruction information, or it may acquire the first instruction information after acquiring a portion of the instructions in the first instruction set. After acquiring the instructions in the first instruction set, the processor may perform the following steps.

[0141] S620 processes the first set of instructions.

[0142] The processor can be based on Figure 2 and Figure 4 The method shown processes the first instruction set, and will not be described in detail here. The embodiments of this application do not limit the specific manner in which the first instruction set is processed.

[0143] S630, release the register associated with the first instruction set according to the first instruction information, wherein the actual lifetime of the register associated with the first instruction set is less than or equal to the first lifetime.

[0144] The processor can release the registers associated with the first instruction set during processing, or it can release the registers associated with the first instruction set after all the first instruction set has been processed. These two methods are described below.

[0145] Method 1: The processor releases the registers associated with the first instruction set during the processing of the first instruction set.

[0146] like Figure 7 As shown, the first instruction set consists of instructions 1 to 6, and the registers associated with the first instruction set are R1 to R4. The first lifetime of R1 is the execution period of instructions 1 to 6, and the second lifetime of R1 is the period from the start of instruction 1 execution to program completion. The first lifetime of R2 is the execution period of instructions 2 to 6, and the second lifetime of R2 is the period from the start of instruction 2 execution to program completion. The first lifetime of R4 is the execution period of instructions 3 to 6, and the second lifetime of R4 is the period from the start of instruction 3 execution to program completion. The first lifetime of R3 is the execution period of instructions 4 to 6, and the second lifetime of R3 is the period from the start of instruction 4 execution to program completion. The second lifetimes of R1 to R4 are not fully reflected in the... Figure 7 In the text, parts not explicitly shown are indicated by ellipses.

[0147] If the first instruction indicates that R1 to R4 should be released, the processor may perform the following operations on R1 to R4:

[0148] When executing instruction 1, R1 is allocated and used by instruction 1. The data in R1 is read by instruction 3 and then R1 is released.

[0149] When executing instruction 2, allocate R2 and use it for instruction 2;

[0150] When executing instruction 3, R4 is allocated and used by instruction 3. The data in R4 is read by instruction 4 and then R4 is released.

[0151] When executing instruction 4, R3 is allocated and used by instruction 4. The data in R3 is read by instruction 5 and then released.

[0152] When executing instruction 5, R2 is reallocated and allocated to instruction 5 for use. The data in R2 is read by instruction 6 and then released.

[0153] R1 is allocated when instruction 6 is executed, and R1 is used by instruction 6. R1 is released after instruction 6 is completed.

[0154] The compiler can add identifiers to the instructions associated with registers that need to be released, instructing the processor to release the corresponding registers. For example, the compiler can add an identifier for R1 to instruction 3, instructing the processor to release R1 after reading the data in R1; the compiler can add an identifier for R4 to instruction 4, instructing the processor to release R4 after reading the data in R4; the compiler can add an identifier for R3 to instruction 5, instructing the processor to release R3 after reading the data in R3; and the compiler can add an identifier for R2 to instruction 6, instructing the processor to release R2 after reading the data in R2. Since the first instruction indicates the range of the first instruction set, the processor can release R1 again after executing the last instruction (instruction 6).

[0155] Based on the above operations, the actual lifetimes of R1 to R4 are shorter than their respective first lifetimes and shorter than their respective second lifetimes. After instruction 6 is executed, R1 to R4 are all released, and the processor has more available registers, thereby improving the utilization rate of register resources.

[0156] Method 2: The processor releases the registers associated with the first instruction set when the first instruction set has been processed.

[0157] like Figure 8 As shown, the first instruction set consists of instructions 1 to 6, and the registers associated with the first instruction set are R1 to R4. The first lifetime of R1 is the execution period of instructions 1 to 6, and the second lifetime of R1 is the period from the start of instruction 1 execution to program completion. The first lifetime of R2 is the execution period of instructions 2 to 6, and the second lifetime of R2 is the period from the start of instruction 2 execution to program completion. The first lifetime of R4 is the execution period of instructions 3 to 6, and the second lifetime of R4 is the period from the start of instruction 3 execution to program completion. The first lifetime of R3 is the execution period of instructions 4 to 6, and the second lifetime of R3 is the period from the start of instruction 4 execution to program completion. The second lifetimes of R1 to R4 are not fully reflected in the... Figure 8 In the text, parts not explicitly shown are indicated by ellipses.

[0158] If the first instruction indicates that R1 to R4 should be released, the processor may perform the following operations on R1 to R4:

[0159] When executing instruction 1, allocate R1 and assign R1 to instruction 1 for use;

[0160] When executing instruction 2, allocate R2 and use it for instruction 2;

[0161] When executing instruction 3, allocate R4 and use it for instruction 3;

[0162] When executing instruction 4, allocate R3 and use it for instruction 4;

[0163] When executing instruction 5, R2 is reallocated and allocated to instruction 5 for use.

[0164] When executing instruction 6, R1 is reallocated and assigned to instruction 6 for use. After instruction 6 is completed, R1 to R4 are released.

[0165] Based on the above operations, the actual lifetimes of R1 to R4 are equal to their respective first lifetimes and all are less than their respective second lifetimes. After instruction 6 is executed, R1 to R4 are all released, giving the processor more available registers and thus improving the utilization of register resources. Furthermore, Method 2 releases registers uniformly upon completion of the first instruction set, eliminating the need for additional flags to instruct the processor to release registers associated with the first instruction set during processing. This reduces the complexity of implementation and is suitable for lightweight processors.

[0166] Figure 7 and Figure 8 In the example shown, the first instruction message indicates the release of all registers associated with the first instruction set. Optionally, the first instruction message may also indicate the release of some registers associated with the first instruction set.

[0167] like Figure 9 As shown, the first instruction set consists of instructions 1 to 6, and the registers associated with the first instruction set are R1 to R4. The first lifetime of R1 is the execution period of instructions 1 to 6, and the second lifetime of R1 is the period from the start of instruction 1 execution to program completion. The first lifetime of R2 is the execution period of instructions 2 to 6, and the second lifetime of R2 is the period from the start of instruction 2 execution to program completion. The first lifetime of R4 is the execution period of instructions 3 to 6, and the second lifetime of R4 is the period from the start of instruction 3 execution to program completion. The first lifetime of R3 is the execution period of instructions 4 to 6, and the second lifetime of R3 is the period from the start of instruction 4 execution to program completion. The second lifetimes of R1 to R4 are not fully reflected in the... Figure 8 In the text, parts not explicitly shown are indicated by ellipses.

[0168] If the first instruction indicates that R2 to R4 should be released, the processor may perform the following operations on R2 to R4:

[0169] When executing instruction 1, allocate R1 and assign R1 to instruction 1 for use;

[0170] When executing instruction 2, allocate R2 and use it for instruction 2;

[0171] When executing instruction 3, R4 is allocated and used by instruction 3. The data in R4 is read by instruction 4 and then R4 is released.

[0172] When executing instruction 4, R3 is allocated and used by instruction 4. The data in R3 is read by instruction 5 and then released.

[0173] When executing instruction 5, R2 is reallocated and allocated to instruction 5 for use. The data in R2 is read by instruction 6 and then released.

[0174] When executing instruction 6, R1 is reallocated and assigned to instruction 6 for use. R1 is not released after instruction 6 has finished executing.

[0175] The compiler can add an identifier to the instruction associated with the register that needs to be released, instructing the processor to release the corresponding register.

[0176] Based on the above operations, the actual lifetimes of R2 to R4 are shorter than their respective first lifetimes and also shorter than their respective second lifetimes. After instruction 6 is executed, R2 to R4 are all released, and the processor has more available registers, thereby improving the utilization rate of register resources.

[0177] Figures 7-9 In the example shown, the lifetimes of the registers used by instructions 1, 3, 4, 5 and 6 do not overlap, while the lifetimes of the registers used by instructions 1, 2, 3 and 4 partially overlap. Therefore, instructions 1, 3, 4, 5 and 6 can use the same register, while instruction 2 can use a separate register.

[0178] like Figure 10 As shown, the first instruction set consists of instructions 1 to 6, and the registers associated with the first instruction set are R1 to R4. The first lifetime of R1 is the execution period of instructions 1 to 6, and the second lifetime of R1 is the period from the start of instruction 1 execution to program completion. The first lifetime of R2 is the execution period of instructions 2 to 6, and the second lifetime of R2 is the period from the start of instruction 2 execution to program completion. The first lifetime of R4 is the execution period of instructions 3 to 6, and the second lifetime of R4 is the period from the start of instruction 3 execution to program completion. The first lifetime of R3 is the execution period of instructions 4 to 6, and the second lifetime of R3 is the period from the start of instruction 4 execution to program completion. The second lifetimes of R1 to R4 are not fully reflected in the... Figure 8 In the text, parts not explicitly shown are indicated by ellipses.

[0179] If the first instruction indicates that R1 to R4 should be released, the processor may perform the following operations on R1 to R4:

[0180] When executing instruction 1, allocate R1 and assign R1 to instruction 1 for use;

[0181] When executing instruction 2, R2 is allocated and used by instruction 2. The data in R2 is read by instruction 5 and then released.

[0182] When executing instruction 3, R1 is reallocated and assigned to instruction 3 for use. That is, the processor writes the result of the addition operation into R1.

[0183] When executing instruction 4, R1 is reallocated and allocated to instruction 4 for use. That is, the processor writes the data that was originally to be written to R3 into R1; the processor releases R4 after instruction 4 is executed.

[0184] When executing instruction 5, R1 is reallocated and allocated to instruction 5. That is, the processor writes the data that was originally to be written to R2 to R1.

[0185] When executing instruction 6, R1 is reallocated and assigned to instruction 6 for use. After instruction 6 is completed, R1 is released.

[0186] The compiler can add an identifier to the instruction associated with the register that needs to be released, instructing the processor to release the corresponding register.

[0187] Based on the above operations, the processor uses only two registers (R1 and R2) during the execution of instructions 1 through 6. The actual lifetimes of R1 through R4 are shorter than their first lifetimes and shorter than their second lifetimes, with R3 and R4 having an actual lifetime of 0. After instruction 6 is executed, R1 and R2 are released, giving the processor more available registers and thus improving the utilization of register resources.

[0188] The previous section detailed an example of a processor releasing a register associated with a first instruction set based on a first instruction message. The following section describes an example of the first instruction message.

[0189] Figure 11 This is a schematic diagram of a first instruction message provided in an embodiment of this application.

[0190] like Figure 11As shown, I1, I1-1, I2, I3, I4, and In are instruction identifiers, and ldr, lvhint, add, mul, and sub are instruction operations. ldr loads data into a register, lvhint provides a hint, add performs addition, mul performs multiplication, and sub performs subtraction. x represents a register.

[0191] For I1, "ldr x8<-[x4,x2]" means reading data from the memory address corresponding to [x4,x2] into register x8.

[0192] For I2, "add x9<-x11,x8" means reading data from registers x11 and x8, performing an addition operation, and writing the result of the addition operation into register x9.

[0193] For I3, "ldr x3<-[x8]" means reading data from the memory address corresponding to [x8] into register x3.

[0194] For I4, "mul x2<-x9,x8" means reading data from registers x9 and x8, performing multiplication, and writing the result of the multiplication into register x2.

[0195] For In, "sub x8<-x4,x5" means reading data from registers x4 and x5, performing a subtraction operation, and writing the result of the subtraction operation into register x8.

[0196] I1-1 is a hint instruction carrying first indication information, inserted between I1 and I2. The processor can recognize I1-1 as a hint instruction based on lvhint. Here, "x9,x8,I4" are information cells in the first indication information. The information cell "I4" in I1-1, combined with the insertion position of I1-1, indicates an instruction set, namely, the instruction set composed of I2, I3, and I4 (an example of a first instruction set). The information cells "x9,x8" in I1-1 are the names of the registers associated with this instruction set that need to be freed.

[0197] After the processor acquires I1-1, it determines the first instruction set and the registers that need to be freed. The processor can free x9 and x8 after I4 execution is complete, for example, by writing the execution result of I4 to x2 and then freeing x9 and x8; ​​the processor can also free x9 and x8 before I4 execution is complete, for example, by immediately freeing x9 and x8 after reading the data from x9 and x8.

[0198] Optionally, the information cells "x9,x8" in I1-1 can also be the names of registers in the registers associated with the first instruction set that do not need to be freed. Then the processor can free registers other than x9 and x8, such as x11 and x3, after I4 execution ends or before I4 execution ends.

[0199] Figure 11 The prompting instruction shown indicates the first instruction set through its own insertion position and the identifier of the end instruction. The first instruction information does not need to carry the number of instructions in the first instruction set, nor does it need to carry the identifier of the start instruction, thereby reducing the resource overhead of the first instruction information.

[0200] Figure 12 This is a schematic diagram of another first instruction information provided by an embodiment of this application.

[0201] like Figure 12 As shown, I1, I2, I3, I4, I4-1, and In are instruction identifiers, and ldr, lvhint, add, mul, and sub are instruction operations. ldr loads data into a register, lvhint provides a prompt, add performs addition, mul performs multiplication, and sub performs subtraction. x represents a register.

[0202] Figure 12 The meanings of I1 to In in Figure 11 The meanings of I1 to In are the same, so I will not repeat them here.

[0203] I4-1 is a hint instruction carrying the first indication information. It is inserted after I4, and the processor can recognize I4-1 as a hint instruction based on lvhint. Here, "x9,x8,I2" are the information cells in the first indication information. The information cell "I2" in I4-1, combined with the insertion position of I4-1, indicates an instruction set, namely, the instruction set composed of I2, I3, and I4 (an example of the first instruction set); the information cells "x9,x8" in I4-1 are the names of the registers that need to be freed in the registers associated with this instruction set.

[0204] After the processor acquires I4-1, it determines the first instruction set and the registers that need to be freed, and then frees x9 and x8.

[0205] Optionally, the information cells "x9,x8" in I4-1 can also be the names of registers in the registers associated with the first instruction set that do not need to be freed. Then the processor can free registers other than x9 and x8 after acquiring I4-1, such as x11 and x3.

[0206] Figure 12The prompting instruction shown indicates the first instruction set by its own insertion position and the identifier of the start instruction. The first instruction information does not need to carry the number of instructions in the first instruction set, nor does it need to carry the identifier of the end instruction, thereby reducing the resource overhead of the first instruction information.

[0207] Figure 13 This is a schematic diagram of another type of first instruction information provided in an embodiment of this application.

[0208] like Figure 13 As shown, I0-1, I1, I2, I3, I4, and In are instruction identifiers, and ldr, lvhint, add, mul, and sub are instruction operations. ldr loads data into a register, lvhint provides a prompt, add performs addition, mul performs multiplication, and sub performs subtraction. x represents a register.

[0209] Figure 13 The meanings of I1 to In in Figure 11 The meanings of I1 to In are the same, so I will not repeat them here.

[0210] I0-1 is a hint instruction carrying the first indication information, inserted before I1. The processor can recognize I0-1 as a hint instruction based on lvhint. Here, "x9,x8,I2,I4" are information cells in the first indication information. The information cells "I2,I4" in I0-1 indicate an instruction set, namely, the instruction set consisting of I2, I3, and I4 (an example of a first instruction set); the information cells "x9,x8" in I0-1 are the names of the registers associated with this instruction set that need to be freed.

[0211] After acquiring I0-1, the processor determines the first instruction set and the registers that need to be freed. The processor can free x9 and x8 after I4 execution is complete, for example, by writing the execution result of I4 to x2 and then freeing x9 and x8; ​​the processor can also free x9 and x8 before I4 execution is complete, for example, by immediately freeing x9 and x8 after reading the data from x9 and x8.

[0212] Optionally, the information cells "x9,x8" in I0-1 can also be the names of registers in the registers associated with the first instruction set that do not need to be freed. Then the processor can free registers other than x9 and x8, such as x11 and x3, after I4 execution ends or before I4 execution ends.

[0213] Figure 13 The displayed prompts include identifiers for the start and end instructions; therefore, Figure 13 The prompt instruction shown can be inserted at a more flexible position, and can be inserted at any position before In.

[0214] Figure 14 This is a schematic diagram of another type of first instruction information provided in an embodiment of this application.

[0215] like Figure 14 As shown, I1, I2, I2-1, I3, I4, and In are instruction identifiers, and ldr, lvhint, add, mul, and sub are instruction operations. ldr loads data into a register, lvhint provides a hint, add performs addition, mul performs multiplication, and sub performs subtraction. x represents a register.

[0216] Figure 14 The meanings of I1 to In in Figure 11 The meanings of I1 to In are the same, so I will not repeat them here.

[0217] I2-1 is a hint instruction carrying the first indication information, inserted between I2 and I3. The processor can recognize I2-1 as a hint instruction based on lvhint. Here, "x9,x8,2" are information cells in the first indication information. The information cell "2" in I2-1 indicates that the number of instructions is 2. The information cell "2", combined with the insertion position of I2-1, indicates an example of the first instruction set, namely, the instruction set consisting of I1 and I2, or the instruction set consisting of I3 and I4. Whether the first instruction set is "I1 and I2" or "I3 and I4" can be determined by the processor based on preset logic. The information cells "x9,x8" in I2-1 are the names of the registers that need to be freed in the registers associated with this instruction set.

[0218] After acquiring I2-1, the processor determines the first instruction set and the registers that need to be freed. For example, if the first instruction set is I3 and I4, the processor can free x9 and x8 after I4 finishes execution, such as by writing the execution result of I4 to x2 and then freeing x9 and x8; ​​the processor can also free x9 and x8 before I4 finishes execution, such as by immediately freeing x9 and x8 after reading the data from x9 and x8.

[0219] Optionally, the information cells "x9,x8" in I2-1 can also be the names of registers in the registers associated with the first instruction set that do not need to be freed. Then the processor can free registers other than x9 and x8, such as x3, after or before the execution of I4.

[0220] Figure 14 The prompting instruction shown indicates the first instruction set by its insertion position and the number of instructions. The first instruction information does not need to carry the identifier of the end instruction and / or the start instruction, thereby reducing the resource overhead of the first instruction information.

[0221] Figures 11-14 In the embodiments shown, the first indication information exists in the form of instructions. The instructions carrying the first indication information can be flexibly inserted into the set of instructions to be processed, thereby expanding the applicable scenarios of method 600.

[0222] The following describes an example of carrying first indication information through metadata.

[0223] like Figure 15 As shown, I1, I2, I3, I4, and In are instruction identifiers, and ldr, add, mul, and sub are instruction operations. ldr loads data into a register, add performs addition, mul performs multiplication, and sub performs subtraction. x represents a register.

[0224] Figure 15 The meanings of I1 to In in Figure 11 The meanings of I1 to In are the same, so I will not repeat them here.

[0225] The metadata carries the first indication information, where “startLive:I2” is the cell indicating the start instruction, indicating that the start instruction of the first instruction set is I2; “endLive:I4” is the cell indicating the end instruction, indicating that the end instruction of the first instruction set is I4; “startLive:I2” and “endLive:I4” together indicate an example of the first instruction set, namely, the instruction set consisting of I2, I3 and I4; “Reg:x9,x8” is the cell indicating whether the registers need to be freed or not.

[0226] Figure 15 The metadata shown includes identifiers for the start and end instructions, thus giving the processor more flexibility in when to retrieve this metadata, allowing it to retrieve the metadata at any time before executing In.

[0227] After acquiring the metadata, the processor determines the first instruction set and the registers that need to be freed. The processor can free x9 and x8 after I4 execution is complete, for example, by writing the execution result of I4 to x2 and then freeing x9 and x8; ​​the processor can also free x9 and x8 before I4 execution is complete, for example, by immediately freeing x9 and x8 after reading the data in x9 and x8.

[0228] Optionally, when the information element "x9,x8" in the metadata indicates the name of a register that does not need to be freed, the processor may free registers other than x9 and x8, such as x11 and x3, after or before the end of I4 execution.

[0229] Figure 16This is a schematic diagram of another type of first instruction information provided in an embodiment of this application.

[0230] like Figure 16 As shown, I1, I2, I3, I4, and In are instruction identifiers, and ldr, add, mul, and sub are instruction operations. ldr loads data into a register, add performs addition, mul performs multiplication, and sub performs subtraction. x represents a register.

[0231] Figure 16 The meanings of I1 to In in Figure 11 The meanings of I1 to In are the same, so I will not repeat them here.

[0232] The metadata carries the first indication information, where “startLive:I2” is an information cell indicating the starting instruction, indicating that the starting instruction of the first instruction set is I2; “3” is an information cell indicating the number of instructions, indicating that the number of instructions in the first instruction set is 3; “startLive:I2” and “3” together indicate an example of the first instruction set, namely, the instruction set consisting of I2, I3 and I4; “Reg:x9,x8” is an information cell indicating whether the registers need to be freed or not.

[0233] Figure 16 The metadata shown includes the identifier of the start instruction and the number of instructions. Therefore, the processor has more flexibility in when to obtain this metadata, and can obtain the metadata at any time before executing In.

[0234] After acquiring the metadata, the processor determines the first instruction set and the registers that need to be freed. The processor can free x9 and x8 after I4 execution is complete, for example, by writing the execution result of I4 to x2 and then freeing x9 and x8; ​​the processor can also free x9 and x8 before I4 execution is complete, for example, by immediately freeing x9 and x8 after reading the data in x9 and x8.

[0235] Optionally, when the information element "x9,x8" in the metadata indicates the name of a register that does not need to be freed, the processor may free registers other than x9 and x8, such as x11 and x3, after or before the end of I4 execution.

[0236] Figure 17 This is a schematic diagram of another type of first instruction information provided in an embodiment of this application.

[0237] like Figure 17As shown, I1, I2, I3, I4, and In are instruction identifiers, and ldr, add, mul, and sub are instruction operations. ldr loads data into a register, add performs addition, mul performs multiplication, and sub performs subtraction. x represents a register.

[0238] Figure 17 The meanings of I1 to In in Figure 11 The meanings of I1 to In are the same, so I will not repeat them here.

[0239] The metadata carries the first indication information, where "endLive:I4" is an information cell indicating the end instruction, indicating that the end instruction of the first instruction set is I4; "3" is an information cell indicating the number of instructions, indicating that the number of instructions in the first instruction set is 3; "endLive:I4" and "3" together indicate an example of the first instruction set, namely, the instruction set consisting of I2, I3 and I4; "Reg:x9,x8" is an information cell indicating whether the registers need to be freed or not.

[0240] Figure 17 The metadata shown includes the identifier of the last instruction and the number of instructions. Therefore, the processor has more flexibility in when to obtain this metadata and can obtain it at any time before executing In.

[0241] After acquiring the metadata, the processor determines the first instruction set and the registers that need to be freed. The processor can free x9 and x8 after I4 execution is complete, for example, by writing the execution result of I4 to x2 and then freeing x9 and x8; ​​the processor can also free x9 and x8 before I4 execution is complete, for example, by immediately freeing x9 and x8 after reading the data in x9 and x8.

[0242] Optionally, when the information element "x9,x8" in the metadata indicates the name of a register that does not need to be freed, the processor may free registers other than x9 and x8, such as x11 and x3, after or before the end of I4 execution.

[0243] Figures 15-17 In the embodiments shown, the first instruction information exists in the form of metadata. Compared with instructions, metadata contains richer information. For example, metadata can contain some source code level information, thereby providing richer management methods for the registers associated with the first instruction set.

[0244] Optionally, the metadata may also include an identifier for the end instruction but exclude an identifier for the start instruction.

[0245] For example, if the metadata includes the identifier of the last instruction as Ix, after the processor obtains the metadata, it can release the registers associated with all instructions before Ix after executing Ix, or it can release the registers associated with some instructions before Ix after executing Ix (the "some instructions" can be determined by the processor). In this way, the first indication information in the metadata does not need to carry the identifier of the start instruction, which reduces the resource overhead of the first indication information.

[0246] In all the examples described above, the processor executes instructions sequentially; that is, the instructions fetched by the processor first are executed first, and the instructions fetched later are executed later. Optionally, the processor can also execute instructions out of order.

[0247] Since the first instruction indicated by the first instruction information is the instruction that is first in the processing order of the first instruction set, and the last instruction indicated by the first instruction information is the instruction that is last in the processing order of the first instruction set, regardless of which method is used to execute the instruction, the processor can always complete the release of the registers associated with the first instruction set after the last instruction in the first instruction set is executed, thus avoiding releasing the registers associated with the first instruction set too early or too late.

[0248] In summary, method 600, by indicating a shorter lifespan—that is, the first lifespan of the register associated with the first instruction set—through the first indication information, can prompt the processor to release the register early. The released register can then be used by other instructions, thereby improving the efficiency of register resource utilization. Since the first indication information indicates the lifespan of a non-pipelined register, this embodiment can optimize register resources used by instructions with short lifespans as well as those used by instructions with long lifespans.

[0249] The following is another method for managing registers provided by an embodiment of this application.

[0250] like Figure 18As shown, the compiler can analyze the program and divide it into two code segments based on its function: source code 1 and source code 2. In source code 1, the content after the first if statement reads two values ​​from memory (i.e., xmx[i][XMN] and hmm->xsc[XTN][MOVE] in the first if statement), performs an addition operation on these two values ​​to obtain result 1, compares result 1 with -INFTY (negative infinity), and stores the larger value in memory (xmx[i][XMB]). In source code 1, the content after the second if statement reads two values ​​from memory (i.e., xmx[i][XMJ] and hmm->xsc[XTJ][MOVE] in the second if statement), performs an addition operation on these two values ​​to obtain result 2, compares result 2 with xmx[i][XMB], and stores the larger value in memory (xmx[i][XMB]). In source code 2, the content after the first if statement indicates that two values ​​are read from memory (i.e., xmx[i-1][XMC] and hmm->xsc[XTC][LOOP] in the first if statement), and the addition operation is performed on these two values ​​to obtain the result 3. The result 3 is compared with -INFTY (negative infinity), and the larger value is stored in memory (xmx[i][XMC]). In source code 2, the content after the second if statement indicates that two values ​​are read from memory (i.e., xmx[i][XME] and hmm->xsc[XTE][MOVE] in the second if statement), and the addition operation is performed on these two values ​​to obtain the result 4. The result 4 is compared with xmx[i][XMC], and the larger value is stored in memory (xmx[i][XMC]).

[0251] Subsequently, the compiler can convert source code 1 and source code 2 into assembly code 1.1 and assembly code 2.1, respectively. In assembly code 1.1 and assembly code 2.1, the first column represents the memory address; the second column represents the machine code; the third column represents the opcode in the assembly instruction; and the fourth column represents the operand in the assembly instruction.

[0252] The compiler can transform assembly code 1.1 and assembly code 2.1 into assembly code 1.2 and assembly code 2.2, respectively. The instructions corresponding to assembly code 1.2 are divided into instruction set 1, and the instructions corresponding to assembly code 2.2 are divided into instruction set 2. Here, w and x represent registers, #-16 represents an operand, lsl#3 indicates that the value in a register needs to be shifted left by 3 bits, and 40ace8 represents the destination address of a jump instruction. Subsequently, the compiler inserts hint instructions into instruction set 1 and instruction set 2, respectively.

[0253] In prompt instruction 1, "b.start 9" indicates that the nine instructions following prompt instruction 1 constitute an instruction set, namely instruction set 1; "[x3,x12,x29,x21,w24]" represents the input registers in the registers corresponding to instruction set 1, meaning that x3, x12, x29, x21, and w24 will have their data read by instruction set 1; "[]" represents registers in the registers corresponding to instruction set 1 that cannot be freed, meaning that the data in these registers needs to be used by subsequent instructions. In prompt instruction 1, the "[]" does not contain any register names, indicating that all registers corresponding to instruction set 1 must be freed.

[0254] In instruction 2, "b.start 9" indicates that the nine instructions following instruction 2 constitute an instruction set, i.e., instruction set 2; "[x3,x2,x4,x12,x21,w24]" represents the input registers in the registers corresponding to instruction set 2, meaning that x3, x2, x4, x12, x21, and w24 will have their data read by instruction set 2; "[]" represents registers in the registers corresponding to instruction set 2 that cannot be freed, meaning that the data in these registers needs to be used by subsequent instructions. In instruction 2, the "[]" does not contain any register names, indicating that all registers corresponding to instruction set 2 must be freed.

[0255] Subsequently, prompt instruction 1, instruction set 1, prompt instruction 2, and instruction set 2 are translated into machine code by the compiler and await processing by the processor. The processor then operates on the registers associated with each instruction set according to the received prompt instructions.

[0256] The foregoing has detailed the method examples provided in the embodiments of this application. It is understood that the corresponding apparatus, in order to achieve the above functions, includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0257] Figure 19 This is a schematic diagram of a register management device provided in an embodiment of this application. The device 1900 includes a processing unit 1910 and a communication unit 1920. The communication unit 1920 performs input steps and / or output steps under the control of the processing unit 1910.

[0258] When device 1900 is used to implement the function of method 600, communication unit 1920 is used to: acquire first indication information, the first indication information indicating the first lifetime of a register associated with the first instruction set, the first lifetime being less than a second lifetime, the second lifetime being the lifetime of the register associated with the first instruction set determined by the processor, the processor being used to process the first instruction set; processing unit 1910 is used to: process the first instruction set; release the register associated with the first instruction set according to the first indication information, wherein the actual lifetime of the register associated with the first instruction set is less than or equal to the first lifetime.

[0259] Optionally, the first lifetime is equal to the processing time of the first instruction set, and the processing unit 1910 is specifically used to: release the register associated with the first instruction set when the processing of the last instruction of the first instruction set is completed, according to the first instruction information, where the last instruction is the instruction in the first instruction set that is processed last.

[0260] Optionally, the first indication information is carried in the first instruction, and the first indication information includes a first information cell, which indicates the first instruction set.

[0261] Optionally, the first information element includes: an identifier of the end instruction, and / or an identifier of the start instruction, wherein the end instruction is the instruction at the end of the processing order in the first instruction set, and the start instruction is the instruction at the beginning of the processing order in the first instruction set.

[0262] Optionally, the first information cell includes the number of instructions in the first instruction set.

[0263] Optionally, the first indication information is carried in metadata. The first indication information includes the identifier of the end instruction, or the first indication information includes the identifier of the start instruction and the identifier of the end instruction. The start instruction is the instruction that is the first instruction in the processing order of the first instruction set, and the end instruction is the instruction that is the last instruction in the processing order of the first instruction set.

[0264] Optionally, the first indication information includes a second information element, which indicates a register in the register associated with the first instruction set that needs to be freed.

[0265] Optionally, the first instruction set is an instruction set of the first program, and the first program also includes a second instruction set, wherein the program function corresponding to the first instruction set is different from the program function corresponding to the second instruction set.

[0266] Optionally, the number of instructions in the first instruction set is positively correlated with the number of processor registers.

[0267] Optionally, before obtaining the first instruction information, the processing unit 1910 is further configured to: run a first program, the first program being a program corresponding to the first instruction set; and provide feedback on the running result, the running result indicating the use of registers during the running of the first program, the running result being used to determine the first instruction information.

[0268] Those skilled in the art will clearly understand that the specific working process of the device 1900 and the technical effects produced by its execution steps can be referred to the description in the corresponding method embodiments above. For the sake of brevity, they will not be repeated here.

[0269] Device 1900 may be a terminal, server, or chip. Processing unit 1910 may be a logic circuit or integrated circuit, etc.; communication unit 1920 may be an input / output interface, pins, or circuits, etc. Communication unit 1920 may be integrated into processing unit 1910 or may exist independently outside of processing unit 1910.

[0270] Figure 20 This is a schematic diagram of another register management device provided in an embodiment of this application. The processor 2000 includes a control unit 2010, wherein the control unit 2010 includes a parsing module 2011 and a register control module 2012. Optionally, the processor 2000 further includes a storage unit 2020 and an arithmetic unit 2030. The control unit 2010, storage unit 2020, and arithmetic unit 2030 can be connected via a bus.

[0271] The parsing module 2011 is used to parse the instruction or metadata carrying the first instruction information and determine the first lifetime of the register associated with the first instruction set; the register control module 2012 is used to control the register associated with the first instruction set according to the first lifetime and release the register at an appropriate time.

[0272] The storage unit 2020 may include registers associated with the first instruction set. The arithmetic unit 2030 is used to process the first instruction set.

[0273] Figure 21 This is a schematic diagram of another device for managing registers provided in an embodiment of this application.

[0274] For ease of explanation, Figure 21 Only the main components of device 2100 are shown. (Example) Figure 21As shown, device 2100 includes a processor 2110, a memory 2120, and an input / output device 2130. The processor 2110 is mainly used for data processing and controlling the entire device 2100, executing software programs, and processing data from these programs, for example, to support the device 2100 in performing the actions described in the above method embodiments. The memory 2120 is mainly used for storing software programs and data. The input / output device 2130, such as a network interface card (NIC) or an antenna, is mainly used for receiving and outputting data. The processor 2110, memory 2120, and input / output device 2130 can be connected via a bus.

[0275] The processor 2110 and memory 2120 can be located on one or more circuit boards. That is, the memory and processor can be set separately on each circuit board, or multiple circuit boards can share the same memory and processor. In addition, necessary circuitry can be set on each circuit board.

[0276] Those skilled in the art will understand that, for ease of explanation, Figure 21 Only one memory and one processor are shown. In a real terminal or server, there may be multiple processors and multiple memories. Memory may also be called storage medium or storage device, etc., and this application does not limit it in this way.

[0277] The processor 2110 can be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by the integrated logic circuitry of the processor's hardware.

[0278] The memory 2120 can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM).

[0279] Finally, the following points should be noted regarding the embodiments of this application:

[0280] First, in the embodiments of this application, the terms "first," "second," and various numerical designations are merely distinctions for ease of description and are not intended to limit the scope of the embodiments of this application.

[0281] Second, in the embodiments of this application, "instruction" can include direct and indirect instructions, as well as explicit and implicit instructions. The information indicated by a certain piece of information is called the information to be instructed. In specific implementations, there are many ways to instruct the information to be instructed. For example, the information to be instructed can be directly instructed, such as the information to be instructed itself or its index. The information to be instructed can also be indirectly indicated by instructing other information, where there is a correlation between the other information and the information to be instructed. Alternatively, only a part of the information to be instructed can be indicated, while the other parts are known or pre-agreed upon. For example, the indication of the information to be indicated can be achieved by pre-agreing on the existence of a certain information element, thereby reducing the instruction overhead to some extent.

[0282] Third, "at least one" means one or more, while "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously. Here, A and B can be a single object or multiple objects. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can each be a single object or multiple objects.

[0283] Fourth, in the embodiments of this application, descriptions such as "when," "in the case of," "if," and "if" all refer to the fact that the device (e.g., a chip, terminal, or server) will make corresponding processing under certain objective circumstances. They are not time limits, nor do they require the device to make a judgment action during implementation, nor do they imply any other limitations.

[0284] Fifth, in the various embodiments of this application, unless otherwise specified or logically conflicting, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

Claims

1. A method of managing a register, characterized by, The method comprises: obtaining first indication information, the first indication information indicating a first life cycle of registers associated with a first instruction set, the first life cycle being smaller than a second life cycle, the second life cycle being a life cycle of registers associated with the first instruction set determined by a processor, the processor being used for processing the first instruction set; processing the first instruction set; releasing the registers associated with the first instruction set according to the first indication information, wherein an actual life cycle of the registers associated with the first instruction set is smaller than or equal to the first life cycle.

2. The method of claim 1, wherein, The first life cycle is equal to a processing time of the first instruction set, and the releasing the registers associated with the first instruction set according to the first indication information comprises: completing the releasing of the registers associated with the first instruction set when processing of a last instruction of the first instruction set is completed according to the first indication information, the last instruction being one instruction located at the end in processing order in the first instruction set.

3. The method according to claim 1 or 2, characterized in that, The first indication information is carried in a first instruction, and the first indication information comprises a first information element, the first information element indicating the first instruction set.

4. The method of claim 3, wherein, The first information element comprises an identification of a last instruction, and / or an identification of a start instruction, wherein the last instruction is one instruction located at the end in processing order in the first instruction set, and the start instruction is one instruction located at the beginning in processing order in the first instruction set.

5. The method according to claim 3 or 4, characterized in that, The first information element comprises a number of instructions of the first instruction set.

6. The method of claim 1 or 2, wherein, The first indication information is carried in metadata, and the first indication information comprises an identification of a last instruction, or the first indication information comprises an identification of a start instruction and an identification of a last instruction, the start instruction being one instruction located at the beginning in processing order in the first instruction set, and the last instruction being one instruction located at the end in processing order in the first instruction set.

7. The method according to any one of claims 3 to 6, characterized in that, The first indication information comprises a second information element, the second information element indicating registers of the registers associated with the first instruction set that need to be released.

8. The method according to any one of claims 1 to 7, characterized in that, The first instruction set is one instruction set of a first program, and the first program further comprises a second instruction set, and a program function corresponding to the first instruction set is different from a program function corresponding to the second instruction set.

9. The method according to any one of claims 1 to 8, characterized in that, The number of instructions of the first instruction set is positively correlated with a number of registers of the processor.

10. The method according to any one of claims 1 to 9, characterized in that, Before the obtaining the first indication information, the method further comprises: running a first program, the first program being a program corresponding to the first instruction set; feeding back a running result, the running result indicating a usage of registers in a running process of the first program, and the running result being used for determining the first indication information.

11. An apparatus for managing a register, the apparatus comprising: The apparatus comprises: a module for executing the method according to any one of claims 1 to 10.

12. An apparatus for managing a register, the apparatus comprising: The apparatus comprises: a processor configured to execute a computer program stored in a memory, so that the apparatus executes the method according to any one of claims 1 to 10; a communication interface coupled with the processor and configured to input or output information.

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