Hybrid NAND adaptive caching method based on integrated circuit

Abstract

The invention relates to the technical field of intelligent chips, in particular to a hybrid NAND self-adaptive caching method based on an integrated circuit, which comprises the following steps: collecting an erasure period, an error rate and a mode switching interval of a physical block; generating a physical damage cardinal number of the quantitative mode switching stress through a stress accumulation model, and calculating a drift compensation factor representing a charge detrapping effect through a time decay function; carrying out differential correction operation on the two blocks to output wear entropy, and sorting the free block pool to select a target physical block; an annular shadow log area is initialized in the cache, metadata micro log entries are written in through a cache aggregation mechanism, and finally garbage collection is triggered to execute consistency updating on a global mapping table. According to the method, high-reliability abrasion balance is achieved by quantifying the comprehensive abrasion of the physical block, high-frequency metadata updating is isolated through the annular log area, write-in amplification is remarkably reduced, the system response speed is increased, and the effective service life of the NAND flash memory is prolonged.

Description

Technical Field

[0001] This invention relates to the field of smart chip technology, specifically to an integrated circuit hybrid NAND adaptive caching method. Background Technology

[0002] In the storage control architecture of intelligent chips, to mitigate the performance difference between high-speed computing units and the write latency of backend non-volatile storage media, a hybrid addressing strategy is typically employed. This involves logically mapping the physical address space of some three-level or four-level units to a pseudo-single-level unit mode, constructing a first-level write cache to handle bursty data flows. This dynamic cache allocation method achieves a balance between performance and capacity by adjusting the size of the cache hierarchy in real time.

[0003] However, in smart chip architectures without external caches, which are limited by integration and power consumption, the above-mentioned hierarchical management method has a significant logical maintenance bottleneck. Since the on-chip system lacks sufficient volatile random access resources to reside a complete logical-physical address mapping table, whenever the boundary of the cache level is dynamically migrated, the controller must frequently perform metadata consistency update operations to synchronously flush the changed mapping relationship to the non-volatile memory area.

[0004] Existing cache address management logic lacks a buffering mechanism for high-frequency mapping changes. Without a dedicated shadow log structure, dynamic refactoring of cache capacity leads to an exponential increase in the write amplification factor of mapping metadata, causing the storage area for management information to be exhausted before the data area. Simultaneously, existing cache block allocation algorithms typically rely solely on simple access or erase counts for scheduling, failing to logically perceive the mode-switching stress caused by physical units switching between different hierarchical modes. Furthermore, they do not incorporate a static weighting factor based on charge trap recovery characteristics into the allocation strategy. These deficiencies in allocation logic prevent the construction of an accurate lifetime measurement model based on wear entropy, causing address units responsible for dynamic cache hierarchy transitions to fail prematurely in high-reliability applications of smart chips.

[0005] Therefore, this invention proposes an adaptive caching method based on integrated circuit hybrid NAND. Summary of the Invention

[0006] The purpose of this invention is to provide an adaptive caching method based on integrated circuit hybrid NAND. By constructing a wear entropy model that introduces charge detrapping compensation and a ring shadow log aggregation mechanism, it can achieve accurate prediction of physical block lifetime and low-overhead consistent updating of metadata, thereby extending the chip's lifespan.

[0007] To achieve the above objectives, the present invention provides the following technical solution: An integrated circuit-based hybrid NAND adaptive caching method includes: Collect the erase cycle, mode switching interval, and bit error rate statistics triggered by voltage transitions of physical blocks in NAND flash memory chips; The erase cycle and bit error rate statistics are input into the stress accumulation model, and the physical damage base of the mode switching stress of the tunnel oxide layer is generated by integral operation. The mode switching interval is processed by the time decay function, and the drift compensation factor characterizing the charge detrapping effect is calculated. The wear entropy is output by performing differential correction calculation on the physical damage base and drift compensation factor through a nonlinear health assessment model; the wear entropy is used to prioritize the idle block pool, select target physical blocks, and establish pseudo-single-layer unit cache level nodes. A circular shadow log area, serving as a metadata index structure, is initialized within the pseudo-single-level unit cache node. Logical physical address translation metadata required for updating the global mapping table is intercepted and encapsulated into micro-log entries containing checksums. The microlog entries are written to the circular shadow log area in full using a cache aggregation mechanism. When the tail pointer reaches a preset threshold, the garbage collection process is triggered. The aggregated microlog entries are parsed, the address translation metadata is reconstructed, and a consistent update is performed on the global mapping table.

[0008] Preferably, the step of inputting the erase cycle and bit error rate statistical indicators into the stress accumulation model and generating the physical damage base of the mode switching stress of the tunnel oxide layer through integral calculation specifically includes: using the current erase cycle of the physical block and the original bit error rate measured before and after mode switching as the statistical indicators; the physical damage base is a variable that takes the current erase cycle as the initial value and accumulates the nonlinear damage increment generated by mode switching; the stress accumulation model is a conversion that normalizes the dimensionless bit error rate change amplitude to the equivalent number of erase cycles through the tunnel oxide layer fatigue coefficient. The model employs a discretized weighted summation algorithm to perform the integral operation. Specifically, the discretized weighted summation algorithm includes: defining a pseudo-single-layer cell mode as a dual-voltage state and a multi-layer cell mode as a multi-voltage state; whenever a physical block switches attributes between the dual-voltage state and the multi-voltage state, calculating the change in the current original bit error rate relative to the previous moment; multiplying the change in the change by a preset tunnel oxide layer fatigue coefficient, and accumulating this as the nonlinear damage increment into the physical damage base, thus quantifying the nonlinear damage generated by the physical block due to repeated voltage tolerance window resets.

[0009] Preferably, the step of processing the mode switching interval through a time decay function and calculating the drift compensation factor characterizing the charge detrapping effect includes: obtaining the resting time window of the physical block; processing the resting time window using a logarithmic time-dependent model, wherein the logarithmic time-dependent model uses a function logic with an exponentially decaying growth rate to calculate the drift compensation factor: the value of the drift compensation factor increases with the increase of the resting time window, and the growth rate of the drift compensation factor gradually decreases until it reaches a preset maximum compensation threshold; substituting the calculated drift compensation factor as a detrapping gain term into the differential correction operation to simulate the charge detrapping characteristics of the threshold voltage in the tunnel oxide layer receding over time; the resting time window is the time interval from the moment the physical block exits the pseudo-single-layer cell mode to the moment it is selected again to perform an erase operation; the logarithmic time-dependent model is a calculation model characterizing the change of the charge detrapping effect over time.

[0010] Preferably, the step of prioritizing the idle block pool using wear entropy and selecting the target physical block is also controlled by a fatigue circuit breaker mechanism: a wear entropy safety threshold is set, and when the wear entropy index of the target physical block in the idle block pool exceeds the safety threshold, the physical block is marked as statically locked; when establishing a pseudo-single-layer unit cache level node, the physical block in the statically locked state is forcibly logically shielded and downgraded to a static address mapping pool that is only used to store data with an access frequency lower than a preset frequency threshold.

[0011] Preferably, the initialization of the circular shadow log area as a metadata index structure within the pseudo-single-layer unit cache level node includes: dividing the target block into multiple physical pages, and configuring a logical pointer associated with the next physical page in the spare area of ​​each physical page; using the page tail linked list pointer to link multiple physical blocks with non-contiguous physical addresses into a logically closed virtual circular buffer; the cache aggregation mechanism is configured to sequentially concatenate micro-log entries in on-chip volatile memory, and only perform writing the micro-log entries once when the page size is full.

[0012] Preferably, after the step of encapsulating the micro-log entry with a checksum, the method further includes: extracting the logical address key value from the logical physical address translation metadata and mapping it to a Bloom filter residing in the on-chip static random access memory of the storage controller; when performing a data read operation, the Bloom filter is queried first, and the traversal retrieval of the micro-log entry is only initiated when the Bloom filter determines that the logical address key value exists in the circular shadow log area, thereby reducing read latency.

[0013] Preferably, the step of performing a consistent update on the global mapping table adopts an atomic replay mechanism: the micro-log entries are encapsulated with monotonically increasing global sequence numbers; when garbage collection and abnormal power failure recovery are triggered, the micro-log entries scattered in the circular shadow log area are reassembled in time according to the global sequence numbers, and the end entries that fail to verify the checksum are discarded. The reassembled address translation metadata is then merged into the global mapping table in batches in an atomic transaction manner.

[0014] Preferably, before intercepting the logical physical address translation metadata required to update the global mapping table and encapsulating it into a micro-log entry with a checksum, a dual-path flow determination is performed: the characteristics of the host write data stream are identified. If the data length is identified as less than a preset page size threshold and the logical address is not contiguous, the steps of encapsulating the micro-log entry and appending it to the circular shadow log area are continued. If the data length is identified as greater than or equal to the preset page size threshold and the logical address is contiguous, the circular shadow log area is bypassed, the data is directly written to the main storage array, and the global mapping table is updated only once at the end of the data stream transmission, thus isolating the blocking interference of large-volume data on the metadata index structure.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention does not rely solely on the number of erase cycles. Instead, it differentially corrects the physical damage baseline caused by mode switching and the drift compensation factor generated by the charge detrapping effect during rest, accurately quantifying the oxide layer health. Simultaneously, it incorporates a fatigue-induced failure mechanism, forcibly downgrading physical blocks with excessive wear entropy to data accessed at frequencies below a preset threshold. This strategy effectively corrects the traditional algorithm's neglect of "self-healing" characteristics, preventing premature failures caused by fragile blocks prematurely bearing the burden of high-stress cache layers, and significantly improving the overall durability of the hybrid NAND architecture.

[0016] 2. By utilizing on-chip volatile memory to aggregate and concatenate fragmented logical-to-physical address translation metadata, a one-time write is performed only when the physical page is full, and the data is appended to a virtual circular buffer of a pseudo-single-level cell in the form of a micro-log. This design transforms high-frequency random updates of metadata into low-frequency sequential full-page writes. While strictly adhering to the modern NAND flash memory's prohibition of multiple partial page programming (NOP limit), it significantly reduces the write amplification factor during the mapping table synchronization process, alleviating system-level memory congestion.

[0017] 3. A Bloom filter residing in the on-chip SRAM is used to pre-screen log entries, reducing latency from invalid Flash reads. Simultaneously, during garbage collection or power-down recovery, global sequence numbers in the micro-logs are used for time-series reordering and atomic merging. This mechanism ensures that even in the event of an abnormal interruption during dynamic cache level adjustments, the global mapping table can be accurately reconstructed, resolving the metadata corruption or loss issues that easily arise when dynamically dividing cache boundaries in traditional solutions. Attached Figure Description

[0018] Figure 1 This is a flowchart of the integrated circuit hybrid NAND adaptive caching method of the present invention; Figure 2 This is a flowchart illustrating the wear entropy calculation and target physical block selection in an embodiment of the present invention; Figure 3 This is a schematic diagram of the dual-path traffic splitting and cache aggregation mechanism in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Other embodiments obtained by those skilled in the art based on the ideas in this specification without creative effort all fall within the protection scope of this invention.

[0020] Reference Figures 1 to 3 This invention provides an adaptive caching method based on integrated circuit hybrid NAND, the specific technical solution of which is as follows: Collect the erase cycle, mode switching interval, and bit error rate statistics triggered by voltage transitions of physical blocks in NAND flash memory chips; The erase cycle and bit error rate statistics are input into the stress accumulation model, and the physical damage base of the mode switching stress of the tunnel oxide layer is generated by integral operation. The mode switching interval is processed by the time decay function, and the drift compensation factor characterizing the charge detrapping effect is calculated. The wear entropy is output by performing differential correction calculation on the physical damage base and drift compensation factor through a nonlinear health assessment model; the wear entropy is used to prioritize the idle block pool, select target physical blocks, and establish pseudo-single-layer unit cache level nodes. A circular shadow log area, serving as a metadata index structure, is initialized within the pseudo-single-level unit cache node. Logical physical address translation metadata required for updating the global mapping table is intercepted and encapsulated into micro-log entries containing checksums. The microlog entries are written to the circular shadow log area in full using a cache aggregation mechanism. When the tail pointer reaches a preset threshold, the garbage collection process is triggered. The aggregated microlog entries are parsed, the address translation metadata is reconstructed, and a consistent update is performed on the global mapping table.

[0021] Example 1: This invention discloses an integrated circuit-based hybrid NAND adaptive caching method. This embodiment uses the internal storage control of a smart chip as a specific application scenario. This smart chip is integrated into a smart security camera as a system-on-a-chip. In this scenario, the storage controller of the smart chip needs to handle the massive, small, and high-frequency random write requests generated by its edge AI analysis module when performing image recognition and event detection tasks, such as coordinate metadata for dynamic target tracking and classification labels for abnormal events. To improve write performance and extend flash memory lifespan without the hardware constraints of an external dynamic random access memory, a method is described below. Figure 1 The specific technical process of the method proposed in this invention in this scenario is summarized as follows: The method collects key performance indicators of physical blocks in NAND flash memory chips, including erase cycle, mode switching interval, and bit error rate triggered by voltage transition; a nonlinear health assessment model is constructed based on the stress accumulation model and time decay function to calculate and generate wear entropy that quantifies the overall wear degree of physical blocks; the idle physical blocks are sorted using this wear entropy, and the target physical blocks are selected to establish a pseudo-single-layer cell cache level; a circular shadow log area is deployed in this cache level, and address translation metadata is intercepted and written through the cache aggregation mechanism, and finally garbage collection is triggered under specific conditions to achieve consistent updates of the global mapping table.

[0022] Furthermore, the step of inputting the erase cycle and bit error rate statistical indicators into the stress accumulation model, and generating the physical damage base of the quantified tunnel oxide layer mode switching stress through integral calculation, specifically includes: using the current erase cycle of the physical block and the original bit error rate measured before and after mode switching as the statistical indicators; the physical damage base is a variable that takes the current erase cycle as the initial value and accumulates the nonlinear damage increment caused by mode switching; the stress accumulation model is a conversion that normalizes the dimensionless bit error rate change amplitude to the equivalent number of erase cycles through the tunnel oxide layer fatigue coefficient. The model employs a discretized weighted summation algorithm to perform the integral operation. Specifically, the discretized weighted summation algorithm includes: defining a pseudo-single-layer cell mode as a dual-voltage state and a multi-layer cell mode as a multi-voltage state; whenever a physical block switches attributes between the dual-voltage state and the multi-voltage state, calculating the change in the current original bit error rate relative to the previous moment; multiplying the change in the change by a preset tunnel oxide layer fatigue coefficient, and accumulating this as the nonlinear damage increment into the physical damage base, thus quantifying the nonlinear damage generated by the physical block due to repeated voltage tolerance window resets.

[0023] Specifically, in the intelligent chip memory controller of this embodiment, the integral operation is the concrete execution of the stress accumulation model, which is implemented as a discretized weighted summation algorithm triggered each time the physical block's operating mode switches. The controller defines physical blocks configured in pseudo-single-level cell (pSLC) mode as a dual-voltage state, in which each memory cell only needs to distinguish two voltage thresholds. In contrast, the three-level cell (TLC) mode of the main memory array is defined as a multi-voltage state, in which each memory cell needs to distinguish eight different voltage thresholds. The controller firmware maintains a physical damage cardinality variable in on-chip static random access memory (SRAM) for each physical block in the flash memory array. The initial value of this variable is set to the current erase cycle read from the flash memory chip metadata area of ​​the physical block.

[0024] A specific example of the discretized weighted summation algorithm is as follows: A physical block B10 in TLC mode has a current erase cycle of 1000, so its initial physical impairment base is 1000. When the cache scheduling logic decides to temporarily convert physical block B10 to pSLC mode for use as a write cache, the controller immediately performs an internal read verification operation on the block after completing the mode conversion, and obtains its initial raw bit error rate (RBER) through the built-in error correction code engine, recording it as RBER_initial=0.00005. After physical block B10 is used as a pSLC cache for a period of time, it is released and switched back to TLC mode. After switching back to TLC mode, the controller performs the same internal read verification again to obtain the raw bit error rate at this moment, recording it as RBER_final=0.00011.

[0025] The controller then calculates the change in bit error rate (BER), ΔRBER = RBER_final - RBER_initial = 0.00006. Subsequently, the controller reads a preset tunnel oxide fatigue coefficient from the firmware configuration area, for example, 250000. This coefficient is pre-calibrated based on the physical characteristics of this type of NAND flash memory through offline wafer-level reliability testing. The calibration method is as follows: A sample physical block is selected and alternately erased / written between pseudo-single-layer cell mode and multi-layer cell mode until it reaches the designed nominal lifetime; the total average BER increment accumulated during this process is recorded; the designed nominal lifetime is divided by this total average BER increment, and the quotient is the tunnel oxide fatigue coefficient. Therefore, this coefficient is used to normalize the dimensionless BER change value to an equivalent number of erase cycles. Its physical meaning is to convert the dimensionless BER change value into an equivalent damage amount equivalent to the number of erase cycles. The controller calculates the nonlinear damage increment introduced by mode switching: Nonlinear damage increment = ΔRBER × tunnel oxide fatigue coefficient = 0.00006 × 250000 = 15. Finally, the controller adds this nonlinear damage increment to the physical damage base of physical block B10, resulting in an updated physical damage base of 1000 + 15 = 1015. This updated value will serve as input for subsequent nonlinear health assessment models.

[0026] In a preferred embodiment, the method further includes: during the garbage collection process, statistically analyzing the original bit error rate of the physical page where the parsed microlog entries are located, and constructing a long-term trend of the bit error rate changing with the global sequence number; and dynamically adjusting the preset tunnel oxide layer fatigue coefficient based on the slope change of the long-term trend.

[0027] Specifically, during each garbage collection, the controller not only parses micro-log entries but also records the raw bit error rate (RBER) of each physical page containing valid logs. The controller maintains a sliding window recording the average RBER of all log pages across the last 10 GC cycles. The controller found that in the early stages of system operation, the slope of this average RBER growth over time (which can be indirectly characterized by the GSN) closely matched the factory model (slope k). However, after six months of operation, the controller calculated that the most recent average RBER growth slope reached 1.2k, indicating that the actual aging rate of physical blocks was 20% faster than predicted by the model. In response, an adaptive calibration mechanism was triggered, and the controller performed linear feedback adjustment to update the tunnel oxide layer fatigue coefficient. The specific adjustment logic is as follows: calculate the deviation ratio of the current slope from the factory reference slope, multiply this deviation ratio by a preset adjustment gain coefficient to obtain an adjustment factor, and finally multiply the original tunnel oxide layer fatigue coefficient by one and add the adjustment factor to obtain the updated coefficient. In this embodiment, based on the above logic, the controller increases the tunnel oxide layer fatigue coefficient (e.g., 250,000) stored in the firmware by 20%, updating it to 300,000. Subsequently, the system uses this coefficient, which better reflects the current actual situation, to calculate nonlinear damage, achieving closed-loop adaptation of the damage assessment model.

[0028] This scheme constructs a feedback loop from "effect" (historical error rate) to "cause" (damage model parameters), enabling the health assessment model to have self-learning and self-calibration capabilities, ensuring its assessment accuracy throughout its entire life cycle.

[0029] The traditional erase cycle count is modified by introducing a dynamic impairment measure based on the magnitude of bit error rate changes. This method can more accurately quantify the accelerated aging effect caused by physical blocks switching between different operating modes. Compared with the traditional method that relies solely on a single erase count, it provides a more accurate benchmark for assessing the health of physical blocks, thereby avoiding improper cache allocation of physical blocks subjected to high mode switching stress and extending the overall effective lifespan of the storage medium.

[0030] Further, the step of processing the mode switching interval through a time decay function and calculating the drift compensation factor characterizing the charge detrapping effect includes: obtaining the static time window of the physical block; processing the static time window using a logarithmic time-dependent model, wherein the logarithmic time-dependent model uses a nonlinear growth logic with saturation characteristics to calculate the drift compensation factor: the value of the drift compensation factor increases with the increase of the static time window, and the growth rate of the drift compensation factor gradually decreases until it reaches a preset maximum compensation threshold; substituting the calculated drift compensation factor as a detrapping gain term into the differential correction operation to simulate the charge detrapping characteristics of the threshold voltage in the tunnel oxide layer receding over time; the static time window is the time interval from the moment the physical block exits the pseudo-single-layer cell mode to the moment it is selected again to perform an erase operation; the logarithmic time-dependent model is a calculation model characterizing the change of the charge detrapping effect over time.

[0031] Specifically, in the intelligent chip storage controller of this embodiment, this calculation step is triggered when a physical block is selected by the garbage collection mechanism or wear leveling logic and is about to be erased. The controller first needs to obtain the idle time window of the physical block. To this end, the controller maintains a timestamp field in the metadata of each physical block. When a physical block (e.g., the aforementioned physical block B10) finishes its pSLC caching task, is reconfigured to TLC mode, and returned to the free block pool, the controller records the current system runtime as its hibernation start timestamp. When physical block B10 is subsequently selected for erasure, the controller obtains the current system runtime again and calculates the difference between the two timestamps. This difference is the idle time window (i.e., the time interval duration). For example, if the hibernation start timestamp is the 1,200,000th second after system startup and the current timestamp is the 1,459,200th second, then the idle time window is 259,200 seconds, or 72 hours.

[0032] After obtaining the resting time window, the controller uses a lookup table embedded in the firmware to determine the drift compensation factor. This lookup table is a concrete implementation of the aforementioned logarithmic time-dependent model, and its values ​​are set according to nonlinear logic where the growth rate decreases over time and tends to saturate, mapping different resting time window intervals to specific compensation factor values. These values ​​are determined by the NAND chip manufacturer through detailed offline characterization tests of the chip's charge retention characteristics at different temperatures and idle durations. In this embodiment, the mapping relationship fixed in the lookup table is specifically set as follows: For a resting time window of less than 1 hour, the corresponding drift compensation factor is 1.00; for a resting time window between 1 and 12 hours, the corresponding drift compensation factor is 1.15 (rapid growth); for a resting time window between 12 and 48 hours, the corresponding drift compensation factor is 1.25 (decreasing growth rate); for a resting time window between 48 and 168 hours (7 days), the corresponding drift compensation factor is 1.30 (further decreasing growth rate); and for a resting time window greater than 168 hours, the corresponding drift compensation factor is 1.32. Here, 1.32 is the saturation compensation threshold determined by the material physical properties of this type of storage medium, which is the aforementioned preset maximum compensation threshold, representing the maximum recovery level achievable by the charge detrapping effect at a specific operating temperature of this type of storage medium. Based on the aforementioned 72-hour resting time window, the controller determines the drift compensation factor for physical block B10 to be 1.30 by querying the table. This factor is then stored for subsequent wear entropy calculations.

[0033] In a preferred embodiment, the step of calculating the drift compensation factor specifically includes: periodically collecting and accumulating the operating temperature of the integrated circuit within the resting time window to generate an integrated heat value; using the resting time window and the integrated heat value as inputs, and calculating the drift compensation factor through a preset two-dimensional data structure. In this step, the calculation of the drift compensation factor is based on the thermal annealing physical characteristics of the semiconductor storage medium: that is, during the resting period in the erase state, a higher ambient temperature can provide activation energy, accelerating the release process of trapped electrons in the oxide layer (de-trapping effect), thereby restoring the threshold voltage window margin of the physical block more quickly than at room temperature. Therefore, a higher integrated heat value is positively correlated to a higher compensation factor in this model.

[0034] Specifically, when physical block B10 enters sleep mode, the controller not only records the start timestamp but also starts a low-power temperature accumulation timer. This timer wakes up every 10 minutes, periodically sampling the operating temperature of the integrated circuit and calculating the equivalent aging time using a discretized Arrhenius acceleration model. Specifically, the controller samples the current temperature at preset time intervals and calculates the acceleration factor within that time interval based on the exponential relationship between the activation energy and the reciprocal of the current temperature. The acceleration factor is multiplied by the time interval length to obtain the equivalent aging increment, and the increments of all time intervals are accumulated to generate a temperature-weighted effective resting time window. During its 72-hour resting window, the controller records a total of 432 temperature sampling points and calculates its average resting temperature to be 45°C. At this time, the controller accesses a two-dimensional matrix lookup table, which is a concrete implementation of the aforementioned two-dimensional data structure. The X-axis of this table represents the resting time, and the Y-axis represents the average resting temperature. The controller queries the coordinates of "72 hours" and "45°C" to obtain a more accurate drift compensation factor, such as 1.42, which is higher than 1.30 at room temperature (25°C) because it accurately quantifies the accelerated charge decapitation effect at higher temperatures.

[0035] This approach improves the recovery model from a one-dimensional time-dependent model to a two-dimensional time- and temperature-dependent model, enabling health assessments to accurately account for thermal relaxation effects and significantly enhancing the model's accuracy and robustness in real-world working environments.

[0036] By quantifying the charge recovery effect of physical blocks during rest periods, the health assessment model can incorporate time-dependent self-healing characteristics. This allows the wear leveling algorithm to prioritize physical blocks whose health has recovered, avoiding concentrated wear on blocks under continuous stress, thereby improving the overall durability and reliability of flash memory.

[0037] Reference Figure 2 The figure illustrates a detailed flowchart of the wear entropy calculation and target physical block selection in an embodiment of the present invention. As shown, after collecting the key performance indicators of the physical blocks, the process is carried out in two parallel paths: first, a base number for quantifying physical damage is generated through a stress accumulation model; second, a compensation factor characterizing the charge recovery effect is calculated through a time decay function. These two key parameters are then combined for a differential correction operation to output the final wear entropy. This wear entropy then serves as the core basis for a decision-making process, which includes a judgment on whether the wear entropy exceeds a safety threshold, and subsequent priority ranking and selection of all candidate blocks.

[0038] Furthermore, the step of prioritizing the idle block pool using wear entropy and selecting the target physical block is also controlled by a fatigue circuit breaker mechanism: a wear entropy safety threshold is set, and when the wear entropy index of the target physical block in the idle block pool exceeds the safety threshold, the physical block is marked as statically locked; when establishing a pseudo-single-layer unit cache level node, the physical block in the statically locked state is forcibly logically shielded and downgraded to a static address mapping pool that is only used to store data with an access frequency lower than a preset frequency threshold.

[0039] Specifically, before performing priority sorting, the storage controller first generates the wear entropy for each idle physical block based on the physical damage baseline and drift compensation factor calculated in the aforementioned steps. This operation is a nonlinear weighted evaluation operation, designed to assess the current charge stability state of the physical block rather than just structural damage. The specific calculation logic is configured to execute the following three-level operation steps: First, gain extraction operation: calculate the difference between the current drift compensation factor and a preset baseline value (usually 1.0) to obtain the net gain reflecting the degree of charge recovery; Second, nonlinear weighted operation: map the net gain to a preset nonlinear weight curve or multiply it by a conservative coefficient to calculate the actual effective recovery correction ratio, which is limited to no more than a preset upper limit threshold to prevent overestimation of the recovery effect; Third, baseline correction operation: multiply the physical damage baseline by the recovery correction ratio to obtain the equivalent recovery amount, and subtract the equivalent recovery amount from the physical damage baseline. The result is the final output wear entropy. For example, if the physical damage baseline is 1015 and the drift compensation factor is 1.30, with a conservative coefficient of 0.5, the system deducts the calculated recovery amount from the baseline, thus quantifying the temporary health recovery due to inactivity. This logic reflects the fact that although the charge detrapping effect temporarily improves the signal-to-noise ratio, physical structural damage still exists. Taking the aforementioned physical block B10 as an example, its physical damage baseline is 1015, and its drift compensation factor is 1.30 (i.e., exceeding the baseline value by 0.3). If the conservative coefficient is set to 0.5, its wear entropy index is approximately 862. This value does not mean that the physical block has actually become "younger," but rather that it has a stronger short-term write tolerance capability at the current moment due to the charge recovery effect. The controller performs this operation on all blocks in the free block pool and sorts them according to the wear entropy value from low to high. Blocks with lower wear entropy are given higher priority and used to establish pseudo-single-layer cell caches.

[0040] The sorting and selection process is controlled by a fatigue circuit breaker mechanism. This mechanism presets a fixed wear entropy safety threshold, which is calibrated based on the design lifespan specification of the NAND chip (e.g., 3000 erase / write cycles). In this embodiment, the threshold is set to 2400, which is 80% of the design lifespan. Each time the free block pool is scanned and sorted, the controller checks the wear entropy calculated for each physical block. If the wear entropy calculated for a physical block (e.g., physical block B25) is found to be 2408, exceeding the safety threshold of 2400, the fatigue circuit breaker mechanism is triggered.

[0041] Upon triggering, the controller immediately performs two operations on physical block B25. First, it marks it as statically locked. This marking is achieved by modifying a status bit in the physical block's internal metadata table of the flash controller; for example, setting the 6th bit of the status byte to "1". Second, in any subsequent selection process for establishing pseudo-single-level cell cache hierarchy nodes, any physical block with the 6th bit of its status byte set to "1" will be forcibly logically masked, i.e., directly excluded from the candidate list. Simultaneously, the marked physical block B25 will be downgraded and allocated to a static address mapping pool used only for storing data accessed at frequencies below a preset frequency threshold. The preset frequency threshold is a low-frequency access benchmark determined based on long-term system operation statistics, for example, defined as fewer than one read within a 168-hour sliding window. This pool is not managed through a separate address translation table, but rather logically divided within a global mapping table using specific attribute bits. Specifically, for all logical block address entries associated with physical block B25, a reserved "pool attribute" bit in their metadata will be changed from "0" (dynamic pool) to "1" (static pool). When the storage controller receives a write request marked as "cold data" (e.g., a system log write command), its allocation logic prioritizes searching the global mapping table for physical blocks with a "pool attribute" of "1" and available space for writing. These types of data are written very infrequently, thus sparing the high-wear block from frequent erase / write pressure.

[0042] This fatigue-based circuit breaker mechanism proactively removes physical blocks nearing the end of their lifespan from high-load cache work sequences by setting a clear health threshold. This approach not only prevents the risk of sudden data loss due to overuse of high-wear blocks but also maximizes their remaining usability by reallocating them to low-frequency write scenarios. Thus, while ensuring the reliability of core data, it further extends the effective lifespan of the entire storage system.

[0043] Furthermore, the initialization of the circular shadow log area as a metadata index structure within the pseudo-single-level unit cache node includes: dividing the target block into multiple physical pages, and configuring a logical pointer associated with the next physical page in the spare area of ​​each physical page; using the page tail linked list pointer to link multiple physical blocks with non-contiguous physical addresses into a logically closed-loop virtual circular buffer; the cache aggregation mechanism is configured to sequentially concatenate micro-log entries in on-chip volatile memory, and only perform writing the micro-log entries once when the page size is full.

[0044] Specifically, when the storage controller selects a target physical block (e.g., physical block C30) based on wear entropy sorting results to establish a pseudo-single-level cell cache hierarchy node, it initializes a circular shadow log area within it. This physical block C30 consists of multiple physical pages. Taking a physical block with 256 pages as an example, each physical page contains a 16 kilobyte (KB) main data area and a 1 kilobyte (KB) spare area. The core of the initialization operation lies in establishing the link relationships between pages. In the spare area of ​​each physical page selected as the log area, the controller reserves a field with a fixed offset (e.g., the last 8 bytes of the spare area) to store a logical pointer. This pointer records the complete physical address of the next logical page in the circular buffer. For example, if the controller decides to use physical blocks C30 and D40 to form a circular log area, the link relationship is established as follows: following the sequential write characteristics of NAND flash memory, the controller writes the physical address of the first physical page of physical block D40 into the spare area pointer field of the last physical page of physical block C30; writes the physical address of page 3 into the spare area of ​​the last physical page of physical block D40; writes the physical address of page 42 into the spare area of ​​page 3; and finally, writes the physical address of page 5 into the spare area of ​​page 42, thus forming a logical closed loop, even though the addresses of these physical pages are not contiguous.

[0045] Meanwhile, the cache aggregation mechanism operates in the on-chip static random access memory (SRAM) of the smart chip. The controller allocates a buffer in the SRAM of the same size as the main data area of ​​the NAND physical page, i.e., 16KB. When the controller intercepts logical physical address translation metadata required to update the global mapping table (e.g., a data structure containing logical address, old physical address, new physical address, and sequence number), it encapsulates it into a fixed-size micro-log entry, such as 128 bytes. This entry is not immediately written to the NAND flash memory, but is appended to the end of the 16KB buffer in the SRAM. The controller continues to perform this appending operation until the SRAM buffer is completely filled, i.e., 16384 / 128 = 128 micro-log entries have been accumulated. Only under this condition will the controller initiate a NAND write operation, writing all 128 aggregated entries in the SRAM buffer as a whole to the physical page pointed to by the current tail pointer of the circular shadow log area at once. After the write operation is complete, the tail pointer automatically points to the next logical page based on the logical pointer in the spare area of ​​that page, preparing for the next full page write.

[0046] This solution aggregates metadata updates in volatile memory, transforming a large number of tiny random writes into single, full-page sequential writes, which greatly reduces the write amplification factor of metadata and improves the system response speed in high-frequency, small-data-volume write scenarios.

[0047] Furthermore, after the step of encapsulating the micro-log entry with a checksum, the method further includes: extracting the logical address key value from the logical physical address translation metadata and mapping it to a Bloom filter residing in the on-chip static random access memory of the storage controller; when performing a data read operation, the Bloom filter is queried first, and the traversal retrieval of the micro-log entry is only initiated when the Bloom filter determines that the logical address key value exists in the circular shadow log area, thereby reducing read latency.

[0048] Specifically, after the smart chip's memory controller generates a micro-log entry and appends it to the aggregation buffer of the on-chip SRAM, but before performing a NAND write, the controller synchronously performs a Bloom filter update operation. This Bloom filter is a fixed-size bit array, such as a 2-kilobyte (KB) memory region, configured in the controller's on-chip SRAM, and pre-sets three independent, low-computation-overhead hash functions (denoted as H1, H2, and H3). The controller extracts the core logical address key, i.e., the logical block address (LBA), from the currently generated micro-log entry. Subsequently, the controller uses this LBA as input to calculate the values ​​of the three hash functions in parallel, obtaining three index positions within the Bloom filter bit array. For example, if the LBA is 0x5A5A5A5A, the bit indices obtained after calculations by H1, H2, and H3 are bits 102, 3075, and 12548, respectively. The controller then sets the bit values ​​at these three positions in the SRAM region to "1".

[0049] When the controller receives a read request from the host, such as reading data with LBA 0xABABABAB, it executes a fast pre-query process. The controller first inputs the requested LBA (0xABABABAB) into the same set of hash functions H1, H2, and H3 to obtain three bit indices. Then, it checks the bit values ​​at these three index positions in the SRAM using a Bloom filter. Two scenarios exist: First, if at least one of the checked bits is "0", the Bloom filter determines that the LBA definitely does not exist in the circular shadow log area. The controller then skips the log area search and directly accesses the global mapping table stored in the NAND main memory to obtain the physical address. Second, if all three checked bits are "1", the Bloom filter determines that the LBA may exist in the circular shadow log area. Only in this case will the controller initiate a full traversal search of all microlog entries in the circular shadow log area to find the latest mapping relationship corresponding to the LBA.

[0050] This Bloom filter, as a highly efficient probabilistic pre-checking mechanism, utilizes minimal SRAM resources to provide a fast rejection path for the vast majority of read requests that miss the log area. This avoids unnecessary, high-latency sequential scans of the circular shadow log area, significantly reducing the system's average read latency, especially under application loads where read operations far outnumber write operations, resulting in a more pronounced performance improvement.

[0051] Furthermore, the step of performing a consistent update on the global mapping table adopts an atomic replay mechanism: the micro-log entries are encapsulated with monotonically increasing global sequence numbers; when garbage collection and abnormal power failure recovery are triggered, the micro-log entries scattered in the circular shadow log area are reassembled in time according to the global sequence numbers, and the end entries that fail to verify the checksum are discarded. The reassembled address translation metadata is then merged into the global mapping table in batches in an atomic transaction manner.

[0052] Specifically, to implement this atomic replay mechanism, the memory controller maintains a 64-bit Global Serial Number (GSN) counter in the on-chip SRAM. Whenever a new micro-log entry is encapsulated, the controller assigns the current GSN counter value to that entry and immediately increments the counter. This GSN, along with logical-physical address translation metadata and a checksum, constitutes the complete structure of the micro-log entry. This update process is illustrated using garbage collection (GC) triggering as an example: when the available space in the circular shadow log area falls below a preset threshold (e.g., 20%), the GC process is activated. The controller first traverses the page tail list pointers of the circular shadow log area, reading the complete content of all log pages into a dedicated SRAM reassembly buffer.

[0053] Within the reorganization buffer, the controller does not rely on the physical or logical order of log pages, but strictly sorts all entries in ascending order based on the GSN encapsulated within each microlog entry. During sorting, the controller synchronously verifies each entry using a checksum (e.g., CRC-32). If an entry fails verification, the controller marks that entry and all entries with higher GSNs as invalid and discards them. This is to address the "torn page" problem caused by incomplete data on the last written page due to abnormal power loss. For example, if the controller verifies that an entry with GSN 3456 fails verification, all entries with GSNs greater than or equal to 3456 will be cleared, ensuring that only complete metadata updates are processed. After reorganization and successful verification, the controller obtains a consistent sequence of metadata updates arranged chronologically.

[0054] Finally, the controller performs a batch merge in an atomic transaction manner. It first reads the entire global mapping table currently stored in the NAND main memory into memory. Then, it applies the aforementioned time-series reorganized metadata update sequence line by line to the mapping table copy in memory. After all applications are complete, the controller requests a new, erased physical block from the free block pool and writes the updated entire mapping table copy to this new block at once. After successful writing and verification, the controller performs a final atomic root pointer update. Two fixed physical locations (pointer slot A and pointer slot B) are reserved in the system reserved area of ​​the NAND flash memory specifically for storing the root pointer. Each pointer slot stores the physical address pointing to the valid global mapping table, along with a monotonically increasing version number. During this update, if the current valid pointer is located in pointer slot A (with version number N), the controller writes a new pointer containing the new mapping table address and version number N+1 to pointer slot B. Only after pointer slot B is written and verified successfully is the entire transaction considered committed. When the system starts up, the controller reads both pointer slots at the same time and uses the one with the highest version number as the currently valid root pointer, thus ensuring that even if a power failure occurs during the root pointer writing process, the system can be restored to the previous consistent state.

[0055] As a preferred implementation, the garbage collection process includes: logically dividing the circular shadow log area into a young generation region and an old generation region; triggering a first type of garbage collection only in the young generation region, which migrates surviving micro-log entries in the young generation to the old generation region; and triggering a second type of garbage collection for the old generation region only when the utilization rate of the old generation region is lower than a second threshold.

[0056] Specifically, the physical block selected for pSLC caching (e.g., containing 256 pages) has its logical address space divided into two parts: the first 32 pages as the young generation and the last 224 pages as the old generation. All newly generated micro-log entries are written to the young generation. When the 32 pages of the young generation are full, a lightweight "Minor GC" is triggered. This GC only scans these 32 pages, migrating all still valid log entries (i.e., those not overwritten by subsequent updates) and writing them sequentially to the end of the old generation. For the old generation, the controller sets an independent GC trigger threshold, such as when utilization is below 30%. Only when, after multiple Minor GCs, the "garbage" space in the old generation caused by overwritten metadata accumulates to more than 70%, will a heavyweight "Major GC" be triggered to reorganize the old generation.

[0057] This generational GC strategy focuses GC on the most frequently changing young generation region, avoiding the ineffective migration of a large amount of stable old generation data, greatly reducing write amplification of metadata itself, and significantly improving the durability of pSLC cache blocks.

[0058] This atomic replay mechanism uses global sequence numbers to ensure the temporal correctness of all metadata updates, preventing logical errors caused by discontinuous physical storage in the log area. By discarding failed checksum entries before merging, it effectively ensures that only consistent and complete data is written to the global mapping table, greatly enhancing the data reliability and recoverability of the file system under sudden events such as abnormal power outages.

[0059] Reference Figure 3 The diagram illustrates the dual-path flow splitting and cache aggregation mechanism in an embodiment of the present invention. As shown, when the host write data stream arrives, it first undergoes a write stream feature identification process. Based on the identification result, the data stream is guided to two different processing paths: if it is identified as a write with a data length less than a preset page size threshold and a non-contiguous logical address, it enters the log processing path, where its metadata is encapsulated, aggregated and buffered in on-chip volatile memory, and finally written as a whole page to the circular shadow log area; if it is identified as a write with a data length greater than or equal to the preset page size threshold and a contiguous logical address, it enters the bypass path, where its data is directly written to the main storage array, thereby isolating the large volume of data from interfering with the metadata index structure.

[0060] Furthermore, before intercepting the logical physical address translation metadata required to update the global mapping table and encapsulating it into a micro-log entry with a checksum, a dual-path flow determination is performed: the characteristics of the host write data stream are identified. If the data length is identified as less than a preset page size threshold and the logical address is not contiguous, the steps of encapsulating the micro-log entry and appending it to the circular shadow log area are continued. If the data length is identified as greater than or equal to the preset page size threshold and the logical address is contiguous, the circular shadow log area is bypassed, the data is directly written to the main storage array, and the global mapping table is updated only once at the end of the data stream transmission, thus isolating the blocking interference of large-volume data on the metadata index structure.

[0061] Specifically, the dual-path flow determination logic is activated first when the smart chip's storage controller receives each write command from the host. This determination is based on two core metrics: the size of the written data and the continuity of the Logical Block Address (LBA). A preset page size threshold is defined in the controller firmware, which is configured to match the main data area capacity of a single physical page of the NAND flash memory chip. In this embodiment, this threshold is set to 16 kilobytes.

[0062] When a write command arrives, the controller will make the following judgment: Scenario 1 (Write with data length less than the preset page size threshold and discontinuous logical addresses): The controller detects that the data payload of a write command is less than 16KB, and its starting LBA is discontinuous with the ending LBA of the previous write command. For example, the controller receives a 4KB write request with a target LBA of 0x1234, while the target LBA of the previous write request was 0xABCD. The controller identifies this as a write with data length less than the preset page size threshold and discontinuous logical addresses. Therefore, the controller selects the first path, i.e., performs the aforementioned micro-log entry encapsulation operation, generates an entry containing the new logical physical address mapping, appends it to the SRAM aggregation buffer, and updates the Bloom filter.

[0063] Scenario 2 (Writes with data length greater than or equal to the preset page size threshold and contiguous logical addresses): The controller detects a write command with a data payload greater than 16KB, or receives multiple write commands with small data payloads but completely contiguous LBA addresses. For example, the controller receives a command requesting to write 1 megabyte (MB) of data, with an initial LBA of 0x8000. The controller identifies this as a write with a data length greater than or equal to the preset page size threshold and contiguous logical addresses. In this case, the controller selects the second path, namely bypassing the circular shadow log area. The user data carried by this command is directly written to the main memory array (physical blocks in TLC mode), and the resulting logical physical address mapping is temporarily stored in a dedicated SRAM cache. The controller continues to process subsequent continuous write streams in this manner until it receives a write command with a non-contiguous LBA or a clear data refresh command. At this point, the controller merges all the accumulated mappings in the SRAM cache and performs a one-time, centralized update to the global mapping table.

[0064] This dual-path routing mechanism dynamically matches the optimal processing flow for different types of write loads. It isolates batch sequential write data streams that put significant pressure on the metadata log system, preventing the circular shadow log area from being quickly filled with a large number of low-value consecutive mapping entries, thus ensuring the efficiency and space for processing core random write requests. In mixed workload scenarios, this significantly reduces the frequency of write amplification and garbage collection.

[0065] This invention proposes an adaptive caching method based on integrated circuit hybrid NAND. By constructing a nonlinear health assessment model that comprehensively considers mode switching stress and charge detrapping effects, it achieves accurate quantification of physical block wear status. This ensures that the selection of pseudo-single-layer cell cache level nodes is always based on the most realistic physical health, avoiding the continued use of physical blocks that have already suffered high-intensity nonlinear damage, thereby significantly extending the overall effective working life of the storage medium in dynamic caching applications. Simultaneously, by introducing a circular shadow log area and a cache aggregation mechanism, high-frequency, discrete metadata updates are transformed into low-frequency, full-page sequential writes, greatly reducing the metadata write amplification factor and effectively alleviating the technical bottleneck of metadata storage area exhausting before data area in intelligent chip architectures without external cache. This method further ensures data consistency and system reliability under abnormal power outages by leveraging an atomic replay mechanism.

[0066] Example 2: This embodiment applies to the storage control of an intelligent chip integrated into a network video recorder (NVR). In this application scenario, the chip, as the core of the NVR, needs to record video data from multiple high-definition cameras (e.g., 8 channels of 1080p) 24 / 7, which constitutes a large-capacity, continuous sequential write load. Simultaneously, the chip's built-in AI module analyzes the video footage in real time, generating a large amount of metadata tags related to events such as motion detection, face recognition, and vehicle recognition. These tags, along with system operation logs and file system indexes, constitute a typical write load that poses a severe challenge to flash memory lifespan, with data lengths less than a preset page size threshold and discontinuous logical addresses. This embodiment will use the storage control of this NVR chip as a background to fully illustrate the overall execution flow of the method of this invention.

[0067] After system initialization, the storage controller needs to select a physical block from its managed NAND flash free block pool to establish a pseudo-single-level cell (pSLC) cache. At this time, the controller first performs a comprehensive health assessment of all candidate physical blocks in the pool. For physical block F100 in the pool, the controller reads its metadata to determine its current erase cycle is 800, using this as the initial value for its physical damage baseline. The controller also finds that when physical block F100 was last released from pSLC mode back to the main storage array (TLC mode), the recorded bit error rate (RBER) was 0.00015, while before this assessment, after completing its most recent data storage in TLC mode, the measured RBER was 0.00020. The controller calculates the difference between the two, 0.00005, and multiplies it by the preset tunnel oxide fatigue coefficient of 250000, obtaining a nonlinear damage increment of 12.5, rounded to 13. This increment is added to the initial value, and the physical damage base of physical block F100 is updated to 813.

[0068] Meanwhile, the controller queries the timestamp metadata of F100 and finds that it has been idle for 24 hours since its last release. Based on the lookup table embedded in the firmware that characterizes the charge detrapping effect, the controller assigns a drift compensation factor of 1.25 to idle times between 12 and 48 hours. Subsequently, the controller performs differential correction calculations, dividing the physical damage base of 813 by the drift compensation factor of 1.25 to calculate the final wear entropy of physical block F100 as 650. After completing this calculation for all idle blocks, the controller performs a fatigue meltdown check. If the wear entropy of a physical block G200 exceeds the preset safety threshold of 2400, it is immediately marked as statically locked, removed from the current cache candidate pool, and its logical address is remapped to a static pool used only for storing cold data such as NVR firmware or factory configuration. After excluding these high-risk blocks, the controller sorts the remaining candidate blocks from low to high wear entropy and selects the physical block with the lowest wear entropy (e.g., physical block H50 with a wear entropy of 645) as the target block to build the pSLC cache.

[0069] After the cache is established, the controller initializes the circular shadow log area within the physical block H50. At this time, the dual-path flow determination logic begins to operate. When the AI ​​module detects a face in the No. 3 camera channel and generates a 256-byte event record, the controller determines that it is a write operation with a data length less than the preset page size threshold and a non-contiguous logical address, and decides to use the log path. The event metadata is written to the pSLC cache, and the resulting logical physical address translation metadata is encapsulated into a micro-log entry containing a CRC checksum. This entry is assigned a Global Sequence Number (GSN) with a current value of 98701, and its logical address key is hashed and updated in the Bloom filter of the on-chip SRAM. This micro-log entry is then appended to the end of the 16KB aggregate buffer in the SRAM, awaiting subsequent full-page writes. Meanwhile, an H.265 video stream with a rate of 8Mbps from the No. 1 camera channel continues to be input. The controller determines that it is a write operation with a data length greater than or equal to the preset page size threshold and a contiguous logical address, and decides to bypass the log area. The video data stream is written directly to the TLC main storage array, and its mapping metadata is only updated once in a centralized manner when the video file segments (e.g., every 5 minutes) are encapsulated.

[0070] When a user plays back a recording or retrieves a specific AI event, the controller receives a read request. It first queries the Bloom filter in SRAM. If the query results indicate that the logical address of the event's metadata does not exist in the log area, it directly accesses the global mapping table. If the results indicate that it might exist, it initiates a traversal search of the circular shadow log area to obtain the latest address.

[0071] Finally, when the used space in the circular shadow log area reaches the 80% threshold, the garbage collection process is triggered. The controller reads all micro-log entries into memory based on the tail-of-page linked list pointers of the log pages and performs a strict time-sequential reassembly based on the GSN within each entry. During reassembly, the controller verifies the CRC code of each entry; if an entry fails verification due to an unexpected power outage, it is discarded. After processing, the controller batches this verified and time-sequentially correct metadata update sequence into the global mapping table in an atomic transaction manner—that is, writing the complete and updated mapping table into a new physical block—and then switches the root pointer. At this point, a complete work cycle ends, the old pSLC cache block H50 is erased and returned to the free block pool, awaiting the next round of health assessment.

[0072] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of protection defined in the claims.

Claims

1. A method for hybrid NAND adaptive cache based on integrated circuits, characterized in that, The method comprises the following steps: Collecting the erase period, mode switching interval and error rate statistical index triggered by voltage transition of a physical block in a NAND flash memory chip; Inputting the erase period and error rate statistical index into a stress accumulation model to generate a physical damage base of the tunnel oxide layer mode switching stress through integral operation; Processing the mode switching interval through a time decay function to calculate a drift compensation factor representing the charge de-trapping effect; Performing differential correction operation on the physical damage base and the drift compensation factor through a non-linear health degree evaluation model to output wear-out entropy; using the wear-out entropy to prioritize the free block pool, selecting a target physical block and establishing a pseudo single-level cell cache level node; Initializing a ring-shaped shadow log area as a metadata index structure in the pseudo single-level cell cache level node, intercepting logical-physical address conversion metadata required for updating a global mapping table and encapsulating it into a micro log entry containing a check code; Using a cache aggregation mechanism to write the micro log entry into the ring-shaped shadow log area in a page, triggering a garbage collection process when the tail pointer reaches a preset threshold, parsing the aggregated micro log entry, reconstructing the address conversion metadata and performing consistent update on the global mapping table.

2. The integrated circuit-based hybrid NAND adaptive cache method of claim 1, wherein, The step of inputting the erase period and error rate statistical index into a stress accumulation model to generate a physical damage base of the tunnel oxide layer mode switching stress through integral operation comprises: The current erase period of the physical block and the original error rate measured before and after mode switching are used as the statistical index; the physical damage base is a variable that takes the current erase period as the initial value and accumulates the non-linear damage increment generated by mode switching; the stress accumulation model is a conversion model that normalizes the dimensionless error rate change amplitude to the equivalent erase period number through the tunnel oxide layer fatigue coefficient; the integral operation is performed using a discrete weighted summation algorithm, which specifically includes: defining the pseudo single-level cell mode as a dual-voltage state and the multi-level cell mode as a multi-voltage state; calculating the change amplitude of the current original error rate relative to the last time whenever the physical block switches attributes between the dual-voltage state and the multi-voltage state; multiplying the change amplitude by the preset tunnel oxide layer fatigue coefficient as the non-linear damage increment added to the physical damage base, quantifying the non-linear damage generated by the repeated reset of the voltage tolerance window. 3.The integrated circuit-based hybrid NAND adaptive cache method of claim 1, wherein, The step of processing the mode switching interval through a time decay function to calculate a drift compensation factor representing the charge de-trapping effect comprises: acquiring a rest time window of the physical block; processing the rest time window by using a logarithmic time-dependent model, wherein the logarithmic time-dependent model adopts a function logic with an exponentially decaying trend of growth rate to calculate the drift compensation factor: the numerical value of the drift compensation factor increases with the increase of the rest time window, and the growth rate of the drift compensation factor gradually decreases until a preset maximum compensation threshold is reached; the calculated drift compensation factor is substituted into a differential correction operation as a de-trapping gain term to simulate the charge de-trapping characteristics of threshold voltage rollback in the tunnel oxide layer over time; the rest time window is the time interval from the time when the physical block exits the pseudo-single-layer cell mode to the time when the next selected erase operation is performed; the logarithmic time-dependent model is a calculation model representing the change of charge de-trapping effect over time.

4. The integrated circuit-based hybrid NAND adaptive cache method of claim 1, wherein, The step of using wear entropy to prioritize the idle block pool and selecting the target physical block is also controlled by the fatigue fuse mechanism: A wear entropy safety threshold is set, and when it is monitored that the wear entropy index of the target physical block in the idle block pool exceeds the safety threshold, the physical block is marked as a static lock state; when establishing the pseudo-single-layer cell cache level node, the physical block in the static lock state is forced to be logically shielded and is downgraded to a static address mapping pool for storing data with an access frequency lower than a preset frequency threshold.

5. The integrated circuit-based hybrid NAND adaptive cache method of claim 1, wherein, The initialization of the annular shadow log area as a metadata index structure in the pseudo-single-layer cell cache level node includes: The target block is divided into multiple physical pages, and a logical pointer associated with the next physical page is configured in the spare area of each physical page; a page tail chain table pointer is used to link multiple physical blocks with non-continuous physical addresses into a logically closed-loop virtual annular buffer area; the cache aggregation mechanism is configured to sequentially splice micro-log entries in the on-chip volatile memory, and perform a write operation on the micro-log entries only once when the entries are filled with a page size.

6. The integrated circuit-based hybrid NAND adaptive cache method of claim 1, wherein, After the step of packaging the micro-log entry containing the check code, the following steps are further included: The logical address key value in the logical physical address conversion metadata is extracted and mapped into a Bloom filter residing in the on-chip static random access memory of the storage controller; when performing a data read operation, the Bloom filter is preferentially queried, and only when the Bloom filter determines that the logical address key value exists in the annular shadow log area, the traversal retrieval of the micro-log entry is started, thereby reducing the read delay.

7. The integrated circuit-based hybrid NAND adaptive cache method of claim 1, wherein, The step of performing consistent update on the global mapping table adopts an atomic replay mechanism: The micro-log entry internally encapsulates a monotonically increasing global sequence number; when triggering garbage collection and abnormal power failure recovery, the micro-log entries dispersed in the annular shadow log area are reorganized in time sequence according to the global sequence number, and the end entries with failed check code verification are discarded, and the reorganized address conversion metadata are batch merged into the global mapping table in an atomic transaction manner.

8. The integrated circuit-based hybrid NAND adaptive cache method of claim 1, wherein, Before the step of intercepting the logical physical address conversion metadata required for updating the global mapping table and packaging it into a micro-log entry containing a check code, a dual-path shunting judgment is further performed: The characteristics of the host write data stream are identified, if the write is identified as a write with data length less than a preset page size threshold and non-continuous logical address, the micro log entry packaging and the step of appending write to the annular shadow log area are continued; if the write is identified as a write with data length greater than or equal to the preset page size threshold and continuous logical address, the annular shadow log area is bypassed, the data is directly written into the main storage array, and the global mapping table is updated only once at the end of the data stream transmission, and the blocking interference of large flow data on the metadata index structure is isolated.

Images