GAMMA correction system for TFT-LCD display driving circuit

Abstract

The invention belongs to the technical field of display driving circuits, and particularly relates to a GAMMA correction system for a TFT-LCD display driving circuit. Comprising a GRAM storage module which writes GAMMA correction lookup table data into a specified address of a storage unit array under the control of an address selection signal; according to the method, original R / G / B three-channel image data output by a video memory SRAM (Static Random Access Memory) is used as a read address signal, and according to an output mode selection signal, the image data of any specified channel is used as a reference channel, and GAMMA correction values corresponding to the image data of the other two channels are read from a memory cell array so as to adjust GAMMA characteristic curves of the other two channels; and outputting corrected R / G / B three-channel image data. The invention aims to solve the problem of adaptability of an existing GAMMA correction system to different display panels and the problem of fitting of a GAMMA curve.

Description

Technical Field

[0001] This invention belongs to the field of display driving circuit technology, and specifically relates to a GAMMA correction system for TFT-LCD display driving circuits. Background Technology

[0002] The current mainstream TFT-LCD display driver chip's GAMMA correction block diagram is as follows: Figure 1 As shown, R / G / B are image data stored in the on-chip SRAM. After data latching and shifting in the subsequent stage, the three primary colors are output through the DAC. The color brightness of the three primary colors is determined by the voltage output by the DAC. After light mixing, various colors are presented.

[0003] Currently, the existing technical solutions are mainly divided into two types: one is linear data combined with nonlinear DAC; the other is nonlinear data combined with linear DAC.

[0004] Technical Solution 1: Linear data combined with a nonlinear DAC; This involves adjusting the grayscale voltage using a combination of linear data and a nonlinear DAC to fit the GAMMA curve, such as... Figure 2 As shown: Linear data, i.e., R / G / B data, is directly input to the DAC via a subsequent latch shifter without any processing, outputting grayscale voltage. Non-linear DACs, taking a 256-level GAMMA correction system as an example, do not have equal resistance between the generated COM voltage and GND; instead, they use a voltage divider with 255 resistors in a certain ratio to fit the 256-level grayscale voltage. However, this technical solution has the following drawbacks: 1) The resolution of GAMMA correction depends on the bit width of the linear data, resulting in insufficient precision and only providing a vague control over image display quality. 2) The non-linear DAC uses resistors with different values ​​according to the proportion of grayscale voltage, requiring high precision in the resistors and being sensitive to process mismatches. 3) One type of non-linear DAC is only compatible with one type of display panel. If the panel parameters change, a redesign is required to adapt to the new grayscale curve, leading to cost waste. 4) Three different DACs are needed to control the emission of the three primary colors (R / G / B), increasing the system complexity.

[0005] Technical Solution Two: Nonlinear Data Combined with a Linear DAC; This involves adjusting the grayscale voltage using nonlinear data combined with a linear DAC to fit the GAMMA curve, such as... Figure 3As shown: Non-linear data, i.e., R / G / B data, undergoes data conversion, then is latched and shifted into the DAC, outputting grayscale voltage. For a linear DAC, taking a 256-level GAMMA correction system as an example, the resistance between the generated COM voltage and GND is equal, and the resolution of GAMMA correction is not limited by the data bit width. However, this second technical solution has the following technical drawbacks: 1) Because the grayscale curve is Y=X*γ, and γ is generally taken as 2.2~2.5, the fitting of the grayscale curve by the equivalent resistor voltage divider across the entire Vcom voltage range will inevitably result in significant differences in the fitting degree in different intervals. 2) Image data processing is only applicable to this display panel; for other display panels, a new circuit for image data processing needs to be designed. Summary of the Invention

[0006] The purpose of this invention is to provide a GAMMA correction system for TFT-LCD display driving circuits. This invention solves the problem that the gamma correction method combining nonlinear data with a linear DAC has large differences in the fitting degree of grayscale voltage in different ranges across the entire Vcom voltage range. Moreover, the circuit has high versatility and can be directly used for gamma correction requirements of different panels, greatly reducing design costs.

[0007] To address the aforementioned technical problems, this invention provides a GAMMA calibration system for TFT-LCD display driving circuits, comprising: The GRAM memory module, under the control of the address selection signal GRAM_AD_SEL, writes the GAMMA correction lookup table data to a specified address in the memory cell array; it uses the original R / G / B three-channel image data output from the video memory SRAM as the read address signals GRAM_R[x:0], GRAM_G[x:0], and GRAM_B[x:0], and selects the output mode selection signal GRAM_DO_SEL[1:0] to select one channel of image data as the reference channel, reads the GAMMA correction values ​​corresponding to the other two channels of image data from the memory cell array, adjusts the GAMMA characteristic curves of the other two channels, and outputs the corrected R / G / B three-channel image data. A multi-segment linear DAC module includes: a segment point generation circuit, a segment point interval precision adjustment circuit, a grayscale voltage generation circuit, and a DAC unit. The segment point generation circuit decodes and selects multiple segment point voltages through a multiplexer to adjust the slope of each segment of the final grayscale voltage. The segment point interval precision adjustment circuit decodes and selects multiple segment point voltages through a multiplexer and connects them to different segments of the grayscale voltage generation circuit to adjust the resolution of each segment of the final grayscale voltage. The resolution of the final grayscale voltage is increased by increasing the number of resistors connected in series in the grayscale voltage generation circuit. The corrected R / G / B three-channel image data is latched and shifted by a subsequent stage and input to the DAC unit to output the corresponding grayscale voltage, which is then driven by the source to drive the TFT-LCD source array.

[0008] Preferably, the GRAM memory module includes: The ROM / OTP non-volatile memory is used to store the data of 6 GAMMA lookup tables corresponding to the R / G / B three channels; when each channel is used as a designated reference channel, the remaining two channels correspond to 2 GAMMA lookup table data. The bus 3-to-2 unit selects the input bus of the remaining two channels from the three data input buses GRAM_DI_R, GRAM_DI_G and GRAM_DI_B according to the reference channel information specified by the output mode selection signal GRAM_DO_SEL[1:0], thereby inputting the two table data of the remaining two channels corresponding to the specified reference channel to the write GAMMA lookup table data unit; The write GAMMA lookup table data unit is used to write the GAMMA correction lookup table data for the remaining two channels corresponding to the specified reference channel. The storage cell array is provided in two groups, each independently storing the GAMMA correction lookup table data of two of the channels written to it; The address processing unit is used to input the original R / G / B three-channel image data output by the video memory SRAM, and according to the output mode selection signal GRAM_DO_SEL[1:0], with the image data of a certain channel as a reference, read the GAMMA correction values ​​corresponding to the image data of the other two channels from the two sets of memory cell arrays respectively. The data conversion unit is used to input the reference data of the specified reference channel and the GAMMA correction values ​​corresponding to the image data of the other two channels, and after data conversion processing, output the corrected R / G / B three-channel image data.

[0009] Preferably, the six GAMMA lookup tables include: When the R channel is used as the specified reference channel, the GAMMA lookup table data of the G channel is G. R-Table and B channel GAMMA lookup table data B R -Table; When the G channel is used as the specified reference channel, the GAMMA lookup table data R of the R channel. G -Table and GAMMA lookup table data for channel B G -Table; When channel B is used as the specified reference channel, the GAMMA lookup table data R of channel R B -Table and G-channel GAMMA lookup table data G B -Table; According to the configuration of the output mode selection signal GRAM_DO_SEL[1:0], two tables of data from the six GAMMA lookup tables are written into the storage cell array. The specific working mechanism is as follows: The default value of GRAM_DO_SEL[1:0] is 2'b00 in the initial power-on state. R -Table, B R - The table is written to the storage cell array; after power-on, when the data of GRAM_DO_SEL[1:0] is switched, the corresponding GAMMA lookup table data will be immediately rewritten to the storage cell array; When switching to GRAM_DO_SEL[1:0]=2'b0X, select G R -Table, B R - The table is written to the storage unit array; When switching to GRAM_DO_SEL[1:0]=2'b10, select R G -Table, B G - The table is written to the storage unit array; When switching to GRAM_DO_SEL[1:0]=2'b11, select R B -Table, G B - The table is written to the storage cell array.

[0010] Preferably, it also includes an address selection module for inputting the address selection signal GRAM_AD_SEL and selecting the read address signals GRAM_R[x:0], GRAM_G[x:0] and GRAM_B[x:0] or the GAMMA correction lookup table data write address signal GRAM_AD[x:0] as the current valid address.

[0011] Preferred options also include: The read / write control circuit is used to control the timing of data writing and reading. Under the control of the write clock signal GRAM_WR_CP, the GAMMA correction lookup table data is written to the specified address of the memory cell array. Under the control of the read clock signal GRAM_RD_CP and the read enable signal GRAM_RD_EH, the original R / G / B three-channel image data output by the video memory SRAM is used as the read address to read the corresponding two-channel correction data from the memory cell array and output it. The row address decoder and column address decoder activate the corresponding word lines and bit lines in each group of the memory cell array according to the row address and column address, respectively, to access the target memory cell; A sensitive amplifier is used to read the data on the storage unit array and amplify it for output to the data conversion unit.

[0012] Preferably, the memory cell array is composed of multiple memory cells controlled by word lines and bit lines. The memory cell includes: PMOS transistors P1~P2 and NMOS transistors N1~N4; the source terminals of PMOS transistors P1~P2 are connected to the power supply VDD, the drain terminal of PMOS transistor P1 is connected to the drain terminal of NMOS transistor N1, the drain terminal of NMOS transistor N3, and the gate terminal of NMOS transistor N4, the gate terminal of PMOS transistor P1 is connected to the gate terminal of NMOS transistor N3, the drain terminal of PMOS transistor P2, the drain terminal of NMOS transistor N2, and the drain terminal of NMOS transistor N4, the source terminal of NMOS transistor N1 is connected to bit line BL1, the gate terminal of NMOS transistor N1 is connected to word line WL, the source terminals of NMOS transistors N3 and NMOS transistor N4 are grounded, the gate terminal of NMOS transistor N2 is connected to word line WL, and the source terminal of NMOS transistor N2 is connected to bit line BL2.

[0013] Preferably, the segment generation circuit includes: a resistor string Rf1 and selectors MUX1~MUX4; one end of the resistor string Rf1 is connected to the power supply VAP, and the other end is grounded; the multiple input terminals of the selectors MUX1~MUX4 are connected to different voltage division segments of the resistor string Rf1; and one output terminal of the selectors MUX1~MUX4 outputs segment voltages VREF1~VREF4.

[0014] Preferably, the segment interval precision adjustment circuit includes: operational amplifiers OPA1~OPA4 and selectors MUX5~MUX8; the non-inverting input terminals of operational amplifiers OPA1~OPA4 are sequentially connected to segment voltages VREF1~VREF4, the inverting input terminals of operational amplifiers OPA1~OPA4 are connected to their output terminals and sequentially generate fine adjustment voltages Va~Vd, which are respectively connected to one input terminal of selectors MUX5~MUX8, and the multiple output terminals of selectors MUX5~MUX8 are connected to different voltage division segments of the grayscale voltage generation circuit.

[0015] Preferably, the grayscale voltage generation circuit includes a resistor string Rf2, and the multiple output terminals of the selectors MUX5~MUX8 are connected to different voltage division points of the resistor string Rf2.

[0016] The present invention also provides a GAMMA calibration method for a TFT-LCD display driving circuit, employing a GAMMA calibration system for a TFT-LCD display driving circuit as described above, comprising: Under the control of the address selection signal GRAM_AD_SEL, the GAMMA correction lookup table data is written to the specified address of the memory cell array through two bus signals in GRAM_DI_R[x:0], GRAM_DI_G[x:0] and GRAM_DI_B[x:0] via the GAMMA correction lookup table data input bus signals. The original R / G / B three-channel image data output from the SRAM is used as signals GRAM_R[x:0], GRAM_G[x:0] and GRAM_B[x:0]. The output mode selects signal GRAM_DO_SEL[1:0], which specifies the image data of a certain channel as the reference channel. The GAMMA correction values ​​corresponding to the image data of the other two channels are read from the memory cell array to adjust the GAMMA characteristic curves of the other two channels, thereby outputting the corrected R / G / B three-channel image data. The corrected R / G / B three-channel image data is latched and shifted by a subsequent stage and input to the DAC unit to output the corresponding grayscale voltage, which is then driven by the source to drive the TFT-LCD source array.

[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention provides an improved data conversion circuit by replacing the data conversion processing unit with a memory-in-memory (GRAM) circuit based on address mapping principles to solve the compatibility problem of existing GAMMA correction systems with different display panels. By optimizing the linear DAC to a multi-segment linear DAC, the fitting of grayscale voltages to the GAMMA curve across different grayscale ranges is achieved. In other words, replacing the data conversion processing unit with GRAM does not introduce additional area, and the compatibility issue with different display panels is resolved. The multi-segment linear DAC improves the fitting accuracy of grayscale voltages to the GAMMA curve. Attached Figure Description

[0018] Figure 1 This is a block diagram of the existing technology for GAMMA correction implementation in TFT-LCDs.

[0019] Figure 2 It is a schematic diagram of a linear data combined with a nonlinear DAC based on existing technology.

[0020] Figure 3 It is a schematic diagram of a nonlinear data combined with a linear DAC based on existing technology.

[0021] Figure 4 This is a block diagram of a GAMMA correction system for a TFT-LCD display driving circuit provided by the present invention.

[0022] Figure 5 This is a circuit diagram of the address selection module provided by the present invention.

[0023] Figure 6 This is a circuit diagram of the memory cell array provided by the present invention.

[0024] Figure 7 This is a circuit diagram of the multi-segment linear DAC module provided by the present invention.

[0025] Figure 8 This is a diagram showing the final effect of the multi-segment linear DAC provided by this invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0027] like Figures 4-7 As shown, this embodiment of the invention provides a GAMMA calibration system for a TFT-LCD display driving circuit, comprising: The GRAM memory module, under the control of the address selection signal GRAM_AD_SEL, writes the GAMMA correction lookup table data to a specified address in the memory cell array; it uses the original R / G / B three-channel image data output from the video memory SRAM as the read address signals GRAM_R[x:0], GRAM_G[x:0], and GRAM_B[x:0], and selects the output mode selection signal GRAM_DO_SEL[1:0] to select one channel of image data as the reference channel, reads the GAMMA correction values ​​corresponding to the other two channels of image data from the memory cell array, adjusts the GAMMA characteristic curves of the other two channels, and outputs the corrected R / G / B three-channel image data. A multi-segment linear DAC module includes: a segment point generation circuit, a segment point interval precision adjustment circuit, a grayscale voltage generation circuit, and a DAC unit. The segment point generation circuit decodes and selects multiple segment point voltages through a multiplexer to adjust the slope of each segment of the final grayscale voltage. The segment point interval precision adjustment circuit decodes and selects multiple segment point voltages through a multiplexer and connects them to different segments of the grayscale voltage generation circuit to adjust the resolution of each segment of the final grayscale voltage. The resolution of the final grayscale voltage is increased by increasing the number of resistors connected in series in the grayscale voltage generation circuit. The corrected R / G / B three-channel image data is latched and shifted by a subsequent stage and input to the DAC unit to output the corresponding grayscale voltage, which is then driven by the source to drive the TFT-LCD source array.

[0028] This invention improves upon existing nonlinear data by combining it with a linear DAC. The main improvements are in the structure of module 1 and module 2, namely... Figure 1 Module 1 is replaced with an integrated SRAM circuit (i.e., a GRAM memory module). This allows for arbitrary conversion of image data across different display panels; only the necessary conversion data needs to be rewritten. Furthermore, the main design concept for the display panel is that a complete pixel, the basic unit of display, is composed of three secondary pixels: red, green, and blue. The gamma curves of these three pixel circuits differ significantly. If a DAC is used to directly output grayscale voltage, three different DACs would be needed to control the illumination of each pixel. This greatly increases system complexity and wastes internal chip space. Using this improved gamma correction scheme, only the grayscale voltage characteristic curves with minor differences need to be adjusted after data conversion before the image data enters the DAC. This requires only one DAC to be used for all three pixel circuits, significantly reducing system complexity and lowering design costs.

[0029] The GRAM memory module includes: The ROM / OTP non-volatile memory is used to store the data of 6 GAMMA lookup tables corresponding to the R / G / B three channels; when each channel is used as a designated reference channel, the remaining two channels correspond to 2 GAMMA lookup table data. The bus 3-to-2 unit selects the input bus of the remaining two channels from the three data input buses GRAM_DI_R, GRAM_DI_G and GRAM_DI_B according to the reference channel information specified by the output mode selection signal GRAM_DO_SEL[1:0], thereby inputting the two table data of the remaining two channels corresponding to the specified reference channel to the write GAMMA lookup table data unit; The write GAMMA lookup table data unit is used to write the GAMMA correction lookup table data for the remaining two channels corresponding to the specified reference channel. The storage cell array is provided in two groups, each independently storing the GAMMA correction lookup table data of two of the channels written to it; The address processing unit is used to input the original R / G / B three-channel image data output by the video memory SRAM, and according to the output mode selection signal GRAM_DO_SEL[1:0], with the image data of a certain channel as a reference, read the GAMMA correction values ​​corresponding to the image data of the other two channels from the two sets of memory cell arrays respectively. The data conversion unit is used to input the reference data of the specified reference channel and the GAMMA correction values ​​corresponding to the image data of the other two channels, and after data conversion processing, output the corrected R / G / B three-channel image data.

[0030] The six GAMMA lookup tables include: When the R channel is used as the specified reference channel, the GAMMA lookup table data of the G channel is G. R -Table and B channel GAMMA lookup table data B R -Table; When the G channel is used as the specified reference channel, the GAMMA lookup table data R of the R channel. G -Table and GAMMA lookup table data for channel B G -Table; When channel B is used as the specified reference channel, the GAMMA lookup table data R of channel R B -Table and G-channel GAMMA lookup table data G B -Table; According to the configuration of the output mode selection signal GRAM_DO_SEL[1:0], two tables of data from the six GAMMA lookup tables are written into the storage cell array. The specific working mechanism is as follows: The default value of GRAM_DO_SEL[1:0] is 2'b00 in the initial power-on state. R -Table, B R - The table is written to the storage cell array; after power-on, when the data of GRAM_DO_SEL[1:0] is switched, the corresponding GAMMA lookup table data will be immediately rewritten to the storage cell array; When switching to GRAM_DO_SEL[1:0]=2'b0X, select G R -Table, B R- The table is written to the storage unit array; When switching to GRAM_DO_SEL[1:0]=2'b10, select R G -Table, B G - The table is written to the storage unit array; When switching to GRAM_DO_SEL[1:0]=2'b11, select R B -Table, G B - The table is written to the storage cell array.

[0031] The aforementioned ROM / OTP, bus 3-to-2 selector, and GAMMA lookup table data write unit constitute a system module. Its function is to write two of the six lookup tables into the memory cell array according to the configuration of GRAM_DO_SEL[1:0]. The specific working mechanism is as follows: The default value of GRAM_DO_SEL[1:0] is 2'b00 in the initial power-on state. R -Table, B R - The table is written to the SRAM storage matrix; after power-on, when the data of GRAM_DO_SEL[1:0] is switched, the corresponding GAMMA lookup table will be immediately rewritten to the SRAM storage cell array.

[0032] When switching to GRAM_DO_SEL[1:0]=2'b0X, select G R -Table, B R - The table is written to the SRAM memory cell array; When switching to GRAM_DO_SEL[1:0]=2'b10, select R G -Table, B G - The table is written to the SRAM memory cell array; When switching to GRAM_DO_SEL[1:0]=2'b11, select R B -Table, G B - The table is written to the SRAM storage cell array.

[0033] It also includes an address selection module, which is used to input the address selection signal GRAM_AD_SEL and select the read address signals GRAM_R[x:0], GRAM_G[x:0] and GRAM_B[x:0] or the GAMMA correction lookup table data write address signal GRAM_AD[x:0] as the current valid address.

[0034] Also includes: The read / write control circuit is used to control the timing of data writing and reading. Under the control of the write clock signal GRAM_WR_CP, the GAMMA correction lookup table data is written to the specified address of the memory cell array. Under the control of the read clock signal GRAM_RD_CP and the read enable signal GRAM_RD_EH, the original R / G / B three-channel image data output by the video memory SRAM is used as the read address to read the corresponding two-channel correction data from the memory cell array and output it. The row address decoder and column address decoder activate the corresponding word lines and bit lines in each group of the memory cell array according to the row address and column address, respectively, to access the target memory cell; A sensitive amplifier is used to read the data on the storage unit array and amplify it for output to the data conversion unit.

[0035] The GRAM memory module is divided into two sets of addresses. One address is used to load the GAMMA lookup table stored in ROM or to manually write the GAMMA lookup table later. The other address is for the data in the SRAM (Screen RAM). Specifically, GRAM_R / G / B <x:0>The image data in the SRAM is used as the address of the GRAM. This address is only used for reading data. Combined with the GRAM_RD_CP read clock, the data in the SRAM is output as the address of the GRAM, resulting in GRAM_R / G / B. <x:0>Regarding the conversion of the implemented data; GRAM_AD <x:0>This is the address for loading the GAMMA lookup table; this address is only used for writing data, in conjunction with GRAM_DI_R / G / B. <x:0>The GAMMA lookup table is loaded into GRAM via the three-primary-color GAMMA lookup table data bus. The choice between the two address types is switched via the GRAM_AD_SEL address bus.

[0036] Furthermore, the gamma curves of the red, green, and blue pixel circuits in a display panel differ significantly. If a DAC is used to directly output grayscale voltage, three different DACs are needed to control the illumination of each of the three pixels. This can be addressed by adjusting the grayscale voltage characteristic curve of the data after reading it from the GRAM using an in-memory computing architecture, before outputting the data to the SRAM. This function can be switched using the GRAM_DO_SEL<1:0> output mode selection, allowing adjustment of the gamma characteristic curves of the other two colors based on any one of the three primary colors.

[0037] The memory cell array is composed of multiple memory cells controlled by word lines and bit lines. Each memory cell includes: PMOS transistors P1~P2 and NMOS transistors N1~N4. The source terminals of PMOS transistors P1~P2 are connected to the power supply VDD. The drain terminal of PMOS transistor P1 is connected to the drain terminal of NMOS transistor N1, the drain terminal of NMOS transistor N3, and the gate terminal of NMOS transistor N4. The gate terminal of PMOS transistor P1 is connected to the gate terminal of NMOS transistor N3, the drain terminal of PMOS transistor P2, the drain terminal of NMOS transistor N2, and the drain terminal of NMOS transistor N4. The source terminal of NMOS transistor N1 is connected to bit line BL1. The gate terminal of NMOS transistor N1 is connected to word line WL. The source terminals of NMOS transistors N3 and NMOS transistor N4 are grounded. The gate terminal of NMOS transistor N2 is connected to word line WL. The source terminal of NMOS transistor N2 is connected to bit line BL2.

[0038] The embodiments of the present invention will Figure 1 Module 2 (linear DAC) is optimized into a multi-segment linear DAC module, which allows for better fitting of grayscale voltage and GAMMA curves for different grayscale ranges. For example... Figure 7 The following is a detailed explanation using a 5-segment linear DAC module as an example.

[0039] The segment generation circuit includes: a resistor string Rf1 and selectors MUX1~MUX4; one end of the resistor string Rf1 is connected to the power supply VAP, and the other end is grounded; the multiple input terminals of the selectors MUX1~MUX4 are connected to different voltage division segments of the resistor string Rf1; and one output terminal of the selectors MUX1~MUX4 outputs segment voltages VREF1~VREF4.

[0040] The segment interval precision adjustment circuit includes: operational amplifiers OPA1~OPA4 and selectors MUX5~MUX8; the non-inverting input terminals of operational amplifiers OPA1~OPA4 are sequentially connected to segment voltages VREF1~VREF4, the inverting input terminals of operational amplifiers OPA1~OPA4 are connected to their output terminals and sequentially generate fine adjustment voltages Va~Vd, which are respectively connected to one input terminal of selectors MUX5~MUX8, and the multiple output terminals of selectors MUX5~MUX8 are connected to different voltage division segments of the grayscale voltage generation circuit.

[0041] The grayscale voltage generation circuit includes a resistor string Rf2, and the multiple output terminals of the selectors MUX5~MUX8 are connected to different voltage division points of the resistor string Rf2.

[0042] The above-described segment generation circuit: Through a series of resistors connected to ground, and decoded by a series of selectors, the voltages of the four segments are initially selected. By selecting the multiplexer, the slope of each segment of the final grayscale voltage can be adjusted. The above-described segment interval precision adjustment circuit: The four segment voltages generated by the segment generation circuit are buffered by a follower and connected to the grayscale voltage generation resistor string through a series of selectors. By selecting the multiplexer, the resolution of each segment of the final grayscale voltage can be adjusted. The above-described grayscale voltage generation circuit: Through a series of resistors connected to ground, the resistance of this resistor string is not limited by the bit width of the video memory image data. Using as many resistors as possible can increase the resolution of the final grayscale voltage.

[0043] The present invention also provides a GAMMA calibration method for a TFT-LCD display driving circuit, comprising: Under the control of the address selection signal GRAM_AD_SEL, the GAMMA correction lookup table data is written to the specified address of the memory cell array through two signals in the GAMMA correction lookup table data input signals GRAM_DI_R[x:0], GRAM_DI_G[x:0] and GRAM_DI_B[x:0]. The original R / G / B three-channel image data output from the SRAM is used as signals GRAM_R[x:0], GRAM_G[x:0] and GRAM_B[x:0]. The output mode selects signal GRAM_DO_SEL[1:0], which specifies the image data of any channel as the reference channel. The GAMMA correction values ​​corresponding to the image data of the other two channels are read from the memory cell array to adjust the GAMMA characteristic curves of the other two channels, thereby outputting the corrected R / G / B three-channel image data. The corrected R / G / B three-channel image data is latched and shifted by a subsequent stage and input to the DAC unit to output the corresponding grayscale voltage, which is then driven by the source to drive the TFT-LCD source array.

[0044] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A gamma correction system for TFT-LCD display driving circuit, characterized in that, The application comprises: A GRAM memory and calculation module, which writes GAMMA correction lookup table data into a specified address of a memory cell array under the control of an address selection signal GRAM_AD_SEL; raw R / G / B three-channel image data output by a display memory SRAM is used as read address signals GRAM_R[x:0], GRAM_G[x:0] and GRAM_B[x:0], and according to an output mode selection signal GRAM_DO_SEL[1:0], image data of a certain channel is used as a reference channel to read GAMMA correction values corresponding to image data of the other two channels from the memory cell array, so as to adjust the GAMMA characteristic curves of the other two channels, thereby outputting corrected R / G / B three-channel image data; A multi-segment linear DAC module, which comprises a segment point generation circuit, a segment point interval precision adjustment circuit, a gray scale voltage generation circuit and a DAC unit; The segment point generation circuit decodes and selects a plurality of segment point voltages through a multiplexer to adjust the slopes of each segment of the final gray scale voltage; the segment point interval precision adjustment circuit decodes and selects a plurality of segment point voltages through a multiplexer to access different segment points of the gray scale voltage generation circuit, so as to adjust the resolution of each segment of the final gray scale voltage; the resolution of the final gray scale voltage is increased by increasing the number of resistance series connections of the gray scale voltage generation circuit; the corrected R / G / B three-channel image data is input to the DAC unit through a later-stage latch and shift, so as to output corresponding gray scale voltages, and drive a TFT-LCD source array through a source driver.

2. The gamma correction system for a TFT-LCD display driving circuit according to claim 1, wherein The GRAM memory and calculation module comprises: A ROM / OTP non-volatile memory for storing 6 GAMMA lookup table data corresponding to R / G / B three channels; when each channel is used as a specified reference channel, 2 GAMMA lookup table data corresponding to the remaining two channels; A bus three-to-two unit for selecting input buses of the remaining two channels from three data input buses GRAM_DI_R, GRAM_DI_G and GRAM_DI_B according to reference channel information specified by the output mode selection signal GRAM_DO_SEL[1:0], so as to input two table data of the remaining two channels corresponding to the specified reference channel into a write GAMMA lookup table data unit; The write GAMMA lookup table data unit is used for writing GAMMA correction lookup table data of the remaining two channels corresponding to the specified reference channel; The memory cell array is provided with two groups, which independently store GAMMA correction lookup table data of two channels written; An address processing unit for inputting raw R / G / B three-channel image data output by a display memory SRAM, and reading GAMMA correction values corresponding to image data of the other two channels from two groups of memory cell arrays according to the output mode selection signal GRAM_DO_SEL[1:0] so as to specify image data of a certain channel as a reference. The data conversion unit is used for inputting the GAMMA correction value corresponding to the reference data of the reference channel and the image data of the other two channels, and outputting the corrected R / G / B three-channel image data after data conversion processing.

3. The GAMMA correction system for a TFT-LCD display driving circuit according to claim 2, wherein the first and second correction circuits are implemented by a single correction circuit. 5 The six GAMMA lookup tables include: GAMMA lookup table data G of the G channel when the R channel is taken as a designated reference channel R GAMMA lookup table data B of the B channel R Table GAMMA lookup table data R for the R channel when the G channel is designated as the reference channel G - Table and GAMMA lookup table data for B channel B G -Table; GAMMA lookup table data R for the R channel when the B channel is designated as the reference channel B - Table and G channel GAMMA lookup table data G B -Table; According to the configuration of the output mode selection signal GRAM_DO_SEL[1:0], two table data in the six GAMMA lookup table data are written into the storage unit array, and the specific working mechanism is as follows: The default value of GRAM_DO_SEL[1:0] is 2'b00 at power-up, and G R -Table, B R -Table write memory cell array; after power-up, when the data of GRAM_DO_SEL[1:0] is switched, the corresponding GAMMA lookup table data will be immediately re-written to the memory cell array; When switching to GRAM_DO_SEL[1 :0]=2'b0X, the selection of G R -Table, B R -Table write to memory cell array; When switching to GRAM_DO_SEL[1 :0]=2'b10, the selection of R G -Table, B G -Table write to memory cell array; When switching to GRAM_DO_SEL[1 :0]=2'b11, the selection of R B -Table, G B -Table write memory cell array.

4. The gamma correction system for a TFT-LCD display driving circuit according to claim 2, wherein the gamma correction system further comprises a gamma correction circuit for generating a gamma correction signal according to the gamma correction data, and a gamma correction look-up table for storing the gamma correction data and outputting the gamma correction data according to the gamma correction signal. The address selection module is further included for inputting the address selection signal GRAM_AD_SEL and selecting the read address signal GRAM_R[x:0], GRAM_G[x:0] and GRAM_B[x:0] or the GAMMA correction lookup table data write address signal GRAM_AD[x:0] as the current effective address.

5. The GAMMA correction system for a TFT-LCD display driving circuit according to claim 2, wherein the first and second correction circuits are implemented by a single correction circuit. 5 The read / write control circuit is further included for controlling the writing and reading timing of the data. Under the control of the write clock signal GRAM_WR_CP, the GAMMA correction lookup table data is written into the specified address of the storage unit array; under the control of the read clock signal GRAM_RD_CP and the read enable signal GRAM_RD_EH, the original R / G / B three-channel image data output by the video memory SRAM is taken as the read address, the corresponding two-channel correction data is read from the storage unit array and outputted; The row address decoder and the column address decoder are respectively used for activating the corresponding word line and bit line in each group of the storage unit array according to the row address and the column address, so as to access the target storage unit. The sense amplifier is used for reading the data on the storage unit array and amplifying and outputting to the data conversion unit. The storage unit array is composed of a plurality of storage units controlled by the word line and the bit line, and the storage unit includes PMOS tubes P1-P2 and NMOS tubes N1-N4; the source end of the PMOS tube P1 is connected to the power supply VDD, the drain end of the PMOS tube P1 is connected to the drain end of the NMOS tube N1, the drain end of the NMOS tube N3 and the gate end of the NMOS tube N4, the gate end of the PMOS tube P1 is connected to the gate end of the NMOS tube N3, the drain end of the PMOS tube P2, the drain end of the NMOS tube N2 and the drain end of the NMOS tube N4, the source end of the NMOS tube N1 is connected to the bit line BL1, the gate end of the NMOS tube N1 is connected to the word line WL, the source ends of the NMOS tube N3 and the NMOS tube N4 are grounded, the gate end of the NMOS tube N2 is connected to the word line WL, and the source end of the NMOS tube N2 is connected to the bit line BL2.

6. The GAMMA correction system for a TFT-LCD display driving circuit according to claim 5, wherein the first and second correction circuits are implemented by a single correction circuit. 5 The segment point generation circuit includes a resistor string Rf1 and selectors MUX1-MUX4; one end of the resistor string Rf1 is connected to the power supply VAP and the other end is grounded; the multiple input ends of the selectors MUX1-MUX4 are connected to different voltage division segment points of the resistor string Rf1; and one output end of the selectors MUX1-MUX4 outputs segment point voltages VREF1-VREF4.

7. The GAMMA correction system for a TFT-LCD display driving circuit according to claim 1, wherein the first and second correction circuits are implemented by a single correction circuit. 7 ​ 8. The GAMMA correction system for a TFT-LCD display driving circuit according to claim 7, wherein the first and second correction circuits are implemented by a single correction circuit. 5 The segment point interval precision adjustment circuit comprises operational amplifiers OPA1-OPA4 and selectors MUX5-MUX8; the non-inverting input terminals of the operational amplifiers OPA1-OPA4 are connected to segment point voltages VREF1-VREF4 in sequence, the inverting input terminals of the operational amplifiers OPA1-OPA4 are connected to their output terminals and generate precision adjustment voltages Va-Vd in sequence, and the precision adjustment voltages Va-Vd are connected to one input terminal of the selectors MUX5-MUX8 in sequence; and the multiple output terminals of the selectors MUX5-MUX8 are connected to different voltage division segment points of the gray scale voltage generation circuit.

9. The GAMMA correction system for TFT-LCD display driving circuit according to claim 8, wherein the first and second correction circuits are implemented by a single correction circuit. 10 The gray scale voltage generation circuit comprises a resistance string Rf2, and the multiple output terminals of the selectors MUX5-MUX8 are connected to different voltage division segment points of the resistance string Rf2.

10. A method for gamma correction of a TFT-LCD display driving circuit, using a system for gamma correction of a TFT-LCD display driving circuit according to any one of claims 1 to 9, characterized in that, Comprise: Under the control of an address selection signal GRAM_AD_SEL, write two bus signals of GAMMA correction lookup table data input bus signals GRAM_DI_R[x:0], GRAM_DI_G[x:0] and GRAM_DI_B[x:0] into a specified address of a storage unit array; Take original R / G / B three-channel image data output by a video memory SRAM as signals GRAM_R[x:0], GRAM_G[x:0] and GRAM_B[x:0], and according to an output mode selection signal GRAM_DO_SEL[1:0], take image data of a certain channel as a reference channel, read GAMMA correction values corresponding to image data of the other two channels from the storage unit array, adjust GAMMA characteristic curves of the other two channels, and output corrected R / G / B three-channel image data; The corrected R / G / B three-channel image data is input to the DAC unit through a later stage latch and shift, so as to output corresponding gray scale voltages, and drive a TFT-LCD source array through a source driver.

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