Multi-mode power management device

Abstract

A multi-mode power management device is provided. In embodiments disclosed herein, the multi-mode power management device may be configured to operate in different power management modes across a wide modulation bandwidth range (e.g., 80 KHz to 200 MHz or more). The multi-mode power management device includes a power management integrated circuit (PMIC) and an envelope tracking integrated (ET) circuit (ETIC) implemented in a separate die. The PMIC is configured to generate a low frequency current and a low frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management device may selectively output one or more of the ET voltage and the low frequency voltage to different stages (e.g., a driver stage and an output stage) of a power amplifier circuit, therefore, the optimal efficiency and linearity of the power amplifier circuit can be maintained across the wide modulation bandwidth range.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on July 22, 2020, with application number 202080052069.2 and title "Multi-mode power management device".

[0002] Related applications

[0003] This application claims the benefit of provisional patent application serial number 62 / 878,358, filed on July 25, 2019, the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0004] The technology disclosed herein generally relates to power management devices. Background Technology

[0005] Mobile communication devices, such as smartphones, have become increasingly prevalent in modern society, providing wireless communication services. The functionality of these devices is driven in part by the many features now enabled on them. This increased processing power means that mobile communication devices have evolved from mere communication tools into sophisticated mobile multimedia hubs capable of delivering enhanced user experiences.

[0006] The redefined user experience has also led to the rise of so-called wearable devices, such as smartwatches. Over time, these wearable devices have evolved from simple accessories into mobile communication devices, becoming sophisticated multi-functional wireless communication devices. Today, most wearable electronic devices are typically equipped with digital and analog circuitry capable of transmitting radio frequency (RF) signals in various wireless communication systems such as LTE, Wi-Fi, and Bluetooth. Similar to mobile communication devices, wearable devices often employ complex power amplifiers to amplify RF signals to help improve coverage, data throughput, and reliability.

[0007] Envelope tracking (ET) is a power management technique designed to improve the efficiency of power amplifiers. In this regard, it may be desirable to employ ET across various wireless communication technologies to help reduce power consumption and heat dissipation in wearable devices. It is worth noting that the RF signals communicating in different wireless communication systems can correspond to different modulation bandwidths (e.g., from 80 kHz to over 200 MHz). Therefore, it may be further desirable to ensure that the power amplifier can maintain optimal efficiency and linearity across a wide modulation bandwidth range. Summary of the Invention

[0008] Embodiments of this disclosure relate to a multi-mode power management device. In the embodiments disclosed herein, the multi-mode power management device can be configured to operate in different power management modes across a wide modulation bandwidth range (e.g., 80 kHz to over 200 MHz). The multi-mode power management device includes a power management integrated circuit (PMIC) and an envelope tracking integrated circuit (ETIC) implemented in a separate die. The PMIC is configured to generate a low-frequency current and a low-frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management device can selectively output one or more of the ET voltages and the low-frequency voltages to different stages of a power amplifier circuit (e.g., a driver stage and an output stage), thereby helping to maintain optimal efficiency and linearity of the power amplifier circuit across the wide modulation bandwidth range.

[0009] In one aspect, a multi-mode power management device is provided. The multi-mode power management device includes a power control interface (PMIC) configured to generate a low-frequency current and a low-frequency voltage. The multi-mode power management device also includes an energy transfer interface (ETIC). The ETIC includes a first node coupled to the PMIC. The ETIC also includes a second node coupled to the first node via a multi-function circuit. The ETIC further includes a first voltage circuit configured to generate a first ET voltage based on a first ET target voltage. The ETIC also includes a second voltage circuit configured to generate a second ET voltage based on a second ET target voltage. The ETIC further includes control circuitry. The control circuitry is configured to cause the first node and the second node to output one or more of the first ET voltage, the second ET voltage, and the low-frequency voltage. The control circuitry is also configured to cause the first node and the second node to output at least the low-frequency current.

[0010] Those skilled in the art will understand the scope of this disclosure and recognize other aspects of it after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0012] Figure 1 This is a schematic diagram of an exemplary multi-mode power management device according to embodiments of the present disclosure; and

[0013] Figure 2 It is a demonstration Figure 1A schematic diagram showing the detailed configuration of a multi-mode power management device under different power management modes. Detailed Implementation

[0014] The embodiments described below illustrate the necessary information to enable those skilled in the art to practice the embodiments and demonstrate the best manner in which the embodiments are practiced. After reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0015] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerations.

[0016] It should be understood that when an element such as a layer, region, or substrate is referred to as "located on another element" or "extends to another element," the element may be directly located on or directly extended onto the other element, or intermediate elements may also be present. In contrast, when an element is referred to as "directly located on another element" or "directly extended onto another element," no intermediate elements are present. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as "located on another element" or "extends on another element," the element may be directly located on or directly extended onto the other element, or intermediate elements may also be present. In contrast, when an element is referred to as "directly located on another element" or "extends directly on another element," no intermediate elements are present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, the element may be directly connected to or coupled to the other element, or intermediate elements may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0017] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the accompanying drawings. It should be understood that, in addition to the orientations depicted in the accompanying drawings, these terms and the terms discussed above are intended to cover different orientations of the apparatus.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that when the terms “comprises,” “comprising,” “includes,” and / or “including” are used herein, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein are to be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0020] Embodiments of this disclosure relate to a multi-mode power management device. In the embodiments disclosed herein, the multi-mode power management device can be configured to operate in different power management modes across a wide modulation bandwidth range (e.g., 80 kHz to over 200 MHz). The multi-mode power management device includes a power management integrated circuit (PMIC) and an envelope tracking integrated circuit (ETIC) implemented in a separate die. The PMIC is configured to generate a low-frequency current and a low-frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management device can selectively output one or more of the ET voltages and the low-frequency voltages to different stages of a power amplifier circuit (e.g., a driver stage and an output stage), thereby helping to maintain optimal efficiency and linearity of the power amplifier circuit across the wide modulation bandwidth range.

[0021] Figure 1 This is a schematic diagram of an exemplary multi-mode power management device 10 configured according to embodiments of the present disclosure. The multi-mode power management device 10 includes a PMIC 12 and an ETIC 14 provided in separate dies. The multi-mode power management device 10 may include or be coupled to a multi-stage power amplifier circuit 16 configured to amplify a radio frequency (RF) signal 18. The multi-stage power amplifier circuit 16 may include a driver stage 20 and an output stage 22. In a non-limiting example, the driver stage 20 includes a power amplifier 24, and the output stage 22 includes one or more power amplifiers 26.

[0022] In the examples discussed herein, the multi-mode power management device 10 can be configured to operate in different power management modes depending on the modulation bandwidth of the RF signal 18. In a non-limiting example, the multi-mode power management device 10 operates in a first power management mode when the modulation bandwidth is greater than 160 MHz (> 160 MHz); in a second power management mode when the modulation bandwidth is between 1 MHz and 160 MHz (> 1 MHz and ≤ 160 MHz); in a third power management mode when the modulation bandwidth is between 120 kHz and 1 MHz (> 120 kHz and ≤ 1 MHz); in a fourth power management mode when the modulation bandwidth is between 80 kHz and 120 kHz (> 80 kHz and ≤ 120 kHz); or in a fifth power management mode when the modulation bandwidth is less than 80 kHz (≤ 80 kHz). Therefore, by operating in different power management modes based on the modulation bandwidth of the RF signal 18, the multi-mode power management device 10 can maintain the optimal efficiency and linearity of the multi-stage power amplifier circuit 16 across a wide modulation bandwidth range.

[0023] PMIC 12 is configured to generate a low-frequency voltage V DC (e.g., constant voltage or modulated constant voltage) and low-frequency current I DC (For example, direct current or modulated direct current). ETIC 14 includes a first voltage current 28A and a second voltage current 28B, the first voltage current being configured to generate a first ET voltage V. CCA The second voltage current is configured to generate a second ET voltage V. CCB ETIC 14 includes a first node 30A and a second node 30B, which can be coupled to the output stage 22 and driver stage 20 of the multi-stage power amplifier circuit 16, respectively. The first node 30A is coupled to a first voltage circuit 28A and PMIC 12. The second node 30B is coupled to a second voltage circuit 28B and the first node 30A via a multifunction circuit 32 (referred to as "LDO / SW"). In a non-limiting embodiment, the multifunction circuit 32 may include a low-dropout (LDO) and a switch (not shown).

[0024] ETIC 14 includes control circuitry 34, which may be, for example, any type of microcontroller or field-programmable gate array (FPGA). It should be understood that the functionality of control circuitry 34 can be shared among multiple control circuits and / or controllers without affecting the functionality and operation of the multimode power management device 10.

[0025] Control circuit 34 is coupled to first voltage circuit 28A, second voltage / current circuit 28B, and multifunction circuit 32. As discussed in detail below, control circuit 34 can control first voltage circuit 28A, second voltage / current circuit 28B, and multifunction circuit 32 individually or jointly, so that first node 30A and second node 30B output low-frequency voltage V in different power management modes. DC First ET voltage V CCA Second ET voltage V CCB One or more of them. Additionally, control circuit 34 can individually or jointly control the first voltage circuit 28A, the second voltage and current circuit 28B, and the multi-function circuit 32 to cause the first node 30A and the second node 30B to output at least a low-frequency current I in different power management modes. DC .

[0026] The control circuit 34 can provide a feedback signal 36 to the PMIC 12. The feedback signal 36 enables the PMIC 12 to adjust the low-frequency current I accordingly. DC and / or low-frequency voltage V DC The control circuit 34 can be coupled to the transceiver circuit 38 that generates the RF signal 18. In this respect, the control circuit 34 is able to determine the modulation bandwidth of the RF signal 18 based on the indication 40 from the transceiver circuit 38, and thus determine different power management modes.

[0027] Figure 2 It is a demonstration Figure 1 A schematic diagram showing the detailed configuration of the multi-mode power management device 10 under different power management modes. Figure 1 and 2 Common elements between them are shown here by reference numerals in the accompanying drawings and will not be described again herein.

[0028] In a non-limiting example, PMIC 12 includes a multilevel charge pump (MCP) 42, which is configured to operate based on a battery voltage V. BAT (For example, 0xV) BAT 1xV BAT or 2xV BAT Generates multi-level low-frequency voltage V DC The PMIC 12 also includes a power inductor 44, which is configured based on a low-frequency voltage V. DC Induced low-frequency current I DC The PMIC 12 further includes a controller 46, which, for example, can be any type of microcontroller or microprocessor. The controller 46 receives a feedback signal 36 from the control circuitry 34 in the ETIC 14. Therefore, the controller 46 can control the MCP 42 to adjust the low-frequency voltage V. DCAnd therefore adjust the low-frequency current I accordingly. DC .

[0029] The first voltage circuit 28A includes a first voltage amplifier 48A (denoted as "vAmpA"), the first voltage amplifier being configured to operate based on a first ET target voltage V. TGTA and the first power supply voltage V SUPA Generate the first initial ET voltage V AMPA In this respect, the first initial ET voltage V AMPA This can correspond to tracking (e.g., rising and falling) the first ET target voltage V. TGTA The time-varying target envelope is the time-varying voltage envelope. The first power supply voltage V can be adjusted. SUPA So that the first voltage amplifier 48A adjusts the first initial ET voltage V AMPA The amplitude and therefore adjust the first ET voltage V CCA The amplitude.

[0030] The first voltage circuit 28A further includes a first offset capacitor 50A, the first offset capacitor having a first capacitance C coupled between the first voltage amplifier 48A and the first node 30A. A (For example, 4.7 µF). The first offset capacitor 50A is configured to apply the first initial ET voltage V. AMPA Increase the first offset voltage V OFFA (For example, 0.8 V) to generate the first ET voltage V CCA (V) CCA = V AMPA + V OFFA ).

[0031] The first voltage circuit 28A further includes a first switch 52A (denoted as "SW"), which is coupled between a first coupling node 54A and ground (GND). The first voltage circuit 28A further includes a first feedback loop 56A, which is configured to provide a first ET voltage V to the first voltage amplifier 48A. CCA Feedback.

[0032] The second voltage circuit 28B includes a second voltage amplifier 48B (denoted as "vAmpB"), which is configured to operate based on a second ET target voltage V. TGTB Second power supply voltage V SUPB Generate the second initial ET voltage V AMPB In this respect, the second initial ET voltage V AMPB This can correspond to tracking (e.g., rising and falling) the second ET target voltage V. TGTB The time-varying target envelope is the time-varying voltage envelope. The second power supply voltage V can be adjusted.SUPB So that the second voltage amplifier 48B adjusts the second initial ET voltage V AMPB The amplitude and therefore adjust the second ET voltage V CCB The amplitude.

[0033] The second voltage circuit 28B also includes a second offset capacitor 50B, the second offset capacitor having a second capacitance C coupled between the second voltage amplifier 48B and the second node 30B. B (For example, 10-100 nF). The second offset capacitor 50B is configured to apply the second initial ET voltage V. AMPB Increase the second offset voltage V OFFB (For example, 0.8 V), to generate a second ET voltage V CCB (V) CCB = V AMPB + V OFFB ).

[0034] The second voltage circuit 28B also includes a second switch 52B (denoted as "SW"), which is coupled between the second coupling node 54B and GND. The second voltage circuit 28B further includes a second feedback loop 56B, which is configured to provide a second ET voltage V to the second voltage amplifier 48B. CCB Feedback.

[0035] ETIC 14 includes a power supply voltage circuit 58, which is configured to generate a first power supply voltage V. SUPA Second power supply voltage V SUPB In a non-limiting example, the power supply voltage circuit 58 can generate a multi-level first power supply voltage V. SUPA Second power supply voltage V SUPB Each of these is designed to help maintain the efficiency and linearity of the first voltage amplifier 48A and the second voltage amplifier 48B.

[0036] ETIC 14 may include a first voltage equalizer circuit 60A (denoted as "VRF") and a second voltage equalizer circuit 60B (denoted as "VRF"). The first voltage equalizer circuit 60A is configured to operate based on a common ET target voltage V. TGT Generate the first ET target voltage V TGTA The second voltage equalizer circuit is configured based on the common ET target voltage V. TGT Generate the second ET target voltage V TGTB Common ET target voltage V TGT A time-varying voltage envelope is generated as a time-varying signal envelope that tracks (e.g., rising and falling) RF signal 18.

[0037] In one embodiment, in the first power management mode, the control circuit 34 is configured to cause the first node 30A to output a first ET voltage V. CCA and low-frequency current I DC The control circuit 34 is also configured to cause the second node 30B to output a second ET voltage V. CCB and low-frequency current I DC Proportional adjustment of low-frequency current I' DC In this respect, driver stage 20 receives a second ET voltage V. CCB and the adjusted low-frequency current I' DC The output stage 22 receives the first ET voltage V. CCA and low-frequency current I DC .

[0038] It is worth noting that when RF signal 18 reaches output stage 22, it has already been amplified by power amplifier 24 in driver stage 20. Therefore, RF signal 18 will correspond to a higher amplitude at output stage 22 than at driver stage 20. Thus, the first ET voltage V... CCA It needs to be greater than or equal to the second ET voltage V CCB (V) CCA ≥ V CCB This is to prevent the RF signal 18 from being distorted at the output stage 22 (e.g., due to amplitude clipping).

[0039] More specifically, the control circuit 34 activates the first voltage amplifier 48A and the second voltage amplifier 48B, so that the first node 30A and the second node 30B respectively output the first ET voltage V. CCA Second ET voltage V CCB Control circuit 34 controls the LDO regulator in multifunction circuit 32 to generate a regulated low-frequency current I'. DC The control circuit 34 also closes the switch in the multi-function circuit 32 to provide an adjusted low-frequency current I' to the second node 30B. DC The control circuit 34 further disconnects the first switch 52A and the second switch 52B, so that the first node 30A and the second node 30B respectively output low-frequency current I. DC and the adjusted low-frequency current I' DC .

[0040] Control circuit 34 can determine the voltage difference (e.g., V) across the first offset capacitor 50A. CCA With V AMPA The voltage difference across the first offset capacitor 50A can be used as the low-frequency current I at the first node 30A. DCThe control circuit 34 provides an indication of excess or deficiency in the voltage. Therefore, the control circuit 34 generates a feedback signal 36 based on the voltage difference. Thus, the controller 46 in the PMIC 12 can control the MCP 42 based on the feedback signal 36 to make the low-frequency voltage V... DC and low-frequency current I DC Decrease or increase.

[0041] Control circuit 34 can determine the voltage difference across the second offset capacitor 50B (e.g., V). CCB With V AMPB The voltage difference across the second offset capacitor 50B can be used as the adjusted low-frequency current I' at the second node 30B. DC The control circuit 34 can control the LDO regulator in the multi-function circuit 32 to reduce or increase the adjusted low-frequency current I'. DC .

[0042] It is worth noting that as the RF signal 18 advances through the driver stage 20 and output stage 22 of the multi-stage power amplifier circuit 16, the RF signal 18 may experience a time delay between the driver stage 20 and the output stage 22. Therefore, the RF signal 18 may experience a transient amplitude change between the driver stage 20 and the output stage 22. In this regard, the first voltage equalizer circuit 60A and the second voltage equalizer circuit 60B can be configured to equalize the first ET target voltage V. TGTA From the second ET target voltage V TGTB The determined time delay between the driver stage 20 and the output stage 22 of the delay multi-stage power amplifier circuit 16. Therefore, the second ET voltage V CCB From the first ET voltage V CCA The time delay determined by the delay helps to accommodate the time delay between driver stage 20 and output stage 22.

[0043] In another embodiment, in the second power management mode, the control circuit 34 is configured to cause the first node 30A and the second node 30B to each output a first ET voltage V. CCA and low-frequency current I DC Specifically, the control circuit 34 activates the first voltage amplifier 48A and deactivates the second voltage amplifier 48B, so that the first node 30A and the second node 30B each output a first ET voltage V. CCA The control circuit 34 also disables the LDO regulator and closes the switch in the multifunction circuit 32 to couple the second node 30B to the first node 30A, thereby receiving the low-frequency current I. DC The control circuit 34 further disconnects the first switch 52A and the second switch 52B, so that the first node 30A and the second node 30B each output a low-frequency current I. DCThe control circuit 34 is further configured to generate a feedback signal 36 based on the voltage difference across the first offset capacitor 50A.

[0044] In another embodiment, in the third power management mode, the control circuit 34 is configured to cause the first node 30A and the second node 30B to each output a second ET voltage V. CCB and low-frequency current I DC Specifically, the control circuit 34 deactivates the first voltage amplifier 48A and activates the second voltage amplifier 48B, so that the first node 30A and the second node 30B each output the second ET voltage V. CCB The control circuit 34 also disables the LDO regulator and closes the switch in the multifunction circuit 32 to couple the second node 30B to the first node 30A, thereby receiving the low-frequency current I. DC The control circuit 34 further disconnects the first switch 52A and the second switch 52B, so that the first node 30A and the second node 30B each output a low-frequency current I. DC The control circuit 34 is further configured to generate a feedback signal 36 based on the voltage difference across the first offset capacitor 50A.

[0045] In another embodiment, in the fourth power management mode, the control circuit 34 is configured to cause the first node 30A and the second node 30B to each output a low-frequency voltage V. DC and low-frequency current I DC Specifically, control circuit 34 deactivates first voltage amplifier 48A and second voltage amplifier 48B. Therefore, the first ET voltage V... CCA Second ET voltage V CCB Neither will be generated. Control circuit 34 also disables the LDO regulator and closes the switch in multifunction circuit 32 to couple the second node 30B to the first node 30A, thereby receiving the low-frequency current I. DC The control circuit 34 further closes the first switch 52A and opens the second switch 52B, causing the low-frequency voltage V at the first node 30A and the second node 30B to... DC The signal is modulated across the first offset capacitor 50A to track the average power of the RF signal 18. In this regard, the low-frequency voltage V... DC This can be referred to as average power tracking (APT) voltage. Control circuitry 34 is further configured to generate a feedback signal 36 based on the voltage difference across the first offset capacitor 50A, and PMIC 12 can accordingly modulate the low-frequency current I. DC Therefore, both driver stage 20 and output stage 22 will be based on the low-frequency voltage V. DC and low-frequency current I DC Let's operate it.

[0046] In another embodiment, in the fifth power management mode, the control circuit 34 is configured to cause the first node 30A and the second node 30B to each output a low-frequency voltage V. DC and low-frequency current I DC Specifically, control circuit 34 deactivates first voltage amplifier 48A and second voltage amplifier 48B. Therefore, the first ET voltage V... CCA Second ET voltage V CCB Neither will be generated. Control circuit 34 also disables the LDO regulator and closes the switch in multifunction circuit 32 to couple the second node 30B to the first node 30A, thereby receiving the low-frequency current I. DC The control circuit 34 further disconnects the first switch 52A and closes the second switch 52B, causing the low-frequency voltage V at the first node 30A and the second node 30B to... DC The signal is modulated across the second offset capacitor 50B to track the average power of the RF signal 18. In this regard, the low-frequency voltage V... DC This is also the APT voltage. Control circuit 34 is further configured to generate a feedback signal 36 based on the voltage difference across the first offset capacitor 50A, and PMIC 12 can accordingly modulate the low-frequency current I. DC Therefore, both driver stage 20 and output stage 22 will be based on the low-frequency voltage V. DC and low-frequency current I DC Let's operate it.

[0047] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A method of operating a multi-mode power management device, comprising: generating a low frequency current and a low frequency voltage; generating a first ET voltage based on a first ET target voltage; generating a second ET voltage based on a second ET target voltage; outputting one or more of the first ET voltage, the second ET voltage, and the low frequency voltage through a first node and a second node; outputting at least the low frequency current through the first node and the second node; and delaying the first ET target voltage from the second ET target voltage to accommodate a time delay within a multi-stage power amplifier circuit that amplifies a radio frequency (RF) signal. in a first power management mode, 2. The method of claim 1, further comprising: outputting the first ET voltage and the low frequency current through the first node; and outputting the second ET voltage less than or equal to the first ET voltage and an adjusted low frequency current proportional to the low frequency current through the second node. in a third power management mode, outputting the first ET voltage and the low frequency current through each of the first node and the second node. in a second power management mode, outputting the second ET voltage and the low frequency current through each of the first node and the second node.

3. The method of claim 1, further comprising: in a fourth power management mode, outputting the low frequency voltage and the low frequency current through each of the first node and the second node.

4. The method of claim 1, further comprising: delaying the first ET target voltage from the second ET target voltage to accommodate a time delay between a driver stage and an output stage in the multi-stage power amplifier circuit.

5. The method of claim 1, further comprising:

7. The method of claim 6, further comprising:

6. The method of claim 1, further comprising: generating the low frequency voltage based on a battery voltage; inducing the low frequency current based on the low frequency voltage; and adjusting the low frequency voltage and the low frequency current based on a feedback signal.

8. The method of claim 7, further comprising: generating a first initial ET voltage based on the first ET target voltage at a first coupling node through a first voltage amplifier; boosting the first initial ET voltage by a first offset voltage through a first offset capacitor to generate the first ET voltage; generating a second initial ET voltage based on the second ET target voltage at a second coupling node through a second voltage amplifier; and boosting the second initial ET voltage by a second offset voltage through a second offset capacitor to generate the second ET voltage.

9. The method of claim 8, further comprising: generating a multi-level power supply voltage for one or more of the first voltage amplifier and the second voltage amplifier; generating the first ET target voltage based on a common ET target voltage; and generating the second ET target voltage based on the common ET target voltage. in a first power management mode, activating the first voltage amplifier and the second voltage amplifier to cause the first node and the second node to output the first ET voltage and the second ET voltage, respectively; controlling a multi-functional circuit coupled between the first node and the second node to generate an adjusted low frequency current proportional to the low frequency current; and ​ 10. The method of claim 8, further comprising: ​ ​ ​ ​ turning off a first switch coupled between the first coupling node and ground and a second switch coupled between the second coupling node and the ground, thereby causing the first node and the second node to output the low frequency current and the adjusted low frequency current, respectively.

11. The method of claim 10, further comprising: generating the feedback signal based on respective voltage differences across the first offset capacitor; and controlling the multi-functional circuit based on respective voltage differences across the second offset capacitor.

12. The method of claim 10, further comprising: delaying the first ET target voltage from the second ET target voltage based on a determined time delay between the driver stage and the output stage of the multi-stage power amplifier circuit.

13. The method of claim 8, further comprising: in a second power management mode, activating the first voltage amplifier and deactivating the second voltage amplifier to cause the first node and the second node to each output the first ET voltage; controlling a multi-functional circuit coupled between the first node and the second node to couple the second node to the first node to receive the low frequency current; and turning off a first switch coupled between the first coupling node and ground and a second switch coupled between the second coupling node and the ground to cause the first node and the second node to each output the low frequency current.

14. The method of claim 13, further comprising: generating the feedback signal based on a voltage difference across the first offset capacitor.

15. The method of claim 8, further comprising: in a second power management mode, deactivating the first voltage amplifier and activating the second voltage amplifier to cause the first node and the second node to each output the second ET voltage; controlling a multi-functional circuit coupled between the first node and the second node to couple the second node to the first node to receive the low frequency current; and turning off a first switch coupled between the first coupling node and ground and a second switch coupled between the second coupling node and the ground to cause the first node and the second node to each output the low frequency current.

16. The method of claim 15, further comprising: generating the feedback signal based on a voltage difference across the first offset capacitor.

17. The method of claim 8, further comprising: in a second power management mode, deactivating the first voltage amplifier and the second voltage amplifier; controlling a multi-functional circuit coupled between the first node and the second node to couple the second node to the first node to receive the low frequency current; and turning on a first switch coupled between the first coupling node and ground and turning off a second switch coupled between the second coupling node and the ground to cause the low frequency voltage to be modulated across the first offset capacitor.

18. The method of claim 17, further comprising: generating the feedback signal based on a voltage difference across the first offset capacitor.

19. The method of claim 8, further comprising: in a second power management mode, deactivating the first voltage amplifier and the second voltage amplifier; controlling a multi-functional circuit coupled between the first node and the second node to couple the second node to the first node to receive the low frequency current; and opening a first switch coupled between the first coupling node and ground and closing a second switch coupled between the second coupling node and the ground to cause the low frequency voltage to be modulated across the second offset capacitor.

20. The method of claim 19, further comprising: generating the feedback signal based on a voltage difference across the first offset capacitor.

21. A wireless device comprising a multi-mode power management apparatus, the multi-mode power management apparatus comprising: a power management integrated circuit (PMIC) configured to generate a low frequency current and a low frequency voltage; an envelope tracking (ET) integrated circuit (ETIC) comprising: a first node coupled to the PMIC; a second node coupled to the first node through a multi-function circuit; a first voltage circuit configured to generate a first ET voltage based on a first ET target voltage; a second voltage circuit configured to generate a second ET voltage based on a second ET target voltage; and a control circuit configured to: cause the first node and the second node to output one or more of the first ET voltage, the second ET voltage, and the low frequency voltage; and cause the first node and the second node to output at least the low frequency current; and a multi-stage power amplifier circuit coupled to the first node and the second node and configured to amplify a radio frequency (RF) signal, wherein the first ET target voltage is delayed from the second ET target voltage to accommodate a time delay within the multi-stage power amplifier circuit.

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