Variable gain CTLE structure and transceiver

Abstract

The invention provides a variable gain CTLE structure and a transceiver, and the structure comprises a load module which is provided with a first access point and a second access point; the transconductance module is composed of a plurality of transconductance units, and each transconductance unit comprises a first branch and a second branch which are symmetrically arranged; one end of the first branch is connected with the first access point, and the other end is connected with the first current source; one end of the second branch is connected with the second access point, and the other end is connected with the second current source; the first branch circuit and the second branch circuit are provided with MOS tubes. A first adjustable resistor and a first adjustable capacitor which are arranged in parallel are also connected between the first branch and the second branch; each transconductance unit is controlled through a current mirror switch, and the gain of each MOS tube is controlled through the current mirror switch. According to the scheme, the wide-range gain adjustment of the CTLE can be realized on the premise of maintaining the CTLE function, and the PGA function is included, so that the analog front-end stage number can be reduced, and the system power consumption and noise can be improved.

Description

Technical Field

[0001] This invention relates to the field of equalizer technology, and more particularly to a variable gain CTLE structure and transceiver. Background Technology

[0002] With the development of AI, big data, and network technologies, there is a growing demand for high-speed data communication. The data transmission rate in wired data communication modules is constantly increasing, posing a significant challenge to the design of wired transceivers. For transmission channels of the same length, data attenuation is positively correlated with the data rate. This attenuation needs to be compensated for by the equalization function of the wired transceiver to ensure high-quality data communication. Therefore, as data rates increase, the requirements for the equalization function of wired transceivers also continuously increase.

[0003] For most types of wired transceivers, the receiver handles the vast majority of equalization requirements. Mainstream receiver-side equalization technologies include continuous-time linear equalizers (CTLEs), programmable-gain amplifiers (PGAs), feed-forward equalizers, and decision-feedback equalizers. Among these, CTLEs and PGAs operate in the continuous-time domain and are typically implemented using analog circuitry; this part is often referred to as the analog front-end.

[0004] The analog front-end consists of two parts: the CTLE and the PGA. Each CTLE and PGA is implemented by cascading one or more circuit stages, and the CTLE and PGA are then cascaded together. The advantage of this cascaded design is its simplicity and the ability to independently configure equalization and gain. However, too many cascaded stages lead to greater power consumption and compromised noise performance. Therefore, there is a pressing need for a CTLE design that can reduce the number of analog front-end stages while maintaining the original functionality and characteristics, thereby improving system power consumption and noise. Summary of the Invention

[0005] The purpose of this invention is to provide a variable gain CTLE structure and transceiver that can achieve a wide range of CTLE gain adjustment while maintaining CTLE functionality, and includes PGA functionality, thereby reducing the number of stages in the analog front end and improving system power consumption and noise.

[0006] The technical solution provided by this invention is as follows: In a first aspect, this application provides a variable gain CTLE structure, including: A load module, the load module including a first access point and a second access point; The transconductance module is composed of a plurality of transconductance units, each of which includes a first branch and a second branch arranged symmetrically; one end of the first branch is connected to the first access point and the other end is connected to a first current source; one end of the second branch is connected to the second access point and the other end is connected to a second current source. Both the first branch and the second branch are equipped with MOSFETs, and the two MOSFETs are respectively used to connect the first input voltage and the second input voltage; a first adjustable resistor and a first adjustable capacitor are also connected in parallel between the first branch and the second branch; Each of the transconductance units is controlled by a current mirror switch. When the current mirror switch is open, the MOSFET corresponding to the transconductance unit provides normal gain; when the current mirror switch is closed, the gain of the MOSFET corresponding to the transconductance unit is 0.

[0007] In some embodiments, the two MOS transistors of each transconductance unit are a first MOS transistor and a second MOS transistor, respectively; The gate of the first MOS transistor is connected to the first input voltage, the drain of the first MOS transistor is connected to the first access point, and the source of the first MOS transistor is connected to the first current source. The gate of the second MOSFET is connected to the second input voltage, the drain of the second MOSFET is connected to the second access point, and the source of the second MOSFET is connected to the second current source. One end of the first adjustable resistor is connected between the source of the first MOSFET and the first current source, and the other end is connected between the source of the second MOSFET and the second current source. One end of the first adjustable capacitor is connected between the source of the first MOSFET and the first current source, and the other end is connected between the source of the second MOSFET and the second current source.

[0008] In some embodiments, the MOS transistor is an NMOS transistor, and the two MOS transistors in each transconductance unit are a first NMOS transistor and a second NMOS transistor, respectively; One end of the first current source and the second current source are respectively connected to the source of the first NMOS transistor and the source of the second NMOS transistor, and the other end of the first current source and the second current source are both grounded.

[0009] In some implementations, the load module includes two second adjustable resistors and a first differential resistor; One end of each of the two second adjustable resistors is connected to a DC power supply, and the other end is connected to the first access point and the second access point, respectively; One end of the first differential resistor is connected between the first access point and a second adjustable resistor, and the other end is connected between the second access point and another second adjustable resistor.

[0010] In some implementations, the load module includes two first adjustable current sources and a second differential resistor; One end of each of the two first adjustable current sources is connected to a power source, and the other end is connected to the first access point and the second access point, respectively. One end of the second differential resistor is connected between the first access point and a first adjustable current source, and the other end is connected between the second access point and another first adjustable current source; The load module further includes a first common-mode feedback circuit, which is used to control the current magnitude of the first adjustable current source.

[0011] In some embodiments, the MOS transistor is a PMOS transistor, and the two MOS transistors in each transconductance unit are a first PMOS transistor and a second PMOS transistor, respectively; One end of the first current source and the second current source are respectively connected to the source of the first PMOS transistor and the source of the second PMOS transistor, and the other end of the first current source and the second current source are both connected to a DC power supply.

[0012] In some implementations, the load module includes two third adjustable resistors and one third differential resistor; One end of each of the two third adjustable resistors is grounded, and the other end is connected to the first access point and the second access point, respectively. One end of the third differential resistor is connected between the first access point and one of the third adjustable resistors, and the other end is connected between the second access point and another of the third adjustable resistors.

[0013] In some implementations, the load module includes two second adjustable current sources and a fourth differential resistor; One end of each of the two second adjustable current sources is grounded, and the other end is connected to the first access point and the second access point, respectively. One end of the fourth differential resistor is connected between the first access point and a second adjustable current source, and the other end is connected between the second access point and another second adjustable current source. The load module further includes a second common-mode feedback circuit, which is used to control the current magnitude of the second adjustable current source.

[0014] In some embodiments, the number of transconductance modules is two, namely a first transconductance module and a second transconductance module; The MOS transistors of each transconductance unit in the first transconductance module are NMOS transistors, and the MOS transistors of each transconductance unit in the second transconductance module are PMOS transistors. The load module includes a fifth differential resistor, the two ends of which are respectively connected to the first access point and the second access point.

[0015] Secondly, this application provides a transceiver including the variable gain CTLE structure described in the first aspect.

[0016] The variable gain CTLE structure and transceiver provided by this invention can achieve wide-range gain adjustment of CTLE while maintaining CTLE functionality, and includes PGA functionality, thereby reducing the number of stages in the analog front end and improving system power consumption and noise. Attached Figure Description

[0017] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this solution.

[0018] Figure 1 This is a logical diagram of the CTLE structure in the prior art; Figure 2 This is a logical schematic diagram of the CTLE structure in this invention; Figure 3 This is a schematic diagram of the CTLE structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the CTLE structure according to another embodiment of the present invention; Figure 5 This is a schematic diagram of the CTLE structure according to another embodiment of the present invention; Figure 6 This is a schematic diagram of the CTLE structure according to another embodiment of the present invention; Figure 7 This is a schematic diagram of the CTLE structure according to another embodiment of the present invention.

[0019] The diagram is labeled as follows: 10-Load module; 11-Second adjustable resistor; 12-First differential resistor; 13-First adjustable current source; 14-Second differential resistor; 15-First common-mode feedback circuit; 16-Third adjustable resistor; 17-Third differential resistor; 18-Second adjustable current source; 19-Fourth differential resistor; 20-Transconductance module; 21-Transconductance unit; 22-First current source; 23-Second current source; 24-First adjustable resistor; 25-First adjustable capacitor; 26-First NMOS transistor; 27-Second NMOS transistor; 28-First PMOS transistor; 29-Second PMOS transistor. Detailed Implementation

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0021] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".

[0022] With the development of AI, big data, and network technologies, there is a high demand for data communication speed. The data transmission rate in wired data communication modules is constantly increasing, which poses a significant challenge to the design of wired transceivers. For transmission channels of the same length, the attenuation of transmitted data is positively correlated with the data rate. This attenuation needs to be compensated for by the equalization function of the wired transceiver to ensure high-quality data communication. Therefore, as the data rate increases, the requirements for the equalization function of wired transceivers also increase. For most types of wired transceivers, the receiver end bears the vast majority of equalization requirements. Mainstream technologies related to receiver equalization include Continuous-Time Linear Equalizer (CTLE), Programmable-Gain Amplifier (PGA), Feed-Forward Equalizer, and Decision-Feedback Equalizer. Among them, CTLE and PGA operate in the continuous-time domain and are usually implemented by analog circuits; this part is often referred to as the analog front-end.

[0023] Reference manual attached Figure 1 In existing technologies, the analog front-end is divided into two parts: CTLE and PGA. Each CTLE and PGA is implemented by cascading one or more circuit stages, and the CTLE and PGA are then cascaded together. The advantage of this cascaded design is its simplicity and the ability to independently configure equalization and gain. However, too many cascaded stages lead to greater power consumption and make it difficult to guarantee noise performance. This is because each input and output node of the analog front-end needs to guarantee the highest bandwidth in the entire link, resulting in high power consumption for its modules. Multiple cascaded stages significantly increase the number of high-bandwidth nodes, exacerbating the power consumption problem. Furthermore, each circuit stage generates noise, which is amplified by the next stage; therefore, as the number of circuit stages increases, the noise performance of the analog front-end deteriorates.

[0024] Therefore, there is an urgent need for a CTLE design that can reduce the number of analog front-end stages while maintaining the original functions and characteristics, thereby improving system power consumption and noise. (See attached reference manual.) Figure 2 This application provides a CTLE structure design that incorporates the functionality of a PGA, enabling simultaneous equalization control and gain control, thereby reducing the number of circuit stages and improving system power consumption and noise. The following is a detailed description of this solution with reference to the accompanying drawings: In one embodiment, refer to the appendix to the specification. Figures 3 to 6 This application provides a variable gain CTLE structure, including a load module 10 and a transconductance (GM) module 20. The load module includes a first access point (VON) and a second access point (VOP).

[0025] The transconductance module 20 consists of a plurality of transconductance (GM) units 21. This application does not limit the number of transconductance units 21, and it should be understood that the GM portion can consist of any number of GM units greater than or equal to two. For example, in one example, the transconductance module 20 consists of four transconductance units 21. In other embodiments, different numbers of transconductance units 21 can be selected according to requirements. Each transconductance unit 21 includes a pair of differential input MOS transistors, a pair of current sources, an adjustable resistor, and an adjustable capacitor.

[0026] Specifically, each transconductance unit 21 includes a first branch and a second branch arranged symmetrically; one end of the first branch is connected to the first access point and the other end is connected to the first current source 22; one end of the second branch is connected to the second access point and the other end is connected to the second current source 23.

[0027] Both the first and second branches are equipped with MOSFETs, which are used to connect to the first and second input voltages, respectively. The input MOSFETs provide the transconductance amplification capability of the system. A first adjustable resistor 24 and a first adjustable capacitor 25 are connected in parallel between the first and second branches. The first adjustable resistor 24 is R1 in the diagram, and the first adjustable capacitor 25 is C1. The first adjustable resistor 24 provides low-frequency attenuation capability, and the first adjustable capacitor 25 provides high-frequency enhancement capability.

[0028] Each transconductance unit 21 is controlled by a current mirror switch. For example, when the transconductance module 20 includes two transconductance units 21, the system provides four current mirror switches "[0,1]", each of which can be controlled independently, and any of them can be selected to be open. When the current mirror switch is open, the MOSFET of the corresponding transconductance unit 21 provides normal gain; when the current mirror switch is closed, the MOSFET of the corresponding transconductance unit 21 has a gain of 0. This allows the corresponding transconductance unit 21 to provide normal or zero gain by adjusting the current mirror switches of different transconductance units 21, thereby enabling the transconductance module 20 as a whole to provide the required gain, achieving a wide range of gain adjustment for CTLE. Furthermore, since the CTLE of this solution includes the function of PGA, the number of stages in the analog front-end can be reduced, which is beneficial to improving system power consumption and noise.

[0029] In one specific embodiment, each transconductance unit 21 has two MOSFETs, namely a first MOSFET and a second MOSFET. The gate of the first MOSFET is connected to a first input voltage, the drain of the first MOSFET is connected to a first access point, and the source of the first MOSFET is connected to a first current source 22. The gate of the second MOSFET is connected to a second input voltage, the drain of the second MOSFET is connected to a second access point, and the source of the second MOSFET is connected to a second current source 23. One end of a first adjustable resistor 24 is connected between the source of the first MOSFET and the first current source 22, and the other end is connected between the source of the second MOSFET and the second current source 23. One end of a first adjustable capacitor 25 is connected between the source of the first MOSFET and the first current source 22, and the other end is connected between the source of the second MOSFET and the second current source 23.

[0030] This application does not limit the specific choice of MOSFET; either NMOS or PMOS transistors can be used. For example, in one example, refer to the attached specification. Figure 3 The MOS transistors are NMOS transistors, and the two MOS transistors in each transconductance unit 21 are a first NMOS transistor 26 and a second NMOS transistor 27, respectively. One end of the first current source 22 and the second current source 23 are connected to the source of the first NMOS transistor 26 and the source of the second NMOS transistor 27, respectively, and the other end of the first current source 22 and the second current source 23 are both grounded.

[0031] The load module 10 includes two second adjustable resistors 11 and a first differential resistor 12. The second adjustable resistor 11 is RL shown in the figure, and the first differential resistor 12 is R2 shown in the figure. One ends of the two second adjustable resistors 11 are both connected to a DC power supply, and the other ends are respectively connected to a first access point and a second access point. One end of the first differential resistor 12 is connected between the first access point and one second adjustable resistor 11, and the other end is connected between the second access point and the other second adjustable resistor 11.

[0032] Attached Figure 3 The low-frequency gain of the shown CTLE structure can be expressed as: ; Attached Figure 3 The high-frequency gain of the shown CTLE structure can be expressed as: ; Let 2 / R1 < gm, then a gain ability with a higher high frequency than low frequency can be obtained, that is, the equalization ability required by CTLE is achieved. Adjusting the size of C1 can change the gain transition frequency, making the equalization ability of CTLE more in line with actual requirements. The n in the expression represents the number of GM units turned on. When the number of GM units turned on is large, the overall gain of CTLE is high; when the number of GM units turned on is small, the overall gain of CTLE is low, thus achieving a large adjustment of the gain of CTLE. And this gain adjustment does not affect the adjustment of the equalization ability by R1 and C1.

[0033] The load module 10 can also be adjusted according to requirements. In one example, referring to the attached drawings in the specification Figure 4 , compared with the attached drawings Figure 3 , the difference is that RL in the load part is replaced by an adjustable current source, and a common-mode feedback circuit is added to control the current magnitude of the current source. Specifically, the load module 10 includes two first adjustable current sources 13 and a second differential resistor 14. One ends of the two first adjustable current sources 13 are both connected to a power supply, and the other ends are respectively connected to a first access point and a second access point. One end of the second differential resistor 14 is connected between the first access point and one first adjustable current source 13, and the other end is connected between the second access point and the other first adjustable current source 13.

[0034] The load module 10 also includes a first common-mode feedback circuit 15, which controls the current magnitude of the first adjustable current source 13. The first common-mode feedback circuit 15 can be composed of an amplifier, with its positive input terminal connected to a reference voltage and its negative input terminal connected to a first access point and a second access point, thereby controlling the current magnitude of the current source. By adding a common-mode feedback mechanism, the common-mode voltages of VOP and VON can be easily controlled, making the design more practical.

[0035] Appendix Figure 4 The low-frequency gain of the CTLE structure shown can be expressed as: ; Appendix Figure 4 The high-frequency gain of the CTLE structure shown can be expressed as: ; Let RL >> R2, then Figure 4 The gain of the CTLE structure shown is Figure 3 The gain of the CTLE structures shown is the same.

[0036] For example, in one example, refer to the instruction manual appendix Figure 5 The MOS transistors are PMOS transistors, and the two MOS transistors in each transconductance unit 21 are the first PMOS transistor 28 and the second PMOS transistor 29, respectively; one end of the first current source 22 and the second current source 23 are connected to the source of the first PMOS transistor 28 and the source of the second PMOS transistor 29, respectively, and the other end of the first current source 22 and the second current source 23 are both connected to a DC power supply.

[0037] The load module 10 includes two third adjustable resistors 16 and one third differential resistor 17; one end of each of the two third adjustable resistors 16 is grounded, and the other end is connected to the first access point and the second access point respectively; one end of the third differential resistor 17 is connected between the first access point and one third adjustable resistor 16, and the other end is connected between the second access point and another third adjustable resistor 16.

[0038] The CTLE structure can achieve attachment Figure 3 The CTLE structure shown has the same function, so it will not be described in detail here.

[0039] Similarly, refer to the attached instruction manual. Figure 6The load module 10 can be adjusted to include two second adjustable current sources 18 and a fourth differential resistor 19. One end of each of the two second adjustable current sources 18 is grounded, and the other end is connected to the first access point and the second access point, respectively. One end of the fourth differential resistor 19 is connected between the first access point and one second adjustable current source 18, and the other end is connected between the second access point and the other second adjustable current source 18. This CTLE structure can achieve... Figure 4 The CTLE structure shown has the same function, so it will not be described in detail here.

[0040] The load module 10 of the CTLE structure can also include a second common-mode feedback circuit, which is the same as the first common-mode feedback circuit 15 mentioned above, and is used to control the current magnitude of the second adjustable current source 18.

[0041] For example, in one example, refer to the instruction manual appendix Figure 7 It can use both NMOS and PMOS simultaneously to achieve [the desired effect]. Figure 3 The CTLE structure shown, attached Figure 4 The CTLE structure shown has the same function. Specifically, in this example, there are two transconductance modules 20, namely a first transconductance module and a second transconductance module; the MOS transistors of each transconductance unit 21 in the first transconductance module are NMOS transistors, and the MOS transistors of each transconductance unit 21 in the second transconductance module are PMOS transistors. The connection method of the NMOS transistors in each transconductance unit 21 of the first transconductance module is the same as that shown in the appendix. Figure 3 The NMOS transistors in the CTLE structure shown are connected in the same way, and the PMOS transistors in each transconductance unit 21 of the second transconductance module are connected in the same way as those in the attached diagram. Figure 4 The PMOS transistors in the CTLE structure shown are connected in the same way, and will not be described in detail here. Furthermore, in this example, the first and second transconductance modules partially act as loads for each other, and no additional load is required to achieve power-to-ground current balance. Therefore... Figure 7 The load in the CTLE structure shown only needs to provide the differential mode portion to control bandwidth and gain. Specifically, load module 10 includes a fifth differential resistor, with its two ends connected to the first and second access points, respectively. Additionally, a common-mode feedback circuit can be added. This common-mode feedback circuit is identical to the aforementioned first common-mode feedback circuit 15 and is used to control the current magnitude of each current source in this example. (Appendix) Figure 7 The CTLE structure shown is compared to the attached Figure 3 The CTLE structure or attachment shown Figure 4 The CTLE structure shown has a gain characteristic that can reach twice the normal value.

[0042] In one embodiment, based on the foregoing embodiments, this application provides a transceiver including the variable gain CTLE structure of the foregoing embodiments.

[0043] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A variable gain CTLE structure, characterized in that, The utility model relates to a kind of load module, including first access point and second access point; Transconductance module is made of several transconductance units, each of which includes symmetrically arranged first branch and second branch;One end of the first branch is connected to the first access point, and the other end is connected to a first current source;One end of the second branch is connected to the second access point, and the other end is connected to a second current source; MOS transistors are provided on the first branch and the second branch, and two MOS transistors are used to connect a first input voltage and a second input voltage, respectively;A first adjustable resistor and a first adjustable capacitor are also connected in parallel between the first branch and the second branch; Each transconductance unit is controlled by a current mirror switch, which provides normal gain to the MOS transistor corresponding to the transconductance unit when the current mirror switch is open, and the gain of the MOS transistor corresponding to the transconductance unit is zero when the current mirror switch is closed. The two MOS transistors of each transconductance unit are a first MOS transistor and a second MOS transistor, respectively; 2. The variable gain CTLE structure of claim 1, wherein, The gate of the first MOS transistor is connected to the first input voltage, the drain of the first MOS transistor is connected to the first access point, and the source of the first MOS transistor is connected to the first current source; The gate of the second MOS transistor is connected to the second input voltage, the drain of the second MOS transistor is connected to the second access point, and the source of the second MOS transistor is connected to the second current source; One end of the first adjustable resistor is connected between the source of the first MOS transistor and the first current source, and the other end is connected between the source of the second MOS transistor and the second current source; One end of the first adjustable capacitor is connected between the source of the first MOS transistor and the first current source, and the other end is connected between the source of the second MOS transistor and the second current source. The MOS transistors are NMOS transistors, and the two MOS transistors of each transconductance unit are a first NMOS transistor and a second NMOS transistor, respectively; 3. The variable gain CTLE structure of claim 2, wherein, One end of the first current source and the second current source is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, respectively, and the other end of the first current source and the second current source is grounded. The load module includes two second adjustable resistors and a first differential resistor; 4. The variable gain CTLE structure of claim 3, wherein, One end of the two second adjustable resistors is connected to a DC power supply, and the other end is connected to the first access point and the second access point, respectively; One end of the first differential resistor is connected between the first access point and one of the second adjustable resistors, and the other end is connected between the second access point and the other second adjustable resistor. The load module includes two first adjustable current sources and a second differential resistor; 5. The variable gain CTLE structure of claim 3, wherein, One end of the two first adjustable current sources is connected to a power supply, and the other end is connected to the first access point and the second access point, respectively; One end of the second differential resistor is connected between the first access point and one of the first adjustable current sources, and the other end is connected between the second access point and the other first adjustable current source. ​ The load module further comprises a first common-mode feedback circuit for controlling the current of the first adjustable current source.

6. The variable gain CTLE structure of claim 2, wherein, The MOS transistor is a PMOS transistor, and the two MOS transistors of each transconductance unit are a first PMOS transistor and a second PMOS transistor, respectively. One end of the first current source and the second current source is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, respectively, and the other end of the first current source and the second current source is connected to a direct current source.

7. The variable gain CTLE structure of claim 6, wherein, The load module comprises two third adjustable resistors and a third differential resistor. One end of the two third adjustable resistors is grounded, and the other end is connected to the first access point and the second access point, respectively. One end of the third differential resistor is connected between the first access point and one third adjustable resistor, and the other end is connected between the second access point and the other third adjustable resistor.

8. The variable gain CTLE structure of claim 6, wherein, The load module comprises two second adjustable current sources and a fourth differential resistor. One end of the two second adjustable current sources is grounded, and the other end is connected to the first access point and the second access point, respectively. One end of the fourth differential resistor is connected between the first access point and one second adjustable current source, and the other end is connected between the second access point and the other second adjustable current source. The load module further comprises a second common-mode feedback circuit for controlling the current of the second adjustable current source.

9. The variable gain CTLE structure of claim 2, wherein, The number of transconductance modules is two, which are a first transconductance module and a second transconductance module. The MOS transistor of each transconductance unit of the first transconductance module is an NMOS transistor, and the MOS transistor of each transconductance unit of the second transconductance module is a PMOS transistor. The load module comprises a fifth differential resistor, and the two ends of the fifth differential resistor are connected to the first access point and the second access point, respectively.

10. A transceiver, characterized by A variable gain CTLE structure comprising any one of claims 1-9.

Images