Noise shaping SAR ADC circuit structure based on error feedback
By employing an error feedback mechanism and oversampling technology, the noise-shaping SAR ADC circuit structure solves the problem of limited accuracy in traditional SAR ADCs, achieving high-precision conversion with high signal-to-noise ratio and low power consumption, thus broadening its applicability in high-end applications.
Patent Information
- Application Number
- CN202511797945.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-02
- Publication Date
- 2026-03-06
AI Technical Summary
The accuracy of traditional SAR ADCs is limited by the matching accuracy of capacitor DACs and comparator noise, which leads to an increase in chip area and power consumption. Furthermore, ΔΣ ADCs have high power consumption and limited speed in high-precision applications.
The noise-shaping SAR ADC circuit structure employs an error feedback mechanism. By shaping the quantization noise to the high-frequency region through the error feedback circuit, combined with oversampling technology, the noise power density within the signal bandwidth is reduced, and the use of high-power operational amplifiers is avoided.
Without increasing complexity or power consumption, it improves the signal-to-noise ratio by 10-20dB, increases the effective number of bits by 2-3 bits, and reduces power consumption by 30%-50%, making it suitable for high-end applications such as medical electrocardiography and audio processing.
Smart Images
Figure CN121618973A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, and in particular to a noise-shaping SAR ADC circuit structure based on error feedback. Background Technology
[0002] Successive approximation analog-to-digital converters (SAR ADCs) have become the preferred solution for energy-constrained applications such as IoT terminals, biomedical sensors, and portable devices due to their excellent power efficiency and relatively simple structure at medium resolution and medium conversion rates. Their core working principle involves using a binary search algorithm, a high-precision capacitor-to-analog converter (CDAC) array, and a one-bit comparator to determine the digital code corresponding to the input analog signal bit by bit.
[0003] However, performance improvements in traditional SAR ADCs face fundamental bottlenecks. First, their accuracy is primarily limited by the matching accuracy of the capacitor DAC. Achieving higher resolution requires an exponential increase in the capacitance per unit capacitor or the use of complex calibration techniques, which leads to a dramatic increase in chip area and introduces additional design complexity and power consumption.
[0004] Secondly, comparator noise (including thermal noise and 1 / f noise) directly limits the lowest achievable quantization noise floor. In deep submicron processes, the effects of device mismatch and voltage fluctuations are even more pronounced, making the design of high-precision SAR ADCs extremely challenging.
[0005] On the other hand, oversampling and noise shaping techniques, exemplified by ΔΣADCs, represent another approach to achieving high-precision conversion. ΔΣADCs achieve extremely high signal-to-noise ratios (SNR) within the target signal bandwidth by oversampling the input signal at a rate much higher than the Nyquist frequency, using integrators and feedback loops to shape the quantization noise to the high-frequency region, and then filtering out out-of-band noise with digital filters. However, this advantage comes at the cost of high power consumption and speed limitations. ΔΣADCs typically require high-speed, high-gain operational amplifiers to construct the loop filters, which is a major source of power consumption in high-speed, high-precision applications. Furthermore, their oversampling characteristics limit the bandwidth of signals that can be processed.
[0006] Therefore, the industry urgently needs an innovative circuit structure that can effectively break through the accuracy bottleneck of SAR ADC without significantly increasing its inherent complexity and power consumption. Summary of the Invention
[0007] Therefore, it is necessary to provide a noise-shaping SAR ADC circuit structure based on error feedback to address the aforementioned technical problems.
[0008] This invention provides a noise-shaping SAR ADC circuit structure based on error feedback, comprising: Timing control circuitry is used to generate and coordinate the clock signals and control timing required by each module. The analog signal input terminal is used to receive the analog signal to be converted and coupled to the noise-shaping SAR ADC module; The noise-shaping SAR ADC module is used to perform successive approximation analog-to-digital conversion on the held sampled signal, output digital code, and integrate noise shaping function to extract quantization error signal; The error feedback circuit is used to integrate and adjust the gain of the quantization error signal, and to superimpose the processed error feedback signal to achieve high-frequency shaping of quantization noise. The digital output terminal is used to output the final digital signal after noise shaping and low-pass filtering. The timing control circuit and the input analog signal terminal are both connected to the input terminal of the noise-shaping SAR ADC module, the output terminal of the noise-shaping SAR ADC module is connected to the digital output terminal, and the noise-shaping SAR ADC module inputs the quantization error signal to the error feedback circuit.
[0009] Furthermore, the timing control circuit adopts a structure combining a ring oscillator and a frequency divider. The sampling clock frequency is 4-8 times the Nyquist frequency. The quantization clock and the sampling clock are complementary clocks with a phase difference of 180°. The frequency of the feedback clock is consistent with the sampling clock.
[0010] Furthermore, the noise-shaping SAR ADC module includes: The sample-and-hold circuit is used to sample the input analog signal at a preset time point and keep the sampled value constant during the conversion to ensure conversion accuracy; A CDAC array is used to convert digital codes into analog voltages for comparison with the input signal; The comparator is used to determine the relationship between the input signal and the DAC output, and outputs a digital decision. The SAR logic control circuit is used to integrate bit-by-bit comparison logic and noise shaping control logic. It controls the switching state of the CDAC array based on the comparator output and adjusts the quantization step size by receiving error feedback signals, thereby achieving the coordinated operation of successive approximation and noise shaping. The sample-and-hold circuit, CDAC array, comparator, and SAR logic control circuit are connected sequentially.
[0011] Furthermore, the CDAC array adopts a structure combining a binary weighted capacitor network and redundant capacitors, and the capacitor units of the CDAC array adopt a metal-insulator-metal or metal-oxide-metal structure, with typical values of 1fF to 10fF for the unit capacitance of each capacitor unit.
[0012] Furthermore, the comparator is a dynamic comparator, with its differential input terminals connected to the differential output nodes of the CDAC array, and its output terminal connected to the SAR logic control circuit to determine the magnitude relationship between the comparison voltage and the reference level.
[0013] Furthermore, the sample-and-hold circuit adopts a bootstrap switching circuit structure, including: A first signal path is used to receive a first differential input signal and includes a plurality of switches connected in series and at least one bootstrap capacitor for sampling the input signal under clock control. The second signal path is used to receive the second differential input signal, and its structure is completely symmetrical with that of the first signal path.
[0014] Furthermore, the sample-and-hold circuit is controlled by the CLK signal, and the gate-source voltage of the switching transistor is kept constant through internal capacitive coupling to ensure sampling linearity; the sampled differential signal is sent to the CDAC array and outputs a differential voltage V. OP / V ON They are connected to the positive and negative input terminals of the comparator respectively, and common-mode noise is suppressed through the fully differential signal processing mechanism.
[0015] Furthermore, the output of the error feedback circuit is connected to the input node or reference node of the CDAC array through a switching network to modulate the potential of the comparison point during the charge redistribution process, thereby achieving error injection.
[0016] Furthermore, the digital output supports two data output modes: speed mode and precision mode. In speed mode, the parallel conversion result of SAR logic is directly output. In precision mode, the output data is first processed by a digital filter to remove quantization noise that has been shaped to a high frequency, and then the filtered data is output through a serial interface.
[0017] Furthermore, the noise-shaping SAR ADC circuit structure supports multi-channel input, and the signals of each channel are processed in a time-division manner through a multiplexer, with the error feedback circuit being shared by each channel.
[0018] The beneficial effects of this invention are as follows: Through an error feedback mechanism, this invention can shape the noise energy during the quantization process to the high-frequency region, thereby reducing the noise power density within the signal bandwidth. Specifically, in each successive approximation conversion, the error feedback circuit extracts the quantization error generated by the comparator decision, accumulates this error through an analog or digital integrator, and then feeds it back to the input node or the conversion process. The feedback operation introduces a high-pass filter effect in the frequency domain, amplifying the quantization noise at high frequencies and weakening it at low frequencies. Simultaneously, this invention, combined with oversampling technology, can improve the signal-to-noise ratio by 10-20 dB and increase the effective number of bits by 2-3 bits. Furthermore, by avoiding the use of high-power operational amplifiers in ΔΣADCs, this invention reduces power consumption by 30%-50% and improves area efficiency by more than 20% at the same accuracy. It also supports dynamic calibration and configurable parameters, adapting to various application scenarios, such as medical electrocardiogram (ECG) acquisition or audio processing, where low noise and high linearity are crucial. This invention achieves high-precision conversion while maintaining the simplicity and low power consumption advantages of SAR ADCs, broadening its applicability in high-end applications. Attached Figure Description
[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a system principle block diagram of a noise-shaping SAR ADC circuit structure based on error feedback according to an embodiment of the present invention; Figure 2 This is a circuit diagram (excluding sample-and-hold circuit) of a noise-shaping SAR ADC module in an error-feedback-based noise-shaping SAR ADC circuit structure according to an embodiment of the present invention. Figure 3 This is a circuit diagram of a sample-and-hold circuit in a noise-shaping SAR ADC circuit structure based on error feedback according to an embodiment of the present invention. Figure 4 This is a circuit diagram of the error feedback circuit in a noise-shaping SAR ADC circuit structure based on error feedback according to an embodiment of the present invention. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0021] Please see Figures 1-4 A noise-shaping SAR ADC circuit structure based on error feedback includes: The timing control circuit is used to generate and coordinate the clock signals and control timing required by each module.
[0022] The input analog signal terminal is used to receive the analog signal to be converted and coupled to the noise-shaping SAR ADC module.
[0023] The noise-shaping SAR ADC module is used to perform successive approximation analog-to-digital conversion on the held sampled signal, output digital code, and integrate noise shaping function to extract quantization error signal.
[0024] The error feedback circuit is used to integrate and adjust the gain of the quantization error signal, and to superimpose the processed error feedback signal to achieve high-frequency shaping of quantization noise.
[0025] The digital output terminal is used to output the final digital signal after noise shaping and low-pass filtering.
[0026] The timing control circuit and the input analog signal terminal are both connected to the input terminal of the noise-shaping SAR ADC module, the output terminal of the noise-shaping SAR ADC module is connected to the digital output terminal, and the noise-shaping SAR ADC module inputs the quantization error signal to the error feedback circuit.
[0027] In the description of this invention, the timing control circuit adopts a structure combining a ring oscillator and a frequency divider. The sampling clock frequency is 4-8 times the Nyquist frequency. The quantization clock and the sampling clock are complementary clocks with a phase difference of 180°. The frequency of the feedback clock is consistent with the sampling clock.
[0028] In the description of this invention, the noise-shaping SAR ADC module includes: The sample-and-hold circuit is used to sample the input analog signal at a preset time point and keep the sampled value constant during the conversion to ensure conversion accuracy.
[0029] A CDAC array is used to convert digital codes into analog voltages for comparison with the input signal.
[0030] The comparator is used to determine the relationship between the input signal and the DAC output, and outputs a digital decision.
[0031] The SAR logic control circuit is used to integrate bit-by-bit comparison logic and noise shaping control logic. It controls the switching state of the CDAC array based on the comparator output and adjusts the quantization step size by receiving error feedback signals, thereby achieving the coordinated operation of successive approximation and noise shaping.
[0032] The sample-and-hold circuit, CDAC array, comparator, and SAR logic control circuit are connected sequentially.
[0033] Specifically, such as Figure 2 As shown, the core components of the noise-shaping SAR ADC module are illustrated, mainly including the CDAC array, comparator, and SAR logic control circuit.
[0034] CDAC array: Employs a binary weighted capacitor network (e.g., C1, C2, C3...) combined with redundant capacitors. The lower plate of each capacitor cell is connected to the reference voltage V via a switch. IP V IN Alternatively, the SAR logic control circuit precisely controls the state of these switches based on the comparator's output decision. During charge redistribution, the CDAC array generates an analog voltage that progressively approximates the sampled voltage. This array uses MIM or MOM capacitors with small unit capacitance (1fF-10fF), which is beneficial for high integration and speed.
[0035] Comparator: A dynamic comparator is used, with its positive and negative inputs connected to the differential output node V of the CDAC array, respectively. P and V N At the effective edge of the quantization clock CLKc, the comparator adjusts the voltage across V. P and V N The value of the result is used to determine the value of the result, and the numerical result Dout is output to the SAR logic.
[0036] SAR logic control circuit (noise shaping): This is the key difference between it and a traditional SAR ADC. It not only executes the conventional bit-by-bit approximation algorithm but also integrates noise shaping control logic. It records the decision and CDAC state for each comparison, thus calculating the quantization error. Simultaneously, it receives the output signal from the error feedback circuit and, based on this, controls additional switches at appropriate times (such as at the beginning of the next sampling or during charge redistribution) to inject the error voltage into the CDAC array, achieving feedback regulation.
[0037] In addition, such as Figure 2 As shown, the noise-shaping SAR ADC module mainly includes the input voltage terminal V. IN V IP V CM The circuit includes capacitors C1 to C36, switches K1 to K36, a comparator, and SAR logic control circuitry.
[0038] The connections form a fully differential capacitor array structure: input voltage V IN Connect one end of capacitor C1 to switch K1, and similarly connect one end of capacitor C2 to switch K2, and so on. V IN Connected to the lower plate of multiple capacitors; similarly, another differential input voltage V IPOne end of capacitor C19 is connected to switch K19, and further capacitors are connected via other switches; Common mode voltage V CM Switch K35 is then connected to one end of capacitor C35, and also to the other capacitors in the array. The other ends (upper plates) of all capacitors (C1 to C36) are connected together and converge to form two key nodes, which serve as the non-inverting input V of the comparator. P and the inverting input V N The comparator compares the voltages at the two nodes and sends its digital output to the SAR logic control circuit.
[0039] In the description of this invention, the CDAC array adopts a structure combining a binary weighted capacitor network and redundant capacitors, and the capacitor unit of the CDAC array adopts a metal-insulator-metal or metal-oxide-metal structure, with a typical value of 1fF to 10fF for the unit capacitance of each capacitor unit.
[0040] In the description of this invention, the comparator is a dynamic comparator, with its differential input terminals connected to the differential output nodes of the CDAC array and its output terminal connected to the SAR logic control circuit, used to determine the magnitude relationship between the comparison voltage and the reference level.
[0041] In the description of this invention, the sample-and-hold circuit adopts a bootstrap switching circuit structure, including: A first signal path is used to receive a first differential input signal and includes a plurality of switches connected in series and at least one bootstrap capacitor for sampling the input signal under clock control.
[0042] The second signal path is used to receive the second differential input signal, and its structure is completely symmetrical with that of the first signal path.
[0043] In the description of this invention, the sample-and-hold circuit is controlled by the CLK signal, and the gate-source voltage of the switching transistor is kept constant through internal capacitive coupling to ensure sampling linearity. The sampled differential signal is sent to the CDAC array and outputs a differential voltage V. OP / V ON They are connected to the positive and negative input terminals of the comparator respectively, and common-mode noise is suppressed through the fully differential signal processing mechanism.
[0044] Specifically, such as Figure 3 The diagram illustrates the implementation of a sample-and-hold circuit, employing a fully differential bootstrap switching structure to ensure excellent linearity over a high input signal range. The circuit structure comprises two completely symmetrical signal paths, each processing the differential input signal V. IP and V IN .
[0045] With V IPTaking the circuit path as an example, it mainly consists of switching transistors M1 and M2, and bootstrap capacitor Cbst. Working principle: When the sampling clock CLK is high, switching transistors M1 and M2 are turned on. The key to the bootstrap technology is that, through the coupling effect of capacitor Cbst, the voltage at the gate of control switching transistor M2 can follow the source voltage V. IP Synchronous variation. This ensures that the gate-source voltage of switch M2 remains constant throughout the sampling period, independent of its on-resistance, thus achieving highly linear sampling.
[0046] The sampled voltage is held on the capacitor of the CDAC array. Figure 2 C1+, etc., on the right side of the middle.
[0047] When CLK goes low, M1 and M2 are turned off, the sampling phase ends, and the holding phase begins. The voltage held on the CDAC array will be used for subsequent successive approximation conversions.
[0048] The fully differential structure effectively suppresses common-mode noise and improves the converter's anti-interference capability. The sampled differential voltage V... OP and V ON It will be fed into the subsequent circuit.
[0049] It should be noted that the output signal V in the sample-and-hold circuit OP V ON The signal V at the comparator input P V N They represent a direct connection and an equivalent relationship, signifying the naming of the same set of differential signals at different stages of the circuit.
[0050] In addition, such as Figure 3 As shown, the sample-and-hold circuit includes the following components: MOSFETs M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, and M22, as well as capacitors C37 and C38.
[0051] The connections are as follows: The drain of MOSFET M1 is connected to the power supply VDD, and its source is connected to the drain of MOSFET M2 and one end of capacitor C37; the source of MOSFET M2 is connected to ground; the source of MOSFET M3 is grounded, and its drain is connected to the other end of capacitor C37; the source of MOSFET M4 is connected to the power supply VDD, and its drain is connected to the source of MOSFET M5; the drain of MOSFET M5 is connected to the source of MOSFET M6; the drain of MOSFET M6 receives the clock signal CLK; the source of MOSFET M7 is connected to the power supply VDD; the source of MOSFET M8 is grounded; the source of MOSFET M9 is also grounded; the source of MOSFET M10 is connected to the signal node VOP; the source of MOSFET M11 is grounded; the source of MOSFET M12 is connected to the signal node VOP. Node VON; the source of MOSFET M13 is grounded; the source of MOSFET M14 is grounded; the source of MOSFET M15 is connected to power supply VDD; the source of MOSFET M16 is connected to power supply VDD; the source of MOSFET M17 is connected to power supply VDD; the source of MOSFET M18 receives the clock signal CLK; the source of MOSFET M19 is connected to the drain of MOSFET M12; the source of MOSFET M20 is connected to the drain of MOSFET M13; the source of MOSFET M21 is connected to signal node VON; the source of MOSFET M22 is grounded; one end of capacitor C37 is connected to the drain of MOSFET M2, and the other end is connected to the drain of MOSFET M3; one end of capacitor C38 is connected to the drain of MOSFET M12, and the other end is connected to the drain of MOSFET M13.
[0052] In the description of this invention, the output of the error feedback circuit is connected to the input node or reference node of the CDAC array through a switching network to modulate the potential of the comparison point during charge redistribution to achieve error injection.
[0053] Specifically, such as Figure 4 The diagram illustrates the implementation of an error feedback circuit, which includes an analog integrator or accumulator. Circuit structure and principle: The core of this circuit is an integrator composed of operational amplifiers, a capacitor Cf for storing the error, and a gain adjustment network that determines the feedback coefficient. The quantized error signal (possibly represented as a voltage) is quantized at the feedback clock CLK. fb Under the control of [the system], the error voltage is applied to the integrating capacitor Cf via a switch. The operational amplifier continuously integrates (accumulates) this error voltage and sets an appropriate feedback strength through a gain adjustment network.
[0054] Error injection: The analog voltage output by the integrator is the processed error feedback signal. For example... Figure 1 and Figure 3As shown, the error feedback signal is connected to specific nodes (such as input nodes or reference voltage nodes) of the CDAC array through a switching network controlled by SAR logic. When the switch is closed, the error feedback signal changes the charge of the relevant CDAC node, thereby fine-tuning the comparator's decision threshold in subsequent conversion cycles to compensate for the previous quantization error. This compensation in the time domain manifests as shaping of quantization noise in the frequency domain.
[0055] In the description of this invention, the digital output terminal supports two data output modes: speed mode and precision mode. In speed mode, the parallel conversion result of the SAR logic is directly output. In precision mode, the output data is first processed by a digital filter to remove quantization noise shaped to a high frequency, and then the filtered data is output through a serial interface.
[0056] In the description of this invention, the noise-shaping SAR ADC circuit structure supports multi-channel input, and the signals of each channel are processed in a time-division manner through a multiplexer, with the error feedback circuit being shared by each channel.
[0057] In actual operation, the entire operation of the error feedback-based noise-shaping SAR ADC circuit is a precisely coordinated closed-loop process, beginning with the activity of the timing control circuit. The timing control circuit starts first, employing a combination of a ring oscillator and a frequency divider to generate the clock signals required by the system, including a sampling clock, a quantization clock, and a feedback clock. The sampling clock frequency is set to 4 to 8 times the Nyquist frequency to achieve oversampling; the quantization clock is complementary to the sampling clock, with a 180-degree phase difference, ensuring seamless connection between the sampling and conversion stages; the feedback clock is synchronized with the sampling clock, providing a timing basis for error injection. These clock signals collectively establish the rhythm of the entire process.
[0058] At the effective edge of the sampling clock, the input analog signal is received through the input analog signal terminal and immediately enters the sample-and-hold circuit. The sample-and-hold circuit adopts a fully differential bootstrap switching structure, containing two completely symmetrical signal paths. When the clock signal CLK is high, the switch is turned on, and the bootstrap capacitor maintains a constant gate-source voltage of the switch through internal coupling, ensuring extremely high sampling linearity over a high input signal range. The sampled differential voltage V OP and V ON It is held on the capacitor of the CDAC array and remains stable during conversion, providing an accurate voltage reference for subsequent successive approximation conversions.
[0059] After the sample-and-hold phase ends, the quantization clock triggers the noise-shaping SAR ADC module to begin operation. The held differential signal V... OP and V ONThe voltage is fed into a CDAC array, which employs a structure combining a binary weighted capacitor network and redundant capacitors. The SAR logic control circuit, based on the comparator's output Dout, progressively controls the switching states in the CDAC array, performing charge redistribution so that the analog voltage output by the CDAC approximates the sampled voltage bit by bit. The comparator, acting as a dynamic comparator, continuously compares V... OP and V ON The magnitude of the value determines the output digital decision. Simultaneously, the SAR logic control circuit not only executes the traditional successive approximation algorithm but also extracts the quantization error signal in real time, calculated by recording the decision sequence and CDAC state during the conversion process. The quantization error signal is immediately sent to the error feedback circuit for processing.
[0060] The error feedback circuit receives the quantization error signal under the control of the feedback clock and integrates and adjusts its gain. The core of this circuit is an integrator structure that accumulates the error signal through an operational amplifier and capacitor network to generate the processed error feedback signal. The strength of the error feedback signal can be adjusted by the capacitor ratio in the circuit to ensure optimized noise shaping. Subsequently, the error feedback signal is fed back to the noise-shaping SAR ADC module and connected to the input or reference node of the CDAC array through a switching network. At the beginning of the next sampling or conversion cycle, the SAR logic control circuit precisely controls the injection timing, modulating the potential of the comparison point with the error feedback signal, thereby achieving error compensation during charge redistribution. The feedback operation introduces a high-pass filter effect in the frequency domain, shaping the quantization noise energy to the high-frequency region and significantly reducing noise within the signal bandwidth.
[0061] Finally, the digital output terminal outputs the final result according to the preset mode. In speed mode, the parallel conversion result of the SAR logic control circuit is directly output, suitable for delay-sensitive applications; in precision mode, the output data is first processed by a digital filter to remove quantization noise shaped to high frequencies, and then a high-precision digital signal is output through a serial interface. The entire process is cyclical: the error generated by each conversion is fed back to correct the next conversion. Through this continuous error shaping mechanism, the system achieves a 10-20dB improvement in signal-to-noise ratio and a 2-3 bit increase in effective bit depth while maintaining low power consumption. With multi-channel input, the error feedback circuit is shared by all channels, and the signal is processed in a time-division multiplexing manner through a multiplexer, further optimizing resource utilization.
[0062] In summary, by utilizing the above-mentioned technical solution of this invention, through an error feedback mechanism, this invention can shape the noise energy during the quantization process to the high-frequency region, thereby reducing the noise power density within the signal bandwidth. Specifically, in each successive approximation conversion, the error feedback circuit extracts the quantization error generated by the comparator decision, accumulates this error through an analog or digital integrator, and then feeds it back to the input node or the conversion process. The feedback operation introduces a high-pass filter effect in the frequency domain, amplifying the quantization noise at high frequencies and weakening it at low frequencies. Simultaneously, this invention, combined with oversampling technology, can improve the signal-to-noise ratio by 10-20 dB and increase the effective bit depth by 2-3 bits. Furthermore, by avoiding the use of high-power operational amplifiers in ΔΣADCs, this invention reduces power consumption by 30%-50% and improves area efficiency by over 20% at the same accuracy. It also supports dynamic calibration and configurable parameters, adapting to various application scenarios, such as medical electrocardiogram (ECG) acquisition or audio processing, where low noise and high linearity are crucial. This invention achieves high-precision conversion while maintaining the simplicity and low power consumption advantages of SAR ADCs, broadening its applicability in high-end applications.
[0063] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
Claims
1. An error feedback based noise shaping SAR ADC circuit structure, characterized in that, The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method.
2. The error feedback based noise shaping SAR ADC circuit structure of claim 1, wherein, The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method.
3. The error feedback based noise shaping SAR ADC circuit structure of claim 1, wherein, The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method.
4. The error feedback based noise shaping SAR ADC circuit structure of claim 3, wherein, The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method.
5. The error feedback based noise shaping SAR ADC circuit structure of claim 4, wherein, The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method.
6. The error feedback based noise shaping SAR ADC circuit structure of claim 3, wherein, The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. 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The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping SAR ADC method. The application relates to a noise shaping SAR ADC module and a noise shaping 7. The error feedback based noise shaping SAR ADC circuit structure of claim 6, wherein, The sampling holding circuit is controlled by a CLK signal, the gate-source voltage of the switch tube is kept constant by internal capacitor coupling, and the sampling linearity is ensured; the sampled differential signal is sent into the CDAC array, and a differential voltage V OP / V ON The positive and negative input ends of the comparator are connected respectively, and common mode noise is inhibited through a fully differential signal processing mechanism.
8. The error feedback based noise shaping SAR ADC circuit structure of claim 1, wherein, The output end of the error feedback circuit is connected to the input node or reference node of the CDAC array through a switch network, and the potential of the comparison point is modulated in the charge redistribution process to achieve error injection.
9. The error feedback based noise shaping SAR ADC circuit structure of claim 1, wherein, The digital output end supports two data output modes, including a speed mode and a precision mode, in the speed mode, the parallel conversion result of the SAR logic is directly output, and in the precision mode, the output data is processed through a digital filter to filter out the quantization noise shaped to high frequency, and then the filtered data is output through a serial interface.
10. The error feedback based noise shaping SAR ADC circuit structure of claim 1, wherein, The noise shaping SAR ADC circuit structure supports multi-channel input, each channel signal is processed by a multiplexer in time, and the error feedback circuit is shared by each channel.