One-time programmable device and manufacturing method thereof

Abstract

The invention provides a one-time programmable device and a manufacturing method thereof. A one-time programmable device includes: a substrate; the first transistor is formed on the substrate and comprises a source region and a drain region; the first transistor is formed on the substrate, the second transistor is formed on the substrate and connected with the first transistor, the second transistor comprises a first gate structure and a second gate structure, the first gate structure and the second gate structure are isolated from each other, and the first gate structure is connected with the source region or the drain region. The invention further provides a manufacturing method of the one-time programmable device. Information can be stored for a long time, so that data reliability and system stability are ensured, electric leakage is reduced, and power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of one-time programmable device technology, and more particularly to one-time programmable devices and their manufacturing processes. Background Technology

[0002] One-time programmable devices are a special type of non-volatile memory that can only be programmed once and cannot be erased or rewritten once programmed.

[0003] Existing one-time programmable devices consist of two PMOS transistors connected in series. One PMOS transistor acts as a gate transistor, while the other PMOS transistor has a floating gate. Programming is achieved by injecting hot electrons into the floating gate to write "1". Summary of the Invention

[0004] This application provides a one-time programmable device and its manufacturing process, which can permanently store information to ensure data reliability and system stability, and reduce leakage current and power consumption.

[0005] To address the aforementioned technical problems, a first aspect of this application provides a one-time programmable device, comprising: a substrate; a first transistor formed on the substrate, including a source region and a drain region; and a second transistor formed on the substrate and connected to the first transistor, wherein the second transistor includes a first gate structure and a second gate structure, the first gate structure and the second gate structure are isolated from each other, and the first gate structure is connected to the source region or the drain region.

[0006] In some embodiments, the first gate structure, the second gate structure, and the gate of the first transistor are located on the same layer; and / or at least one of the first gate structure and the second gate structure is formed in the same step as the gate of the first transistor.

[0007] In some embodiments, at least one of the first gate structure and the second gate structure is a metal gate.

[0008] In some embodiments, the second transistor further includes a first dielectric layer disposed between the first gate structure and the second gate structure to isolate the first gate structure from the second gate structure.

[0009] In some embodiments, both the first gate structure and the second gate structure are metal gates; or one of the first gate structure and the second gate structure is a metal gate, while the other is a polysilicon gate.

[0010] In some embodiments, both the first gate structure and the second gate structure are doped polysilicon gates, and the doping types of the first gate structure and the second gate structure are opposite to form a PN junction in contact with each other, wherein the PN junction isolates the first gate structure and the second gate structure.

[0011] In some embodiments, the substrate includes a semiconductor active region and a shallow trench isolation structure, the shallow trench isolation structure surrounding the semiconductor active region to isolate adjacent semiconductor active regions from each other; the first transistor is formed in the semiconductor active region, and the second transistor is formed on the shallow trench isolation structure.

[0012] In some embodiments, the first transistor includes: a third gate structure disposed above the active region of the semiconductor, the third gate structure serving as the gate of the first transistor; a source region and a drain region formed in the active region of the semiconductor and located on both sides of the third gate structure; the source region being connected to the first gate structure via a connecting plug and a connecting line; and the second gate structure being connected to a corresponding source line via a second gate contact plug.

[0013] In some embodiments, the programming transistor is programmed in response to the disruption of the isolation between the first gate structure and the second gate structure, forming a conductive path between the first gate structure and the second gate structure.

[0014] To address the aforementioned technical problems, a second aspect of this application also provides a method for fabricating a one-time programmable device, comprising: providing a substrate, wherein the substrate includes a semiconductor active region and a shallow trench isolation structure, the shallow trench isolation structure surrounding the semiconductor active region to isolate adjacent semiconductor active regions from each other; forming a first transistor in the semiconductor active region, including a source region and a drain region; forming a second transistor on the shallow trench isolation structure, the second transistor being connected to the first transistor, wherein the second transistor includes a first gate structure and a second gate structure, the first gate structure and the second gate structure being isolated from each other, and the first gate structure being connected to the source region or the drain region.

[0015] In some embodiments, both the first gate structure and the second gate structure are metal gates; or one of the first gate structure and the second gate structure is a metal gate and the other is a polysilicon gate; or both the first gate structure and the second gate structure are doped polysilicon gates.

[0016] In some embodiments, in response to both the first gate structure and the second gate structure being metal gates, the step of forming a first transistor in the semiconductor active region and creating a second transistor on the shallow trench isolation structure includes: forming a first dummy gate and a second dummy gate on the shallow trench isolation structure, and forming a third dummy gate on the semiconductor active region, wherein the first dummy gate, the second dummy gate, and the third dummy gate are all doped polysilicon gates; removing the first dummy gate and oxidizing the side of the second dummy gate near the first dummy gate to form a first dielectric layer; filling the original region of the first dummy gate with a first metal to form a first gate structure; removing the second dummy gate and the third dummy gate, and filling the original regions of the second dummy gate and the third dummy gate with a second metal to form a second gate structure and a third gate structure, respectively; wherein the first gate structure, the second gate structure, and the first dielectric layer constitute the second transistor, and the third gate structure serves as the gate of the first transistor.

[0017] In some embodiments, the third gate structure of the first transistor is connected to a corresponding bit line via a first gate contact plug; the drain region of the first transistor is connected to a corresponding word line via a drain contact plug; the source region of the first transistor is connected to the first gate structure via a connection plug and a connection line; and the second gate structure is connected to the source line via a second gate contact plug.

[0018] In some embodiments of this application, a second transistor is connected to the first transistor, wherein the first gate structure of the second transistor is isolated from the second gate structure, and the first gate structure of the second transistor is connected to the source region or the drain region of the first transistor. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 A schematic diagram of a one-time programmable device provided in an embodiment of this application; Figure 2 A flowchart illustrating a manufacturing process for a one-time programmable device according to an embodiment of this application; Figure 3 A schematic diagram illustrating the formation of a first pseudo-gate, a second pseudo-gate, and a third pseudo-gate for a one-time programmable device; Figure 4A schematic diagram of removing the first dummy gate for a one-time programmable device; Figure 5 A schematic diagram of forming the first dielectric layer for a one-time programmable device; Figure 6 A schematic diagram of filling the first gate structure for a one-time programmable device; Figure 7 A schematic diagram of removing the second and third dummy gates for a one-time programmable device; Figure 8 A schematic diagram of filling the second and third gate structures for a one-time programmable device. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] The terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0022] In the embodiments of this application, all directional indicators (such as up, down, left, right, front, back, top, bottom, etc.) are only used to explain the relative positional relationship and movement of each component in a specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0023] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] In related technologies, existing one-time programmable (OTP) devices typically employ two PMOS transistors connected in series. One PMOS transistor acts as a gate transistor, controlling the current during programming and reading, while the other, with a floating gate, serves as the programming transistor. During programming, a high voltage is applied to the control gate of the programming transistor. This causes electrons in the semiconductor substrate to gain sufficient energy to tunnel through the insulating layer and inject into the floating gate via quantum tunneling. This process, known as hot electron injection, causes the floating gate to become negatively charged. This negative charge attracts positive charges from the substrate, forming a stronger inversion layer and lowering the absolute value of the threshold voltage. After programming, the PMOS transistor can conduct at a lower gate voltage, allowing it to remain on during subsequent read operations to write a "1". However, due to factors such as defects in the insulating layer, radiation damage, or temperature fluctuations, the charge on the floating gate may leak over time, potentially leading to the gradual loss of stored information.

[0026] To address the aforementioned technical problems, some embodiments of this application provide a one-time programmable device. The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] Figure 1 This is a schematic diagram of a one-time programmable device provided in an embodiment of this application.

[0028] The one-time programmable device 1 includes a substrate 10, a first transistor 20 and a second transistor 30 formed on the substrate 10. The first transistor 20 includes a source region 202 and a drain region 203. The second transistor 30 includes a first gate structure 301 and a second gate structure 302. The first gate structure 301 is connected to the source region 202 or the drain region 203 so that the second transistor 30 is connected to the first transistor 20. An isolation is provided between the first gate structure 301 and the second gate structure 302 to isolate the first gate structure 301 and the second gate structure 302 from each other. In response to the isolation between the first gate structure 301 and the second gate structure 302 being broken, a conductive path is formed between the first gate structure 301 and the second gate structure 302, the first transistor 20 and the second transistor 30 are turned on, the second transistor 30 is programmed, and the one-time programmable device 1 is programmed.

[0029] In one embodiment, the substrate 10 of the one-time programmable device 1 includes a semiconductor active region 101 and a shallow trench isolation structure 102. The shallow trench isolation structure 102 surrounds the semiconductor active region 101 to isolate adjacent semiconductor active regions 101 from each other. By arranging the first transistor 20 and the second transistor 30 in different regions, electrical interference between them can be effectively avoided. At the same time, the isolation characteristics of the shallow trench isolation structure 102 are used to significantly reduce the leakage current between adjacent devices.

[0030] A first transistor 20 is formed in a semiconductor active region 101, including a third gate structure 201, a source region 202, and a drain region 203. The third gate structure 201 serves as the gate of the first transistor 20 and as the control portion of the first transistor 20, used to control the conduction and cutoff of the first transistor 20. Exemplarily, it is made of metal or doped polysilicon. The source region 202 and the drain region 203 are formed in the semiconductor active region 101 on both sides of the third gate structure 201. A second transistor 30 is formed on a shallow trench isolation structure 102, including a first gate structure 301 and a second gate structure 302.

[0031] The first transistor 20 further includes a first gate oxide layer 204 disposed between the bottom of the third gate structure 201 and the semiconductor active region 101, serving as an insulating layer. The second transistor 30 further includes a second gate oxide layer 304 disposed between the bottom of the first gate structure 301 and the second gate structure 302 and the shallow trench isolation structure 102, serving as an insulating layer. In some embodiments, the first gate oxide layer 204 and the second gate oxide layer 304 are oxidized and fabricated simultaneously, and can be silicon dioxide or a compound of silicon and oxygen.

[0032] In one embodiment, the first gate structure 301, the second gate structure 302, and the gate of the first transistor 20 are located on the same layer; and / or at least one of the first gate structure 301 and the second gate structure 302 is formed in the same step as the gate of the first transistor 20. "Same layer" means that these structures are formed on the same physical level of the semiconductor substrate 10 by photolithography and etching processes. "Same step" means that at least one of the first gate structure 301 and the second gate structure 302 and the gate of the first transistor 20 are processed simultaneously using the same photoresist coating, exposure, and etching process.

[0033] By setting the first gate structure 301, the second gate structure 302 and the gate of the first transistor 20 on the same layer, the number of photolithography and etching processes can be reduced, the manufacturing complexity can be reduced and the dimensional consistency between the gate structures can be improved.

[0034] In one embodiment, at least one of the first gate structure 301 and the second gate structure 302 of the second transistor 30 is a metal gate. The second transistor 30 further includes a first dielectric layer 303 disposed between the first gate structure 301 and the second gate structure 302 to isolate the first gate structure 301 and the second gate structure 302, preventing them from making direct contact, while allowing them to break down when a sufficiently high voltage is applied. A conductive path is formed between the first gate structure 301 and the second gate structure 302, connecting the first gate structure 301 and the second gate structure 302, thereby allowing current to flow between the two gates. Consequently, the first transistor 20 and the second transistor 30 are turned on, and the second transistor 30 is programmed. Generally, the material of the metal gate can be titanium nitride, titanium, titanium-aluminum alloy, aluminum, aluminum-silicon alloy, tantalum-aluminum alloy, tantalum nitride, tungsten, tungsten nitride, chromium, niobium, etc., and is not limited thereto. The first dielectric layer 303 has good insulation properties and reduces leakage current. Specifically, the first dielectric layer 303 is an insulating material, such as silicon oxide and silicon nitride, which are commonly used choices and are not limited here.

[0035] The use of metal gates in the first gate structure 301 and / or the second gate structure 302 can reduce gate resistance and improve the switching speed and operational stability of the one-time programmable device 1. By breaking down the first dielectric layer 303 to form a controllable conductive path, one-time programming functionality can be achieved, and data is less likely to be lost.

[0036] In one embodiment, both the first gate structure 301 and the second gate structure 302 are metal gates; or one of the first gate structure 301 and the second gate structure 302 is a metal gate, and the other is a polysilicon gate. The metal gate has lower resistivity and better conductivity, which can improve the switching speed of the device; the polysilicon gate can be generated by chemical vapor deposition and has good compatibility with the substrate 10. When a combined structure of metal gate and polysilicon gate is used, the metal gate can effectively reduce the gate resistivity and improve current conduction performance, while the polysilicon gate helps simplify the manufacturing process. When used together, both maintain good conductivity and can adapt to the needs of different process conditions, thereby improving the overall reliability and efficiency of the device.

[0037] In one embodiment, the first gate structure 301 and the second gate structure 302 of the second transistor 30 are both doped polysilicon gates. One is a P-type doped polysilicon gate, and the other is an N-type doped polysilicon gate. The two are adjacent to each other to form a PN junction, which isolates the first gate structure 301 and the second gate structure 302. The doping type of the third gate structure 201 of the first transistor 20 is opposite to that of the first gate structure 301 of the second transistor 30, but the same as that of the second gate structure 302. To connect the second transistor 30 and the first transistor 20, the first gate structure 301 of the second transistor 30 is connected to the source region 202 or the drain region 203 of the first transistor 20. The following example illustrates the connection of the first gate structure 301 of the second transistor 30 to the source region 202 of the first transistor 20. The second gate structure 302 is connected to the source line, the drain region 203 of the first transistor 20 is connected to the word line, and the third gate structure 201 of the first transistor 20 is connected to the bit line. When unprogrammed, the PN junction of the second transistor 30 is reverse biased, blocking the path from the first transistor 20 to the source line. During programming, a reverse breakdown voltage is applied to the PN junction, forming a conductive channel between the first gate structure 301 and the second gate structure 302. The second transistor 30 is then programmed, creating a conduction path from the first transistor 20 to the source line. Furthermore, when both the first gate structure 301 and the second gate structure 302 of the second transistor 30 are doped polysilicon gates, a first dielectric layer 303 can be added between them. This first dielectric layer 303 isolates the first gate structure 301 and the second gate structure 302, preventing direct contact and thus improving the isolation effect.

[0038] After the second transistor 30 breaks down, it will remain in a low-impedance state, allowing current to flow. In this embodiment, this is represented by a logic "1" state, which can be detected during reading. If the second transistor 30 is not broken down, it will block current flow, representing a logic "0". In other embodiments, the second transistor 30 may also be represented by a logic "0" state after it breaks down; this is not a limitation.

[0039] The doping type of the first gate structure 301 and the second gate structure 302 of the second transistor 30 is selected as needed. In some embodiments, the source region 202 and the drain region 203 of the first transistor 20 are P-type doped, the third gate structure 201 is an N-type doped polysilicon gate, the first gate structure 301 is a P-type doped polysilicon gate, and the second gate structure 302 is an N-type doped polysilicon gate; or the source region 202 and the drain region 203 of the first transistor 20 are N-type doped, the third gate structure 201 is a P-type doped polysilicon gate, the first gate structure 301 is an N-type doped polysilicon gate, and the second gate structure 302 is a P-type doped polysilicon gate.

[0040] In one embodiment, the third gate structure 201 is connected to the corresponding bit line via the first gate contact plug 401 to control the switching state of the first transistor 20; the drain region 203 is connected to the corresponding word line via the drain region 203 contact plug to provide operating voltage during programming or reading, for selecting a specific memory cell; the source region 202 is connected to the first gate structure 301 via the connecting plug 403 and the connecting line 404, connecting the first transistor 20 and the second transistor 30 in series, thereby realizing signal transmission and control, as well as current transmission; the second gate structure 302 is connected to the corresponding source line via the second gate contact plug 405, receiving external voltage signals through the source line to establish a breakdown voltage difference during programming and to provide a reference potential during reading.

[0041] Before programming, the first transistor 20 is in the off state, and the second transistor 30 is in a high-resistance insulating state because the PN junction is reverse cut off or the first dielectric layer 303 is not broken down. Therefore, current cannot pass through the one-time programmable device 1.

[0042] During programming, the first transistor 20 is turned on by the bit line, allowing current to flow. A high voltage is applied to the word line, while the source line is grounded, creating a strong electric field across the second transistor to break down the PN junction or the first dielectric layer 303. In other embodiments, the high voltage can also be directly applied to the connection line 404 to break down the PN junction and / or the first dielectric layer 303. After the second transistor 30 breaks down, it will remain in a low-impedance state, which in this embodiment is represented by a logic "1" state and can be detected during reading. In other embodiments, the second transistor 30 can also be represented by a logic "0" state after breakdown; this is not a limitation.

[0043] During the read operation, the first transistor 20 is turned on, allowing current to flow. If the second transistor 30 is damaged during programming, it will remain on, allowing current to flow, representing logic "1". If the second transistor 30 is not damaged, it will block current from flowing, representing logic "0".

[0044] The one-time programmable device 1 provided in this embodiment connects the second transistor 30 to the first transistor 20. By breaking down the first dielectric layer 303 or PN junction of the second transistor 30, a conductive path is formed between the first gate structure 301 and the second gate structure 302, allowing current to pass through the first transistor 20 and the second transistor 30, thus achieving non-volatile data storage. Furthermore, the one-time programmable device 1 has a compact structure. Compared to related technologies, this application achieves circuit conduction through the breakdown of the second transistor 30. Since the breakdown process is irreversible, once the second transistor 30 is broken down, it will maintain a low impedance state, thereby achieving a programming state and enabling long-term information storage to ensure data reliability and system stability. The high impedance state before programming reduces leakage current and power consumption. In related technologies, one-time programmable devices consist of two PMOS transistors connected in series, occupying a large area. In contrast, this application uses one first transistor 20 and two adjacent first gate structures 301 and second gate structures 302, resulting in a smaller area and a more compact structure.

[0045] Furthermore, to address the aforementioned problems, a second aspect of this application provides a manufacturing method for a one-time programmable device 1, which will be described in detail below with reference to the accompanying drawings and embodiments.

[0046] Figure 2 A flowchart illustrating a manufacturing process for a one-time programmable device according to an embodiment of this application is provided. The method specifically includes: Step S1: Provide a substrate, wherein the substrate includes a semiconductor active region and a shallow trench isolation structure, the shallow trench isolation structure surrounding the semiconductor active region to isolate adjacent semiconductor active regions from each other; Step S2: A first transistor is formed in the active region of the semiconductor, including a source region and a drain region; a second transistor is formed on the shallow trench isolation structure, the second transistor being connected to the first transistor, wherein the second transistor includes a first gate structure and a second gate structure, the first gate structure and the second gate structure are isolated from each other, and the first gate structure is connected to the source region or the drain region.

[0047] As described in the above embodiments, in this application, both the first gate structure 301 and the second gate structure 302 are metal gates; or one of the first gate structure 301 and the second gate structure 302 is a metal gate, while the other is a polysilicon gate; or both the first gate structure 301 and the second gate structure 302 are doped polysilicon gates. The following describes the fabrication method using a second transistor where both the first gate structure 301 and the second gate structure 302 are metal gates as an example.

[0048] In the specific implementation process, see Figures 1 to 8 , Figure 1A schematic diagram of a one-time programmable device provided in an embodiment of this application; Figure 2 A flowchart illustrating a manufacturing process for a one-time programmable device according to an embodiment of this application; Figure 3 A schematic diagram illustrating the formation of a first pseudo-gate, a second pseudo-gate, and a third pseudo-gate for a one-time programmable device; Figure 4 A schematic diagram of removing the first dummy gate for a one-time programmable device; Figure 5 A schematic diagram of forming the first dielectric layer for a one-time programmable device; Figure 6 A schematic diagram of filling the first gate structure for a one-time programmable device; Figure 7 A schematic diagram of removing the second and third dummy gates for a one-time programmable device; Figure 8 A schematic diagram of filling the second and third gate structures for a one-time programmable device.

[0049] The formation of a first transistor 30 in the semiconductor active region 101 and the formation of a second transistor 20 on the shallow trench isolation structure 102 specifically include the following steps: Step S21: A first dummy gate and a second dummy gate are formed on the shallow trench isolation structure, and a third dummy gate is formed on the semiconductor active region, wherein the first dummy gate, the second dummy gate and the third dummy gate are doped polysilicon gates.

[0050] For details, see Figure 3 , Figure 3 This diagram illustrates the formation of a first dummy gate, a second dummy gate, and a third dummy gate for a one-time programmable device. In this embodiment, a first gate oxide layer 204 is formed between the bottom of the third dummy gate 503 and the active semiconductor region 101 to provide insulation. The first gate oxide layer 204 can be silicon dioxide or a silicon-oxygen compound. A second gate oxide layer 304 is formed between the first dummy gate 501, the second dummy gate 502, and the shallow trench isolation structure 102. The first gate oxide layer 204 and the second gate oxide layer 304 can be formed by a deposition process. The first gate oxide layer 204 and the second gate oxide layer 304 can be silicon dioxide or a silicon-oxygen compound. Furthermore, the material of the second gate oxide layer 304 can be the same as or different from the material of the first gate oxide layer 204.

[0051] Step S22: Remove the first dummy gate and oxidize the side of the second dummy gate near the first dummy gate to form a first dielectric layer.

[0052] For details, see Figure 4 and Figure 5 , Figure 4 A schematic diagram of removing the first dummy gate for a one-time programmable device; Figure 5This is a schematic diagram of forming the first dielectric layer for a one-time programmable device. In this embodiment, an etching process can be used for removal. A gap is formed in the region of the original first dummy gate 501, as shown in the diagram. Figure 4 As shown. In other embodiments, the first dummy gate 501 can also be removed by other methods, such as chemical etching, reactive ion etching, or other dry etching. The first dielectric layer 303 can be generated by natural oxidation or other methods, and there are no limitations on this.

[0053] Step S23: Fill the original region of the first dummy gate with the first metal to form the first gate structure.

[0054] For details, see Figure 6 , Figure 6 A schematic diagram of filling the first gate structure for a one-time programmable device. In this embodiment, the first metal is filled in the gap to form the first gate structure 301. The first metal is formed by depositing metal material in the gap. The material of the first metal can be selected by comprehensively considering the required electrical characteristics. Generally speaking, copper, tungsten and aluminum are commonly used choices.

[0055] Step S24: Remove the second dummy gate and the third dummy gate, and fill the original regions of the second dummy gate and the third dummy gate with a second metal to form a second gate structure and a third gate structure, respectively; wherein, the first gate structure, the second gate structure and the first dielectric layer constitute the second transistor, and the third gate structure serves as the gate of the first transistor.

[0056] For details, see Figure 7 and Figure 8 , Figure 7 A schematic diagram of removing the second and third dummy gates for a one-time programmable device; Figure 8 This diagram illustrates the filling of a second and third gate structure for a one-time programmable device. In this embodiment, a photomask process (also known as photolithography and etching steps) is used to remove the second dummy gate 502 and the third dummy gate 503. A photomask is used to protect the first dielectric layer 303 generated in the aforementioned steps, forming a gap in the area where the original second dummy gate 502 and third dummy gate 503 were located. The gap is as follows: Figure 7 As shown. The original regions of the second dummy gate 502 and the third dummy gate 503 are respectively filled with a second metal to form the second gate structure 302 and the third gate structure 201, as shown. Figure 8 As shown, the material of the second metal can be the same as or different from that of the first metal. Generally speaking, the material of the second metal is such as copper, tungsten, aluminum, etc.

[0057] In some embodiments, forming the first transistor 30 in the semiconductor active region 101 further includes: using the third gate structure 201 as a mask to perform source region ion and drain region ion implantation, so as to form a source region 202 and a drain region 203 in the active region 101 below the third gate structure 201, with the source region 202 and the drain region 203 located on both sides of the third gate structure 201, respectively.

[0058] In some embodiments, see also Figure 1 The method further includes connecting the third gate structure 201 of the first transistor 20 to the corresponding bit line via the first gate contact plug 401; connecting the drain region 203 of the first transistor 20 to the corresponding word line via the drain contact plug 402; connecting the source region 202 of the first transistor 20 to the first gate structure 301 via the connecting plug 403 and the connecting line 404; and connecting the second gate structure 302 to the corresponding source line via the second gate contact plug 405; wherein the first gate structure 301, the second gate structure 302 and the third gate structure 201 of the first transistor 20 are located on the same layer; and / or at least one of the first gate structure 301 and the second gate structure 302 is formed in the same step as the third gate structure 201 of the first transistor 20.

[0059] In this application, one of the first gate structure 301 and the second gate structure 302 is a metal gate, and the other is a polysilicon gate; or the process method in which both the first gate structure 301 and the second gate structure 302 are doped polysilicon gates can be adapted according to the above process method.

[0060] The manufacturing process of the one-time programmable device 1 provided in this embodiment involves forming a first transistor 20 in the semiconductor active region 101, forming a second transistor 30 on the shallow trench isolation structure 102, connecting the second transistor 30 to the first transistor 20, and forming a conductive path between the first gate structure 301 and the second gate structure 302 by breaking down the isolation of the second transistor 30. This allows current to pass through the first transistor 20 and the second transistor 30, achieving non-volatile data storage. Furthermore, the one-time programmable device 1 has a compact structure. Compared to related technologies, this application achieves circuit conduction through the breakdown of the second transistor 30. Since the breakdown process is irreversible, once the second transistor 30 is broken down, it will maintain a low impedance state, thereby achieving a programming state. This allows for long-term information storage, ensuring data reliability and system stability. The high impedance state before programming reduces leakage current and power consumption.

[0061] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the contents of this application's specification and figures, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A one-time programmable device, characterized by, Comprising: a substrate; a first transistor formed on the substrate, comprising a source region and a drain region; a second transistor formed on the substrate and connected with the first transistor, wherein the second transistor comprises a first gate structure and a second gate structure, the first gate structure and the second gate structure are isolated from each other, and the first gate structure is connected with the source region or the drain region.

2. The one-time programmable device according to claim 1, wherein: the first gate structure, the second gate structure and the gate of the first transistor are formed in the same layer; and / or at least one of the first gate structure and the second gate structure is formed in the same step as the gate of the first transistor.

3. The one-time programmable device according to claim 1, wherein: at least one of the first gate structure and the second gate structure is a metal gate.

4. The one-time programmable device according to claim 1, wherein: the second transistor further comprises a first dielectric layer arranged between the first gate structure and the second gate structure to isolate the first gate structure and the second gate structure.

5. The one-time programmable device according to claim 3, wherein: both the first gate structure and the second gate structure are metal gates; or one of the first gate structure and the second gate structure is a metal gate, and the other is a polysilicon gate.

6. The one-time programmable device according to claim 1, wherein: both the first gate structure and the second gate structure are doped polysilicon gates, and the doping types of the first gate structure and the second gate structure are opposite to each other to form a PN junction therebetween, the PN junction isolates the first gate structure and the second gate structure.

7. The one-time programmable device according to claim 6, wherein: the substrate comprises semiconductor active regions and shallow trench isolation structures, the shallow trench isolation structures surround the semiconductor active regions to isolate adjacent semiconductor active regions from each other; the first transistor is formed on the semiconductor active region, and the second transistor is formed on the shallow trench isolation structure.

8. The one-time programmable device according to claim 7, wherein: the first transistor comprises: a third gate structure arranged above the semiconductor active region, the third gate structure serving as the gate of the first transistor; a source region and a drain region formed in the semiconductor active region and located on both sides of the third gate structure; the source region connects the first gate structure through a connection plug and a connection line; and the second gate structure is connected to a corresponding source line through a second gate contact plug.

9. The one-time programmable device according to claim 1, wherein: in response to the isolation between the first gate structure and the second gate structure being destroyed, a conductive path is formed between the first gate structure and the second gate structure, and the programming tube is programmed.

10. A process for manufacturing a one-time programmable device, characterized in that, Comprising: A substrate is provided, wherein the substrate comprises a semiconductor active region and a shallow trench isolation structure surrounding the semiconductor active region to isolate adjacent semiconductor active regions from each other; A first transistor is formed in the semiconductor active region, comprising a source region and a drain region, and a second transistor is formed on the shallow trench isolation structure, connected to the first transistor, wherein the second transistor comprises a first gate structure and a second gate structure, the first gate structure and the second gate structure are isolated from each other, and the first gate structure is connected to the source region or the drain region.

11. The process method of claim 10, wherein: the first gate structure and the second gate structure are both metal gates; or one of the first gate structure and the second gate structure is a metal gate, and the other is a polysilicon gate; or the first gate structure and the second gate structure are both doped polysilicon gates.

12. The process method of claim 11, wherein, in response to the first gate structure and the second gate structure being both metal gates, the forming a first transistor in the semiconductor active region and a second transistor on the shallow trench isolation structure comprises: forming a first dummy gate and a second dummy gate on the shallow trench isolation structure, and a third dummy gate on the semiconductor active region, wherein the first dummy gate, the second dummy gate, and the third dummy gate are respectively doped polysilicon gates; removing the first dummy gate, and performing an oxidation process on a side of the second dummy gate close to the first dummy gate to form a first dielectric layer; filling a first metal in a former region of the first dummy gate to form a first gate structure; removing the second dummy gate and the third dummy gate, and filling a second metal in former regions of the second dummy gate and the third dummy gate respectively to form a second gate structure and a third gate structure; wherein the first gate structure, the second gate structure, and the first dielectric layer constitute the second transistor, and the third gate structure serves as a gate of the first transistor. Further comprising:

13. The process of claim 10, wherein, connecting the third gate structure of the first transistor to a corresponding bit line through a first gate contact plug; connecting the drain region of the first transistor to a corresponding word line through a drain contact plug; connecting the source region of the first transistor to the first gate structure through a connection plug and a connection line; connecting the second gate structure to a source line through a second gate contact plug. ​

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