SiC MOSFET Structure and Fabrication Method

Abstract

This application relates to a SiC MOSFET structure and its fabrication method, comprising: a substrate, wherein a first type of well region extends into the substrate via a first surface; a second type of source region is included within the well region, spaced apart along a first direction and extending along a second direction; a second type of doped pillar is located within the well region between adjacent source regions, extending along a third direction and penetrating the well region; the first width of the doped pillar is smaller than the first width of the well region between adjacent source regions; a plurality of trenches extend along a third direction, with their bottom surfaces higher than the bottom surfaces of the well regions; the plurality of trenches extend along the first direction and are spaced apart along the second direction; a gate is located on the top surface of the well region and the doped pillar between adjacent source regions, including a trench gate located within the plurality of trenches. The channel mobility is approximately 10 times higher than that of trench devices. In this case, the current density of the device is greatly improved, the chip area can be further reduced, and economic efficiency is greatly improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a SiC MOSFET structure and its fabrication method. Background Technology

[0002] With the continuous development of modern electronic technology, higher requirements are being placed on semiconductor materials, especially in fields such as high voltage, high frequency, high power, high temperature, and radiation resistance. Silicon carbide (SiC) has advantages such as a wide bandgap, high critical breakdown field strength, high saturated electron mobility, high melting point, and high thermal conductivity, which can meet the needs of high-performance power electronic devices.

[0003] With the development of semiconductor technology, small size, high power, and high performance have become the main development trends. The continuous miniaturization of the physical size of devices has driven the continuous reduction of the design pitch of their cells. The size of planar cells has approached the process limit, while trench cell designs have problems such as reliability and high on-resistance at high temperatures. Summary of the Invention

[0004] Therefore, it is necessary to provide a SiC MOSFET structure and its fabrication method to address the technical problems in the existing technology, which can at least further reduce the size of SiC-based chips.

[0005] In a first aspect, this application provides a SiC MOSFET structure, comprising: a substrate, wherein the substrate includes a first type of well region extending into the substrate via a first surface of the substrate; and the well region includes a second type of source region spaced apart along a first direction and extending along a second direction.

[0006] The second type of doped pillar is located in the well region between adjacent source regions and extends in the third direction and penetrates the well region; the first width of the doped pillar is smaller than the first width of the well region between adjacent source regions.

[0007] Multiple trenches extend along a third direction, with their bottom surfaces higher than the bottom surface of the trap area; the multiple trenches extend along a first direction and are spaced apart along a second direction.

[0008] A gate is located on the top surface of a well region and a doped pillar between adjacent source regions, including a trench gate located within a plurality of trenches;

[0009] The first direction, the second direction, and the third direction are perpendicular to each other; the first type of conductivity is opposite to the second type of conductivity; the first width is used to characterize the dimension along the first direction.

[0010] In some embodiments, the sidewalls of the trench gate are (11-20) crystal planes;

[0011] The spacing between adjacent trench grids along the second direction ranges from 0.03μm to 1μm.

[0012] In some embodiments, a first type of shielding area is provided at the bottom of the trench;

[0013] The second width of the shielding area is smaller than the second width of the trench;

[0014] The second width is used to characterize the dimension along the second direction.

[0015] In some embodiments, the top surface of the substrate includes a gate oxide layer and a gate conductive layer arranged in a direction opposite to a third party;

[0016] The orthogonal projection of the gate conductive layer on the first surface is located on the top surface of the well region and doped pillar between adjacent source regions, and together with the gate oxide layer directly below, it is used to form the gate.

[0017] In some embodiments, a dielectric layer is disposed on the outer surface of the gate;

[0018] The first width of the gate oxide layer is greater than the first width of the gate conductive layer, and the width of the dielectric layer is the same as the first width of the gate oxide layer, such that the orthogonal projection of part of the gate oxide layer and the dielectric layer on the first surface is located in part of the top surface and trench of the source region.

[0019] In some embodiments, the substrate includes a second type of current spreading layer located directly beneath the well region;

[0020] The doped pillars extend into the current spreading layer along the third direction.

[0021] In some embodiments, a source metal is disposed between adjacent dielectric layers; the bottom surface of the source metal is located within the top surface of the source region.

[0022] In some embodiments, the spacing between adjacent shielding zones is the same;

[0023] The second width of each shielding zone is the same;

[0024] The second width of each trench grid is the same.

[0025] Secondly, this application also provides a method for fabricating a SiC MOSFET structure, forming a SiC MOSFET structure as described in any of the above embodiments, the method comprising: providing a substrate; the substrate including a first type of well region extending into the substrate via a first surface of the substrate; the well region including a second type of source region spaced apart along a first direction and extending along a second direction;

[0026] A second type of doped pillar is formed in the well region between adjacent source regions, extending in a third direction and penetrating the well region; the first width of the doped pillar is smaller than the first width of the well region between adjacent source regions.

[0027] Multiple trenches are formed on the substrate, extending along a third direction, with their bottom surfaces higher than the bottom surfaces of the well region; the multiple trenches extend along a first direction and are spaced apart along a second direction.

[0028] A gate is formed on the top surface of the well region and the doped pillar between adjacent source regions; the gate includes a trench gate located in a plurality of trenches;

[0029] The first direction, the second direction, and the third direction are perpendicular to each other; the first type of conductivity is opposite to the second type of conductivity; the first width is used to characterize the dimension along the first direction.

[0030] In some embodiments, the sidewalls of the trench gate are (11-20) crystal planes;

[0031] After forming multiple trenches, an ion implantation process is performed on the bottom of the multiple trenches to form a first type of shielding area;

[0032] The second width of the shielding area is smaller than the second width of the trench;

[0033] The second width is used to characterize the dimension along the second direction.

[0034] The SiC MOSFET structure and its fabrication method provided in this application have the following unexpected technical effects:

[0035] The gate in the SiC MOSFET structure is divided into two parts. One part is located on the top surface of the well region between adjacent source regions and the doped pillars, and extends along the second direction to form a planar gate. The other part is located in multiple trenches to form a trench gate. By adding trench gates to form trench channels, and adding fin-like structures along the second direction, a Fin effect is generated between the channels of the (11-20) crystal plane, thereby further reducing the channel resistance.

[0036] Compared to the classic SiC MOSFET structure, the composite structure combining planar and trench channels achieves more effective channels within the same chip area, improving the current carrying capacity per unit area, thereby allowing for further miniaturization of the chip size and improving economic efficiency. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a three-dimensional schematic diagram of a SiC MOSFET structure provided in one embodiment of this application;

[0039] Figure 2 for Figure 1 Planar schematic diagrams along the XOY and XOZ cross-sections;

[0040] Figure 3 for Figure 2 The cross-sectional view of the SiC MOSFET structure at tangent AA' shown in (a) is shown in the figure.

[0041] Figure 4 for Figure 2 The cross-sectional view of the SiC MOSFET structure at tangent BB' shown in (a) is shown in the figure.

[0042] Figure 5 for Figure 2 The cross-sectional view of the SiC MOSFET structure at the tangent CC' shown in (a) is shown in the figure.

[0043] Figure 6 This is a flowchart of a method for fabricating a SiC MOSFET structure provided in one embodiment of this application;

[0044] Figure 7 This is a schematic cross-sectional view of the structure obtained after steps S20-S40 in the preparation method provided in one embodiment;

[0045] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the trench in step S60 of the preparation method provided in one embodiment;

[0046] Figure 9 for Figure 8 A schematic diagram of the cross-section of the structure after the shielding zone is formed;

[0047] Figure 10 This is a cross-sectional schematic diagram of the structure obtained after forming the gate in step S80 of the preparation method provided in one embodiment.

[0048] Explanation of reference numerals in the attached figures:

[0049] 1. Substrate; 2. Current spreading layer; 11. Well region; 12. Source region; 13. Doped pillar; 14. Shielding region; 30. Gate; 301. Planar gate; 302. Trench gate; 303. Trench; 31. Gate oxide layer; 32. Gate conductive layer; 40. Dielectric layer; 50. Contact hole. Detailed Implementation

[0050] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0052] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0053] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0056] In advanced manufacturing processes for Si-based logic circuits, starting from 20nm and below, the technology has transitioned from planar transistors to three-dimensional FinFET structures. FinFET technology can drastically reduce chip size, resulting in significant economic benefits. Due to its unique mechanical properties, SiC has much higher hardness and Young's modulus than Si, making the process of realizing 3D structures more challenging.

[0057] Furthermore, as mentioned earlier, SiC planar cells are limited by channel length and JFET width, and cell size (pitch) has reached design and process limits, with on-resistance R...on Further optimization requires consideration of new structures. Groove structures, due to the need to protect the bottom of the groove, also face design and manufacturing limitations.

[0058] Based on this, the embodiments of this application first provide a SiC MOSFET structure, Figure 1 This is a schematic diagram of the overall structure of the SiC MOSFET provided in this embodiment. Figure 2 (a) in the middle is Figure 1 A planar schematic diagram along the XOY cross-section. Figure 2 (b) in the middle is Figure 1 A planar schematic diagram along the XOZ cross-section. Figure 3 for Figure 2 (a) is a schematic diagram of the cross section at tangent AA'. Figure 4 for Figure 2 (a) is a schematic diagram of the cross section at the tangent BB'. Figure 5 for Figure 2 (a) is a cross-sectional view at the tangent CC'. For ease of understanding, the substrate in this embodiment may include a first surface on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and third directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). The first, second, and third directions may be mutually perpendicular. In this embodiment, the first direction is defined as the X-axis direction, the second direction as the Z-axis direction, and the opposite direction of the third direction as the Y-axis direction. Furthermore, it should be understood that the figures are not drawn to the actual scale of the device and are only for illustrative purposes.

[0059] First, such as Figure 1 As shown, the SiC MOSFET structure includes a substrate 1, a first-type well region 11, a second-type source region 12, a second-type doped pillar 13, multiple trenches, and a gate 30. In this embodiment, the first-type conductivity type is defined as N-type, and the second-type conductivity type is defined as P-type; further, P+ type represents heavily doped P-type, and P- type represents lightly doped P-type.

[0060] The substrate 1 may include a substrate and an epitaxial layer grown on the substrate. In some embodiments, a drain region is provided at the bottom of the substrate, and a second type (i.e., N-type) current spreading layer 2 is provided within the epitaxial layer. The epitaxial layer and the substrate together constitute the substrate 1 mentioned in the embodiments of this application. The current spreading layer 2 is used to increase the flow area of ​​the drain current, reduce the on-resistance of the device, and improve the high current carrying capacity.

[0061] Specifically, such as Figure 2 As shown, a P-type well region 11, an N+ type source region 12, and an N-type doped pillar 13 are formed in the epitaxial layer through ion implantation, and multiple trenches extending along the OZ direction are formed by photolithography and etching processes. The well region 11, source region 12, and doped pillar 13 all extend longitudinally from the first surface along the YO direction; in the OX direction, the source region 12 and doped pillar 13 are arranged alternately within the well region 11, extending along the OZ direction to form a repeating unit structure. Within the smallest repeating unit structure shown in the dashed box, the well region 11 separates the source region 12 and the current spreading layer 2, and simultaneously serves as a channel carrier, forming a conductive channel under the control of the gate 30. The source region 12, as a highly doped electron injection terminal, contacts the metal along the YO direction to achieve a low-resistance connection, forming a PN structure bulk diode with the well region 11. The doped pillar 13 penetrates the well region 11 along the OZ direction, establishing an auxiliary vertical conductive path from the source region 12 to the current spreading layer 2, significantly reducing the on-resistance, and suppressing the premature turn-on of the body diode in the well region 11 by modulating the depletion region, thereby enhancing the device's anti-latch-up capability.

[0062] like Figure 3 , Figure 4 As shown, the epitaxial layer also includes multiple trenches extending along the YO direction, with their bottom surface higher than the bottom surface of the well region 11 (i.e., not penetrating the well region 11), while extending along the OX direction and spaced apart in the OZ direction, to provide space for the trench gate 302. The gate 30 includes a first portion located on the top surface of the well region 11 and the doped pillar 13 between adjacent source regions 12, and a second portion simultaneously filled in the multiple trenches. The first portion is used to form a planar gate 301, and the second portion is used to form a trench gate 302. Introducing the trench gate 302 into the planar gate 301 type cell structure significantly increases the channel density while maintaining the cell size and cell density unchanged. At the same time, adjusting the thickness of the epitaxial layer between the trench gates 302 causes the trench-type channel to generate a Fin effect, thereby obtaining a higher channel mobility and achieving the purpose of reducing the chip size.

[0063] For example, the spacing between adjacent trench gates 302 along the OZ direction ranges from 0.03 μm to 1 μm. For instance, 0.03 μm, 0.1 μm, 0.5 μm, or 1 μm, etc.

[0064] For example, the second width (i.e., the dimension along the OZ direction) of the trench gate 302 ranges from 0.5 μm to 3 μm. For example, 0.5 μm, 1 μm, 2 μm, or 3 μm, etc.

[0065] like Figures 2-5As shown, the gate 30 mainly comprises two core structures: a gate oxide layer 31 and a gate conductive layer 32. The top surface of the epitaxial layer also includes a dielectric layer 40 and a source metal. The dielectric layer 40 covers the outer surface of the gate 30 and is used to achieve insulation between the gate 30 and the source metal. The first width of the gate oxide layer 31 is greater than that of the gate conductive layer 32, and the width of the dielectric layer 40 is the same as that of the gate oxide layer 31, partially covering the top surface and trench of the source region 12. The source metal is located between adjacent dielectric layers 40, and its bottom surface is located within the top surface of the source region 12, used to connect all source regions 12 and realize the electrical connection between the external circuit and the source.

[0066] The specific direction of current conduction is as follows: Figure 2 , Figure 3 As shown, the channels are concentrated in the doped pillars 13 between the bottom of the planar gate 301 and the trench gate 302. The crystal plane of the sidewall of the trench gate 302 is (11-20). The channel of the planar gate 301 is on the (0001) Si plane, and due to the high interface state density, the channel mobility is low; while the channel of the trench gate 302 is on the (11-20) crystal plane, the interface state distribution is relatively flat, and the channel mobility is high, which is beneficial to reducing the on-resistance at high temperatures and improving the temperature stability and reliability of the device. The higher the channel mobility, the better it is for reducing the on-resistance R. on The reduction in mobility, combined with the Fin effect (where the mobility is at the bulk mobility), results in a channel mobility that is approximately 10 times higher than that of a single trench gate 302 device.

[0067] In some embodiments, such as Figures 3-5 As shown, a first-type shielding area 14 (i.e., P+ type shielding area 14) is provided at the bottom of the trench gate 302 to alleviate the electric field concentration problem at the bottom of the trench, prevent premature breakdown of the gate oxide layer 31, and improve gate oxide reliability. It should be noted that the spacing of the shielding areas 14 along the OZ direction is the same, and the second width of the shielding area 14 should not be greater than the second width of the trench gate 302 to avoid encroaching on the area of ​​the effective trench.

[0068] Other examples Figure 5 As shown, some trenches are filled with dielectric layer 40, and the gate and source are directly connected by dielectric layer 40 to avoid gate-source short circuit.

[0069] The method for fabricating the above-mentioned semiconductor structure is described below. For some embodiments, please refer to... Figures 6-10 The method includes steps S20-S60.

[0070] Step S20: Provide a substrate 1; a first type well region 11 extending into the substrate 1 via a first surface of the substrate 1; the well region 11 includes second type source regions 12 spaced apart along a first direction and extending along a second direction.

[0071] Step S40: A second type of doped pillar 13 is formed in the well region 11 between adjacent source regions 12, extending in the third direction and penetrating the well region 11; the width of the doped pillar 13 is smaller than the width of the well region 11 between adjacent source regions 12.

[0072] Step S60: A plurality of trenches 303 extending along a third direction are formed on the substrate 1, with their bottom surfaces being higher than the bottom surfaces of the well region 11; the plurality of trenches 303 extend along a first direction and are spaced apart along a second direction.

[0073] Step S80: A gate 30 is formed on the top surface of the well region 11 and the doped pillar 13 between adjacent source regions 12; the gate 30 includes a trench gate 302 located in a plurality of trenches 303; wherein the first direction, the second direction and the third direction are perpendicular to each other; the first type of conductivity is opposite to the second type of conductivity; the first width is used to characterize the size along the first direction.

[0074] It should be understood that, although Figure 6 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, Figure 6 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0075] The extended steps of steps S20 and S40 include: providing a substrate and forming an epitaxial layer on the top surface of the substrate. The silicon carbide epitaxial layer can be formed using a self-doped epitaxial process, i.e., while forming the silicon carbide epitaxial layer, impurity ions are simultaneously doped into the silicon carbide epitaxial layer. Furthermore, the epitaxial layer and the substrate are used to constitute the substrate 1 mentioned in this application. Next, an ion implantation process is used to form a well region 11, a source region 12, and a doped pillar 13.

[0076] In some embodiments, a current spreading layer 2 is further provided within the epitaxial layer, and the resulting structure is as follows: Figure 7 As shown, where, Figure 7 Image (a) is a planar schematic diagram of a SiC MOSFET along the XOY cross-section. Figure 7 (b) is a schematic diagram of the cross-section at the tangent AA'. Figure 7 (c) in the figure is a planar schematic diagram of a SiC MOSFET along the XOZ cross-section.

[0077] Specifically, in embodiments where substrate 1 includes a P-type substrate 1, source region 12 can be formed by implanting N-type ions; correspondingly, in embodiments where substrate 1 includes an N-type substrate 1, source region 12 can be formed by implanting P-type ions. In some embodiments, the P-type impurity ions include one or more of boron ions, aluminum ions, gallium ions, or indium ions, and the N-type impurity ions include one or more of nitrogen ions, phosphorus ions, arsenic ions, or antimony ions.

[0078] The extension step of step S60 includes: coating a photoresist onto the first surface and patterning it, then etching to obtain a plurality of trenches 303; wherein the plurality of trenches 303 are spaced apart along the OZ direction and extend along the OX and YO directions, with a specific structure as shown below. Figure 8 As shown; ion implantation is performed on the bottom of multiple trenches 303 to form a P+ type shielding region 14, the specific structure of which is as follows. Figure 9 As shown.

[0079] For example, the depth range of multiple trenches 303 is 0.5μm-2μm, such as 0.5μm, 1μm, 1.5μm or 2μm, etc.

[0080] In the extended step of step S80, after forming the gate oxide layer 31 and the polysilicon layer in the first surface and the plurality of trenches 303, a portion of the polysilicon layer is removed. The polysilicon layer located on the top surface of the well region 11 and the doped pillar 13 between adjacent source regions 12 is used to form the gate conductive layer 32, as shown in the specific structure. Figure 10 As shown.

[0081] Following step S80, the method further includes: forming a dielectric layer 40 covering the gate 30 and the first surface using any deposition method; forming a contact hole 50 penetrating the dielectric layer 40 along the YO direction and exposing a portion of the top surface of the source region 12 using an etching process; the resulting structure is as follows: Figure 1 As shown; subsequent filling with metal and completion of the metal layer, passivation layer and back-side process.

[0082] For example, the dielectric layer 40 can be formed using a material with a high k dielectric constant. Examples include alumina (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), zirconium oxide (ZrO₂), tantalum oxide (Ta₂O₅), titanium oxide (TiO₂), or strontium titanium oxide (SrTiO₃). In the above embodiments, an unexpected technical effect of this application is:

[0083] Based on the planar gate cell of SiC MOSFET, a trench gate structure is added along the OZ direction, realizing the three-dimensional integration of planar and trench channels. Through process control, the thickness of SiC between trenches is shortened, and the thickness of the SiC region between trenches is reduced, causing a Fin effect at the (11-20) crystal plane of the trench sidewalls. Taking advantage of the higher mobility of the (11-20) crystal plane channel, the mobility of the trench channel is increased from 120 cm⁻¹. 2 / V·s~200cm 2 / V·s increased to 900cm 2 / V·s~1000cm 2 The voltage / V·s increases exponentially, further reducing the on-resistance R. on .

[0084] With the same chip area, the current density of the device is greatly improved, providing a key technical path for further reducing chip size, improving wafer utilization and economic benefits under the same performance requirements.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A SiC MOSFET structure, characterized in that, include: A substrate, wherein the substrate includes a first type of well region extending into the substrate via a first surface of the substrate; the well region includes second type of source regions spaced apart along a first direction and extending along a second direction; The second type of doped pillar is located in the well region between adjacent source regions and extends along a third direction and through the well region, and extends along the second direction; the first width of the doped pillar is smaller than the first width of the well region between adjacent source regions; Multiple trenches extend along the third direction, with their bottom surfaces higher than the bottom surface of the well region; the multiple trenches extend along a first direction and are spaced apart along a second direction. A gate, located on the top surface of the well region between adjacent source regions and the doped pillars, includes a trench gate located within the plurality of trenches; wherein, by adjusting the epitaxial layer thickness between the trench gates, a portion of the doped pillars located between adjacent trenches constitutes a fin-shaped channel region; A first type of shielding area is provided at the bottom of the trench, the second width of the shielding area is smaller than the second width of the gate, and the bottom surface is higher than the bottom surface of the well region; The first direction, the second direction, and the third direction are perpendicular to each other; the first type of conductivity is opposite to the second type of conductivity; the first width is used to characterize the dimension along the first direction; the second width is used to characterize the dimension along the second direction.

2. The SiC MOSFET structure according to claim 1, characterized in that, The sidewalls of the trench gate are (11-20) crystal planes; The spacing between adjacent trench grids along the second direction ranges from 0.03 μm to 1 μm.

3. The SiC MOSFET structure according to claim 2, characterized in that, The depth of the various trenches ranges from 0.5 μm to 2 μm.

4. The SiC MOSFET structure according to claim 3, characterized in that, The top surface of the substrate includes a gate oxide layer and a gate conductive layer arranged in a direction opposite to the third direction; The orthogonal projection of the gate conductive layer on the first surface is located on the top surface of the well region between the adjacent source regions and the doped pillar, and together with the gate oxide layer directly below, it forms the gate.

5. The SiC MOSFET structure according to claim 4, characterized in that, A dielectric layer is disposed on the outer surface of the gate; The first width of the gate oxide layer is greater than the first width of the gate conductive layer, and the width of the dielectric layer is the same as the first width of the gate oxide layer, such that the orthographic projection of a portion of the gate oxide layer and the dielectric layer on the first surface is located within a portion of the top surface of the source region and the trench.

6. The SiC MOSFET structure according to claim 5, characterized in that, The substrate includes a second type of current spreading layer located directly below the well region; The doped pillar extends along the third direction into the current spreading layer.

7. The SiC MOSFET structure according to claim 5, characterized in that, A source metal is disposed between adjacent dielectric layers; the bottom surface of the source metal is located within the top surface of the source region.

8. The SiC MOSFET structure according to any one of claims 3-7, characterized in that, The spacing between adjacent shielding zones is the same; The second width of each of the shielding zones is the same; The second width of each of the aforementioned trench gates is the same.

9. A method for fabricating a SiC MOSFET structure, characterized in that, include: A substrate is provided; the substrate includes a first type of well region extending into the substrate via a first surface of the substrate; the well region includes a second type of source region spaced apart along a first direction and extending along a second direction; A second type of doped pillar is formed in a well region between adjacent source regions, extending along the second direction, extending along the third direction and penetrating the well region; the first width of the doped pillar is smaller than the first width of the well region between adjacent source regions; A plurality of trenches are formed on the substrate, extending along the third direction, with their bottom surfaces higher than the bottom surfaces of the well region; The plurality of grooves extend along a first direction and are spaced apart along a second direction; A gate is formed on the top surface of the well region and the doped pillar between adjacent source regions; the gate includes a trench gate located within the plurality of trenches; wherein, by adjusting the epitaxial layer thickness between the trench gates, a portion of the doped pillar located between adjacent trenches constitutes a fin-shaped channel region; a first type of shielding region is provided at the bottom of the trench, the second width of the shielding region is smaller than the second width of the gate, and the bottom surface is higher than the bottom surface of the well region; Wherein, the first direction, the second direction, and the third direction are perpendicular to each other; the first type of conductivity is opposite to the second type of conductivity; the first width is used to characterize the dimension along the first direction; and the second width is used to characterize the dimension along the second direction.

10. The preparation method according to claim 9, characterized in that, The sidewalls of the trench gate are (11-20) crystal planes; After the plurality of trenches are formed, an ion implantation process is performed on the bottom of the plurality of trenches to form a first type of shielding area; The spacing between adjacent trench grids along the second direction ranges from 0.03 μm to 1 μm; The depth of the various trenches ranges from 0.5 μm to 2 μm.

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