Wafer-level heterogeneous integration method and structure of III-V group semiconductor wafer and CMOS (complementary metal oxide semiconductor) wafer
By using a wafer-level heterogeneous integration method for III-V group semiconductor wafers and CMOS wafers with high-entropy alloys as bonding layers at low temperatures, the bonding stress and warpage problems caused by the mismatch of thermal expansion coefficients are solved, achieving efficient and reliable electrical interconnection and extended device life.
Patent Information
- Application Number
- CN202511921817.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-18
- Publication Date
- 2026-03-06
AI Technical Summary
III-V semiconductor wafers and CMOS wafers suffer from bonding stress, warpage, and reliability issues due to the mismatch in their coefficients of thermal expansion. Existing MBE technology is also expensive and difficult to integrate.
Using high-entropy alloys as bonding layers, III-V semiconductor wafers and CMOS wafers are bonded at low temperatures. By preparing first and second high-entropy alloy thin films and forming bonding layers at low temperatures, combined with magnetron sputtering deposition and chemical mechanical polishing, wafer-level heterogeneous integration is achieved.
It effectively releases internal stress caused by thermal expansion coefficient mismatch, provides robust and reliable electrical interconnection, extends device life, and reduces the risk of mechanical stress during processing and use.
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Figure CN121619983A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a wafer-level heterogeneous integration method and structure for III-V group semiconductor wafers and CMOS wafers. Background Technology
[0002] The mismatch in thermal expansion coefficients between III-V semiconductor materials and silicon-based CMOS can lead to bonding stress, warpage, and reliability issues. Furthermore, conventional bonding processes are highly sensitive to thermal budgets and can easily damage the performance of precision transistors in CMOS circuits.
[0003] Existing solutions include developing MBE (molecular beam epitaxy) technology to grow III-V materials on CMOS, but MBE technology is costly and complex to control at the process level, lacks mature and easily integrated mass production processes, and is not easy to integrate into existing semiconductor production lines.
[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a wafer-level heterogeneous integration method and structure for III-V semiconductor wafers and CMOS wafers. Summary of the Invention
[0005] The purpose of this invention is to provide a wafer-level heterogeneous integration method and structure for III-V semiconductor wafers and CMOS wafers, which can solve the bonding stress, warpage and reliability problems caused by the mismatch of thermal expansion coefficients between III-V materials and silicon-based CMOS by using high-entropy alloys as bonding layers.
[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:
[0007] A wafer-level heterogeneous integration method for III-V group semiconductor wafers and CMOS wafers includes:
[0008] A III-V wafer is provided, a first dielectric layer is prepared on the surface of the III-V wafer, and a first high-entropy alloy thin film is prepared on the first dielectric layer;
[0009] A CMOS wafer is provided, a second dielectric layer is prepared on the surface of the CMOS wafer, and a second high-entropy alloy thin film is prepared on the second dielectric layer;
[0010] The III-V wafer and the CMOS wafer are aligned and laminated, and the first high-entropy alloy film and the second high-entropy alloy film are bonded together in a low-temperature environment to form a bonding layer.
[0011] In one or more embodiments of the present invention, the low-temperature environment includes: gradually increasing the temperature from 77K liquid nitrogen temperature to a first temperature, wherein the first temperature is 150~200°C.
[0012] In one or more embodiments of the present invention, the first high-entropy alloy thin film, the second high-entropy alloy thin film, and the interconnect layer comprise FeMnCoCrN-based high-entropy alloys;
[0013] The first dielectric layer and the second dielectric layer comprise silicon dioxide.
[0014] In one or more embodiments of the present invention, the thickness of the first high-entropy alloy film is 50~200nm;
[0015] The thickness of the second high-entropy alloy film is 50~200nm.
[0016] In one or more embodiments of the present invention, the CMOS wafer includes a silicon-based CMOS readout integrated circuit.
[0017] In one or more embodiments of the present invention, the wafer-level heterogeneous integration method further includes:
[0018] Before preparing the first high-entropy alloy thin film on the first dielectric layer, the surface of the first dielectric layer is subjected to chemical mechanical polishing treatment;
[0019] Before preparing the second high-entropy alloy thin film on the second dielectric layer, the surface of the second dielectric layer is subjected to chemical mechanical polishing.
[0020] In one or more embodiments of the present invention, a first high-entropy alloy thin film and / or a second high-entropy alloy thin film are prepared by magnetron sputtering deposition.
[0021] In one or more embodiments of the present invention, the CMOS wafer includes a plurality of optoelectronic devices, the electrodes of the optoelectronic devices are located on the surface of the CMOS wafer, and the wafer-level heterogeneous integration method further includes:
[0022] Etching vias to form windows exposing the electrodes, wherein the vias penetrate the III-V wafer, the first dielectric layer, the bonding layer, and the second dielectric layer;
[0023] A passivation layer is prepared, which covers the sidewall of the via.
[0024] An interconnect layer is fabricated to achieve electrical interconnection, the interconnect layer covering the passivation layer and the electrode, and extending to a portion of the surface of the III-V wafer.
[0025] In one or more embodiments of the present invention, the III-V wafer includes a substrate located away from the first dielectric layer, and the wafer-level heterogeneous integration method further includes removing the substrate before etching vias.
[0026] In one or more embodiments of the present invention, after etching the via, a passivation layer is prepared on the inner wall of the via, the passivation layer does not cover the CMOS wafer surface located at the bottom of the via, and the interconnect layer covers the passivation layer.
[0027] In one or more embodiments of the present invention, the wafer-level heterogeneous integration method further includes:
[0028] An antireflection film is prepared on the surface of the interconnect layer, the antireflection film filling the via and extending to the surface of the III-V wafer.
[0029] Another aspect of the present invention provides a wafer-level heterogeneous integration structure for a III-V group semiconductor wafer and a CMOS wafer, the wafer-level heterogeneous integration structure being fabricated based on a wafer-level heterogeneous integration method for a II-V group semiconductor wafer and a CMOS wafer.
[0030] Compared with the prior art, the wafer-level heterogeneous integration method and structure of the III-V semiconductor wafer and CMOS wafer of the present invention, wherein the first high-entropy alloy thin film and the second high-entropy alloy thin film are bonded to form a bonding layer in a low-temperature environment, effectively releasing the internal stress caused by the mismatch of thermal expansion coefficients. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a flowchart of a wafer-level heterogeneous integration method in one embodiment of the present invention;
[0033] Figure 2 This is a schematic diagram of the structure of a III-V wafer in one embodiment of the present invention;
[0034] Figure 3 This is a schematic diagram of the structure of a III-V wafer, a first dielectric layer, and a first high-entropy alloy thin film in one embodiment of the present invention;
[0035] Figure 4 This is a schematic diagram of the structure of a CMOS wafer in one embodiment of the present invention;
[0036] Figure 5 This is a schematic diagram of the structure of a CMOS wafer, a second dielectric layer, and a second high-entropy alloy thin film in one embodiment of the present invention;
[0037] Figure 6This is a schematic diagram of the structure after bonding a III-V wafer to a CMOS wafer in one embodiment of the present invention;
[0038] Figure 7 This is a schematic diagram of another structure after bonding a III-V wafer to a CMOS wafer in one embodiment of the present invention;
[0039] Figure 8 This is a schematic diagram of the wafer-level heterogeneous integration method after the first etching in one embodiment of the present invention;
[0040] Figure 9 This is a schematic diagram of the wafer-level heterogeneous integration method after the second etching in one embodiment of the present invention;
[0041] Figure 10 This is a schematic diagram of the preparation of the passivation layer in one embodiment of the present invention;
[0042] Figure 11 This is a schematic diagram of the fabrication of an interconnect layer in one embodiment of the present invention;
[0043] Figure 12 This is a schematic diagram of a wafer-level heterogeneous integration structure in one embodiment of the present invention. Detailed Implementation
[0044] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.
[0045] As mentioned in the background section, III-V semiconductor materials typically possess excellent optoelectronic properties and high-frequency performance, while silicon materials offer good integrated circuit compatibility. Therefore, combining the two helps to realize high-efficiency heterogeneous integrated circuits. However, direct bonding of III-V semiconductor wafers to silicon wafers also presents certain technical challenges, mainly manifested in material mismatch, significant differences in lattice constants, and stress, dislocations, and crystal defects, all of which affect device performance. Furthermore, the difference in their coefficients of thermal expansion can lead to thermal stress during high-temperature processing, impacting packaging reliability.
[0046] Combination Figure 1 As shown, in order to solve the above-mentioned technical problems, this disclosure proposes a wafer-level heterogeneous integration method for III-V group semiconductor wafers and CMOS wafers, including:
[0047] S1, providing a III-V wafer, preparing a first dielectric layer on the surface of the III-V wafer, and preparing a first high-entropy alloy thin film on the first dielectric layer;
[0048] S2, providing a CMOS wafer, fabricating a second dielectric layer on the surface of the CMOS wafer, and fabricating a second high-entropy alloy thin film on the second dielectric layer;
[0049] S3, the III-V wafer and the CMOS wafer are aligned and pressed together, and the first high-entropy alloy film and the second high-entropy alloy film are bonded together in a low-temperature environment to form a bonding layer.
[0050] Understandably, high-entropy alloy materials exhibit strong plasticity matching ability at low temperatures, causing them to undergo micro-plastic deformation under bonding pressure, perfectly filling the microscopic unevenness of the bonding surface, achieving ultra-high strength atomic-level bonding, and effectively releasing internal stress caused by the mismatch of thermal expansion coefficients through plastic deformation.
[0051] Furthermore, the CMOS wafer incorporates several optoelectronic devices, with the electrodes of these devices located on the surface of the CMOS wafer. Wafer-level heterogeneous integration methods also include:
[0052] S4, etch vias to form windows that expose electrodes, wherein the vias penetrate the III-V wafer, the first dielectric layer, the bonding layer, and the second dielectric layer;
[0053] S5, Prepare a passivation layer that covers the sidewalls of the via.
[0054] S6, an interconnect layer is fabricated to achieve electrical interconnection. The interconnect layer covers the passivation layer and the electrode, and extends to a portion of the surface of the III-V wafer.
[0055] This disclosure uses high-entropy alloys instead of traditional tungsten or copper as filler materials for contact plugs and interconnects. It utilizes the excellent low-temperature conductivity of high-entropy alloys to provide more robust and reliable electrical interconnects than traditional materials. This reduces problems such as voids and cracks caused by thermal mismatch in subsequent processes or temperature cycles, and can withstand the mechanical stress of wafer-level heterogeneous integrated structures in subsequent processing and use, thus extending device life.
[0056] In one embodiment, a certain pressure is applied to the III-V wafer and the CMOS wafer during the bonding process, and the bonding is set to a controllable low-temperature environment.
[0057] Specifically, the controllable low-temperature environment includes a slow and gradual increase in temperature from 77K liquid nitrogen to a relatively low first temperature, wherein the first temperature range is 150~200°C. The high-entropy alloy exhibits excellent low-temperature conductivity, and both the first and second high-entropy alloy films possess high strength and ductility, enabling them to withstand mechanical stresses during processing and use.
[0058] In one embodiment, the first high-entropy alloy thin film, the second high-entropy alloy thin film, and the interconnect layer all comprise FeMnCoCrN-based high-entropy alloys.
[0059] High-entropy alloys (HEAs) are alloys composed of five or more metals in equal or approximately equal amounts. FeMnCoCrN-based high-entropy alloys are an important branch of high-entropy alloys, developed from the classic FeMnCoCr system, by introducing nitrogen (N) as a key interstitial atom, significantly altering the alloy's microstructure and properties. For example, Fe... 49 Mn 30 Co 10 Cr 10 N1 exhibits excellent mechanical properties at both 293 K and 77 K, with yield strength and ultimate tensile strength reaching 1078 MPa and 1630 MPa at low temperatures, respectively, and uniform elongation of 33.5%.
[0060] In one embodiment, a first high-entropy alloy thin film and a second high-entropy alloy thin film are prepared by magnetron sputtering deposition, both having a thickness range of 50~200 nm.
[0061] Understandably, magnetron sputtering deposition (PVD) is well known in the prior art, so its principles will not be described in detail here.
[0062] In one embodiment, the CMOS wafer includes a silicon-based CMOS readout integrated circuit. The silicon-based CMOS readout integrated circuit includes a plurality of spaced-apart optoelectronic devices, that is, the surface of the CMOS wafer facing the second dielectric layer has a plurality of electrodes (including positive or negative electrodes), and the etching positions of the vias correspond to the positions of the electrodes.
[0063] In one embodiment, the first dielectric layer and the second dielectric layer comprise silicon dioxide.
[0064] The wafer-level heterogeneous integration method also includes treating the surfaces of the first and second dielectric layers to atomic-level flatness to prepare for high-quality bonding, specifically:
[0065] Before preparing the first high-entropy alloy thin film on the first dielectric layer, the surface of the first dielectric layer is subjected to chemical mechanical polishing treatment. Before preparing the second high-entropy alloy thin film on the second dielectric layer, the surface of the second dielectric layer is subjected to chemical mechanical polishing treatment.
[0066] In one embodiment, the III-V wafer includes a substrate. It is understood that the substrate is located away from the first dielectric layer; therefore, the wafer-level heterogeneous integration method further includes removing the substrate before etching vias.
[0067] Furthermore, the process of preparing the passivation layer specifically includes:
[0068] A passivation layer is prepared on the inner wall of the via, which covers the inner wall of the via and the CMOS wafer surface (i.e. the electrode surface of the optoelectronic device in the CMOS wafer) located at the bottom of the via.
[0069] By etching away the passivation layer at the bottom of the via, a window is formed that exposes the optoelectronic device, ensuring that the interconnect layer and the electrodes of the optoelectronic device are electrically connected.
[0070] The wafer-level heterogeneous integration method also includes: preparing an antireflection film on the surface of the interconnect layer, wherein the antireflection film fills the vias and extends to the entire surface of the III-V wafer.
[0071] Understandably, after the interconnect layer is fabricated, the vias are not completely filled. The vias are filled with an anti-reflection film and the entire III-V wafer surface is covered to complete the device fabrication.
[0072] Antireflective coatings include silicon oxide or silicon nitride.
[0073] Furthermore, this disclosure also provides a wafer-level heterogeneous integration structure of a III-V semiconductor wafer and a CMOS wafer, which is prepared based on the above-described wafer-level heterogeneous integration method of a II-V semiconductor wafer and a CMOS wafer.
[0074] The present invention will be further described below with reference to specific embodiments.
[0075] Example 1:
[0076] Combination Figures 2-12 As shown, the wafer-level heterogeneous integration method for III-V group semiconductor wafers and CMOS wafers in this embodiment specifically includes:
[0077] S101, a III-V wafer 10 is provided, a first dielectric layer 14 is prepared on the surface of the III-V wafer 10, and after the surface of the first dielectric layer 14 is chemically and mechanically polished, a first high-entropy alloy thin film 15 is prepared on the first dielectric layer 14 by magnetron sputtering deposition, wherein the first high-entropy alloy thin film 15 includes a FeMnCoCrN-based high-entropy alloy, and the first dielectric layer 14 includes silicon dioxide;
[0078] Combination Figure 2 and Figure 3 As shown, the III-V wafer includes a substrate 11, an etch stop layer 12, and a device layer 13 stacked sequentially. In this embodiment, the III-V wafer 10 uses III-V group semiconductor materials such as gallium arsenide (GaAs) and indium phosphide (InP).
[0079] In this embodiment, the thickness of the first high-entropy alloy film 15 is 100 nm.
[0080] It is understood that III-V semiconductor wafers are well known in the prior art. For III-V semiconductor wafers with different functions, there are many possible layer structures. Other layer structures may also be set between the substrate, etch stop layer and device layer. These will not be described in detail here. This embodiment only illustrates the more common or necessary layer structures. Any known or unknown III-V semiconductor wafer can be used here without restriction.
[0081] S102, a CMOS wafer 20 is provided, a second dielectric layer 22 is prepared on the surface of the CMOS wafer, and after the surface of the second dielectric layer 22 is chemically mechanically polished, a second high-entropy alloy thin film 23 is prepared on the second dielectric layer 22 by magnetron sputtering deposition. The first high-entropy alloy thin film 15 includes a FeMnCoCrN-based high-entropy alloy, and the first dielectric layer 14 includes silicon dioxide.
[0082] like Figure 4 As shown, the CMOS wafer 20 in this embodiment is a silicon-based CMOS readout integrated circuit, which has a plurality of spaced-apart optoelectronic devices 21. It can be understood that the optoelectronic devices 21 have electrodes 211, which are located on the surface of the CMOS wafer.
[0083] like Figure 5 As shown, the second dielectric layer 22 covers the surface of the CMOS wafer (and also covers the electrode 211 of the optoelectronic device 21). In this embodiment, the thickness of the second high-entropy alloy thin film 23 is 100 nm.
[0084] S103 applies pressure to bond III-V wafers and CMOS wafers.
[0085] Combination Figure 6 As shown, the first high-entropy alloy film 15 and the second high-entropy alloy film 23 are aligned, and the ambient temperature is gradually and slowly increased from 77K liquid nitrogen temperature to 200°C. During the heating process, pressure is applied to the III-V wafer and the CMOS wafer for bonding. The first high-entropy alloy film 15 and the second high-entropy alloy film 23 are bonded in a low-temperature environment to form a bonding layer 30.
[0086] S104, Remove substrate 11 to expose device layer 13 of III-V wafer.
[0087] Combination Figure 7As shown, the etch stop layer 12 is a functional thin-film material used in semiconductor manufacturing processes. Its core function is to precisely control the etching depth during the etching process, protect the underlying sensitive structure, and prevent device damage or performance failure caused by over-etching. It is typically deposited above the device layer that needs protection (such as transistors, interconnects, sensitive thin films, etc.). When the etching process reaches this layer, due to the material's significantly different etching selectivity compared to the surrounding medium (i.e., stronger resistance to etching gases / liquids), the etching rate drops sharply or even stops, thus achieving precise control by stopping etching at the target depth. Based on the analysis, after removing the substrate, the etch stop layer 12 is also adaptively removed, thereby exposing the device layer 13.
[0088] S105, etch vias to form windows that expose electrode 211, wherein the vias penetrate the III-V wafer, the first dielectric layer 14, the bonding layer 30 and the second dielectric layer 22;
[0089] S105 specifically includes:
[0090] like Figure 8 As shown, the device mesa structure in the III-V wafer is first prepared by etching the device layer 13 for the first time. The etching position of the first etching corresponds to the position of the optoelectronic device 21 in the vertical direction in the CMOS wafer.
[0091] like Figure 9 As shown, the first dielectric layer 14, bonding layer 30 and second dielectric layer 22 are etched downwards along the position of the first etching to expose the electrode 211 of the optoelectronic device 21.
[0092] S106, prepare passivation layer 16, which covers the sidewall of the through hole.
[0093] Combination Figure 10 As shown, S106 specifically includes:
[0094] A passivation layer 16 is prepared on the inner wall of the via, and the passivation layer 16 covers the inner wall of the via and the CMOS wafer surface (i.e. part of the surface of electrode 211) located at the bottom of the via.
[0095] By etching away the passivation layer 16 at the bottom of the via, a window is formed that exposes the electrode 211, so that the subsequent interconnect layer can be electrically connected to the electrode 211 of the optoelectronic device 21.
[0096] It is understood that the materials and preparation methods of the passivation layer 16 are well known in the prior art and will not be described in detail here. Any known or unknown passivation layer 16 may be used without restriction.
[0097] S107, Prepare interconnect layer 17 to achieve electrical interconnection.
[0098] Combination Figure 11 As shown, interconnect layer 17 covers passivation layer 16 and extends to a portion of the surface of III-V wafer 10. In this embodiment, interconnect layer 17 comprises a FeMnCoCrN-based high-entropy alloy.
[0099] S108, an antireflection film 18 is prepared on the surface of interconnect layer 17.
[0100] Combination Figure 12 As shown, the antireflective film 18 fills the vias and extends to the surface of the III-V wafer 10. In this embodiment, the antireflective film 18 includes silicon oxide.
[0101] As can be seen from the above technical solutions, the present invention has the following beneficial effects:
[0102] The first high-entropy alloy film and the second high-entropy alloy film are bonded together in a low-temperature environment to form a bonding layer 30, which effectively releases the internal stress caused by the mismatch of thermal expansion coefficients.
[0103] By using high-entropy alloy materials as the electrical interconnect material for through holes, more reliable electrical interconnects are provided, extending device lifespan.
[0104] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0105] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A wafer-level heterogeneous integration method of a III-V semiconductor wafer and a CMOS wafer, characterized by, The wafer-level heterogeneous integration method comprises: providing a III-V wafer, preparing a first dielectric layer on the surface of the III-V wafer, and preparing a first high-entropy alloy thin film on the first dielectric layer; providing a CMOS wafer, preparing a second dielectric layer on the surface of the CMOS wafer, and preparing a second high-entropy alloy thin film on the second dielectric layer; aligning and pressing the III-V wafer and the CMOS wafer, and bonding the first high-entropy alloy thin film and the second high-entropy alloy thin film to form a bonding layer in a low-temperature environment.
2. The wafer-level hetero-integration method of a III-V semiconductor wafer and a CMOS wafer of claim 1, wherein, The low-temperature environment comprises gradually increasing the temperature from 77K liquid nitrogen temperature to a first temperature, wherein the first temperature is 150-200°C.
3. The wafer level hetero integration method of a group III-V semiconductor wafer with a CMOS wafer according to claim 1, wherein, The first high-entropy alloy thin film and / or the second high-entropy alloy thin film comprises a FeMnCoCrN-based high-entropy alloy; and / or, The first dielectric layer and / or the second dielectric layer comprises silicon dioxide.
4. The wafer-level hetero-integration method of a III-V semiconductor wafer and a CMOS wafer of claim 1, wherein, The thickness of the first high-entropy alloy thin film is 50-200nm; and / or, The thickness of the second high-entropy alloy thin film is 50-200nm.
5. The wafer level hetero integration method of a group III-V semiconductor wafer with a CMOS wafer according to claim 1, wherein, The CMOS wafer comprises a silicon-based CMOS readout integrated circuit.
6. The wafer level hetero integration method of a group III-V semiconductor wafer with a CMOS wafer according to claim 1, wherein, The wafer-level heterogeneous integration method further comprises: performing chemical mechanical polishing treatment on the surface of the first dielectric layer before preparing the first high-entropy alloy thin film on the first dielectric layer; performing chemical mechanical polishing treatment on the surface of the second dielectric layer before preparing the second high-entropy alloy thin film on the second dielectric layer.
7. The wafer level hetero integration method of a group III-V semiconductor wafer with a CMOS wafer according to claim 1, wherein, The first high-entropy alloy thin film and / or the second high-entropy alloy thin film is prepared by a magnetron sputtering deposition method.
8. The wafer level hetero integration method of a group III-V semiconductor wafer with a CMOS wafer according to claim 1, wherein, The CMOS wafer has a plurality of optoelectronic devices, and electrodes of the optoelectronic devices are located on the surface of the CMOS wafer, and the wafer-level heterogeneous integration method further comprises: etching a through hole to form a window exposing the electrodes, wherein the through hole penetrates the III-V wafer, the first dielectric layer, the bonding layer, and the second dielectric layer; preparing a passivation layer covering the sidewall of the through hole, preparing an interconnection layer to achieve electrical interconnection, wherein the interconnection layer covers the passivation layer and the electrodes and extends to part of the surface of the III-V wafer, and the interconnection layer comprises a high-entropy alloy.
9. The wafer-level hetero-integration method of a III-V semiconductor wafer and a CMOS wafer of claim 8, wherein, The III-V wafer has a substrate away from the first dielectric layer, and the wafer-level heterogeneous integration method further comprises removing the substrate before etching the through hole.
10. The wafer-level hetero-integration method of a III-V semiconductor wafer and a CMOS wafer of claim 8, wherein, The wafer-level heterogeneous integration method further comprises: preparing an anti-reflection film on the surface of the interconnection layer, wherein the anti-reflection film fills the through hole and extends to the surface of the III-V wafer.
11. The wafer level hetero integration method of a group III-V semiconductor wafer and a CMOS wafer of claim 8, wherein, The interconnection layer comprises a FeMnCoCrN-based high-entropy alloy.
12. A wafer-level heterogeneous integrated structure of a III-V semiconductor wafer and a CMOS wafer, characterized in that, The wafer-level heterogeneous integration structure is prepared based on the wafer-level heterogeneous integration method of the group II-V semiconductor wafer and the CMOS wafer according to any one of claims 1-11.