Surface mounting method suitable for chip-to-wafer hybrid bonding

Abstract

The invention relates to a surface mounting method suitable for hybrid bonding of a chip to a wafer, belongs to the technical field of semiconductor packaging, and solves the problem of large surface mounting error of an existing surface mounting method. The method comprises the following steps: step (1), visible light pre-alignment: placing a chip above a wafer, upwards and downwards identifying alignment marks on the surfaces of the chip and the wafer respectively through visible light between the chip and the wafer, realizing pre-alignment of the chip and the wafer, and removing the visible light after pre-alignment; and (2) infrared light fine alignment: moving the pre-aligned chip to the wafer, upwards and accurately identifying alignment marks on the chip and the surface of the wafer through infrared light below the wafer, and accurately aligning the chip and the wafer in the process of moving the chip to the wafer. Through a method of combining visible light pre-alignment and infrared light fine alignment, movement deviation caused in the mounting process after visible light alignment is avoided, and the mounting precision of bonding from a chip to a wafer is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to a mounting method suitable for chip-to-wafer hybrid bonding. Background Technology

[0002] Chip-to-wafer (D2W) hybrid bonding is a novel bonding method that bonds diced chips onto a wafer. This method can screen known good chips and freely mount chips of different types and sizes, offering high flexibility. It is considered an ideal solution for achieving high-density three-dimensional interconnect integration of chips in the future. In the D2W hybrid bonding process, alignment marks are first made on both the wafer and the diced chip, and then the marks on the chip and wafer are aligned and bonded.

[0003] In existing chip-to-wafer mounting methods, the mounting error between the chip and the wafer is relatively large. Summary of the Invention

[0004] Based on the above analysis, the embodiments of the present invention aim to provide a mounting method suitable for chip-to-wafer hybrid bonding, in order to solve the problem of large mounting errors in existing mounting methods.

[0005] On one hand, embodiments of the present invention provide a mounting method suitable for chip-to-wafer hybrid bonding, the method comprising:

[0006] Step (1), visible light pre-alignment: Place the chip above the wafer, and use visible light located between the chip and the wafer to identify the alignment marks on the surface of the chip and the wafer by looking up and down respectively, so as to achieve pre-alignment of the chip and the wafer. After pre-alignment, remove the visible light.

[0007] Step (2), infrared fine alignment: The pre-aligned chip moves toward the wafer, and the alignment marks on the chip and wafer surface are accurately identified by infrared light located below the wafer. During the process of the chip moving toward the wafer, the chip and wafer are precisely aligned.

[0008] Preferably, step (2) includes: during the process of moving the chip to the wafer, infrared light is used to track and correct the alignment position of the chip and the wafer multiple times.

[0009] Preferably, step (2) includes: the chip travels 0.2-10cm to the wafer and infrared light is used for fine alignment.

[0010] Preferably, the distance the chip travels towards the wafer in each subsequent movement is 1-3 cm shorter than the distance traveled in the previous movement.

[0011] Preferably, the wavelength of the infrared light is 700-1000nm.

[0012] Preferably, the diameter of the infrared light spot is 10-800 micrometers.

[0013] Preferably, the distance between the infrared light source and the wafer is 0.5-10 cm.

[0014] Preferably, the chip travels towards the wafer at a speed of 0.1-10 cm / s.

[0015] Preferably, in step (1), the distance between the chip and the wafer is 1-30cm.

[0016] Preferably, the chip has a size of 1mm×1mm-40mm×40mm.

[0017] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0018] 1. Since metal lines exist within the wafer, infrared light cannot penetrate them. Therefore, this invention first pre-aligns the alignment marks on the chip and wafer using visible light. After pre-alignment, the projections of the upper and lower alignment marks on the horizontal plane will partially overlap. Then, the chip is moved towards the wafer. During this movement, infrared light is used to accurately identify the alignment marks on the chip and wafer surfaces. By combining visible light pre-alignment with infrared light fine alignment, the method avoids the movement deviation caused by visible light alignment during the mounting process, improving the mounting accuracy of chip-to-wafer bonding. The mounting alignment accuracy range is 50-350nm.

[0019] 2. In this invention, during the process of moving the chip to the wafer, infrared light is used to track and correct the alignment position of the chip and the wafer multiple times. That is, the chip is aligned and corrected with infrared light once every time it moves a certain distance to the wafer. Through multiple alignments during the movement, the mounting accuracy is further improved.

[0020] 3. The mounting efficiency of this invention is 1000-3000 pieces / minute. Although this invention adds an infrared light alignment process on the basis of visible light alignment, its efficiency is not significantly affected compared with visible light alone.

[0021] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0022] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0023] Figure 1 This is a flowchart of the wafer-to-chip mounting method for Comparative Example 1.

[0024] Figure 2 This is a flowchart of the wafer-to-chip mounting method of the present invention;

[0025] Figure 3 This is a flowchart of the wafer activation and cleaning process;

[0026] Figure 4 This is a flowchart of the chip activation and cleaning process.

[0027] Figure label:

[0028] 1-Chip; 2-Wafer; 3-Alignment mark; 4-Visible light source; 5-Infrared light source; 6-Vacuum tip; 7-Plasma; 8-Cleaning solution; 9-Blue film. Detailed Implementation

[0029] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0030] The inventors found that the method of directly bonding the chip and wafer by simply using visible light to identify the alignment marks of the chip and wafer by looking up and down, and then removing the visible light, results in a large bonding error. The main reasons include: (1) Due to the high flatness of the wafer surface, the surface is mirror-like. Scanning the alignment marks of the chip above and the wafer below with visible light is very easy to cause reflection, resulting in errors in identification accuracy and alignment accuracy; (2) During the vertical downward movement of the chip after visible light alignment, the movement trajectory is uncontrollable, resulting in bonding accuracy that is much lower than alignment accuracy; (3) During the chip bonding process, the chip shape is affected by the control of the pins or pressure difference, which further increases the bonding error.

[0031] Therefore, the present invention provides a mounting method suitable for chip-to-wafer hybrid bonding, such as... Figure 2 As shown, the method includes:

[0032] Step (1), visible light pre-alignment: Place chip 1 above wafer 2, and use visible light located between chip 1 and wafer 2 to identify alignment marks 3 on the surfaces of chip 1 and wafer 2 by looking up and down respectively, to achieve pre-alignment of chip 1 and wafer 2. After pre-alignment, remove the visible light.

[0033] Step (2), infrared fine alignment: After pre-alignment, chip 1 moves to wafer 2, and the alignment marks 3 on the surface of chip 1 and wafer 2 are accurately identified by infrared light located below wafer 2. During the process of chip 1 moving to wafer 2, chip 1 and wafer 2 are precisely aligned.

[0034] Compared to existing technologies, this invention first pre-aligns the alignment marks on the chip and wafer using visible light. After pre-alignment, the projections of the upper and lower alignment marks on the horizontal plane will partially overlap. Then, the chip is moved towards the wafer. During the movement, infrared light is used to accurately identify the alignment marks on the chip and wafer surfaces. By combining visible light pre-alignment and infrared light fine alignment, the method avoids the movement deviation caused by visible light alignment during the mounting process, thus improving the mounting accuracy of chip-to-wafer bonding.

[0035] For example, in step (1), the spacing between the chip and the wafer is 1-30 cm.

[0036] For example, the size of the chip 1 is 1mm×1mm-40mm×40mm. For example, 5mm×5mm, 10mm×10mm, 15mm×15mm, 20mm×20mm, 25mm×25mm, 30mm×30mm, 35mm×35mm.

[0037] For example, the thickness of chip 1 is 30-800 micrometers.

[0038] For example, wafer 2 has a size of 4-12 inches.

[0039] For example, the thickness of wafer 2 is 0.2-20 mm.

[0040] It should be noted that wafer 2 can be an unbonded wafer or a wafer sample that has achieved one or more layers of W2W / D2W bonding.

[0041] For example, the diameter of the visible light spot is 1-2000 micrometers.

[0042] For example, the wavelength of visible light is 400-760nm.

[0043] For example, the pattern of alignment mark 3 is one or more combinations of triangle, circle, ring, cross, and square.

[0044] It should be noted that the alignment mark 3 has no metal wiring layer inside, which is beneficial for infrared light recognition.

[0045] For example, the side length of alignment mark 3 is 2-200 micrometers.

[0046] For example, visible light can be provided by visible light source 4. After visible light pre-alignment is completed, visible light source 4 is removed.

[0047] In a preferred embodiment, step (2) includes: during the movement of chip 1 toward wafer 2, infrared light is used to track and correct the alignment position of chip 1 and wafer 2 multiple times.

[0048] Specifically, chip 1 moves a certain distance towards wafer 2 and is aligned and corrected once using infrared light. During the movement, alignment and correction are performed multiple times to further improve the mounting accuracy.

[0049] For example, step (2) includes: the chip 1 moves 0.2-10cm to the wafer 2 and performs a fine alignment with infrared light once.

[0050] For example, the infrared light is finely aligned 1-5 times, such as 2 times, 3 times, or 4 times.

[0051] For example, the distance that chip 1 travels towards wafer 2 in a subsequent step is 1-3 cm shorter than the distance traveled in the previous step. This helps to further improve alignment accuracy.

[0052] For example, the wavelength of the infrared light is 700-1000nm. Examples include 750nm, 800nm, 850nm, 900nm, and 950nm. Infrared light of this wavelength has good penetrability, allowing it to pass through the wafer from the back side to identify alignment marks on the surface.

[0053] The infrared light spot should cover the alignment mark; for example, the diameter of the infrared light spot is 10-800 micrometers.

[0054] For example, infrared light can be provided by infrared light source 5. After visible light pre-alignment, the visible light source is removed, and infrared light source 5 is moved to below wafer 2. During the process of the chip moving to the wafer, infrared light source 5 emits infrared light upward. After the infrared light penetrates the wafer, it identifies the alignment marks 3 on the surface of chip 1 and wafer 2, and performs precise infrared light alignment.

[0055] It should be noted that the movement of chip 1 can be controlled by a robotic arm, which fixes chip 1 onto the suction head 6 of the robotic arm.

[0056] It should be noted that both the visible light source 4 and the infrared light source 5 of the present invention are equipped with cameras. During the visible light pre-alignment and infrared light precise alignment process, the cameras take pictures of the alignment marks before each alignment step and feed the pictures back to the control system. The control system controls the robotic arm to move the chip based on the picture feedback results, thereby improving the alignment accuracy between the chip 1 and the wafer 2.

[0057] For example, the distance between the infrared light source and the wafer 2 is 0.5-10cm. Examples include 1cm, 2cm, 3cm, 4cm, 5cm, 6cm, 7cm, 8cm, and 9cm. This distance is a safe distance between the lens and the sample; if the distance is too far, the penetration effect will be reduced; if the distance is too close, there is a risk of collision damage.

[0058] For example, the traveling speed of the chip 1 towards the wafer 2 is 0.1-10 cm / s. For example, 1 cm / s, 2 cm / s, 3 cm / s, 4 cm / s, 5 cm / s, 6 cm / s, 7 cm / s, 8 cm / s, and 9 cm / s.

[0059] For example, the speed at which chip 1 travels towards wafer 2 in subsequent movements is less than the speed at which it travels in previous movements, which helps to further improve alignment accuracy.

[0060] For example, the ambient temperature for chip-to-wafer mounting is within the range of 25°C ± 0.2°C.

[0061] For example, wafer 2 is activated and cleaned before chip 1 and wafer 2 are mounted.

[0062] Specifically, such as Figure 3 As shown, the activation and cleaning of wafer 2 includes: chemical mechanical polishing (CMP) of the wafer surface, after which the surface roughness is less than 0.5 nm; then plasma activation of the wafer surface, using one or more combinations of nitrogen, argon or oxygen, after which the surface contact angle is less than 5°; then cleaning of the wafer surface, using one or more combinations of deionized water, citric acid, and SC1 as cleaning solution 8, and then drying the surface after cleaning.

[0063] For example, chip 1 is activated and cleaned before chip 1 and wafer 2 are mounted.

[0064] Specifically, such as Figure 4 As shown, the activation and cleaning of chip 1 includes: cutting the CMP wafer into small chips 1, adhering chip 1 to the blue film 9 with a surface roughness of less than 0.5 nm; performing plasma activation on chip 1 on the blue film 9, using one or more combinations of nitrogen, argon or oxygen, with a surface contact angle of less than 5° after activation; and then cleaning chip 1, using one or more combinations of deionized water, citric acid, and SC1 as the cleaning solution 8, and then drying the surface after cleaning.

[0065] The following specific embodiments further illustrate the mounting method of the present invention applicable to chip-to-wafer hybrid bonding.

[0066] Example 1

[0067] This embodiment provides a mounting method suitable for chip-to-wafer hybrid bonding, including:

[0068] (1) Activation and cleaning of wafers: The wafer size is 12 inches and the wafer thickness is 775μm. The wafers are sequentially subjected to chemical mechanical polishing (CMP), plasma activation and cleaning processes. After CMP, the surface roughness is less than 0.5nm. Nitrogen gas is used for plasma activation. After activation, the surface contact angle is less than 5°. Deionized water is used for cleaning. After cleaning, the surface is spun dry.

[0069] (2) Chip activation and cleaning: The wafer size is 12 inches and the wafer thickness is 775μm. After CMP, the wafer is diced into small chips, which are then adhered to the diced blue film with a surface roughness of less than 0.5nm. The chips on the blue film undergo plasma activation and cleaning processes. Nitrogen gas is used for plasma activation, and the surface contact angle after activation is less than 5°. Deionized water is used for cleaning, and the surface is spun dry after cleaning.

[0070] (3) D2W Pickup and Pre-alignment: The processed chip and wafer are placed on their respective carriers, face up. During the chip-to-wafer (D2W) bonding process, the chip is first picked up from the blue film by a robotic arm, flipped, and then transferred to the top of the wafer. At this time, a visible light camera moves between the chip and the wafer, and identifies the alignment marks on the chip and wafer surfaces by looking up and down, respectively, to correct the chip position and achieve pre-alignment of the chip and wafer. The visible light spot diameter is 200 micrometers, the distance between the chip and the wafer is 10 cm, the chip size is 3 mm * 8 mm, the wafer size is 12 inches, the alignment mark is a square with a side length of 30 micrometers, and there is no metal wiring layer inside the alignment mark 3.

[0071] (4) D2W Infrared High-Precision Alignment and Mounting: After the chip and wafer are pre-aligned using visible light, the visible light camera is removed, and the chip begins to move downwards in preparation for mounting. This movement process is divided into three stages: the first stage involves moving 5cm followed by infrared alignment and correction at a speed of 5cm / s; the second stage involves moving another 4cm followed by infrared alignment and correction at a speed of 3cm / s; and the third stage involves moving 1cm to contact the wafer surface for alignment and mounting at a speed of 1cm / s. The wavelength of the infrared light is 808nm, the spot diameter is 50 micrometers, and the infrared camera is 3cm away from the bottom wafer. The infrared camera emits infrared light upwards, which penetrates the wafer and identifies the alignment marks 3 on the chip and wafer surface for precise infrared alignment.

[0072] (5) D2W Annealing: After visible light pre-alignment and infrared light high-precision alignment and mounting, the pre-bonding of the dielectric layer is achieved. The pre-bonded sample is placed in an annealing furnace for heating treatment and annealed at 300°C for 2 hours. After high-temperature annealing treatment, the chip and wafer achieve good bonding.

[0073] The alignment accuracy of the chips during wafer mounting is 100nm. The mounting efficiency is 2000 chips / minute.

[0074] Example 2

[0075] This embodiment provides a mounting method similar to Embodiment 1 for chip-to-wafer hybrid bonding, except that step (4) includes: after the chip and wafer are pre-aligned with visible light, the visible light camera is removed, and the chip begins to move downwards in preparation for mounting. This moving process is divided into four stages: the first stage involves moving 4cm and then performing infrared alignment and correction at a speed of 4cm / s; the second stage involves moving another 3cm and then performing infrared alignment and correction at a speed of 3cm / s; the third stage involves moving another 2cm and then performing infrared alignment and correction at a speed of 2cm / s; and the fourth stage involves moving 1cm to contact the wafer surface for alignment and mounting at a speed of 1cm / s. The wavelength of the infrared light is 808nm, the spot diameter is 50 micrometers, and the infrared camera is 3cm away from the bottom wafer.

[0076] The alignment accuracy of the chip when it is mounted onto the wafer is 80nm.

[0077] Example 3

[0078] This embodiment provides a mounting method similar to that of Embodiment 1 for chip-to-wafer hybrid bonding. The difference is that in step (4), after the chip and wafer are pre-aligned with visible light, the visible light camera is removed, and the chip begins to move downwards in preparation for mounting. This moving process is divided into two stages: in the first stage, the chip moves 5cm and then undergoes infrared alignment and correction at a speed of 5cm / s; in the second stage, the chip moves another 5cm to contact the wafer surface for alignment and mounting at a speed of 3cm / s.

[0079] The alignment accuracy of the chip when mounting it onto the wafer is 150nm.

[0080] Example 4

[0081] This embodiment provides a mounting method similar to that of Embodiment 1 for chip-to-wafer hybrid bonding, except that the moving speed of the chip to the wafer in the three stages is 5 cm / s.

[0082] The alignment accuracy of the chip when it is mounted onto the wafer is 180nm.

[0083] Example 5

[0084] This embodiment provides a mounting method similar to that of Embodiment 1 for chip-to-wafer hybrid bonding, except that the wavelength of the infrared light is 650nm.

[0085] The alignment accuracy of the chip when mounting it onto the wafer is 200nm.

[0086] Example 6

[0087] This embodiment provides a mounting method similar to that of Embodiment 1 for chip-to-wafer hybrid bonding, except that the wavelength of the infrared light is 1100nm.

[0088] The alignment accuracy of the chip when it is mounted onto the wafer is 180nm.

[0089] Example 7

[0090] This embodiment provides a mounting method similar to that of Embodiment 1 for chip-to-wafer hybrid bonding, except that the distance between the infrared light source and the wafer is 15 cm.

[0091] The alignment accuracy of the chip when it is mounted onto the wafer is 250nm.

[0092] Example 8

[0093] This embodiment provides a mounting method similar to Embodiment 1 for chip-to-wafer hybrid bonding, except that the moving speeds of the chip to the wafer in the three stages are 12cm / s, 11cm / s, and 10cm / s, respectively.

[0094] The alignment accuracy of the chip when mounting it onto the wafer is 300nm.

[0095] Comparative Example 1

[0096] This comparative example provides a mounting method suitable for chip-to-wafer hybrid bonding, such as... Figure 1 As shown, it includes:

[0097] (1) Activation and cleaning of wafers: The wafer size is 12 inches and the wafer thickness is 775μm. The wafers are sequentially subjected to chemical mechanical polishing (CMP), plasma activation and cleaning processes. After CMP, the surface roughness is less than 0.5nm. Nitrogen gas is used for plasma activation. After activation, the surface contact angle is less than 5°. Deionized water is used for cleaning. After cleaning, the surface is spun dry.

[0098] (2) Chip activation and cleaning: The wafer size is 12 inches and the wafer thickness is 775μm. After CMP, the wafer is diced into small chips, which are then adhered to the diced blue film with a surface roughness of less than 0.5nm. The chips on the blue film undergo plasma activation and cleaning processes. Nitrogen gas is used for plasma activation, and the surface contact angle after activation is less than 5°. Deionized water is used for cleaning, and the surface is spun dry after cleaning.

[0099] (3) D2W Pickup and Alignment: The processed chip and wafer are placed on their respective carriers, face up. During the chip-to-wafer (D2W) bonding process, a robotic arm first picks up the chip from the blue film, flips it, and transfers it above the wafer. At this time, a visible light camera moves between the chip and the wafer, identifies the alignment marks on the chip and wafer surfaces, corrects the chip position, and aligns the chip and wafer. After alignment, the chip is moved towards the wafer until it is bonded. The visible light spot diameter is 200 micrometers, the distance between the chip and the wafer is 10 cm, the chip size is 3 mm * 8 mm, the wafer size is 12 inches, and the alignment mark is a square with a side length of 30 micrometers.

[0100] (4) D2W Annealing: After the chip and wafer are aligned and mounted by visible light, the dielectric layer is pre-bonded. The pre-bonded sample is placed in an annealing furnace for heating treatment at 300°C for 2 hours. After high-temperature annealing, the chip and wafer are bonded.

[0101] The alignment accuracy of the chips during wafer mounting is 400nm. The mounting efficiency is 2002 chips / minute.

[0102] As can be seen from the results of Examples 1-8 and Comparative Example 1, the chip-to-wafer mounting method of the present invention achieves high alignment accuracy. Although the present invention adds an infrared alignment step to the visible light alignment, its efficiency is not significantly affected compared to visible light alone.

[0103] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A mounting method suitable for chip-to-wafer hybrid bonding, characterized by, The method comprises: Step (1), visible light pre-alignment: placing the chip above the wafer, identifying the alignment marks on the chip and wafer surfaces respectively by visible light between the chip and wafer, realizing the pre-alignment of the chip and wafer, and removing the visible light after pre-alignment; Step (2), infrared light fine alignment: moving the pre-aligned chip to the wafer, and accurately identifying the alignment marks on the chip and wafer surfaces by infrared light below the wafer, and accurately aligning the chip and wafer during the movement of the chip to the wafer.

2. The method of claim 1, wherein, Step (2) comprises: during the movement of the chip to the wafer, the infrared light tracks and corrects the alignment position of the chip and wafer for multiple times.

3. The method of claim 2, wherein, Step (2) comprises: the infrared light performs fine alignment once every 0.2-10 cm of the movement of the chip to the wafer.

4. The method of claim 3, wherein, The distance of the movement of the chip to the wafer after the last time is 1-3 cm smaller than the distance of the movement of the chip to the wafer before the last time.

5. The method of claim 1, wherein, The wavelength of the infrared light is 700-1000 nm.

6. The method of claim 1, wherein, The spot diameter of the infrared light is 10-800 microns.

7. The method of claim 1, wherein, The distance between the light source of the infrared light and the wafer is 0.5-10 cm.

8. The method of claim 1, wherein, The movement speed of the chip to the wafer is 0.1-10 cm / s.

9. The method of claim 1, wherein, In step (1), the distance between the chip and the wafer is 1-30 cm.

10. The method of claim 1, wherein, The size of the chip is 1 mm×1 mm-40 mm×40 mm.

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