Method for improving stability of stacking precision between batches of wafers
By monitoring the PSA-RA time and updating the process calibration coefficients in real time, the problem of unstable stacking accuracy between wafer batches was solved, achieving stability of stacking accuracy between wafer batches and accuracy of offset compensation, and reducing deviations introduced by machine defects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-03-06
AI Technical Summary
In existing semiconductor manufacturing technologies, the stacking accuracy between wafer batches is unstable, especially the stacking accuracy of the first wafer, which leads to a decrease in device performance and an increase in production line load. Furthermore, existing solutions cannot effectively reduce the X-direction deviation introduced by machine defects.
By monitoring the PSA-RA time during wafer transshipment in real time, the offset compensation value in the X direction is calculated and sent to the exposure equipment in real time to adjust the parameters. At the same time, the process calibration coefficients are updated and corrected to improve the stability of stacking accuracy.
This effectively reduces the X-direction deviation of the first wafer caused by changes in alignment mark stress, ensures the stability of the stacking accuracy between wafer batches on the production line, and improves the accuracy of offset compensation values.
Smart Images
Figure CN121620152A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically to a method for improving the stacking accuracy between wafer batches. Background Technology
[0002] In advanced semiconductor manufacturing processes, the shrinking technology nodes have made the requirements for wafer-to-wafer (W2W) stacking accuracy (OVL) stability extremely stringent, directly impacting device performance and yield. Therefore, ensuring qualified wafer-to-wafer stacking accuracy is a core task. Currently, the industry uses feedforward (FF) and feedback (FB) corrections to reduce wafer-to-wafer differences by updating stacking accuracy characteristic data. However, process instability and equipment limitations lead to significant wafer-level differences, especially the first-wafer stacking accuracy issue: even a deviation of only 1nm can cause a sharp increase in the hold ratio, which is judged as OOC (Out of Control), increasing production line load and costs.
[0003] Currently, during single-wafer processing on the production line, if the first wafer of the next batch is passed through a different chuck than the previous batch, it causes a delay in Reticle Alignment (RA), resulting in increased wafer size and abnormal stacking accuracy of the first wafer. Current manufacturer and equipment improvements involve replacing the hydrophobic sealing film on the alignment marks to reduce stress-induced deformation. However, this solution cannot reduce the X-direction deviation introduced by the processing sequence and machine defects, and it is also lagging, requiring frequent replacement of the hydrophobic film. Summary of the Invention
[0004] This application provides a method for improving the stacking accuracy between wafer batches, which can improve the stability of the stacking accuracy between wafer batches online.
[0005] This application provides a method for improving the stability of wafer batch stacking accuracy, including:
[0006] S1: When the nth batch of wafers is processed online, the PSA-RA time of the first wafer is monitored in real time. The PSA-RA time is the interval between the wafer alignment step and the mask alignment step, where n = 1, 2, 3...;
[0007] S2: When the PSA-RA time is greater than a preset threshold, the X-direction offset compensation value is calculated according to the PSA-RA time and the set compensation value calculation formula.
[0008] The formula for calculating the compensation value is as follows:
[0009] Tx 补偿 =K n-1 / T n3 ;
[0010] Among them, Tx 补偿 K is the offset compensation value in the X direction. n-1 T is the process calibration coefficient. n For the nth batch of PSA-RA time;
[0011] S3: The X-direction offset compensation value is sent to the exposure device in real time, so that the exposure device can adjust the corresponding parameters and perform exposure processing.
[0012] In some embodiments, for the first batch of wafers, the initial process calibration factor K0 = 14s*nm.
[0013] In some embodiments, after step S3, the method further includes:
[0014] S4: Obtain the measured value of the superposition accuracy of the nth batch, and obtain the measured value of the offset in the X direction based on the measured value of the superposition accuracy;
[0015] S5: Calculate the process calibration coefficient correction value for the nth batch of wafers. The calculation formula is as follows:
[0016] K n '=Tx 实测 / T n 3 ;
[0017] Wherein, K n 'Tx' is the correction value for the process calibration factor of the nth batch of wafers. 实测 This is the measured value of the offset in the X direction;
[0018] S6: Based on the process calibration coefficient correction value of the nth batch of wafers, correct the process calibration coefficient of the next batch.
[0019] In some embodiments, in the step of correcting the process calibration coefficient of the next batch based on the process calibration coefficient correction value of the nth batch of wafers, the calculation formula is:
[0020] K n =λK n '+(1-λ)K n-1 ;
[0021] Wherein, K n λ represents the corrected process calibration coefficient for the next batch, where λ is the weighting coefficient.
[0022] In some embodiments, the weighting coefficient λ is set to 30%.
[0023] In some embodiments, when the unupdated duration of the process calibration coefficient reaches a preset number of days threshold, the batch number n of the current production batch is reset to 1.
[0024] The technical solution of this application has at least the following advantages:
[0025] 1. By monitoring the PSA-RA time of the first wafer in real time during the online processing of the nth batch of wafers, and calculating the X-direction offset compensation value according to the set compensation value calculation formula when the PSA-RA time exceeds the preset threshold, the X-direction offset compensation value is sent to the exposure equipment in real time so that the exposure equipment can adjust the corresponding parameters and perform exposure processing. This can reduce the excessive X-direction deviation of the first wafer caused by the stress change of the alignment mark k, and ensure the stability of the stacking accuracy between batches of online wafers.
[0026] 2. By updating and correcting the process calibration coefficients, the accuracy of obtaining the X-direction offset compensation value has been improved. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0028] Figure 1 This is a flowchart of a method for improving the stability of wafer batch stacking accuracy provided in an exemplary embodiment of this application;
[0029] Figure 2 This is a flowchart of a method for improving the stability of wafer batch stacking accuracy provided in another exemplary embodiment of this application. Detailed Implementation
[0030] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0031] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0033] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0034] This application provides a method for improving the stability of wafer batch stacking accuracy. The method is executed by a control terminal equipped with an inter-batch closed-loop control system. (Refer to...) Figure 1 The method includes the following steps:
[0035] S1: When the nth batch of wafers is shipped online, monitor the PSA-RA time of the first wafer in real time.
[0036] Wherein, PSA-RA time is the interval between the wafer alignment step and the mask alignment step, and n is the batch number, which can be a positive integer such as 1, 2, or 3.
[0037] In practice, before wafer transshipment, staff activate the batch-to-batch closed-loop control system on the control terminal and select the "first wafer effect compensation" option. When the nth batch of wafers is transshipped online, the control system collects the PSA-RA time of the first wafer in the current nth batch.
[0038] S2: When the PSA-RA time is greater than the preset threshold, the X-direction offset compensation value is calculated according to the PSA-RA time and the set compensation value calculation formula.
[0039] The formula for calculating the compensation value is as follows:
[0040] Tx 补偿 =K n-1 / T n 3 ;
[0041] In this formula, Tx 补偿 K is the offset compensation value in the X direction. n-1 T is the process calibration coefficient. n This refers to the PSA-RA time for the nth batch.
[0042] In implementation, a threshold for PSA-RA time is preset in the control terminal, for example, this threshold can be 10 seconds. When the control terminal identifies that the PSA-RA time of the first wafer is greater than this threshold, it will retrieve the preset compensation value calculation formula, substitute the PSA-RA time into it, and then calculate the X-direction offset compensation value.
[0043] Furthermore, in this step, for the first batch of wafers, i.e. when n=1, the initial process calibration coefficient K0=14s*nm.
[0044] S3: Send the X-direction offset compensation value to the exposure equipment in real time, so that the exposure equipment can adjust the corresponding parameters and perform exposure processing.
[0045] In practice, the control terminal sends the calculated X-direction offset compensation value to the exposure equipment in real time, so that the exposure equipment can adjust the process parameters according to the X-direction offset compensation value to offset the impact of the X-direction offset on the stacking accuracy.
[0046] Furthermore, refer to Figure 2 Following step S3 above, the method for improving the stability of wafer batch stacking accuracy may further include the following steps:
[0047] S4: Obtain the measured value of the superposition accuracy of the nth batch, and obtain the measured value of the offset in the X direction based on the measured value of the superposition accuracy.
[0048] For example, the superposition accuracy of the nth batch can be measured by a superposition accuracy measurement device. The control terminal can obtain the superposition accuracy of the nth batch from the superposition accuracy measurement device and decompose it to obtain the measured value of the X-direction offset.
[0049] S5: Calculate the process calibration coefficient correction value for the nth batch of wafers.
[0050] The calculation formula in this step is as follows:
[0051] K n '=Tx 实测 / T n 3;
[0052] In this formula, K n 'Tx' is the correction value for the process calibration factor of the nth batch of wafers. 实测 This is the measured value of the offset in the X direction.
[0053] In practice, the control terminal calculates the process calibration coefficient correction value K for the nth batch of wafers according to the above calculation formula. n '.
[0054] S6: Based on the process calibration coefficient correction value of the nth batch of wafers, correct the process calibration coefficient of the next batch.
[0055] During implementation, the sealing hydrophobic membrane will gradually age with the accumulation of usage time. Therefore, in order to ensure the accuracy of the process calibration coefficient K value, the control terminal will correct the process calibration coefficient of the next batch based on the process calibration coefficient correction value of the nth batch of wafers.
[0056] Furthermore, in step S6, the calculation formula is as follows:
[0057] K n =λK n '+(1-λ)K n-1 ;
[0058] Among them, K n λ represents the corrected process calibration coefficient for the next batch, where λ is the weighting coefficient.
[0059] Furthermore, the weighting coefficient λ can be set to 30%, meaning that the influence of the latest batch of wafers on the process calibration coefficient of the next batch is 30%, while the influence of historical data is 70%.
[0060] Furthermore, in actual production, considering factors such as PM (preventive maintenance) of the exposure machine, when the unupdated time of the process calibration coefficient reaches a preset threshold of days, the batch number n of the current production batch is reset to 1. For example, the preset threshold of days can be 60 days. When the unupdated time of the process calibration coefficient exceeds 60 days, the old historical data has poor compatibility with the newly started exposure machine. Therefore, the batch number n of the current production batch can be reset to 1, and the initial process calibration coefficient K0 can be used again for compensation value prediction.
[0061] The method for improving the stability of wafer batch stacking accuracy provided in this application embodiment has two aspects. On the one hand, by monitoring the PSA-RA time of the first wafer in real time during the online shipment of the nth batch of wafers, and calculating the X-direction offset compensation value according to the set compensation value calculation formula when the PSA-RA time is greater than a preset threshold, the X-direction offset compensation value is sent to the exposure equipment in real time so that the exposure equipment can adjust the corresponding parameters and perform exposure processing. This can reduce the excessive X-direction deviation of the first wafer caused by the stress change of the alignment mark, and ensure the stability of the online wafer batch stacking accuracy. On the other hand, by updating and correcting the process calibration coefficient, the accuracy of obtaining the X-direction offset compensation value is improved.
[0062] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for improving overlay accuracy stability between wafer lots, the method comprising: The method comprises the following steps: S1: when the first wafer of the nth batch of wafers is on-line, the PSA-RA time of the first wafer is monitored in real time, the PSA-RA time is the interval time between the wafer alignment step and the mask alignment step, wherein n = 1, 2, 3……; S2: when the PSA-RA time is greater than the preset threshold value, the X-direction offset compensation value is calculated according to the PSA-RA time and the set compensation value calculation formula; The compensation value calculation formula is: Tx 补偿 = K n-1 / T n 3 ; wherein, Tx 补偿 is the X-direction offset compensation value, the K n-1 is the process calibration coefficient, T n is the PSA-RA time of the nth batch; S3: the X-direction offset compensation value is sent to the exposure equipment end in real time, so that the exposure equipment end adjusts the corresponding parameters and performs exposure processing.
2. The method of claim 1, wherein, For the first batch of wafers, the initial process calibration coefficient K0 = 14s*nm.
3. The method of claim 1, wherein the method further comprises: After the step S3, the method further comprises the following steps: S4: obtaining the superposition accuracy measured value of the nth batch of wafers, and obtaining the X-direction offset measured value based on the superposition accuracy measured value; S5: calculating the process calibration coefficient correction value of the nth batch of wafers, and the calculation formula is: K n ’ = Tx 实测 / T n 3 ; Wherein, the K n is the process calibration coefficient correction value of the nth batch of wafers, Tx 实测 is the measured value of the X direction offset S6: based on the process calibration coefficient correction value of the nth batch of wafers, the process calibration coefficient of the next batch is corrected.
4. The method of claim 3, wherein the method further comprises: In the step of correcting the process calibration coefficient of the next batch based on the process calibration coefficient correction value of the nth batch of wafers, the calculation formula is: K n = λK n ' + (1 - λ)K n-1 ; Wherein, the K n is the corrected process calibration coefficient of the next batch, and λ is a weight coefficient.
5. The method of claim 4, wherein the method further comprises: The weight coefficient λ is set to 30%.
6. The method of claim 3, wherein the method further comprises: When the non-updated duration of the process calibration coefficient reaches the preset day threshold, the batch number n of the current production batch is reset to 1.