Module packaging structure and process
By using a semi-embedded module packaging structure and advanced technology, the problems of large board area, long interconnection distance and high parasitic inductance in traditional packaging are solved, realizing high-density integration of multiple chips and efficient heat dissipation, and adapting to the packaging requirements of different application scenarios.
Patent Information
- Application Number
- CN202511799521.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-02
- Publication Date
- 2026-03-06
AI Technical Summary
In existing semiconductor packaging technologies, traditional power device modules suffer from problems such as large board area, high parasitic inductance, large switching losses, long interconnection distances, and difficulty in compatibility with advanced interconnection technologies. In particular, EMC interference control is difficult in high-frequency applications, and the packaging method is limited by the frame structure, making it difficult to adapt to the requirements of high-density integration of multiple chips and high creepage distance.
It adopts a semi-buried module packaging structure and advanced packaging technology. By stacking the structure, the board area and interconnection distance are reduced. Vertical conductive channels and redistribution layers are introduced for electrical connection. Combined with dielectric layer and molding process, the shape and area of the pads are adjusted. A double-blade process is used to form a stepped structure to enhance heat dissipation and soldering reliability.
It achieves high-density integration of multiple chips, reduces package size and parasitic parameters, enhances heat dissipation, reduces switching losses and inductance, adapts to the needs of different chips and PCBs, and improves packaging flexibility and reliability.
Smart Images
Figure CN121620239A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a module packaging structure and process. Background Technology
[0002] In the semiconductor packaging field, there are two traditional types of power device modules. One type is the through-hole leadframe structure, represented by the TO247-4, which separates the power and signal terminals through four pins. The metal base directly contacts the heatsink, with a typical thermal resistance of approximately 0.8℃ / W (junction to case). However, the pin layout occupies a large PCB area, and the height usually exceeds 5mm, requiring additional assembly space. It has high parasitic inductance and high switching losses, making it suitable for medium-power applications below 1200V. In high-frequency applications, EMC interference control is difficult. The other type has high process maturity and significant cost advantages for small batches, but the pin solder joints are susceptible to vibration, resulting in a low pass rate for automotive-grade Grade 0 certification.
[0003] Another type is the surface-mount leadframe structure represented by QDPAK DUAL / DFN. QDPAK DUAL is essentially an integrated form of two QDPAK packages, compatible with both high and low voltage devices. It employs a Kelvin source connection design, directly dissipating heat through a top metal cover, achieving thermal decoupling between the device and the PCB. However, this packaging method reduces the space available for placing the chip on the base island; large IGBT chips cannot be packaged this way.
[0004] Furthermore, for some products requiring high creepage distances, typically above 6.45mm, increasing the size of the molding compound is necessary, which alters the package appearance. Existing packaging technologies all suffer from insurmountable problems and defects. QDPAK DUAL and TO247-4, limited by their frame structures, struggle to be compatible with advanced interconnect technologies and face the long-term risk of becoming obsolete through technological iteration. Summary of the Invention
[0005] The purpose of this invention is to provide a modular packaging structure that addresses the shortcomings of existing technologies, reduces the board area and interconnection distance, decreases parasitic parameters and switching losses, achieves high-density integration of multiple chips, seamlessly connects to next-generation materials such as glass substrates, and adjusts the shape and soldering area of output pads according to the area requirements and application scenarios of different chips and PCBs.
[0006] To achieve the above technical objectives, the present invention provides a module packaging structure for accelerating the driving of high-voltage devices, comprising: a first chipset and a second chipset, wherein: the substrate and front side of the first chipset face the bottom and interior of the module packaging structure, respectively; a first vertical conductive channel is arranged vertically inward from the bottom of the module packaging structure; the first vertical conductive channel is arranged on the outside of the first chipset; the upper part of the first vertical conductive channel is connected to a redistribution layer RDL located in the middle layer of the module packaging structure; a first spacing space is provided between the front side of the first chipset and the lower surface of the redistribution layer RDL; and the first chipset and the redistribution layer RDL are interconnected via the first vertical conductive channel; the second chipset is arranged above the redistribution layer RDL and interconnected with the redistribution layer RDL; a second spacing space is provided between the top of the module packaging structure and the upper surface of the redistribution layer RDL, which is encapsulated using a molding process.
[0007] This invention provides a modular packaging structure to accelerate the driving of high-voltage devices. It introduces an advanced semi-embedded packaging process, adopts a stacked structure to reduce the area occupied by the devices on the board and the interconnection distance, reduces parasitic parameters, and enhances heat dissipation. The shape and soldering area of the output pads can be adjusted according to different chips, different PCB board area requirements and application scenarios.
[0008] As a further improvement, the bottom and top of the module packaging structure have a substrate and a cover plate, respectively. The first chipset is embedded in the substrate, a dielectric is arranged in the first spaced arrangement space, and a molding compound is arranged in the second spaced arrangement space. The module packaging structure outputs external pads at the bottom and packaging pads at the middle. The external packaging of the second chipset completes the semi-embedded arrangement and forms the stacked packaging structure of the module packaging structure.
[0009] As a further improvement, the back side of the substrate of the first chipset is directly used as an independent pad for heat dissipation.
[0010] As a further improvement, the back side of the substrate of the first chipset also has a thick electroplated copper layer, which is exposed to enhance heat dissipation.
[0011] As a further improvement, the first vertical conductive channel has multiple channels, which are respectively located on the outside of the first chipset and arranged vertically inward. The redistribution layer RDL also has a dielectric layer. The pad area of the module package structure is located in the middle of the substrate. The electroplated thick copper layer is copper-tin plated. A first carrier board is arranged between the electroplated thick copper layer and the substrate of the first chipset. A second carrier board is arranged between the redistribution layer RDL and the second chipset.
[0012] As a further improvement, the second chipset is arranged in a flip-chip configuration with its front side facing the second carrier board and its back side facing the cover plate; the substrate of the second chipset is bonded to the bonding area on the second carrier board via bonding wires, and pads on the carrier board are arranged between the front side of the second chipset and the second carrier board.
[0013] As a further improvement, the second chipset is arranged with its back side facing the second carrier board and its front side facing the cover plate; the front side of the second chipset is bonded to the bonding area on the second carrier board by bonding wires, and pads on the carrier board are arranged between the substrate of the second chipset and the second carrier board.
[0014] As a further improvement, the module packaging structure uses a double-blade process to make the outer end of the soldered outer pin have a stepped structure, forming a soldering area and physical locking. The copper layer thickness of the soldered outer pin is between 20 and 100 μm, and the cutting depth of the first cut is 50% of the copper layer thickness.
[0015] Accordingly, the present invention also provides a module packaging process, which employs: an internal chip and an external chip, and includes: an internal chip process, an external chip process, and a molding process to make the module package a stacked packaging structure; the internal chip process includes: performing a mounting process on the internal chip, pre-embedding Cu pillars to form a first vertical conductive channel, and performing a front redistribution layer (RDL) process to form an interconnection between the internal chip and the redistribution layer (RDL) through the first vertical conductive channel, with a first spacing arrangement space between them, and the internal chip is embedded in the packaging substrate; the external chip process includes: the external chip is arranged in a mounting manner using a bonding process or a flip-chip process, arranged above the redistribution layer (RDL) and interconnected with it, with a second spacing arrangement space between the top of the module package and the upper surface of the redistribution layer (RDL) to form an external output pad for the module package at the bottom and an output packaging pad in the middle, and the external chip external packaging completes a semi-embedded arrangement.
[0016] As a further improvement, before and after the front redistribution layer (RDL) process, a dielectric layer process and a dielectric layer windowing process are included. Optionally, a back-side thick copper process is performed after the dielectric layer process to add pads to the back of the internal chip. When the external chip is mounted, its front side is bonded to the RDL via bonding wires. When the external chip is flip-chip mounted, its back-side substrate is bonded to the RDL via bonding wires, and its front side is interconnected with the RDL via pads on a carrier board. Printing, dicing, and testing processes are also included after the molding process. Attached Figure Description
[0017] Figure 1 This is a schematic diagram illustrating the principle of the first embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the principle of the second embodiment of the present invention; Figure 3 This is a three-dimensional schematic diagram of the first embodiment of the present invention; Figure 4 This is a three-dimensional schematic diagram of the second embodiment of the present invention; Figure 5 for Figure 1 and Figure 2 Enlarged schematic diagram of area A in the middle; Figure 6 This is a schematic diagram of the shape of the first welding pin of the present invention; Figure 7 This is a schematic diagram of the shape of the second welding pin of the present invention; Figure 8 This is a schematic diagram of the shape of the third welding pin of the present invention; Figure 9 For existing technology Thermal simulation diagram; Figure 10 This is a thermal simulation diagram of the present invention; Figure 11 This is a process flow diagram of the present invention.
[0018] Reference numerals: 1. Substrate; 2. Pad area; 3. First chipset; 4. Second chipset; VIA1. First vertical conductive channel; 5. Electroplated thick copper layer; 6. Redistribution layer RDL; 7. Pad on carrier; 8. Cover plate; 10. Module packaging structure; 12. Step structure; 13. First carrier; 14. Second carrier; 15. Molded enclosure; 16. Dielectric; 17. Bonding wire; 18. Bonding area. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] In the description of this invention, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "inner", "outer", "lateral", and "vertical" is based on the orientation or positional relationship shown in the accompanying drawings and is only for the convenience of describing this invention, and is not intended to indicate or imply that the device or component referred to must have a specific orientation, and therefore should not be construed as a limitation of this invention.
[0021] like Figures 1 to 5 As shown, the present invention provides a module packaging structure for accelerating the driving of high-voltage devices, comprising: a first chipset 3 and a second chipset 4, wherein: the substrate and front side of the first chipset 3 face the bottom and interior of the module packaging structure 10, respectively; a first vertical conductive channel VIA1 is arranged vertically inward from the bottom of the module packaging structure 10; the first vertical conductive channel VIA1 is arranged on the outside of the first chipset 3; the upper part of the first vertical conductive channel VIA1 is connected to a redistribution layer RDL6 located in the middle layer of the module packaging structure 10; a first spacing arrangement space is provided between the front side of the first chipset 3 and the lower surface of the redistribution layer RDL6; and the first chipset 3 and the redistribution layer RDL6 are interconnected via the first vertical conductive channel VIA1; the second chipset 4 is arranged above the redistribution layer RDL6 and interconnected with the redistribution layer RDL6; a second spacing arrangement space is provided between the top of the module packaging structure 10 and the upper surface of the redistribution layer RDL6, which is encapsulated using a molding process.
[0022] This invention provides a modular packaging structure for accelerating the driving of high-voltage devices. It introduces an advanced semi-embedded packaging process, employing a stacked structure to reduce the device's footprint and interconnection distance, decrease parasitic parameters, and enhance heat dissipation. The shape and area of the output pads can be adjusted according to different chips, PCB board requirements, and application scenarios. The second spacing space in its packaging structure allows for direct application of traditional molding compound processes, reducing the difficulty, cost, and impact of fully embedded processes.
[0023] As a further improvement, the module packaging structure 10 has a substrate 1 and a cover plate 8 at the bottom and top, respectively. The first chipset 3 is embedded in the substrate 1. A dielectric 16 is arranged in the first spaced arrangement space and a molding compound 15 is arranged in the second spaced arrangement space. The module packaging structure outputs external pads at the bottom and packaging pads at the middle. The second chipset 4 is externally packaged to complete the semi-embedded arrangement and forms the stacked packaging structure of the module packaging structure 10.
[0024] As a further improvement, the back side of the substrate of the first chipset 3 is directly used as an independent pad for heat dissipation.
[0025] As a further improvement, the back side of the substrate of the first chipset 3 also has an electroplated thick copper layer 5, which is exposed to enhance heat dissipation.
[0026] As a further improvement, the first vertical conductive channel VIA1 has multiple channels, which are respectively located on the outside of the first chipset 3 and arranged vertically inward. The redistribution layer RDL6 also has a dielectric layer. The pad area 2 of the module package structure 10 is located in the middle of the substrate 1. The electroplated thick copper layer 5 is copper-tin plated. A first carrier plate 13 is arranged between the electroplated thick copper layer 5 and the substrate of the first chipset 3. A second carrier plate 14 is arranged between the redistribution layer RDL6 and the second chipset 4.
[0027] As a further improvement, the second chipset 4 is arranged in a flip-chip configuration with its front side facing the second carrier board 14 and its back side facing the cover plate 8; the substrate of the second chipset 4 is bonded to the bonding area 18 located on the second carrier board 14 by bonding lines 17, and the front side of the second chipset 4 and the second carrier board 14 are provided with pads 7 on the carrier board.
[0028] As a further improvement, the second chipset 4 is arranged with its back side facing the second carrier board 14 and its front side facing the cover plate 8; the front side of the second chipset 4 is bonded to the bonding area 18 located on the second carrier board 14 through bonding lines 17, and the substrate of the second chipset 4 is provided with a pad 7 on the carrier board between the substrate of the second chipset 4 and the second carrier board 14.
[0029] As a further improvement, such as Figure 5 As shown, the module packaging structure 10 uses a double-blade process to make the outer end of the welded outer pin into a stepped structure 12, forming a welding area and physical locking. The copper layer thickness of the welded outer pin is between 20 and 100 μm, and the cutting depth of the first blade is 50% of the copper layer thickness.
[0030] Accordingly, the present invention also provides a module packaging process, which employs: an internal chip and an external chip, and includes: an internal chip process, an external chip process, and a molding process to make the module package a stacked packaging structure; the internal chip process includes: performing a mounting process on the internal chip, pre-embedding Cu pillars to form a first vertical conductive channel, and performing a front redistribution layer (RDL) process to form an interconnection between the internal chip and the redistribution layer (RDL) through the first vertical conductive channel, with a first spacing arrangement space between them, and the internal chip is embedded in the packaging substrate; the external chip process includes: the external chip is arranged in a mounting manner using a bonding process or a flip-chip process, arranged above the redistribution layer (RDL) and interconnected with it, with a second spacing arrangement space between the top of the module package and the upper surface of the redistribution layer (RDL) to form an external output pad for the module package at the bottom and an output packaging pad in the middle, and the external chip external packaging completes a semi-embedded arrangement.
[0031] As a further improvement, before and after the front redistribution layer (RDL) process, a dielectric layer process and a dielectric layer windowing process are included. Optionally, a back-side thick copper process is performed after the dielectric layer process to add pads to the back of the internal chip. When the external chip is mounted, its front side is bonded to the RDL via bonding wires. When the external chip is flip-chip mounted, its back-side substrate is bonded to the RDL via bonding wires, and its front side is interconnected with the RDL via pads on a carrier board. Printing, dicing, and testing processes are also included after the molding process.
[0032] To address the problems and limitations of traditional module packaging, this invention introduces a semi-buried advanced packaging process. By directly interconnecting internal copper layers, it reduces the board area and interconnection distance, enabling high-density integration of multiple chips. This also reduces parasitic parameters and switching losses. As a fundamental form of 2.5D / 3D packaging, the fully buried solution can seamlessly integrate with next-generation materials such as glass substrates. The shape and area of the output pads can be adjusted according to different chips, PCB board area requirements, and application scenarios. In contrast, QDPAK DUAL and TO247-4, limited by their frame structure, are difficult to be compatible with advanced interconnect technologies and face the risk of long-term technological obsolescence.
[0033] This invention employs a semi-submerged substrate fabrication process: First, one power switch chip is submerged into the substrate. Advanced processes such as VIA (Variable Aperture Alignment), RDL (Redirect Linearization), and pre-embedded copper pillars are used to achieve the shortest path electrical connection. The lower output module has external pads, and the upper output packaging pads complete the semi-submerged process. The other chip is externally packaged, achieving a stacked packaging structure, which reduces package size and shortens interconnect lines. Furthermore, a thick copper layer is electroplated on the back of the wafer, and the exposed pads enhance device heat dissipation. The product is cut using a double-blade process, resulting in stepped external pins that increase the welding area and provide physical locking, effectively improving welding reliability. Specifically, the copper layer thickness is between 20 and 100 μm, and the first cut depth needs to be controlled to approximately 50% of the copper layer thickness.
[0034] In such Figure 1 and Figure 3 In the first embodiment of the present invention shown, the semi-submersible substrate interconnects two chips through an adhesive bonding process or a bonding process, and then performs plastic encapsulation. In such... Figure 2 and Figure 4In the second embodiment of the present invention shown, the semi-submerged substrate interconnects two chips using a Flip Chip+Clip (or bonding-external chip substrate) process, and then performs molding. The dielectric material is ceramic, PCB, etc., and the chips are MOSFETs, JFETs, etc., made of materials such as Si, SiC, GaN, etc. The first vertical conductive channel VIA1 is copper, and the pads on the substrate are copper.
[0035] Due to the advanced packaging structure and corresponding process of this invention, the pin shape and soldering area can be arbitrarily adjusted according to the PCB board settings, and are not limited to... Figure 6 , Figure 7 , Figure 8 The graphics in the image. The present invention has the following technical effects: 1. Reduced package size: The commonly used package shape is QDPAK QUAL, with a package volume of approximately 36mm³. The use of the process described in this invention will be evaluated based on the chip size. The package can be completed using a general form factor, and the package size can be reduced by about 75%, resulting in advantages such as increased integration and reduced board area.
[0036] 2. Reduced interconnection distance: The average length of the source electrode bonding wire in QDPAK DUAL / DFN / TO247-4 and other solutions is about 0.4mm, while the average height of the source electrode copper pillar in the embedded solution is about 0.2mm, which greatly reduces the interconnection distance and shortens the signal transmission distance by more than 50%.
[0037] 3. Reduce inductance: By using a top-to-bottom interconnection method, parasitic inductance is effectively reduced while shortening the interconnection distance. The traditional packaging method has a parasitic inductance of 0.444nH, while the semi-buried structure has a parasitic inductance of 0.288nH, a reduction of approximately 35%. At the same time, the junction temperature difference between the two is very small. For example... Figure 9 and Figure 10 As shown, the back of the insulating substrate type chip can be used only as a heat dissipation pad, which can increase the heat dissipation path while increasing the packaging density.
[0038] 4. Different chip sizes can be packaged in various aspect ratios, such as DFN, QFN, and LGA, offering high process flexibility. When using the invented process, the substrate can be adapted primarily based on the size of the largest chip, eliminating the need for customization and mold-making costs. This saves development costs without increasing the requirements for the packaging process, providing universal flexibility.
[0039] It should be understood that the scope of protection sought by this invention is not limited to the non-limiting embodiments, which are merely illustrative examples. The substantive scope of protection claimed in this application is further embodied in the scope provided by the independent claims and their dependent claims.
Claims
1. A module package structure, comprising: A first chip set and a second chip set are characterized in that: The substrate and the front face of the first chip set are respectively oriented towards the bottom and the interior of the module packaging structure, a first vertical conductive channel is arranged vertically inward from the bottom of the module packaging structure, the first vertical conductive channel is arranged on the outer side of the first chip set, the upper part of the first vertical conductive channel is connected to a redistribution layer (RDL) located in a layer in the module packaging structure, a first spacing arrangement space is arranged between the front face of the first chip set and the lower surface of the redistribution layer (RDL), and the first chip set and the redistribution layer (RDL) are interconnected through the first vertical conductive channel; The second chip set is arranged above the redistribution layer (RDL) and is interconnected with the redistribution layer (RDL), and a second spacing arrangement space is arranged between the top of the module packaging structure and the upper surface of the redistribution layer (RDL) for encapsulation by a plastic encapsulation process.
2. The module package structure of claim 1, wherein: The bottom and the top of the module packaging structure respectively have a base plate and a cover plate, the first chip set is embedded in the base plate, a medium is arranged in the first spacing arrangement space, and a plastic encapsulation body is arranged in the second spacing arrangement space, the module packaging structure has external module pads on the lower side and encapsulation pads in the middle, the second chip set is arranged in a semi-embedded manner after encapsulation, and a stacked packaging structure of the module packaging structure is formed.
3. The module package structure for speeding up driving of high voltage devices according to claim 1, wherein: The back face of the substrate of the first chip set directly serves as an independent pad for heat dissipation.
4. The module package structure for speeding up driving of high voltage devices according to claim 1, wherein: The back face of the substrate of the first chip set further has a thick copper plating layer, and the thick copper plating layer is exposed and arranged for enhanced heat dissipation.
5. The module package structure of claim 4, wherein: The first vertical conductive channel has a plurality of channels and is respectively arranged on the outer side of the first chip set and vertically inward, the redistribution layer (RDL) further has a medium layer, the pad area of the module packaging structure is located in the middle of the base plate, the thick copper plating layer is copper plating tin, a first carrier plate is arranged between the thick copper plating layer and the substrate of the first chip set, and a second carrier plate is arranged between the redistribution layer (RDL) and the second chip set.
6. The module package structure of claim 5, wherein: The second chip set is arranged in a flip-chip manner with the front face facing the second carrier plate and the back face facing the cover plate; the substrate of the second chip set is connected to a bonding area on the second carrier plate through a bonding wire to form a bonding connection, and a carrier plate pad is arranged between the front face of the second chip set and the second carrier plate.
7. The module package structure of claim 5, wherein: The second chip set is arranged in a flip-chip manner with the back face facing the second carrier plate and the front face facing the cover plate; the front face of the second chip set is connected to a bonding area on the second carrier plate through a bonding wire to form a bonding connection, and a carrier plate pad is arranged between the substrate of the second chip set and the second carrier plate.
8. The module package structure of claim 5, wherein: The module packaging structure is subjected to a double-knife process to make the outer end of a welded outer pin have a stepped structure and form a welding area and physical locking, and the thickness of the copper layer of the welded outer pin is between 20 and 100 um, and the cutting depth of the first knife is 50% of the thickness of the copper layer.
9. A module packaging process employing: an internal chip and an external chip, characterized by: It comprises: An internal chip process, an external chip process, and a plastic encapsulation process to make the module packaging have a stacked packaging structure; The internal chip process includes: mounting the internal chip, embedding Cu column to form a first vertical conductive channel, and performing a front redistribution layer (RDL) process to form interconnection between the internal chip and the redistribution layer RDL through the first vertical conductive channel, and a first spacing arrangement space between them, and embedding the internal chip into the encapsulated substrate; The external chip process includes: arranging the external chip in a mounting manner by using a bonding process or arranging the external chip in a flip-chip manner by using a flip-chip process, arranging the external chip above the redistribution layer RDL and interconnecting the external chip with the redistribution layer RDL, and having a second spacing arrangement space between the top of the module package and the upper surface of the redistribution layer RDL to form an output module external pad at the bottom of the module package and an output pad for encapsulation, and completing the semi-embedded arrangement of the external chip package.
10. The process of claim 9, wherein: Before and after the front redistribution layer RDL process, a dielectric layer process and a dielectric layer windowing process are further included, and after the dielectric layer process, a back thick copper process is further selected to add pads to the back of the internal chip; When the external chip is arranged in a mounting manner, the front surface of the external chip is connected to the redistribution layer RDL through bonding wires, and when the external chip is arranged in a flip-chip manner, the substrate on the back surface of the external chip is connected to the redistribution layer RDL through bonding wires, and the front surface of the external chip is interconnected with the redistribution layer RDL through the pads on the carrier board; After the plastic packaging process, printing, cutting and testing processes are further included.