Semiconductor package with directional locking structure

Abstract

The invention relates to a semiconductor package. The semiconductor package includes a semiconductor die, a molding material, and a conductive structure. A conductive structure is at least partially stacked with the semiconductor die, the conductive structure including a plurality of slots positioned around points of the semiconductor die. The plurality of slots are configured to equalize thermal stress around a point of the semiconductor die during operation of the semiconductor die, wherein the thermal stress is associated with a coefficient of thermal expansion mismatch between the conductive structure and the molding material. Further, at least a portion of the molding material is in contact with the conductive structure.

Description

Cross-reference to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 510,569, filed June 27, 2023, entitled “IMPROVED SEMICONDUCTOR DEVICEPACKAGES,” the entire contents and all purposes of which are incorporated herein by reference. Technical Field

[0002] This application relates to semiconductor device packaging. In particular, some embodiments relate to semiconductor packages with double-sided heat dissipation structures and related manufacturing methods. Some embodiments relate to semiconductor packages with orientation-locking structures having one or more slots on the lead frame of the semiconductor package. Some embodiments relate to semiconductor packages with nested pin structures having drain leads on one side and device leads (such as gate leads and / or sensing leads) on the other side. Background Technology

[0003] Semiconductor devices are used in a wide variety of applications. In some applications, semiconductor devices may experience high electrical loads, which can lead to significant heat generation. Technical problems associated with high electrical loads may exist, such as harmful heating of the semiconductor device by the high load. In some applications, semiconductor devices may experience interface connection failures between components due to uneven thermal stress, such as uneven thermal expansion or contraction on the components of the semiconductor device. Technical problems associated with interface connection failures may exist during the operation of the semiconductor device. In some applications, semiconductor devices may experience... Summary of the Invention

[0004] The innovations described in the claims have several aspects, none of which is solely responsible for their desired properties. Without limiting the scope of the claims, some of the prominent features of this disclosure will now be briefly described.

[0005] One aspect of this disclosure is a semiconductor package with a double-sided heat dissipation structure. The semiconductor package includes a semiconductor die having a first side and a second side, a heat sink on the first side of the semiconductor die, a lead frame on the second side of the semiconductor die, and a die clamp positioned between the semiconductor die and a portion of the lead frame. The second side is positioned opposite to the first side. The die clamp is positioned between the semiconductor die and a portion of the lead frame. Furthermore, the die clamp and the lead frame are engaged at a connection point.

[0006] In one embodiment, the die clamp may include an opening at the connection point.

[0007] In one embodiment, the lead frame may include a gate lead and a Kelvin source lead. A first connection point in the connection points may engage the die clamp and the gate lead, and a second connection point in the connection points may engage the die clamp and the Kelvin source lead.

[0008] In one embodiment, the semiconductor package may be free of solder between the lead frame and the die clamp.

[0009] In one embodiment, the connection point can provide an alignment point between the lead frame and the die clamp for welding the die clamp and the lead frame.

[0010] In one embodiment, the semiconductor die may include a field-effect transistor. Furthermore, the lead frame may include electrical contacts to terminals of the semiconductor die, and the terminals of the semiconductor die may include source terminals, gate terminals, and Kelvin source terminals.

[0011] In one embodiment, a first side of the lead frame may include a plurality of leads. The plurality of leads may include two source leads connected to a source terminal of the semiconductor die, a gate lead connected to a gate terminal of the semiconductor die, and a Kelvin source lead connected to a Kelvin source terminal of the semiconductor die. The gate lead and the Kelvin source lead may be positioned between the two gate leads. Furthermore, a second side of the lead frame is positioned opposite the first side of the lead frame. The lead frame may also include one or more drain leads electrically connected to a drain terminal of the semiconductor die. Additionally, the semiconductor package may include a sensing lead located on the first side of the lead frame, and the sensing lead may be positioned between the two source leads.

[0012] In one embodiment, the lead frame may include leads, and at least a portion of the leads may extend beyond the heat sink and may be flat.

[0013] In one embodiment, the semiconductor package may further include a thermistor die. Additionally, the lead frame may include thermistor leads electrically connected to terminals of the thermistor die.

[0014] In one embodiment, the semiconductor package may further include die attachment solder positioned between a heat sink and a first side of the semiconductor die.

[0015] In one embodiment, the heat sink can be electrically connected to the drain terminal of the semiconductor die.

[0016] In one embodiment, the die clamp can be positioned within the coverage area of ​​the lead frame.

[0017] Another aspect of the present invention is a method for assembling a semiconductor package. The method includes joining a die clamp and a lead frame at multiple connection points, and, after joining, soldering the die clamp to a semiconductor die. After soldering, the die clamp and lead frame are located on the side of the semiconductor die opposite to the heat sink.

[0018] In one embodiment, joining may include welding.

[0019] In one embodiment, the semiconductor die may include a field-effect transistor, and the lead frame may include a gate lead and a Kelvin source lead.

[0020] In one embodiment, the die clamp may include multiple openings at the connection point.

[0021] In one embodiment, the method may further include reflowing solder to connect the heat sink and the semiconductor die before soldering.

[0022] In one embodiment, the method may further include pre-molding the heat sink before welding.

[0023] In one embodiment, the method may further include connecting the thermistor die to the lead frame via leads.

[0024] Another aspect of the present invention is a semiconductor package. The semiconductor package includes: a semiconductor die including a field-effect transistor, a molding material, and a conductive structure at least partially stacked with the semiconductor die. The conductive structure includes a plurality of trenches positioned around a point on the semiconductor die. The plurality of trenches are configured to equalize thermal stress around a point on the semiconductor die during operation. The thermal stress is related to a mismatch in the coefficient of thermal expansion between the conductive structure and the molding material. At least a portion of the molding material is in contact with the conductive structure.

[0025] In one embodiment, multiple slots may be oriented in a radial pattern around points on a semiconductor die.

[0026] In one embodiment, each of the plurality of slots may have a length in a direction away from that point and may have a width in a direction perpendicular to the length. The length may be longer than the width.

[0027] In one embodiment, the semiconductor package may also have a heat sink on the side of the semiconductor die opposite to the conductive structure, with each of the plurality of slots being at least partially positioned above the heat sink.

[0028] In one embodiment, each of the plurality of slots may be positioned at least partially above the semiconductor die.

[0029] In one embodiment, the conductive structure may be a lead frame. Furthermore, the lead frame may include a plurality of leads along one side of the semiconductor package, the plurality of leads including two source leads, a sensing lead positioned between the two source leads, and a gate lead positioned between the two source leads. Additionally, the semiconductor package may include a die clamp positioned between a portion of the semiconductor die and the lead frame, the die clamp and the lead frame being joined at a connection point.

[0030] In one embodiment, the conductive structure may be a die board.

[0031] Another aspect of this disclosure is a semiconductor package. The semiconductor package includes a semiconductor die, a molding material, and a lead frame at least partially stacked with the semiconductor die, the lead frame having a plurality of slots positioned around points on the semiconductor die. The plurality of slots are configured to equalize thermal stress around points on the semiconductor die, and at least a portion of the molding material is in contact with the lead frame.

[0032] In one embodiment, multiple slots may be oriented in a radial pattern around points on a semiconductor die.

[0033] In one embodiment, at least one of the multiple slots may have a rectangular shape.

[0034] In one embodiment, at least one of the multiple slots may have a curved shape.

[0035] In one embodiment, each of the plurality of slots may include a length in a direction away from the point and a width in a direction perpendicular to the length, such that the length may be longer than the width.

[0036] In one embodiment, the point may be the center point of the semiconductor package.

[0037] In one embodiment, the semiconductor package may further include a heat sink on the side of the semiconductor die opposite the lead frame. Each of the plurality of slots may be positioned at least partially above the heat sink. Furthermore, at least one of the plurality of slots may extend beyond the heat sink.

[0038] In one embodiment, two or more of the slots may have different lengths.

[0039] In one embodiment, each of the multiple slots may have the same width.

[0040] In one embodiment, the semiconductor die may include a field-effect transistor (FET). Furthermore, the lead frame may include a plurality of leads, including two source leads electrically connected to the source of the FET, a gate lead electrically connected to the gate of the FET, and a sensing lead. Additionally, the plurality of leads may be positioned on a first side of the lead frame, and the gate lead and the sensing lead may be positioned between the two source leads.

[0041] In one embodiment, thermal stress may be caused by a mismatch in the coefficient of thermal expansion (CTE) between the lead frame and the molding material.

[0042] In one embodiment, the semiconductor package may further include a thermistor electrically connected to a sensing lead in the lead frame.

[0043] In one embodiment, the semiconductor package may further include die-coating material positioned between the die and the lead frame. The slot may be sized to allow the die-coating material to be injected through the slot during manufacturing.

[0044] Another aspect of this disclosure is a semiconductor package including a semiconductor die and a plurality of leads. The semiconductor die includes a field-effect transistor having a source, a gate, and a drain. The plurality of leads include two drain leads connected to the drain, two source leads connected to the source, a gate lead connected to the gate, and a sensing lead positioned between the two source leads. The gate lead is positioned between the two source leads. The two source leads, the gate lead, and the sensing lead are positioned on a first side of the semiconductor package opposite a second side of the semiconductor package. The drain lead is positioned on the second side.

[0045] In one embodiment, the semiconductor package may further include a heat sink positioned on the side of the semiconductor die opposite the lead frame, and the lead frame may include a plurality of leads. Additionally, the lead frame may include a plurality of slots radially positioned around a point. Furthermore, the semiconductor package may include a die clamp positioned between the semiconductor die and a portion of the lead frame, and the die clamp and the lead frame may engage at a connection point.

[0046] In one embodiment, the plurality of leads may include Kelvin source leads connected to the Kelvin source terminals of the semiconductor die, such that the Kelvin source leads can be positioned between two source leads on the first side.

[0047] In one embodiment, each of the plurality of leads may be a flat lead.

[0048] In one embodiment, the semiconductor package may further include a sensing die. Furthermore, sensing leads may be connected to terminals of the sensing die. Additionally, the sensing die may be a thermistor die.

[0049] In one embodiment, similar to the two source leads being located on the first side, the two drain leads can be located at relative positions on the first side.

[0050] Another aspect of this disclosure is a semiconductor assembly including a printed circuit board (PCB), a first semiconductor package on the PCB, and a second semiconductor package on the PCB. The first semiconductor package includes a first field-effect transistor and a first plurality of leads, wherein the first plurality of leads includes two source leads and a gate lead, the gate lead being positioned between the two source leads on one side of the first semiconductor package. The second semiconductor package includes a second field-effect transistor and a second plurality of leads. The second plurality of leads includes two drain leads positioned on one side of the first semiconductor package. The first and second semiconductor packages are positioned such that the two drain leads are aligned with and electrically connected to the two source leads.

[0051] In one embodiment, the first plurality of leads may include a sensing lead positioned between two source leads on one side of the first semiconductor package. Furthermore, the first semiconductor package may include a thermistor die electrically connected to the sensing lead.

[0052] In one embodiment, the first plurality of leads may include a Kelvin source lead positioned between two source leads located on one side of the first semiconductor package.

[0053] In one embodiment, one side of the second semiconductor package may not have a lead between the two drain leads.

[0054] In one embodiment, one side of the second semiconductor package may be without leads in the region aligned with the gate leads.

[0055] In one embodiment, the two source leads may be flat leads having a flat portion extending beyond the molding material of the first semiconductor package.

[0056] In one embodiment, the first semiconductor package and the second semiconductor package may be two instances of the same semiconductor package design.

[0057] In one embodiment, each of the first plurality of leads and the second plurality of leads may be a flat lead.

[0058] In one embodiment, the first semiconductor package may include a die plate and a lead frame on opposite sides, and the lead frame may include a first plurality of leads.

[0059] In one embodiment, the first semiconductor package may include a lead frame including a first plurality of leads. The lead frame may include a plurality of slots radially positioned around a point.

[0060] To summarize this disclosure, certain aspects, advantages, and novel features of the innovations are described herein. It should be understood that all of these advantages may not necessarily be achieved according to any particular embodiment. Therefore, an innovation may be embodied or realized in a manner that achieves or optimizes one or more advantages taught herein, without necessarily achieving other advantages taught or suggested herein. Attached Figure Description

[0061] These and other features, aspects, and advantages of this disclosure have been described with reference to the accompanying drawings of certain embodiments, which are intended to illustrate, but are not limited to, this disclosure. It should be understood that the drawings, which are incorporated in and form part of this specification, are for illustrating the concepts disclosed herein and may not be drawn to scale.

[0062] Figure 1A A cross-section of an example device according to some embodiments is shown.

[0063] Figure 1B A cross-section of another example embodiment using a gap conductor is shown.

[0064] Figure 1C A cross-section of another example embodiment is shown.

[0065] Figure 1D Another cross-section of another example embodiment is shown.

[0066] Figure 2A An exploded view of an example of a packaged IC device according to some embodiments is shown.

[0067] Figure 2B An exploded view of another example of a packaged IC device according to some embodiments is shown.

[0068] Figure 3 Selected steps of the process for assembling packaged IC devices are shown.

[0069] Figure 4 An example combined lead frame structure including a lead frame and a die clamp is shown.

[0070] Figure 5A and Figure 5B Bottom and top views of example packaged IC devices according to some embodiments are shown respectively.

[0071] Figure 6A and Figure 6B Bottom and top views of a pre-molded lead frame according to some embodiments are shown respectively.

[0072] Figure 6CAn example of a pre-molded leadframe is shown after the placement of die clamp solder, die clamp, auxiliary die solder, and auxiliary die stacked on top of the die clamp.

[0073] Figure 6D Examples of several pre-molded lead frames are shown.

[0074] Figure 7 Components of a packaged IC device according to some embodiments are shown.

[0075] Figure 8A A packaged IC device with radially distributed slots is shown according to some embodiments.

[0076] Figure 8B A packaged IC device with distributed slots according to some embodiments is shown.

[0077] Figure 8C A packaged IC device with distributed slots according to some embodiments is shown.

[0078] Figure 8D An example of a lead frame with distributed slots according to some embodiments is shown.

[0079] Figure 8E An example of a lead frame with distributed slots according to some embodiments is shown.

[0080] Figure 8F An example of a lead frame with distributed circular slots according to some embodiments is shown.

[0081] Figure 8G An example of a lead frame with radially distributed helical grooves according to some embodiments is shown.

[0082] Figure 9 A simplified pin example according to some embodiments is shown.

[0083] Figure 10 An example of a “head-to-toe” arrangement of a semiconductor device according to some embodiments is shown.

[0084] Figure 11 Examples of surface-mount packaged IC devices according to some embodiments are shown. Detailed Implementation

[0085] The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this specification, reference is made to the accompanying drawings, wherein the same reference numerals and / or terms may denote the same or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it should be understood that some embodiments may include more elements than shown in the figures and / or a subset of the elements shown in the figures. Additionally, some embodiments may combine any suitable combination of features from two or more figures. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims. introduction

[0086] Electronic components comprising one or more integrated circuit (IC) dies can be deployed in a variety of applications. For example, such components can form part of a power electronic system. In some cases, such a power electronic system can be used to provide power for heating, ventilation, and air conditioning (HVAC) systems, electric vehicles, etc. For example, in an electric vehicle, such a system can be used to convert alternating current (AC) to direct current (DC) for charging, from DC to AC, or from DC at a first voltage to DC at a different second voltage to provide power output. Power electronic systems can also be used as part of stationary energy storage systems, such as systems for storing solar energy, or for other applications requiring power delivery. For example, a power electronic system can be used to convert DC from solar panels or batteries to AC. In some cases, such a power electronic system can be used in utility applications, such as grid-connected inverters that convert DC to AC for plugging into the grid. These are just examples, and such systems can have many other applications. In some cases, components of such a system can include diode switches, field-effect transistors (FETs) (such as metal-oxide-semiconductor field-effect transistors (MOSFETs), (e.g., GaN MOSFETs), insulated-gate bipolar transistors, other bipolar transistors, etc.), or any suitable combination thereof. In some applications, such switches can be included in inverters that convert direct current (DC) voltage to alternating current (AC) voltage. These components can generate a significant amount of heat during operation.

[0087] Thermal management can be achieved by using relatively large leadframes, die boards, heat sinks, etc. Multiple reflow steps can be used during manufacturing, and components may shift during assembly. Misalignment can lead to degraded device performance and / or shortened lifespan, or even device malfunction.

[0088] Power electronic systems generate significant amounts of heat under both steady-state load conditions and power surge conditions. High temperatures can cause serious problems. For example, overheating can lead to performance degradation, reduced reliability, and shortened lifespan. For instance, overheating or large temperature fluctuations can cause one or more of the following: component damage, shortened lifespan, reduced reliability, and performance degradation. For example, excessive thermal stress can weaken solder joints and / or damage semiconductor components. Illustratively, the substrate (or the frame upon which the IC is implemented) of a power electronic system may have different coefficients of thermal expansion (CTE) in different portions of the substrate. These mismatches in CTE on the substrate can create one or more areas of concentrated thermal stress, resulting in mechanical stress on the substrate that can cause delamination of components implemented on the substrate. For example, during operation, specific areas of the electrical component substrate may experience concentrated thermal stress, resulting in differences in expansion or contraction compared to other areas. Such concentrated thermal stress due to CTE mismatch can cause electrical components to be detached from the substrate. In some applications, power surge loads can cause temperatures to rise rapidly. High-power surge loads may be encountered in various applications, such as when starting portable compressors, HVAC systems, refrigeration systems, electric motors, etc.

[0089] Thermal considerations can conflict with other design considerations. For example, higher switching speeds can be achieved by placing components very close together. However, placing components close together can present challenges for temperature management.

[0090] Assembling power electronic components can also present some challenges. For example, high-power connections and low-power connections (e.g., for temperature sensing, gate control, etc.) can be handled differently. For instance, lead frames can be used for high-power connections, and die clips can be used for low-power connections. Die clips can be conductors placed on top of other components that require electrical or thermal connections, or both.

[0091] This disclosure provides technical solutions for addressing one or more of the aforementioned technical challenges and / or one or more other technical challenges. Any suitable combination of the principles and advantages of these technical solutions can be implemented together in a packaged IC device.

[0092] Various aspects of this disclosure provide the inclusion of gap conductors between heat sinks in a packaged IC device. These conductors can provide one or more signal, drive, sensing, or other connections to dies positioned between the heat sinks. The gap conductors can be connected to enable electrical functions and / or assist assembly to reduce manufacturing steps. Die clips and lead frames can be pre-assembled. This can provide manufacturing advantages. In some aspects of this disclosure, the semiconductor package can include thermal stress management such that thermal expansion and / or contraction can be balanced around a center point or other point (such as a hot spot). This can be achieved through various slot patterns, such as radial features around a center point or other point. In some aspects of this disclosure, the semiconductor package can have an alignment architecture that allows for the positioning of contacts of the packaged IC device. For example, multiple packaged devices can have contacts aligned with each other. High-power signals can be directly propagated to adjacent and / or adjacent packaged IC devices. Other lower connections (e.g., signals, sensing, drives) can be nested or clustered to avoid power conduction paths. Package design with gap conductor

[0093] Various aspects of this disclosure relate to semiconductor devices with gap conductors. In power integrated circuits (ICs), electrical contacts used to carry high voltages may be relatively large, for example, to reduce resistive losses. However, large, bulky electrical conductors can occupy a significant amount of space and may involve a large amount of material, potentially leading to larger and more expensive devices. In some cases, signal, drive, sensing, and other electrical contacts can be relatively small compared to contacts carrying high voltages.

[0094] In some cases, gap conductors can be used to connect signals, drive (e.g., gate drive), sense, etc. As described herein, they can simplify the manufacturing process in some situations. In some embodiments, signal and / or sensing conductors can be stacked between other thermal and / or electrical conductors. Leads can be shaped to contact conductors adjacent to the die. For example, leads can be shaped to connect to one or more of a bottom heatsink, a top heatsink, a die clip, and / or a die plate. In some cases, gap conductors can be connected to the IC die. The IC die discussed herein is a semiconductor die.

[0095] Figures 1A-1D The use of gap conductors is shown in various example embodiments. Figure 1A A cross-section of an example device 100A according to some embodiments is shown. Figure 1AIn this embodiment, device 100A may include a bottom heat sink 102, a top heat sink 104, a gap conductor 106, and an IC die 108. The IC die 108 may be a semiconductor die. The IC die 108 may include one or more of the switches and / or transistors discussed herein. In some embodiments, the bottom heat sink 102, the top heat sink 104, or both may be used for thermal management. In some embodiments, the bottom heat sink 102, the top heat sink 104, or both may be used for electrical connection to the IC die 108. Figure 1A In the example, the bottom heatsink 102 and the top heatsink 104 can be used to provide electrical connections to the source and drain of the IC die 108. The gap conductor 106 can be used to provide signal and sensing conductors. Figure 1A As shown, the gap conductor 106 can be electrically connected (e.g., directly electrically connected) to the IC die 108.

[0096] Figure 1B A cross-section of another example embodiment of the example device 100B using a gap conductor is shown. Figure 1B In this configuration, device 100B may include a bottom heatsink 102, a top heatsink 104, a gap conductor 106, and an IC die 108. The gap conductor 106 may be connected to the top heatsink 104 via a connector 112. The connector 112 may include, for example, solder. The gap conductor 106 may be connected to the bottom heatsink 102 via a connector 110. The connector 110 may also include, for example, solder. In some configurations, the gap conductor 106 may be connected to either the bottom heatsink 102 or the top heatsink 104, but not both simultaneously. In such a configuration, only one of the connectors 110 or 112 may be included. Figure 1B The arrangement shown can be used for various purposes, such as sensing voltage or temperature.

[0097] Figure 1C A cross-section of another example device, 100C, is shown. Figure 1C In this device 100C, a bottom heat sink 102, a top heat sink 104, a gap conductor 106, and an IC die 108 may be included. The device may also include an additional component 114. The additional component 114 may be, but is not limited to, a thermistor for sensing internal temperature, another integrated circuit die, etc. The gap conductor 106 may be in electrical contact with one or both of the IC die 108 and the additional component 114.

[0098] Figure 1D Another cross-section of another example device, 100D, is shown. Figure 1DIn this configuration, the bottom heat sink 102 is absent and has been replaced by conductor 120. Conductor 120 is electrically connected to IC die 108 via top heat sink 104 and component 116, and conductor 118 can be electrically connected to IC die 108. In some embodiments, component 116 may be, for example, solder. In some embodiments, component 116 may include passive components such as resistors, capacitors, inductors, conductive spacers, pads, etc.

[0099] There are various possibilities for providing the gap conductor. For example, the gap conductor can be embedded (e.g., partially embedded) in resin, molding compound, etc. In some embodiments, the gap conductor can be exposed or partially exposed on one side of the device. In some embodiments, the gap conductor can be raised. In some embodiments, the gap conductor can be flat. pre-assembly of die clamps and lead frames

[0100] In some embodiments, die clips and lead frames can be used to provide various electrical connections. For example, the die clip, lead frame, or both may include source leads, gate leads, Kelvin source leads, thermistor leads, etc. In some embodiments, some leads (e.g., source leads) may be relatively large, while other leads (e.g., gate leads, sensing leads) may be relatively small. In some embodiments, die clips can be used for smaller contacts. Using die clips allows for electrical separation between source leads and other leads (e.g., gate leads, sensing leads). However, using separate die clips and lead frames can present some challenges. For example, additional processing steps may be performed to secure the die clip to the IC die and attach the die clip to the lead frame. These additional steps can provide opportunities for manufacturing defects, thereby reducing device yield.

[0101] In some methods, as part of the packaged IC device assembly process, the die clip components can be soldered, laser-welded, or otherwise secured together. The leadframe in any of the embodiments discussed below can be... Figures 1A to 1D The top heatsink of any suitable embodiment. The die board in any of the embodiments discussed below can be... Figures 1A to 1D The heat sink can be any suitable embodiment. The die clamp of any embodiment discussed below can be... Figures 1A to 1D Any suitable embodiment of the gap conductor or heat sink.

[0102] Figure 2A An exploded view of an example of a packaged IC device 200A according to some embodiments is shown. Figure 2AAs shown, a packaged IC device may include a lead frame 201, a die clip 204, a die clip solder 206, an IC die 208, a die attachment solder 210, a die board 212, and a housing 214. The IC die 208 may also be referred to as a semiconductor die. In some embodiments, the packaged IC device 200A may include additional components, such as a thermistor die clip 216, a thermistor die clip solder 218, a thermistor die 220, and a thermistor solder 222. As described in more detail herein, in some embodiments, the lead frame 201 and the die board 212 may be assembled prior to the assembly of the packaged IC device. In some embodiments, the die board 212 and the housing 214 may be assembled prior to the assembly of the packaged IC device.

[0103] In some examples, the lead frame 201 and die plate 212 of the packaged IC device 200A can be referred to as a double-sided heat dissipation structure. In some cases, the packaged IC device 200A may include an IC die 208, a die plate 212, and a lead frame 201. The die plate 212 may be formed of a thermally conductive material and is referred to as a heat sink. In some embodiments, the lead frame 201 may be positioned on one side of the IC die 208, and the die plate 212 may be positioned on the opposite side of the IC die 208. In some cases, the die plate 212 is positioned within the coverage area of ​​the lead frame 201.

[0104] Figure 2B An exploded view of components of an example packaged IC device 200B according to some embodiments is shown. Figure 2B As shown, the packaged semiconductor element 250 can be mounted on the lead frame 202A. In some embodiments, the lead frame 202A may provide electrical contacts for electrical connection to terminals (such as drain, source, gate, and / or Kelvin source terminals) of the IC die 208. Furthermore, the lead frame 202A may also provide electrical contacts for electrical connection to the thermistor 220.

[0105] like Figure 2B As shown, the packaged semiconductor element 250 may include a heat sink die clip 252, a bonding layer 254 (e.g., die back and spacer solder), a spacer 256, an IC die 208, and a bonding layer 258 (e.g., die back and spacer solder). In some examples, the bonding layers 254 and 258 may be formed based on a pattern that may include multiple regions to provide electrical connections to corresponding die connection terminals (e.g., contact terminals), such as the source (including Kelvin source), drain, and gate of the IC die 208. In some examples, the bonding layers 254 and 258 may be formed of a conductive material, such as, but not limited to, solder, conductive epoxy, etc. In some embodiments, the packaged semiconductor element 250 may also include a thermistor die 220 and a thermistor die clip 216.

[0106] Leadframe 202A may include various electrical contacts. Leadframe 202A may include conductive frames, such as leadframes for packaging semiconductor element 110. These frames may be implemented using a pattern that provides terminals (such as drain, source, and gate) for the IC die 208. Figure 2B (not shown) and / or electrical contacts of the terminals of the thermistor die 220.

[0107] Further reference Figure 2B In some examples, field-effect transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., GaN MOSFETs) can be implemented on IC die 208. Therefore, IC die 208 may include terminals such as drain, source, Kelvin source, and gate. In some cases, bonding layer 254 may be assembled (e.g., bonded) on top of IC die 208. Furthermore, bonding layer 258 may be configured to bond IC die 208 to lead frame 202A. In some applications, bonding layers 254 and 258 may be formed using the same type of molding material (e.g., conductive molding material).

[0108] In some embodiments, the lead frame 202A may have flat leads, such as... Figure 2B The flat leads 270 and 280 are shown. For example, one side (e.g., the bottom side) of leadframe 202A may have flat lead 270, and the other side (e.g., the top side) of leadframe 202A may have flat lead 280. In some examples, flat lead frames 270 and 280 extend outside the heat sink clip 252. For example, when packaged semiconductor element 250 is assembled on leadframe 202A, flat lead frames 270 and 280 extend outside the packaged semiconductor element 250. In some examples, according to embodiments disclosed herein, flat lead 270 may include source leads, gate leads, Kelvin source leads, and sensing leads. In some applications, the sensing lead may be a temperature sensing lead electrically connected to the thermistor die 220. According to embodiments disclosed herein, flat lead 280 may include a drain lead. For example, Figure 7 The detailed physical layout of the leads and lead frames is provided.

[0109] In some embodiments, the flat leads 270 and 280 of the leadframe 202A can make the profile of the packaged IC device 200B thinner (e.g., lower profile). In some examples, the flat leads 270 and 280 can serve as electrical contacts (e.g., terminals) of the packaged IC device 200B, wherein the flat leadframe has an appropriate thickness to facilitate the transmission of generated signals or electrical power. For example, the thickness of the flat leads 270 and 280 can be a minimum of 5 mils or 0.127 mm. In some examples, the flat leads may include wettable sides.

[0110] Figure 3 An example semiconductor assembly corresponding to the steps of the assembly process of packaged IC device 200A is shown. In step 302, solder can be printed onto a die board, and the die can be placed on the solder. For example, a first reflow process can be performed by heating. After the first reflow process, in step 304, solder can be printed, and the die clip can be positioned in place (e.g., partially on the die). In step 306, a second reflow process can be performed to secure the die clip to the die. In step 308, solder can be printed, and the lead frame can be positioned. In step 310, a third reflow process can be performed to secure the lead frame. In some cases, steps 312 and 314 can be performed to include a thermistor assembly, which may result in one or more additional reflow steps.

[0111] Figure 3 The process described may have several drawbacks. For example, alignment errors may occur each time an additional component is added. In some cases, components may move during the processing steps. For example, components may move during the reflow step. The number of reflow steps affects the choice of solder and other materials. For example, the first reflow step may preferably use a solder (e.g., solder paste) with a higher melting point than the solder used in subsequent reflow steps, so that the first solder does not become fluid again in subsequent reflow steps.

[0112] Several benefits can be achieved by reducing the number of steps involved in assembling packaged IC devices. For example, assembly time can be reduced. Yield can also be increased due to a lower chance of errors. In some cases, components can be prepared prior to the final assembly process, and only known good components can be used in the final assembly. For example, in some embodiments, leadframe 201 and die clamp 204 can be secured to each other in a process separate from the packaged IC device assembly process. Laser welding, ultrasonic welding, or other suitable bonding methods allow the combination of thin, delicate structures bonded to the die (or other components) to be pre-coupled as needed to other conductors of other thicknesses (e.g., providing source or drain connections). For multilayer stacked components, this can reduce handling and misalignment as the components are stacked together.

[0113] Figure 4An example combined leadframe structure 400 is shown, which includes a leadframe 201 and a die clamp 204. The die clamp 204 can be secured to the leadframe 201 in various ways, such as by welding (e.g., laser welding, ultrasonic welding, or any other suitable welding) or any other suitable joining method. In some embodiments, the die clamp 204 may include electrical contacts to terminals of an IC die 208. Furthermore, the leadframe 201 may include a plurality of leads, and each lead is connected to one of the electrical contacts of the die clamp 204. In some examples, such as... Figure 4 As shown, lead frame 201 may include source lead 402A or two source leads 402A and 402B. Lead frame 201 may also include gate lead 404, Kelvin source lead 406, and thermistor connector 408. Thermistor connector 408 is an example of a sensing lead.

[0114] In some embodiments, die clip 204 may be assembled with lead frame 201. Die clip 204 may be connected to electrical terminals of IC die 208 at one or more contact points (such as contact point 422). Contact point 422 may be electrically connected to terminals of IC die 208. Figure 4 Provided only as an example embodiment, and the die clip 204 may have various contact points for electrical connection to the terminals of the IC die 208, such as drain, source, and gate terminals and / or Kelvin source terminals. This disclosure does not necessarily limit the configuration (or layout or pattern) of the die clip 204.

[0115] Lead 410 must not extend beyond the packaged IC device and cannot be used for electrical connections. Kelvin source lead 406 can be stepped down and soldered to leadframe 201 to sense the voltage of leadframe 201. It should be understood that... Figure 4 This is merely an example; in practice, the number of leads can vary, and leads can be used to supplement or replace other leads. Figure 4 The lead wire shown.

[0116] In some embodiments, the lead frame 201 and the die clamp 204 may be pre-joined, for example at connection points 412A-412E. Connection points 412A-412E may be, for example, laser-welded connectors. Furthermore, connection points 412A-412E may serve as alignment points between the lead frame 201 and the die clamp 204. By pre-joining the lead frame 201 and the die clamp 204, the manufacturing process can be improved, for example, by reducing the number of reflow steps. Figure 3 Step 304 (welding process) and Figure 3The reflow process in step 306 can be eliminated by pre-bonding the leadframe 201 and die clamp 204. When the leadframe 201 and die clamp 204 are pre-bonded by soldering, there should be no solder between the leadframe 201 and die clamp 204. Therefore, the semiconductor package can be without solder between the leadframe 201 and die clamp 204. After the leadframe 201 and die clamp 204 are bonded, the die clamp 204 can be soldered to the IC die 208. The leadframe 201 and die clamp 204 can be soldered in the same reflow step.

[0117] The die clamp 204 may include openings at connection points 412A-412E. These openings facilitate soldering of the die clamp 204 and the lead frame 201. Figure 4 In the figure, die clamp 204 includes a first opening 424A corresponding to gate lead 404. As shown, die clamp 204 and gate lead 404 can be joined at the first connection point 412A among connection points 412A-412E. Die clamp 204 may include a second opening 424B corresponding to Kelvin source lead 406. Die clamp 204 and Kelvin source lead 406 can be joined at the second connection point 412B among connection points 412A-412E. Die clamp 204 may include an opening 424C corresponding to a third connection point 412C for joining lead 410, and an opening 426D corresponding to a fourth connection point 412D and a fifth connection point 412E for joining source leads 402A and 402B. In some embodiments, laser welding can be applied to the openings at connection points 412A-412E (e.g., by using a thinner welding material over each opening). In some applications, welding can be performed along the side, or special weld sheet shapes can be used to minimize welding deformation.

[0118] Furthermore, for multi-stacked component applications, the pre-bonded leadframe 201 and die clamp 204 can reduce processing by fewer assembly steps and can reduce the risk of misalignment at each layer of the stack on the component. In some embodiments, defective pre-bonded leadframes may be rejected and cannot be used to manufacture devices. In some embodiments, defective pre-bonded leadframes may be reworked before use to correct any problems.

[0119] In some embodiments, one or more additional leads may extend from the source portion 402B of the lead frame 201. Figure 4 (Not shown in the image). In such an embodiment, gate lead 404, Kelvin source lead 406, thermistor lead 408, and lead 410 may be located between the two source leads.

[0120] Figure 5A and Figure 5BBottom and top views of example packaged IC devices according to some embodiments are shown respectively. Figure 5A As shown, a packaged IC device may include a lead frame 201, a die board 212, a housing 214, source leads 402, and leads 502. In some cases, leads 402 and 502 may extend outside the housing 214. In some embodiments, the lead frame 201 may be at least partially exposed on the bottom surface of the packaged IC device, although in other embodiments, the lead frame 201 may not be exposed (e.g., only the source leads 402 may be exposed, rather than a larger portion of the lead frame 201). The packaged IC device may include leads 502, which may include, for example, one or more thermistor leads, one or more gate leads, one or more Kelvin source leads, etc. Components of the packaged IC device may be disposed within the housing 214. In some embodiments, additional leads may extend from the source portion 402B of the lead frame 201 ( Figure 5A (Not shown in the image).

[0121] like Figure 5B As shown, in some embodiments, the die board 212 may be at least partially exposed on the top surface of the packaged IC device. In some embodiments, the die board 212 may not be partially exposed. For example, the top surface may be completely surrounded by the housing 214. In some embodiments, the die board 212 may function as a heat sink. In some embodiments, a separate heat sink may be used. For example, in some embodiments, the die board 212 may not extend vertically to the top surface of the packaged IC device, and a separate heat sink may be placed on top of the die board 214 and may be in thermal communication with the die board 212.

[0122] In some conventional methods used to manufacture packaged IC devices, electronic components can be assembled in early steps, and after assembly, the electronic components can be packaged (e.g., partially packaged) in a housing. However, in some embodiments, it can be advantageous to form the housing at least partially before assembling all electronic components. For example, in some embodiments, the die board and housing can be formed before assembling the various components of the packaged IC device. In some embodiments, a pre-molded die board can be partially overmolded, which can encapsulate high-voltage surfaces.

[0123] Pre-molded die plates and their associated housings can offer several advantages. For example, pre-molding can create flanges or other inward or outward features that can be used to hold other components in precise position, height, or both. This can reduce defects that may occur during manufacturing, such as during transport, during solder paste placement, during sub-assembly stacking, during reflow steps, etc., caused by movement, displacement, tilting, denting, etc. In some embodiments, the pre-molded lead frame can act as a dam or cavity, which can help contain flowable sealants that can be used for various purposes, such as localized stress reduction on the die, sealing (e.g., low-hardness die sealant or "spherical top"). For example, a less rigid sealant can be used to protect some components from the effects of more rigid molding compounds that may be used in subsequent steps.

[0124] Figure 6A and Figure 6B Bottom and top views of a pre-molded core plate 600 according to some embodiments are shown. Figure 6A As shown, the pre-molded die board 600 may include a die board 212 and a housing 214. The die board 212 may include a drain contact 602. In the illustrated example, a single large drain contact is depicted. However, it should be understood that multiple drain contacts may be present. In some embodiments, the die board 212 may include other contacts in addition to or in lieu of the drain contact 602. Figure 6B As shown, in some embodiments, the die board 212 may be partially exposed and may be used as a heat sink.

[0125] Figure 6C An example of a pre-molded die board 600 is shown after the die clamp 204 and die clamp solder 206 have been placed. Figure 6C As shown, flange 604 can support die clamp 204, which can help hold die clamp 204 in the proper position and at the desired height.

[0126] Figure 6D Examples of multiple pre-molded mandrel plates 600 are shown. Lead frames 600 can be attached to a support frame 606. The support frame 606 can be used during manufacturing to facilitate the transport, positioning, alignment, etc., of the pre-molded lead frames. The support frame 606 itself may include a molding resin channel structure for injecting resin into multiple mold cavities, commonly referred to as a runner system. Thermal stress management

[0127] Thermal stress management is crucial in semiconductor devices. It is particularly challenging in high-power semiconductor devices, which operate over relatively wide temperature ranges. Uneven thermal stress can lead to increased device wear, shortened lifespan, and even malfunctions, such as die cracking or solder joint breakage. In some cases, thermal stress can cause delamination between the die and conductor.

[0128] In some embodiments, the leadframe and / or other structures (such as die locking slots, conductor leads, etc.) can be designed and shaped to be oriented and formed around the die center. In some embodiments, mechanical stress can be oriented radially or centrally. In some embodiments, a geometrically neutral point or center point can be established, and thermal expansion and contraction can be balanced around this point. By uniformly distributing stress around a point, the risk of device damage due to thermal stress can be reduced. In these embodiments, the leadframe can correspond to the leadframe 202A of the packaged IC device 200B. Figure 2B As shown, the packaged semiconductor element 250 may include at least an IC die 208 bonded above the lead frame 202A. Various slot patterns and / or structures can be implemented in the lead frame 202A as disclosed herein. For illustrative purposes, reference is made to... Figure 2B Feature description Figure 7 .

[0129] Figure 7 Illustrations are shown according to some embodiments Figure 2B An example of a packaged IC device 200B. The packaged IC device 200B includes a packaged semiconductor element 250 positioned over a conductive structure, such as a leadframe 202A, via a bonding layer 258. In some embodiments, an IC die 208 included in the packaged semiconductor element 250 may be positioned or bonded over a central portion 710 of the leadframe 202A. The central portion 710 of the leadframe 202A may be attached to the IC die 208. For example, lead contacts 712, 714, and 716 are electrically connected to the gate terminal and the Kelvin source terminal of the IC die 208, respectively.

[0130] Leadframe 202A may include multiple leads connected to terminals of IC die 208. In some examples, source leads 720A, 720B are electrically connected to the source terminals of IC die 208. Gate lead 724 of the multiple leads is connected to the gate terminal of IC die 208 via lead point 714. Additionally, Kelvin source lead 726 of the multiple leads is connected to the Kelvin source terminal of IC die 208 via lead point 716. In some examples, leadframe 202A may include one or more additional die-bonded portions located within central portion 710. For example, a sensing die or another component configured to sense electrical characteristics (such as voltage, current, power, etc.) of the IC die may be attached to one of the one or more additional die-bonded portions. For example, sensing lead 722 of the multiple leads is connected to the sensing terminal of the sensing die via lead point 712. In some cases, a thermistor die may be electrically coupled to leadframe 202A at location 730. A thermistor die can be an example of a sensing die. A thermistor die can be configured to sense the temperature of components, such as a packaged IC device, IC die 208, leadframe 202A, and / or any other components included in the packaged IC device. In some embodiments, leadframe 202A may include one or more additional leads for electrical connection to terminals(s) of an additional IC die(s). For example, thermistor lead 728 is electrically connected to the thermistor die via bridge 732 (e.g., wire or metal). In these embodiments, thermistor lead 728 can be used to sense the temperature of components included in the packaged IC device. Therefore, thermistor lead 728 is an example of a sensing lead. The number and type of additional dies and leads are illustrative only, and in some applications, more than one additional die or lead may be used.

[0131] Drain leads 740A and 740B can be electrically connected to the drain terminal of IC die 208. For example, Figure 2B The heat sink clip 252 shown may include a heat dissipation layer below its top surface. The heat dissipation layer may be formed of a conductive material. The heat dissipation layer can dissipate heat generated by the IC die 208. Furthermore, the heat dissipation layer may be electrically connected to the drain terminal of the IC die 208. In some embodiments, drain leads 740A and 740B may be connected to the heat dissipation layer. For example, the upper portion 740 of the lead frame 202A may be connected to the heat dissipation layer via a bonding layer 254, such that the bonding layer 254 is positioned between the upper portion 740 of the lead frame 202A and the heat dissipation layer.

[0132] like Figure 7As shown, leadframe 202A may include a plurality of slots 702 distributed on leadframe 202A. For example, the plurality of slots 702 may be distributed around the location where the die will be placed on the leadframe. As shown, the slots are radially oriented around the central portion 710 of leadframe 202A. The slots 702 may uniformly distribute stress around the center point of packaged IC device 200B. This can uniformly apply stress from coefficient of thermal expansion (CTE) mismatch on packaged IC device 200B. In some embodiments, a heat sink may be positioned on the side of IC die 208 opposite to leadframe 202A. For example, if IC die 208 is positioned above leadframe 202A, the heat sink may be positioned above IC die 208. Furthermore, if IC die 208 is positioned below leadframe 202A, the heat sink may be positioned above IC die 208. In addition, in these embodiments, each slot 702A-702K is at least partially positioned above or below the heat sink.

[0133] Alternatively or in another location, the tank can be located Figure 2A The packaged IC device 200A is implemented on a die board 212. In some embodiments, the die board 212 and the housing 214 of the packaged IC device 200A may be separate components. In some other embodiments, the die board 212 and the housing 214 may be a single component, for example... Figures 6A-6D The pre-molded lead frame 600. The die board 212 may include a plurality of slots distributed around the die board 212. For example, the plurality of slots may be distributed around the location where the die will be placed on the die board 212, for example, the slots may be oriented around a hot spot on the IC die, having Figure 7 Similar patterns to the plurality of slots 702 shown in and / or other embodiments.

[0134] Figures 8A-8G Various example patterns of slots implemented on the lead frame are shown. In some embodiments, the pattern and each shape of the slots can be designed and / or optimized to effectively distribute thermal stress on the lead frame. Figures 8A to 8G Lead frames 202A to 202G, implementing the example patterns, are shown respectively. These different patterns and shapes of the slots can be designed and / or optimized to uniformly distribute thermal stress on the lead frame due to CTE mismatch without creating concentrated thermal stress in specific portions of the lead frame. Reference Figures 8A to 8G Any suitable principles and advantages discussed can be implemented together. For example, one embodiment may include one or more slots from one embodiment of these embodiments and one or more slots from another embodiment of these embodiments.

[0135] Figure 8A A packaged IC device 200B with radially distributed slots 702A-702K in a lead frame 202A is shown. Figure 8A Including with Figure 7 The same semiconductor package. Leadframe 202A is also included. Figure 2B As shown in the figure. In some embodiments, slots 702A-702K are radially distributed around the central portion 710 where the IC die 208 is located. In some embodiments, each slot in slots 702A-702K may have a rectangular shape. In some examples, the length of each slot in slots 702A-702K is greater than the width of each slot in slots 702A-702K. In some cases, two or more slots 702A-702K may have different lengths and / or widths. In some embodiments, each slot in slots 702A-702K has a length in a direction away from a point (such as the center point) and a width in a direction perpendicular to the length. In these embodiments, the length of each slot may be longer than its width.

[0136] Figure 8B A packaged IC device 200C with a leadframe 202B is shown. The leadframe 202B may include distributed slots 820A-820F, such as... Figure 8B As shown. Slots 820A-820F typically have an asterisk pattern. For illustrative purposes, Figure 8B A bottom view of the packaged IC device 200C (bottom view of the lead frame 202B) is shown. In some embodiments, slots 820A-820F are distributed around a central portion 710, wherein the IC die 208 is positioned on opposite sides of the central portion 710. In some embodiments, slots 820A, 820C, and 820E may be adjacent to or abut against corresponding corners of the central portion 710. Furthermore, slots 820B, 820D, and 820F may extend beyond corresponding sides of the central portion 710. Each slot in slots 820A-820F may have a rectangular shape. As shown, the length of each slot in slots 820A-820F is greater than the width of each slot in slots 820A-820F. In some cases, two or more slots in slots 820A-820F may have different lengths and / or widths.

[0137] In some embodiments, such as Figure 8BFurther shown, a portion of each of the slots 820A-820F may be located within the central portion 710 of the lead frame connected to the IC die. For example, portions 822A-822F of the corresponding slots 820A-820F are located within the central portion 710. In some embodiments, each portion of portions 822A-822F may be a path for injecting die coating material during manufacturing. For example, the die coating material may flow into the edge of the IC die 208. The die coating material flow may be a capillary flow, passing through the slots and reaching adjacent edges around the die corners. The die coating material may be a primer and is configured to mitigate thermal stress on the central portion 710 of the lead frame 202B. Furthermore, the die coating material may provide a CTE buffer layer on the lead frame 202B. In some embodiments, the die coating material has a low viscosity, thus allowing the die coating material to drip through portions 822A-822F (e.g., through the bottom of the packaged IC device 200C, e.g., as shown in the image). Figure 8B (As shown) the die coating material can flow into the IC die 208 via gravity or capillary action. In some embodiments, the die corners along the edge of the IC die 208 can be areas of electrical or mechanical stress, therefore, for example, as Figure 8B As shown, placing slots 820A-820F and corresponding portions 822A-822F on these areas can alleviate electrical and mechanical stresses on the IC die 208. The die coating material can be any suitable commercial material, such as a polyimide-silicone copolymer, and those skilled in the art of semiconductor assembly can select the die coating material from commercially available materials. This disclosure does not limit the type of die coating material.

[0138] Figure 8C A packaged IC device 200D with a lead frame 202C is shown. The lead frame 202C may include distributed slots 830A-830F. Figure 8C A bottom view of a packaged IC device 200D is shown. In some embodiments, slots 830A-830F are distributed around a central portion 710, wherein an IC die 208 is positioned on opposite sides of the central portion 710. In some embodiments, slots 830A, 830C, and 830E may be adjacent to or abut against corresponding corners of the central portion 710. Furthermore, slots 830B, 830D, and 830F may extend beyond three sides of the central portion 710. In some embodiments, at least one of the slots 830A-830F may have a semi-circular shape. For example, as... Figure 8CAs shown, slot 830F may have a semi-circular shape, and a semi-circular portion 832F may be located within the central portion 710. A portion of slot 830F may not extend through the entire thickness of the lead frame 202C, and only the rectangular portion of slot 830F may extend through the entire thickness of the lead frame 202C. In some examples, at least one of slots 830A-830F may have a rectangular shape. For example, slots 830A-830E may have a rectangular shape, and each rectangular slot in slots 830A-830E may each have a portion 832A-832E located above the central portion 710. Any or all of the rectangular slots 830A-830E may have rounded corners. As shown, the length of each rectangular slot in slots 830A-830E may be greater than the width of each slot in slots 830A-830E. In some cases, two or more slots in slots 830A-830E may have different lengths and / or widths.

[0139] In some embodiments, during manufacturing, die coating material can be injected through grooves 830A-830F. For example, die coating material can be dispensed by dripping or spraying during manufacturing. The liquid die coating material can be collected and delivered between the lead frame 202C and the clip structure to present the liquid die coating material to the edge of the IC die. For example, groove 830F may have a slope that allows the die to pass through a rectangular portion extending through the entire thickness of the lead frame 202C.

[0140] Figure 8D An example of a leadframe 202D with distributed slots 840A-840E is shown. For example, leadframe 202D can replace leadframe 202A in packaged IC device 200B. Leadframe 202D can be implemented in any other suitable packaged IC device. Leadframe 202D includes slots 840A-840E. Slots 840A-840E of leadframe 202D can balance radial expansion and / or contraction due to CTE mismatch around the points of the packaged IC device. During manufacturing, a liquid die coating and / or adhesion promoter can be distributed through slots 840A-840E of leadframe 202D. Slots 840A-840E can facilitate structural bonding of molding compounds on the conductors of leadframe 202D. Slots 840A to 840E can be implemented according to any suitable principles and advantages disclosed herein. Each of slots 840A-840E can have a generally rectangular shape. The corners of slots 804A-8040E can be rounded. A portion 842A-842E of each slot in slots 840A-840E can overlap with the coverage area of ​​the semiconductor die, respectively.

[0141] Figure 8EAn example of a leadframe 202E with distributed slots 850A-850F is shown. Leadframe 202E can be implemented based on any suitable principles and advantages disclosed herein. For example, leadframe 202E can replace leadframe 202A in packaged IC device 200B. Leadframe 202E includes slots 850A-850F distributed at points around the packaged IC device. Slots 850A-850F have a pattern different from the slots in other example embodiments. Slots 850A-850F can implement any suitable function of the slots disclosed herein. A portion 852A-852E of the corresponding slots 850A-850E can overlap with the coverage area of ​​the IC die.

[0142] Figure 8F An example of a leadframe 202F with distributed slots 860A-860D is shown. Leadframe 202F can be implemented based on any suitable principles and advantages disclosed herein. For example, leadframe 202E can replace leadframe 202A in packaged IC device 200B. Slots 860A-860D have patterns and shapes different from those of the slots in other example embodiments. In some embodiments, slots 860A-860D are positioned at each corresponding corner of the central portion 710 of leadframe 202F where IC die 208 is located. In some embodiments, each slot in slots 860A-860D may have a circular shape. In some examples, two or more slots in slots 860A-860D may have different diameters. In some embodiments, two or more slots in slots 860A-860D may have substantially the same diameter.

[0143] Figure 8G An example of a leadframe 202G with distributed slots 870A-870G is shown. Leadframe 202G can be implemented based on any suitable principles and advantages disclosed herein. For example, leadframe 202E can replace leadframe 202A in packaged IC device 200B. Figure 8G As shown, slots 870A-870G are radially distributed around the central portion 710 where the IC die 208 is located. In some embodiments, each slot in slots 870A-870G may be curved or arcuate. In some applications, a portion of one or more slots may be curved or arcuate. In some cases, two or more slots in slots 870A-870G may have different shapes and / or sizes. In some embodiments, two or more slots in slots 870A-870G may have the same shape and / or size. Power and signal

[0144] Integrated circuit packages are typically integrated into larger circuits that may include many components. Arranging these components can be challenging due to the potential need for thermal management, electrical connection management, or both. In some cases, the placement of various electronic components on a circuit board (e.g., on a printed circuit board) may be limited by specifications related to thermal performance, electrical wiring, or both. In some cases, the cost of a printed circuit board may be influenced by the components used on the board and their arrangement. For example, complex electrical wiring may involve multiple layers. In some cases, placing components close to each other can be beneficial, for example, to reduce signal loss that may occur as it propagates from one component to another.

[0145] In some embodiments, components can be arranged in series. For example, the drain of the first component can be connected to the source of the second component. In power electronic devices using components arranged in series, it may be desirable to place the drain of the first component as close as possible to the source of the second component. However, doing so can present some challenges. For example, aligning the source and drain might be straightforward if they were the only electrical connection, but in practice, many electronic components have other connections, such as gates, Kelvin sources, thermistors, etc. One or more other connections can be achieved by gap conductors positioned between heat sinks, for example, as referenced. Figures 1A to 1D The discussion is ongoing. Alternatively or additionally, one or more other connections may be implemented using any die clip disclosed herein. According to some embodiments, a pocket may be provided that enables tight, head-to-toe connections of components, allowing connection of the source and drain of adjacent components while facilitating other electrical connections (e.g., gate, sensing pin, etc.) while avoiding power conduction paths, including high voltage potential differences between conductors and involving the implementation of minimum spacing or pitch.

[0146] Although source and drain leads may be discussed below, any suitable principles and advantages discussed with reference to source and drain leads can be applied to emitter and collector leads or any other suitable lead group. Source and drain leads can be used with packaged IC devices containing field-effect transistors. Such field-effect transistors can be included in power electronic devices, such as inverters that generate AC voltage from DC voltage (or vice versa). For illustrative purposes, reference may be made to... Figure 2B and Figure 7 To describe the characteristics Figures 9-10 .

[0147] Figure 9 A simplified pinout example according to some embodiments is shown. For example... Figure 9As shown, the semiconductor device may have a first source lead 902, a second source lead 904, and a gate lead 906 disposed on one side of the semiconductor device. A drain lead 908 may be disposed on the opposite side of the device. In a series arrangement, the drain lead 908 of the first semiconductor device may be connected to the first source lead 902 and the second source lead 904 of the second semiconductor device. In some embodiments, only a single source lead may exist. In some embodiments, additional leads may be provided.

[0148] Figure 10 An example of a head-to-toe arrangement of a semiconductor device according to some embodiments is shown. Figure 10 In the configuration, the first packaged IC device 200B-1 and the second packaged IC device 200B-2 are arranged in a top-to-bottom configuration. Each of the first packaged IC device 200B-1 and the second packaged IC device 200B-2 may be... Figure 2B and Figure 7 The packaged IC device shown is 200B.

[0149] The first packaged IC device 200B-1 may include a first source lead 720A, a second source lead 720B, a gate lead 724A, a Kelvin source lead 726A, a thermistor lead 728A, and a sensing lead 722A. On opposite sides, the first device 200B-1 may have a first drain lead 740A and a second drain lead 740B. The second packaged IC device 200B-2 may have a first source lead 720C, a second source lead 720D, a gate lead 724B, a Kelvin source lead 726B, a thermistor lead 728B, and a sensing lead 722B disposed on a first side of the second packaged IC device 200B-2. The second packaged IC device 200B-2 may have a first drain lead 740A and a second drain lead 740D disposed on a second side opposite to the first side.

[0150] like Figure 10 As shown, the first drain 740A of the first packaged IC device 200B-1 can be electrically connected to the first source lead 720C of the second packaged IC device 200B-2, and the second drain 740B of the first packaged IC device 200B-1 can be electrically connected to the second source lead 720D of the second packaged IC device 200B-2. Electrical connections to the gate lead 724B, Kelvin source lead 726B, thermistor lead 728B, and sensing lead 722B can be provided without intersecting the power conduction path defined by the positions of the source and drain of the first packaged IC device 200B-1 and the second packaged IC device 200B-2. The power conduction path is provided by the PCB.

[0151] Despite Figure 10In the packaged IC device, the first packaged IC device 200B-1 and the second packaged IC device 200B-2 include thermistor leads 728A and 728B, Kelvin source leads 726A and 726B, and sensing leads 722A and 722B. However, in some other applications, one or more of these leads may be omitted, and / or in some applications, one or more other leads may be included between source leads 720A and 720B. For example, if a thermistor die is not implemented in one or both of the first packaged IC device 200B-1 and the second packaged IC device 200B-2, thermistor leads 728A and 728B may be omitted.

[0152] Figure 10 Thermal management features for managing thermal expansion and / or contraction are also illustrated. In some embodiments, each of the first packaged IC device 200B-1 and the second packaged IC device 200B-2 may include any suitable conductive layer for the thermal management features, such as Figures 8A-8D Any slot pattern shown. In some examples, the first packaged IC device 200B-1 and the second packaged IC device 200B-2 may have the same slot pattern as each other.

[0153] Figure 11 An example of a packaged IC device according to an embodiment is shown. Figure 11 The diagram shows a lead frame 202B (as shown). Figure 8B A view of the packaged IC device 202 (shown). Figure 11 The packaged IC device shown can be implemented based on any suitable principles and advantages disclosed herein. In some examples, according to some embodiments, the packaged IC device can be implemented such that it can be mounted on a printed circuit board (PCB). Figure 11 Surface-mount devices (not shown). For example, in Figure 11 In this process, surface mount packaged IC devices can be mounted onto a PCB. Before mounting to the PCB, mounting epoxy resin can be applied to the surface of the surface mount packaged IC device. The PCB may include contact pads for electrical coupling to the packaged IC device via multiple leads (e.g., source leads 720A, 720B, sense lead 722, gate lead 724, Kelvin source lead 726, and drain leads 740A, 740B). Slots 820 (e.g., slots 820A-820F, such as...) Figure 8B (As shown) can provide a continuous load path through the lead frame, which can reduce and / or prevent the lead frame from delaminating with the molding material under thermal stress. Additional Examples

[0154] In the foregoing specification, this disclosure has been described with reference to specific embodiments. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of this disclosure. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0155] In fact, although this disclosure is made in the context of certain embodiments and examples, those skilled in the art will understand that the invention is not limited to the specifically disclosed embodiments, but extends to other alternative embodiments and / or uses of the invention and its equivalents. Furthermore, while several variations of the embodiments have been shown and described in detail, other modifications within the scope of this disclosure will be readily apparent to those skilled in the art based on this disclosure. It is also conceivable that various combinations or sub-combinations of specific features and aspects of the embodiments can be made, and such combinations or sub-combinations still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined or substituted with each other to form different modes of the various embodiments disclosed herein. No method disclosed herein needs to be performed in the order described. Therefore, the scope of this disclosure should not be limited to the specific embodiments described above.

[0156] It should be understood that each of the systems and methods disclosed herein has several innovative aspects, none of which is solely responsible for or requires the desired properties disclosed herein. The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure.

[0157] Some features described in this specification in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, or even initially claimed in this way, in some cases, one or more features in the claimed combination may be removed from the combination, and the claimed combination may refer to a sub-combination or a variation of the sub-combination. For each embodiment, no single feature or set of features is necessary or indispensable.

[0158] It should also be understood that, unless otherwise specifically stated or understood in the context of use, the conditional language used herein (such as “can,” “could,” “might,” “may,” “eg,” etc.) is generally intended to convey that certain embodiments include certain features, elements, and / or steps that are not included in other embodiments. Therefore, such conditional language does not generally imply that one or more embodiments require features, elements, and / or steps in any way, or that one or more embodiments must include logic for determining whether to include or perform such features, elements, or steps in any particular embodiment, with or without author input or prompting. The terms “comprising,” “including,” “having,” etc., are synonyms and are used inclusively in an open-ended manner, not excluding other elements, features, behaviors, operations, etc. Furthermore, the use of the term “or” is inclusive (not exclusive); therefore, when used to connect a series of elements, the word “or” refers to one, some, or all of the elements in the list. Furthermore, unless otherwise stated, the articles “a,” “an,” and “the” used in this application and the appended claims should be interpreted as “one or more” or “at least one.” Similarly, while operations may be depicted in a specific order in the drawings, it should be understood that it is not necessary to perform these operations in the specific order shown or sequentially, or to perform all of the operations shown, in order to achieve the desired result. Furthermore, the drawings may schematically depict another example process in the form of a flowchart. However, other operations not shown may be incorporated into the schematically depicted example methods and processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the operations shown. Furthermore, in other embodiments, operations may be rearranged or reordered. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated into a single software product or packaged into multiple software products. Furthermore, other embodiments are within the scope of the following claims. In some cases, the actions described in the claims may be performed in a different order and may still achieve the desired result.

[0159] Furthermore, while the methods and apparatus described herein are readily available in various modifications and alternative forms, specific examples have been shown in the accompanying drawings and described in detail herein. However, it should be understood that this disclosure is not limited to the particular forms or methods disclosed, but rather covers all modifications, equivalents, and alternatives falling within the spirit and scope of the various implementations described and the appended claims. Furthermore, any particular feature, aspect, method, property, characteristic, quality, attribute, element, etc., disclosed herein in relation to an implementation or embodiment may be used in all other implementations or embodiments set forth herein. No method disclosed herein needs to be performed in the order described. Methods disclosed herein may include certain actions taken by a practitioner; however, these methods may also include any third-party instructions regarding these actions, whether express or implied. The scope of this disclosure also includes any and all overlapping, sub-scopes, and combinations thereof. Languages ​​such as “up to,” “at least,” “greater than,” “less than,” “between,” etc., include referenced numbers. Numbers preceded by terms such as “about” or “approximately,” include referenced numbers and should be interpreted as appropriate (e.g., as accurate as possible in this case, such as ±5%, ±10%, ±15%, etc.). Phrases beginning with terms such as “substantially” include the cited phrases and should be interpreted according to the specific circumstances (e.g., as reasonably as possible within the given context). For example, “substantially constant” includes “constant”. Unless otherwise stated, all measurements are performed under standard conditions, including temperature and pressure.

[0160] As used herein, the phrase “at least one of” in a list of items refers to any combination of those items, including a single member. For example, “at least one of A, B, or C” is intended to cover: A, B, C, A and B, A and C, B and C, and A, B, and C. Unless otherwise specified, conjunctions such as “at least one of X, Y, and Z” should be understood in conjunction with the context in which items, terms, etc., can be at least one of X, Y, or Z. Therefore, such conjunctions do not generally imply that some embodiments require the presence of at least one of X, at least one of Y, and at least one of Z. The headings (if any) provided herein are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0161] Therefore, the claims are not intended to be limited to the embodiments shown herein, but should be given the widest scope consistent with this disclosure, the principles and novel features disclosed herein.

Claims

1. A semiconductor package comprising: a semiconductor die comprising a field effect transistor; a molding material; and a conductive structure at least partially stacked with the semiconductor die, the conductive structure comprising a plurality of slots positioned around a point of the semiconductor die, the plurality of slots configured to equalize thermal stress around the point of the semiconductor die during operation of the semiconductor die, the thermal stress associated with a coefficient of thermal expansion mismatch between the conductive structure and the molding material, and at least a portion of the molding material in contact with the conductive structure.

2. The semiconductor package of claim 1, wherein the plurality of slots are oriented in a radial pattern around the point of the semiconductor die.

3. The semiconductor package of claim 1, wherein each slot of the plurality of slots has a length in a direction away from the point and has a width in a direction perpendicular to the length, the length being longer than the width.

4. The semiconductor package of claim 1, further comprising a heat sink on a side of the semiconductor die opposite the conductive structure, wherein each slot of the plurality of slots is at least partially positioned over the heat sink.

5. The semiconductor package of claim 1, wherein each slot of the plurality of slots is at least partially positioned over the semiconductor die.

6. The semiconductor package of claim 1, wherein the conductive structure is a leadframe.

7. The semiconductor package of claim 6, wherein the leadframe comprises a plurality of leads along a side of the semiconductor package, the plurality of leads comprising two source leads, a sense lead positioned between the two source leads, and a gate lead positioned between the two source leads.

8. The semiconductor package of claim 6, further comprising a die clip positioned between the semiconductor die and a portion of the leadframe, wherein the die clip and the leadframe are joined at a junction.

9. The semiconductor package of claim 1, wherein the conductive structure is a die plate.

10. A semiconductor package comprising: a semiconductor die; a molding material; and a leadframe at least partially stacked with the semiconductor die and comprising a plurality of slots positioned around a point of the semiconductor die, the plurality of slots configured to equalize thermal stress around the point of the semiconductor die, and at least a portion of the molding material in contact with the leadframe.

11. The semiconductor package of claim 10, wherein the plurality of slots are oriented in a radial pattern around the point of the semiconductor die.

12. The semiconductor package of claim 10, wherein at least one slot of the plurality of slots has a rectangular shape.

13. The semiconductor package of claim 10, wherein each slot of the plurality of slots has a length in a direction away from the point and has a width in a direction perpendicular to the length, the length being longer than the width. ​ ​ 14. The semiconductor package of claim 10, wherein the point is a center point of the semiconductor package.

15. The semiconductor package of claim 10, further comprising a heat spreader on a side of the semiconductor die opposite the leadframe, wherein each slot of the plurality of slots is positioned at least partially over the heat spreader.

16. The semiconductor package of claim 10, wherein two or more slots of the plurality of slots have different lengths.

17. The semiconductor package of claim 10, wherein the semiconductor die comprises a field effect transistor, and wherein the leadframe comprises a plurality of leads including two source leads electrically connected to a source of the field effect transistor, a gate lead electrically connected to a gate of the field effect transistor, and a sense lead, and wherein the plurality of leads are positioned on a first side of the leadframe, and wherein the gate lead and the sense lead are positioned between the two source leads.

18. The semiconductor package of claim 10, wherein the thermal stress is caused by a coefficient of thermal expansion (CTE) mismatch between the leadframe and the molding material.

19. The semiconductor package of claim 10, further comprising a thermistor electrically connected to a sense lead of the leadframe.

20. The semiconductor package of claim 10, further comprising a die coat material positioned between the die and the leadframe, the slots being sized to allow injection of the die coat material through the slots during manufacturing.

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