Chip testing system and method and related equipment

Abstract

The invention provides a chip testing system and method and related equipment, and the system comprises a probe assembly which comprises a probe and is used for being connected with a chip; the testing device is connected with the probe assembly and is used for testing the chip through the probe assembly; a limiting groove is formed in the upper surface of the carrier plate and used for containing a chip, a communicating groove is formed in the side wall of the limiting groove, the communicating groove extends in the depth direction of the limiting groove and penetrates through the upper surface of the carrier plate, and the bottom wall, in the depth direction of the limiting groove, of the communicating groove is flush with the groove bottom of the limiting groove. The width of the communication groove is smaller than that of the limiting groove, so that the probe is separated from the chip when the probe is moved into the communication groove from the limiting groove, and the problem that the detection process is interrupted due to the fact that the probe of the chip testing device is adhered to the chip is solved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing system, method and related equipment. Background Technology

[0002] After the probes of the chip testing device complete the test, they may adhere to the chip due to material properties or other factors. This problem can interrupt the testing process, affect testing efficiency, and cause many inconveniences to subsequent testing work. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a chip testing system, method and related equipment to solve the problem of the testing process being interrupted due to the probes of the chip testing device sticking to the chip.

[0004] To achieve the above objectives, this application provides a chip testing system, comprising: A probe assembly, including probes, for connection to a chip; A testing device, connected to the probe assembly, is used to test the chip through the probe assembly; A carrier board has a limiting groove on its upper surface for placing a chip. A connecting groove is formed on the side wall of the limiting groove. The connecting groove extends along the depth direction of the limiting groove and penetrates the upper surface of the carrier board. Its bottom wall in the depth direction of the limiting groove is flush with the bottom of the limiting groove so that the probe can move into the limiting groove. The width of the connecting groove is smaller than the width of the limiting groove so that the probe can disengage from the chip when it moves from the limiting groove into the connecting groove.

[0005] Optionally, the probe assembly further includes a probe holder and a lifting mechanism. The lifting mechanism is disposed on the probe holder and connected to the probe to control the connection or disconnection of the probe with the chip.

[0006] Optionally, multiple limiting slots are provided, and the testing system further includes a probe station and a displacement mechanism. The displacement mechanism is mounted on the probe station and connected to the probe base to control the probe on the probe base to move to different limiting slots and connect to the chip therein.

[0007] Optionally, a pressure sensor is also included, which is disposed on the probe and is used to detect the pressure value when the probe is connected to the chip.

[0008] Optionally, it also includes: a control module, which is connected to the probe assembly and is used to control the probe on the probe assembly to move to the limiting groove and connect with the chip, and to control the probe on the probe assembly to move upward to detach from the chip after the chip has completed the test; An image recognition module, connected to the control module, is used to identify whether the chip has detached from the probe when the probe moves upward. If the chip is found to be still attached to the probe, the control module controls the probe to move the chip back into the limiting groove and controls the probe to move from the limiting groove into the communicating groove to detach the chip from the probe.

[0009] Optionally, the limiting groove includes multiple chip carrier surfaces, which gradually decrease in size from top to bottom along the height direction of the limiting groove to accommodate chips of different sizes.

[0010] Based on the same inventive concept, this disclosure also provides a chip testing method applicable to any of the testing systems described above, comprising the following steps: Place the chip in the limiting groove on the carrier board; The test device is connected to the probe assembly, and the probes on the probe assembly are controlled to extend into the limiting groove and connect to the chip. The test device then tests the chip performance. After the chip performance test is completed, the control probe moves upward and it is determined whether the chip has detached from the probe; In response to the determination that a chip has not detached from the probe, the probe is controlled to move downward to place the chip back into the limiting slot, and the probe is controlled to move from the limiting slot to the connecting slot to detach the chip.

[0011] Optionally, the step of connecting the testing device to the probe assembly, controlling the probes on the probe assembly to extend into the limiting groove and connect to the chip, and the testing device testing the chip performance includes: The probe on the control probe assembly is moved down a preset distance to connect with the chip; The testing device sends a test signal to the chip to determine whether the chip's performance is abnormal; In response to the determination that the chip performance is abnormal, the connection between the probe and the chip is determined by detecting the pressure value when the probe is connected to the chip. In response to the confirmation that the connection between the probe and the chip was not abnormal, the testing device sent a test signal to the chip again to test the chip performance.

[0012] Optionally, in response to determining that the chip performance is abnormal, the method of determining whether the connection between the probe and the chip is abnormal by detecting the pressure value when the probe is connected to the chip includes: In response to the determination that the chip performance is abnormal, the pressure value when the detection probe is connected to the chip is checked to see if it is the preset pressure value; If the pressure value when the probe is connected to the chip is a preset pressure value, it is determined that there is no abnormality in the connection between the probe and the chip; If the pressure value when the probe is connected to the chip is not the preset pressure value, it is determined that the connection between the probe and the chip is abnormal.

[0013] Optionally, after determining that the pressure value when the probe is connected to the chip is not a preset pressure value, the method further includes: in response to determining that the connection between the probe and the chip is abnormal, controlling the probe to move up or down so that the pressure value when the probe is connected to the chip is a preset pressure value, and the testing device sends a test signal to the chip again to test the chip performance.

[0014] Based on the same inventive concept, this disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method described above when executing the computer program.

[0015] Based on the same inventive concept, this disclosure also provides a non-transitory computer-readable storage medium that stores computer instructions for causing a computer to perform the method described above.

[0016] As described above, the chip testing system provided in this application includes a probe assembly, a testing device, and a carrier board. The probe assembly includes probes for connecting to the chip, and the testing device is connected to the probe assembly for testing the chip through the probe assembly. A limiting groove on the carrier board is used to place the chip. A connecting groove is formed on the side wall of the limiting groove. The connecting groove extends along the depth direction of the limiting groove and penetrates the upper surface of the carrier board. Its bottom wall in the depth direction of the limiting groove is flush with the bottom of the limiting groove to form a continuous channel, allowing the probe to move horizontally from the limiting groove to the connecting groove. The width of the connecting groove is smaller than the width of the limiting groove. When the chip adheres to the probe and fails to detach, the probe is controlled to move horizontally from the limiting groove to the connecting groove. At this time, the chip cannot move synchronously with the probe due to the limitation of the groove wall, while the probe can move smoothly along the continuous channel, thus achieving stable detachment of the chip from the probe, thereby improving the continuity and efficiency of the testing process. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram showing the probe assembly according to an embodiment of this application; Figure 2This is a schematic diagram showing the carrier board in an embodiment of this application; Figure 3 A schematic diagram showing the limiting groove and the connecting groove in an embodiment of this application; Figure 4 This is a schematic diagram illustrating the testing method in an embodiment of this application; Figure 5 This is a structural diagram of an electronic device shown in an embodiment of this application.

[0019] Reference numerals: 1. Probe assembly; 11. Probe; 12. Probe holder; 2. Carrier plate; 21. Limiting groove; 22. Communicating groove; 23. Chip carrier surface; 3. Displacement mechanism; 4. Probe stage. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] As mentioned in the background, chips are core components of electronic devices, and their performance stability and reliability directly determine the effectiveness of end products. Therefore, they need to undergo comprehensive testing. The core purpose of testing is to screen out chips with circuit defects, substandard performance, insufficient reliability, and other problems, ensuring that delivered chips perform normally and avoiding end-device malfunctions due to chip quality issues.

[0023] In the chip testing process, the probe, as the core contact component between the testing device and the chip, may adhere to the chip after completing electrical performance tests and other related tests. This can be due to various factors such as molecular adhesion between the probe and the chip contact surface, residual test pressure, material surface tension, or the compatibility between the chip pin metal plating and the probe material. This abnormal situation can directly lead to the forced interruption of the testing process, reduce the continuity of batch testing operations, and significantly reduce overall testing efficiency.

[0024] The following is in conjunction with the appendix Figure 1-5 The embodiments of this application will be described in detail below.

[0025] For the purposes mentioned above, such as Figure 1 , Figure 2 and Figure 3 As shown, this application provides a chip testing system, including: The probe assembly 1 includes a probe 11 for connection to the chip; A testing device, connected to the probe assembly 1, is used to test the chip through the probe assembly 1; The carrier 2 has a limiting groove 21 on its upper surface for placing a chip. The side wall of the limiting groove 21 has a connecting groove 22. The connecting groove 22 extends along the depth direction of the limiting groove 21 and penetrates the upper surface of the carrier 2. Its bottom wall in the depth direction of the limiting groove 21 is flush with the bottom of the limiting groove 21 so that the probe 11 can move into the limiting groove 21. The width of the connecting groove 22 is smaller than the width of the limiting groove 21 so that the probe 11 can detach from the chip when it moves from the limiting groove 21 into the connecting groove 22.

[0026] Specifically, the aforementioned chip testing system includes a probe assembly 1, a testing device, and a carrier board 2. The probe assembly 1 includes probes 11 for connecting to the chip. The probes 11 can be made of materials such as tungsten or beryllium copper alloy with high conductivity and high hardness. The probe tips are precision ground to ensure stable transmission of electrical signals to the chip. The testing device includes testing instruments such as a vector network analyzer to test various electrical parameters of the chip.

[0027] The carrier plate 2 is provided with a limiting groove 21. The size and shape of the limiting groove 21 are adapted to the chip to limit the chip and prevent chip misalignment that could lead to poor contact with the probe 11, thereby effectively improving the accuracy of the test data. A connecting groove 22 is formed on the side wall of the limiting groove 21 and extends along the depth direction of the limiting groove 21 (the thickness direction of the carrier plate 2) and penetrates the upper surface of the carrier plate 2. Therefore, the connecting groove 22 has an opening in the depth direction of the limiting groove 21. The bottom wall of the connecting groove 22 in the depth direction of the limiting groove 21 is flush with the bottom of the limiting groove 21, and the opening in the depth direction of the limiting groove 21 communicates with the opening of the limiting groove 21 (i.e., the depth of the connecting groove 22 is consistent with that of the limiting groove 21) to form a continuous moving channel, facilitating the movement of the probe 11 from the limiting groove 21 into the connecting groove 22. The width of the connecting groove 22 is greater than the diameter of the probe 11 to allow the probe 11 to pass through smoothly, and is significantly smaller than the width of the limiting groove 21. When the probe 11 moves into the connecting groove 22, the limiting groove 21 is provided with the side wall of the connecting groove 22 to limit the chip, and the chip cannot move with the probe 11, thereby realizing the smooth separation of the chip from the probe 11.

[0028] For example, the limiting groove 21 is a square groove formed on the upper surface of the carrier board 2, the size of which is adapted to the square chip, providing a stable accommodating space for the chip. The connecting groove 22 is a narrow groove formed on the inner side wall of the limiting groove 21. To adapt to the test point requirements on the chip, multiple connecting grooves 22 can be provided. For example, two connecting grooves 22 can be provided, symmetrically arranged in the middle area of ​​two opposite side walls (such as the left side wall and the right side wall) of the limiting groove 21, which facilitates the movement of the probe 11.

[0029] In this embodiment, the chip testing system includes a probe assembly 1, a testing device, and a carrier board 2. The probe assembly 1 includes probes 11 for connecting to the chip. The testing device is connected to the probe assembly 1 to test the chip through the probe assembly 1. The limiting groove 21 on the carrier plate 2 is used to place the chip. The side wall of the limiting groove 21 is provided with a connecting groove 22. The connecting groove 22 extends along the depth direction of the limiting groove 21 and penetrates the upper surface of the carrier plate 2. Its bottom wall in the depth direction of the limiting groove 21 is flush with the bottom of the limiting groove 21 to form a continuous channel so that the probe 11 can be translated from the limiting groove 21 to the connecting groove 22. The width of the connecting groove 22 is smaller than the width of the limiting groove 21. When the chip and the probe 11 are stuck together, the probe 11 is controlled to be translated from the limiting groove 21 to the connecting groove 22. At this time, the chip cannot move synchronously with the probe 11 because of the limitation of the groove wall of the limiting groove 21, while the probe 11 can be smoothly translated along the continuous channel, so as to achieve the smooth separation of the chip and the probe 11, thereby improving the continuity of the detection process and the detection efficiency.

[0030] In some embodiments, the probe assembly 1 further includes a probe holder 12 and a lifting mechanism. The lifting mechanism is disposed on the probe holder 12 and connected to the probe 11 to control the connection or disconnection of the probe 11 with the chip.

[0031] Specifically, the probe holder 12, serving as the mounting reference for the entire probe assembly 1, is typically made of a high-rigidity material. It has interfaces for connecting to the testing device (such as signal transmission interfaces and power supply interfaces), and a mounting position for the lifting mechanism is reserved at the top. The lifting mechanism is integrated into the probe holder 12, and its core function is to drive the probe 11 to move up and down in the vertical direction (i.e., the thickness direction of the carrier plate 2), thereby controlling the connection or disconnection between the probe 11 and the chip. Specifically, the lifting mechanism can employ various driving methods: for example, a piezoelectric ceramic actuator can be used, which controls the extension and retraction amount through a voltage signal (with minimum driving accuracy down to the nanometer level), achieving micro-amplitude lifting and lowering of the probe 11, suitable for testing pressure-sensitive precision chips.

[0032] In this embodiment, the probe holder 12 serves as an integrated reference, providing a stable mounting platform for the probe 11 and the lifting mechanism. The lifting mechanism is connected to the probe 11, enabling controllable drive for the connection / disconnection of the probe 11 and the chip. Compared to traditional manual operation or passive contact methods, the lifting mechanism can make the probe 11 contact the chip test point through precise stroke control, improving the stability and efficiency of the connection.

[0033] In some embodiments, multiple limiting slots 21 are provided, and the testing system further includes a probe station 4 and a displacement mechanism 3. The displacement mechanism 3 is mounted on the probe station 4 and connected to the probe base 12 to control the probe 11 on the probe base 12 to move to different limiting slots 21 and connect to the chip therein.

[0034] Specifically, multiple limiting slots 21 on the carrier board 2 are arranged in an array (e.g., a 7×5 matrix), and each limiting slot 21 can independently hold a chip to be tested, forming a basic unit for batch testing. Multiple probe assemblies 1 can be set to simultaneously test different chips, greatly improving testing efficiency. All probe assemblies 1 are integrated on the same probe stage 4 and mounted on the probe stage 4 via a displacement mechanism 3 (e.g., an XYZ three-axis precision slide). A through hole is opened in the center of the probe stage 4, and the stage where the carrier board 2 is placed is located directly below it.

[0035] During testing, the displacement mechanism 3 first drives the probe holder 12 to move the probe 11 above the hole in the probe stage 4. Then, the probe 11 extends through the hole into the corresponding limiting groove 21 of the carrier board 2 and docks with the test point of the chip in the groove to complete the test. After the chip in the limiting groove 21 is tested, the lifting mechanism drives the probe 11 to move upward. The displacement mechanism 3 drives the probe holder 12 to move horizontally so that the probe 11 moves directly above the next limiting groove 21. The lifting mechanism cooperates to drive the probe 11 to descend and contact the chip, and the test of all chips in the array is completed in sequence.

[0036] In this embodiment, multiple limiting slots 21 provide a basis for batch testing, enabling the carrier board 2 to accommodate multiple chips. The displacement mechanism 3 drives the probe assembly 1 to switch precisely between different limiting slots 21, realizing a continuous testing process for multiple chips, which is especially suitable for the large-scale chip testing needs in mass production scenarios.

[0037] In some embodiments, the chip testing system further includes a pressure sensor disposed on the probe 11 for detecting the pressure value when the probe 11 is connected to the chip.

[0038] Specifically, the pressure sensor can be a miniaturized pressure sensor adapted to the size of probe 11 (such as a cylindrical sensor with a diameter matching probe 11), integrated into the top of probe 11 or at the connection between probe 11 and probe holder 12 via an embedded structure. This ensures that the electrical signal transmission of probe 11 is not interfered with, while also directly sensing the pressure feedback when the tip of probe 11 contacts the chip test point. The pressure sensor is connected to the control module of the test system via wires, converting the detected pressure into an electrical signal and transmitting it in real time. The control module has a preset pressure value. When probe 11 approaches the chip under the drive of the lifting mechanism, the sensor provides real-time pressure feedback: if the pressure is lower than the preset pressure value, the control unit drives the lifting mechanism to continue descending until the pressure reaches the preset pressure value; if the pressure exceeds the upper limit, the control unit immediately triggers the lifting mechanism to reverse, causing probe 11 to rise slightly to reduce the pressure until the pressure reaches the preset pressure value.

[0039] In this embodiment, by setting a pressure sensor on the probe 11, the pressure value when the probe 11 contacts the chip can be monitored in real time. By controlling the pressure value to a reasonable value, the test signal can be transmitted stably. At the same time, it can also prevent excessive pressure from damaging the chip pads or the tip of the probe 11, while reducing the wear of the probe 11 and extending the service life of the equipment.

[0040] In some embodiments, the chip testing system further includes a control module, which is connected to the probe assembly 1 and is used to control the probe 11 on the probe assembly 1 to move to the limiting groove 21 to connect with the chip, and to control the probe 11 on the probe assembly 1 to move upward to detach from the chip after the chip has completed the test. An image recognition module, connected to the control module, is used to identify whether the chip has detached from the probe 11 when the probe 11 moves upward. If the chip is found to be still attached to the probe 11, the control module controls the probe 11 to move the chip back into the limiting groove 21 and controls the probe 11 to move from the limiting groove 21 into the communicating groove 22 to detach the chip from the probe 11.

[0041] Specifically, the control module, acting as the core hub, can utilize an STM32 series microcontroller. It connects not only the lifting mechanism and displacement mechanism 3 of probe assembly 1, but also the pressure sensor, integrating the feedback signal from the pressure sensor. During routine testing, the control module drives the displacement mechanism 3 according to a preset program, moving probe 11 to the target limiting slot 21. It also controls the lifting mechanism to connect probe 11 to the chip, simultaneously controlling the contact pressure between probe 11 and the chip to a preset value based on the pressure data from the pressure sensor, ensuring a reliable connection. After testing, the control module controls probe 11 to move upwards to prepare for switching test positions. During the upward movement of probe 11, if the image recognition module determines that the chip has not detached from probe 11, the control module immediately activates an emergency program, moving probe 11 and the adsorbed chip back to the original limiting slot 21. Once the chip is placed stably, the control module drives probe 11 into the connecting slot 22, detaching probe 11 from the chip. Simultaneously, after detachment, the control module controls the chip to repeat the above steps to enter the next limiting slot 21, until all chips on the carrier board 2 have been tested.

[0042] The image recognition module includes a high-definition camera that uses machine vision algorithms to identify whether the chip moves with the probe 11. If it does not detach, the control module is immediately triggered. The image recognition module can also identify the positioning holes around the limiting groove 21 to achieve initial positioning of the limiting groove 21. In addition, before the probe 11 descends, the image recognition module can perform high-precision image acquisition of the chip within the limiting groove 21, identify the test sites on the chip surface, and convert them into precise spatial position data, which is then fed back to the control module. Based on this data, the control module calibrates the movement path of the probe 11 to ensure that the probe tip is precisely aligned with the test site, improving the accuracy of the test.

[0043] The testing system also includes a host computer, which serves as the human-computer interaction center. It supports operators in configuring test parameters (such as the coordinates of the limit slot 21 and the pressure threshold), displaying images, pressure curves and progress in real time, automatically storing test data and generating reports, and facilitating full-process visual monitoring.

[0044] In this embodiment, the control module drives the probe assembly 1 to achieve precise docking with the chip and automatic detachment after testing, ensuring the efficient execution of the conventional process. The image recognition module monitors the chip status in real time as the probe 11 moves upward. Once it detects that the chip has not detached from the probe 11 due to electrostatic adsorption or other reasons, it immediately triggers the control module to send the chip back to the limiting slot 21. Then, by moving the probe 11 from the limiting slot 21 into the connecting slot 22, the chip is blocked by the side wall of the limiting slot 21 and separated from the probe 11. This reduces test interruptions caused by chip retention, improves the testing efficiency of batch chips, and significantly enhances the intelligence level of the testing process.

[0045] In some embodiments, such as Figure 3 As shown, the limiting groove 21 includes multiple chip carrier surfaces 23, which gradually decrease in size from top to bottom along the height direction of the limiting groove 21 to accommodate chips of different sizes.

[0046] Specifically, the limiting groove 21 is a stepped recess, with multiple chip-bearing surfaces 23 arranged from top to bottom along its depth direction (i.e., the thickness direction of the carrier plate 2). Each bearing surface is a horizontal platform, and the area of ​​each level (above) is larger than that of the next level (below), forming a stepped structure that is wider at the top and narrower at the bottom. For example, the size of the uppermost bearing surface is adapted to the largest chip size (e.g., 10mm × 10mm). 0.5mm below it is the second bearing surface, with a smaller size of 8mm × 8mm, adapted to medium-sized chips. 0.5mm below that is the third bearing surface, with a size of 5mm × 5mm, adapted to small-sized chips. The edges of each bearing surface are transitioned by a bevel. Figure 3 (Shaded area) ensures that chips of different sizes can be stably supported by the corresponding level of the bearing surface when placed, and that the chip edge fits against the side wall of the limiting groove 21 to achieve precise positioning.

[0047] In this embodiment, when testing chips of different sizes, there is no need to replace the carrier board 2. It is only necessary to place the chip into the corresponding layer of the carrier surface according to the chip size, which improves the versatility of the carrier board 2.

[0048] Based on the same inventive concept, such as Figure 4 As shown, this disclosure also provides a chip testing method applicable to any of the testing systems described above, comprising the following steps: S100: Place the chip in the limiting groove 21 on the carrier board 2; In this step, the operator or automated feeding mechanism places the chip to be tested into the limiting groove 21 of the carrier board 2. The chip is initially positioned under the constraint of the side wall of the limiting groove 21. If the limiting groove 21 is a stepped multi-bearing surface structure, the corresponding level of bearing surface can be selected according to the chip size to ensure that the bottom of the chip is in close contact with the bearing surface and there is no obvious gap between the edge and the groove wall.

[0049] S200: Connect the test device to the probe assembly 1, control the probe 11 on the probe assembly 1 to extend into the limiting groove 21 and connect with the chip, and the test device tests the chip performance. In this step, the testing device (such as a signal generator, oscilloscope, etc.) is connected to the signal interface of probe assembly 1 via wires to establish an electrical signal transmission path. The control module drives the displacement mechanism 3 to move probe assembly 1 above the target limiting groove 21. The image recognition module captures an image of the chip surface, identifies the coordinates of the test site, and calibrates the movement path of probe 11 to ensure that the probe tip is aligned with the chip test site. The control module activates the lifting mechanism to drive probe 11 to descend vertically until a stable electrical connection is formed with the chip. After the chip performance test is completed, the control module moves probe 11 upward, and the image recognition module immediately captures an image of the bottom of probe 11 to determine whether the chip moves with probe 11.

[0050] S300: In response to determining that a chip has not detached from probe 11, control probe 11 to move down and place the chip back into the limiting groove 21, and control probe 11 to move from the limiting groove 21 to the connecting groove 22 so as to detach it from the chip.

[0051] In this step, if the image recognition module determines that the chip has not detached, the control module immediately controls the lifting mechanism to slowly descend, so that the bottom of the chip re-contacts the bearing surface of the limiting groove 21, ensuring that the chip is placed stably. After confirming that the chip is in place, the control module drives the probe 11 to move horizontally towards the connecting groove 22. Because the chip is wider than the connecting groove 22, it is blocked by the side wall of the limiting groove 21 and detaches from the probe 11. After detachment, the probe 11 can be moved into the connecting groove 22 to wait for the next test, or it can be directly driven to the next limiting groove 21 by the displacement mechanism 3. If the chip detaches successfully, the control module drives the probe assembly 1 to move directly to the next limiting groove 21, repeating step S200 until all chips on the carrier board 2 have been tested.

[0052] In this embodiment, the chip testing method is adapted to the above-described testing system and has the beneficial effects of the corresponding embodiments, which will not be elaborated further here.

[0053] In some embodiments, in step S200, connecting the testing device to the probe assembly 1, controlling the probe 11 on the probe assembly 1 to extend into the limiting groove 21 and connect to the chip, and the testing device testing the chip performance includes: S201: Control probe 11 on probe assembly 1 to move down a preset distance to connect with the chip; In this step, the lifting mechanism of the driving probe assembly 1 drives the probe 11 to move down a preset distance, so that the tip of the probe 11 contacts the chip test point, and the pressure sensor records the initial contact pressure value simultaneously.

[0054] S202: The testing device sends a test signal to the chip to determine whether the chip performance is abnormal; In this step, the testing device sends a preset test signal (such as an electrical signal of a specific voltage and frequency) to the chip through probe 11 and receives the feedback signal from the chip. It then uses signal characteristic analysis (such as signal strength, response time, waveform integrity, etc.) to determine whether there are any abnormalities in the chip performance (such as short circuit, open circuit, excessive signal attenuation, etc.).

[0055] S203: In response to determining that the chip performance is abnormal, the connection between the probe 11 and the chip is determined by detecting the pressure value when the probe 11 is connected to the chip. S204: In response to the determination that there is no abnormality in the connection between probe 11 and the chip, the test device sends a test signal to the chip again to test the chip performance.

[0056] Specifically, in actual testing, even if the probe 11 is driven downwards at a preset distance, the chip's surface unevenness (such as local protrusions or tilting) may still cause excessive pressure (damaging the chip or probe 11), insufficient pressure (signal connection issues), or no contact at all between the probe 11 and the test point. If such connection abnormalities are not identified, they can easily lead to test signal distortion, thus misjudging a qualified chip as having performance abnormalities. Therefore, if the chip performance is determined to be abnormal in step S202, step S203 is triggered. The system retrieves the real-time pressure data recorded by the pressure sensor and compares it with the preset pressure value. If the pressure value is not the preset pressure value, it is initially determined that the connection between probe 11 and the chip is abnormal, and the position or pressure of probe 11 needs to be adjusted before retesting. If the pressure value is normal, it indicates that the connection is not abnormal, and the problem is likely a performance issue with the chip itself. At this time, step S204 is executed, and the testing device sends a test signal again (signals of different intensities or frequencies can be used for verification) to eliminate misjudgments caused by single signal interference and ensure the accuracy of the test results.

[0057] In this embodiment, probe 11 moves downwards at a uniformly set preset distance to connect with the chip. This preset distance ensures a stable connection between probe 11 and the chip test point under normal operating conditions, guaranteeing efficient progress of routine testing. However, when the chip performance is initially determined to be abnormal, to rule out connectivity issues caused by uneven chip surface, the system performs a secondary verification using real-time data from the pressure sensor, quickly detecting abnormal contact pressure (too high or too low) caused by uneven chip surface. This method of achieving rapid connection at a preset distance first, and then calibrating the connection with pressure detection, avoids frequent adjustments to the preset distance to adapt to the surface differences of individual chips, effectively preserving the efficiency of batch testing; at the same time, pressure feedback enables adaptation to individual chip differences, allowing probe 11 to adapt to chips with different surface conditions, significantly reducing the test misjudgment rate caused by surface unevenness.

[0058] In some embodiments, in step S203, in response to determining that the chip performance is abnormal, determining whether the connection between the probe 11 and the chip is abnormal by detecting the pressure value when the probe 11 is connected to the chip includes: S2031: In response to determining that the chip performance is abnormal, check whether the pressure value when the detection probe 11 is connected to the chip is a preset pressure value; S2032: In response to the determination that the pressure value when the probe 11 is connected to the chip is a preset pressure value, it is determined that the connection between the probe 11 and the chip is not abnormal; S2033: In response to the determination that the pressure value when the probe 11 is connected to the chip is not a preset pressure value, it is determined that the connection between the probe 11 and the chip is abnormal; S2034: In response to the determination that the connection between probe 11 and chip is abnormal, the probe 11 is controlled to move up or down so that the pressure value when probe 11 is connected to chip is the preset pressure value, and the test device sends a test signal to chip again to test chip performance.

[0059] Specifically, upon determining that the chip performance is abnormal, step S2031 is executed. The system retrieves the pressure value of probe 11 when it is connected to the chip, which is monitored in real time by the pressure sensor, and compares it with a preset pressure value (this preset pressure value is not just a single specific data point, but can be a collection of data). If the pressure value is consistent with the preset value (step S2032), it is determined that the connection between probe 11 and the chip is not abnormal, ruling out performance misjudgment caused by contact problems. If the pressure value deviates from the preset value (step S2033), it is determined that the connection is abnormal, which may be due to poor contact or overpressure caused by uneven chip surface, probe 11 position misalignment, etc. At this time, step S2034 is triggered, and the control module drives probe 11 to move slightly up or down (the adjustment range is accurate to the micrometer level). At the same time, the pressure sensor provides real-time feedback of the adjusted pressure value until the pressure stabilizes within the preset value range. Then, the testing device sends a test signal to the chip again to re-test the performance. If the chip performance still has problems in this test, the chip is determined to be unqualified.

[0060] In this embodiment, the system first checks whether the pressure between probe 11 and the chip meets a preset value. If it does, the connection is normal, and the problem originates from the chip itself. If it does not meet the preset value, the system determines that the connection is faulty. In this case, the system automatically adjusts the probe 11 up and down until the pressure returns to the preset value, and then retests the chip performance. This method avoids misjudging poor connection as chip failure and can quickly repair contact problems through automatic adjustment, making the test results more reliable and efficient. It is especially suitable for batch testing of chips with individual differences such as surface unevenness.

[0061] It should be noted that the method in this embodiment can be executed by a single device, such as a computer or server. The method can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method in this embodiment, and the multiple devices will interact with each other to complete the method described.

[0062] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0063] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the testing method described in any of the above embodiments.

[0064] Figure 5 This embodiment illustrates a more specific hardware structure of an electronic device. The device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0065] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0066] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0067] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0068] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0069] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0070] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0071] The electronic devices described above are used to implement the corresponding test methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0072] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to perform the test method as described in any of the above embodiments.

[0073] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0074] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the test method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0075] It is understood that before using the technical solutions of the various embodiments in this disclosure, users will be informed of the type, scope of use, and usage scenarios of the personal information involved in an appropriate manner, and user authorization will be obtained.

[0076] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose, based on the prompt message, whether to provide personal information to the software or hardware such as electronic devices, applications, servers, or storage media performing the operations of this disclosed technical solution.

[0077] As an optional but not limited implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0078] It is understood that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0079] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application is limited to these examples; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0080] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0081] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0082] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the claims of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A chip testing system, characterized by, The utility model relates to a test system of chip, including: Probe assembly (1) including probe (11) for connecting with chip; Test device is connected with probe assembly (1), to carry out test to chip through probe assembly (1); Carrier plate (2), the upper surface of carrier plate (2) is provided with limiting groove (21) to place chip, the side wall of limiting groove (21) is provided with communicating groove (22), communicating groove (22) extends along the depth direction of limiting groove (21) and penetrates the upper surface of carrier plate (2), the bottom wall in the depth direction of limiting groove (21) is flush with the groove bottom of limiting groove (21), to move into limiting groove (21) from probe (11), the width of communicating groove (22) is less than the width of limiting groove (21), to separate from chip when probe (11) moves into communicating groove (22) from limiting groove (21).

2. The chip testing system of claim 1, wherein Probe assembly (1) still includes probe holder (12) and lifting mechanism, lifting mechanism is arranged on probe holder (12) and is connected with probe (11), to control probe (11) and chip connect or disconnect.

3. The chip testing system of claim 2, wherein Limiting groove (21) is provided with multiple, the test system still includes probe platform (4) and displacement mechanism (3), displacement mechanism (3) is installed on probe platform (4) and is connected with probe holder (12), to control probe (11) on probe holder (12) moves to different limiting groove (21) and is connected with chip in it.

4. The chip testing system of claim 1, wherein Still include pressure sensor, pressure sensor is arranged on probe (11), to detect the pressure value when probe (11) is connected with chip.

5. The chip testing system of claim 1, wherein Still include: Control module, control module is connected with probe assembly (1), to control probe (11) on probe assembly (1) and move to limiting groove (21) and chip connect, and control probe (11) on probe assembly (1) and move up to separate from chip after chip completes test; Image recognition module, image recognition module is connected with control module, to identify whether chip separates from probe (11) when probe (11) moves up, and under the working condition that chip is identified to not separate from probe (11), control module controls probe (11) and drives chip to place in limiting groove (21) again, and controls probe (11) and moves into communicating groove (22) from limiting groove (21) to make chip separate from probe (11).

6. The chip testing system of claim 1, wherein Limiting groove (21) includes multiple chip bearing surfaces (23), multiple chip bearing surfaces (23) gradually reduce from top to bottom along the height direction of limiting groove (21), to adapt to chip of different sizes.

7. A method of testing a chip, suitable for use in a testing system according to any one of claims 1-6, characterized in that, Including following steps: Chip is placed in limiting groove (21) on carrier plate (2); Test device is connected with probe assembly (1), control probe (11) on probe assembly (1) and extend into limiting groove (21) and connect with chip, and test device tests chip performance; After the chip performance test is completed, the probe (11) is controlled to move upward, and it is determined whether the chip is separated from the probe (11); In response to determining that the chip is not separated from the probe (11), the probe (11) is controlled to move downward to place the chip in the limiting groove (21) again, and the probe (11) is controlled to move from the limiting groove (21) to the communication groove (22) to separate the chip.

8. The test method of claim 7, wherein, The test device is connected with the probe assembly (1), the probe (11) on the probe assembly (1) is controlled to extend into the limiting groove (21) and be connected with the chip, the test device tests the chip performance, and the method comprises the following steps: The probe (11) on the probe assembly (1) is controlled to move downward by a preset distance to be connected with the chip; The test device sends a test signal to the chip to determine whether the chip performance is abnormal; In response to determining that the chip performance is abnormal, it is determined whether the connectivity of the probe (11) and the chip is abnormal by detecting the pressure value when the probe (11) is connected with the chip; In response to determining that the connectivity of the probe (11) and the chip is not abnormal, the test device sends a test signal to the chip again to test the chip performance.

9. The test method of claim 8, wherein, The method comprises the following steps: In response to determining that the chip performance is abnormal, it is determined whether the connectivity of the probe (11) and the chip is abnormal by detecting the pressure value when the probe (11) is connected with the chip; In response to determining that the connectivity of the probe (11) and the chip is not abnormal, the test device sends a test signal to the chip again to test the chip performance. The processor implements the method of any one of claims 6 to 10 when executing the program.

10. The test method of claim 9, wherein, The computer instructions are used to make the computer execute the method of any one of claims 6 to 10. The computer program instructions make the computer execute the method of any one of claims 6 to 10 when the computer program instructions run on the computer.

11. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The computer program instructions make the computer execute the method of any one of claims 6 to 10 when the computer program instructions run on the computer.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein, ​ 13. A computer program product comprising computer program instructions, characterised in that, ​

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