Mark pattern, mask pattern and measurement method

Abstract

The invention provides a mark pattern, a mask pattern and a measurement method, and the mark pattern capable of simultaneously carrying out critical dimension measurement and overlay error measurement is formed by designing a plurality of alternately arranged L-shaped front-layer patterns and current patterns. The problem that the measurement accuracy and repeatability are affected by low contrast images and unstable IBO parameters due to graph damage caused by the technology and the light source problem in the prior art is solved, the front-layer graph and the current graph are integrally designed together, the graph marking structure is simplified, the layout occupied area is reduced, and the measurement accuracy and repeatability are improved. According to the method, the cutting channel space is saved, the alignment errors in the X direction and the Y direction in the mask plate plane can be measured, the CD and the alignment error measuring method are simpler, more convenient and faster, and therefore the overall precision and efficiency of integrated circuit manufacturing are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a marking pattern, a mask pattern, and a measurement method. Background Technology

[0002] In semiconductor manufacturing, overlay measurement is a critical step in ensuring precise alignment of multilayer patterns, which is essential for improving the performance and reliability of integrated circuits. However, existing overlay marking patterns have limitations in image-based overlay (IBO) measurement. First, processes such as chemical mechanical polishing (CMP) during manufacturing can cause deformation of the overlay pattern, affecting measurement accuracy. Second, lighting issues can also affect measurement results; low-contrast images reduce the reliability of image processing, leading to measurement errors. Furthermore, the instability of IBO parameters further impacts the repeatability and accuracy of measurement results. Besides accuracy issues, existing overlay marking pattern designs and measurement methods are inherently complex, increasing both the difficulty of the manufacturing process and the area occupied by the layout.

[0003] In addition, such as Figure 1 As shown, the existing mask pattern 1's critical dimension (CD) markers are usually placed separately for the previous pattern 11 and the current pattern 12, occupying a large area of ​​the pattern and having a single function. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a marking pattern, a mask pattern, and a measurement method to solve the problems of complex design of overlay marking patterns, low accuracy of overlay error measurement, single function of CD measurement marking patterns, and large area occupied by the pattern in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a marking graphic, the marking graphic comprising:

[0006] Several L-shaped front layer patterns, each L-shaped front layer pattern including a first straight line segment extending along the X direction and a second straight line segment extending along the Y direction, and all the first straight line segments are spaced apart along the Y direction, and all the second straight line segments are spaced apart along the X direction, wherein the X direction and the Y direction are located in the mask plane and are perpendicular to each other.

[0007] Several L-shaped current graphics, each L-shaped current graphic including a third straight line segment extending along the X direction and a fourth straight line segment extending along the Y direction, wherein all the third straight line segments are spaced apart along the Y direction, all the fourth straight line segments are spaced apart along the X direction, and the first straight line segment and the third straight line segment are arranged alternately, the second straight line segment and the fourth straight line segment are arranged alternately, and all the previous graphics and all the current graphics do not form overlapping areas.

[0008] Optionally, the extension lengths of the first straight line segments of two adjacent front-layer graphics are different, the extension lengths of the second straight line segments of two adjacent front-layer graphics are different, the extension lengths of the third straight line segments of two adjacent current graphics are different, the extension lengths of the fourth straight line segments of two adjacent current graphics are different, and the third straight line segment is flush with the end of the first straight line segment on the adjacent side, and the fourth straight line segment is flush with the end of the second straight line segment on the adjacent side.

[0009] Optionally, the marked graphics include N+1 previous graphics and N current graphics, where N is a positive integer, and each of the third line segments is located between two adjacent first line segments, and each of the fourth line segments is located between two adjacent second line segments.

[0010] Further, the marking graphics include 6 previous layer graphics and 5 current graphics. The first and second line segments of the same previous layer graphic have equal extension lengths, and the third and fourth line segments of the same current graphic have equal extension lengths. All the first line segments are sequentially named as the first segment, second segment, third segment, fourth segment, fifth segment, and sixth segment along the Y direction. All the third line segments are sequentially named as the seventh segment, eighth segment, ninth segment, tenth segment, and eleventh segment along the Y direction. The ends of the first, fifth, sixth, seventh, and eleventh segments are flush, the ends of the second, fourth, eighth, and tenth segments are flush, and the ends of the third and ninth segments are flush. The extension lengths of the third, first, and second segments decrease sequentially.

[0011] Optionally, the first line segment and the third line segment are arranged alternately with their edges aligned, and the second line segment and the fourth line segment are arranged alternately with their edges aligned.

[0012] Optionally, the first straight segment has the same width as the third straight segment, and the second straight segment has the same width as the fourth straight segment.

[0013] The present invention also provides a mask pattern, the mask pattern comprising a plurality of marker patterns as described in any of the above claims.

[0014] The present invention also provides a measurement method, the measurement method comprising:

[0015] A substrate is provided on which a front layer pattern, a current layer and a photoresist layer are sequentially formed, and the photoresist layer is photolithographically patterned based on the mask pattern as described in claim 7.

[0016] Measure the key dimensions of the front-layer pattern and the patterned photoresist layer, and measure the overlay error between the front-layer pattern and the patterned photoresist layer;

[0017] The current pattern is obtained by etching the current layer based on the patterned photoresist layer;

[0018] Measure the key dimensions of the current graphic and measure the overprinting error between the current graphic and the previous graphic.

[0019] Optionally, the key dimensions of the current pattern are measured using a CDSEM machine, and the overlay error between the current pattern and the previous pattern is measured using a CDSEM machine.

[0020] Optionally, the measurement method further includes a step of comparing and analyzing the overlay error between the measured current pattern and the previous pattern with the overlay error between the measured previous pattern and the patterned photoresist layer.

[0021] As described above, the marking pattern, mask pattern, and measurement method of the present invention have the following beneficial effects:

[0022] The marking pattern of this invention includes multiple L-shaped front-layer patterns and current patterns, with the L-shaped patterns of the front-layer patterns and the L-shaped patterns of the current patterns arranged alternately to form a marking pattern capable of simultaneously performing CD measurement and overlay error measurement. This marking pattern solves the problems of pattern damage caused by the process, low-contrast images due to light source issues, and unstable IBO parameters affecting the measurement accuracy and repeatability of existing overlay error measurement marking patterns. Furthermore, by integrating the front-layer patterns and current patterns into a single design, this marking pattern simplifies the marking pattern structure, reduces the layout area occupied, and saves dicing space compared to existing CD measurement and overlay error measurement marking patterns. It also makes the measurement method simpler and faster, improving the overall accuracy and efficiency of integrated circuit manufacturing.

[0023] The mask pattern of the present invention includes multiple marking patterns capable of simultaneously performing CD measurement and overlay error measurement. By integrating the previous layer pattern with the current pattern, the marking pattern simplifies the marking pattern structure, reduces the area occupied by the layout, saves dicing space, and can measure overlay errors in the X and Y directions within the mask plane. In addition, it makes the CD and overlay error measurement methods simpler and faster, improving the overall accuracy and efficiency of integrated circuit manufacturing.

[0024] The measurement method of this invention involves sequentially forming a front layer pattern, a current layer, and a photoresist layer on a substrate, and then using the mask pattern described in the above embodiments to photolithographically pattern the photoresist layer. Subsequently, the critical dimensions of the front layer pattern and the patterned photoresist layer are measured, as well as the overlay error between them. Next, the current layer is etched based on the patterned photoresist layer to form the current pattern, and the critical dimensions of the current pattern and its overlay error with the front layer pattern are further measured. In existing technologies, typically only the overlay error between the front layer pattern and the patterned photoresist layer is measured. When measuring the overlay error at the site where the current pattern is etched, transmission electron microscopy (TEM) is usually used to confirm whether the overlay is misaligned, a very time-consuming verification process. The measurement method of this embodiment can measure the overlay error simultaneously with the measurement of the critical dimensions of the current pattern, which helps to accelerate the development process of new products, improve the response speed and flexibility of the production line, and achieve higher production efficiency. Attached Figure Description

[0025] Figure 1 The diagram shows a planar structure of a mask pattern as an example of the prior art.

[0026] Figure 2 The diagram shows a planar structure of the marking graphic of the present invention.

[0027] Figure 3 The diagram shows a planar structure of a mask pattern as an example of the present invention.

[0028] Figure 4 The diagram shown is a flowchart of the measurement method of the present invention.

[0029] Figure 5 and Figure 6 The diagram shows a cross-sectional structure as presented in the measurement method steps of the present invention.

[0030] Figure 7 This is a schematic diagram of a planar structure used in the measurement method of the present invention to measure the overlay error between the current pattern and the previous pattern.

[0031] Component labeling explanation: 1, 3 Mask pattern, 11, 21 Previous layer pattern, 12, 22 Current pattern, 2 Marker pattern, 211 First straight line segment, 212 Second straight line segment, 213 First center position, 101 First segment, 102 Second segment, 103 Third segment, 104 Fourth segment, 105 Fifth segment, 106 Sixth segment, 221 Third straight line segment, 222 Fourth straight line segment, 223 Second center position, 107 Seventh segment, 108 Eighth segment, 109 Ninth segment, 110 Tenth segment, 111 Eleventh segment, 30 Substrate, 31 Current layer, 32 Photoresist layer, 33 Functional area, S1~S6 Steps. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please see Figures 2 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] This embodiment provides a marker graphic 2, such as Figure 2 As shown, the marker graphic 2 includes:

[0035] A plurality of L-shaped front layer patterns 21, each L-shaped front layer pattern 21 includes a first straight line segment 211 extending along the X direction and a second straight line segment 212 extending along the Y direction, and all the first straight line segments 211 are spaced apart along the Y direction, and all the second straight line segments 212 are spaced apart along the X direction, wherein the X direction and the Y direction are located in the mask plane and are perpendicular to each other.

[0036] Several L-shaped current graphics 22, each L-shaped current graphic 22 including a third straight line segment 221 extending along the X direction and a fourth straight line segment 222 extending along the Y direction, wherein all the third straight line segments 221 are spaced apart along the Y direction, all the fourth straight line segments 222 are spaced apart along the X direction, and the first straight line segment 211 and the third straight line segment 221 are arranged alternately, the second straight line segment 212 and the fourth straight line segment 222 are arranged alternately, and all the previous layer graphics 21 and all the current graphics 22 do not form overlapping areas.

[0037] The marking pattern in this embodiment includes multiple L-shaped front-layer patterns and current patterns, with the L-shaped patterns of the front-layer patterns and the current patterns arranged alternately to form a marking pattern capable of simultaneously performing CD measurement and overlay error measurement. This marking pattern solves the problems of pattern damage caused by the process, low-contrast images due to light source issues, and unstable IBO parameters affecting the measurement accuracy and repeatability of existing overlay error measurement marking patterns. Furthermore, by integrating the front-layer patterns and current patterns into a single design, this marking pattern simplifies the marking pattern structure, reduces the layout area, and saves dicing space compared to existing CD measurement and overlay error measurement marking patterns. It also makes the measurement method simpler and faster, improving the overall accuracy and efficiency of integrated circuit manufacturing.

[0038] As an example, such as Figure 2 As shown, the extension lengths of the first straight line segment 211 of two adjacent front layer graphics 21 are different, the extension lengths of the second straight line segment 212 of two adjacent front layer graphics 21 are different, the extension lengths of the third straight line segment 221 of two adjacent current graphics 22 are different, the extension lengths of the fourth straight line segment 222 of two adjacent current graphics 22 are different, and the third straight line segment 221 is flush with the end of the first straight line segment 211 on the adjacent side, and the fourth straight line segment 222 is flush with the end of the second straight line segment 212 on the adjacent side.

[0039] As a preferred example, the marker graphic 2 includes N+1 previous layer graphics 21 and N current graphics 22, where N is a positive integer, and illustratively, N≥2. Furthermore, each third line segment 221 is located between two adjacent first line segments 211, and each fourth line segment 222 is located between two adjacent second line segments 212.

[0040] As a further example, such as Figure 2As shown, in this embodiment, the marker graphic 2 includes 6 preceding graphic 21 and 5 current graphic 22. The first straight line segment 211 and the second straight line segment 212 of the same preceding graphic 21 have equal extension lengths, and the third straight line segment 221 and the fourth straight line segment 222 of the same current graphic 22 have equal extension lengths. All the first straight line segments 211 are sequentially named as first segment 101, second segment 102, third segment 103, fourth segment 104, fifth segment 105 and sixth segment 106 along the Y direction. All the third straight line segments 221 are sequentially named as first segment 101, second segment 102, third segment 103, fourth segment 104, fifth segment 105 and sixth segment 106 along the Y direction. The directions are sequentially: seventh segment 107, eighth segment 108, ninth segment 109, tenth segment 110, and eleventh segment 111. The ends of the first segment 101, fifth segment 105, sixth segment 106, seventh segment 107, and eleventh segment 111 are aligned; the ends of the second segment 102, fourth segment 104, eighth segment 108, and tenth segment 110 are aligned; and the end of the third segment 103 is aligned with the end of the ninth segment 109. Furthermore, the extension lengths of the third segment 103, first segment 101, and second segment 102 decrease sequentially. The number of the preceding layer graphic 21 and the current graphic 22 in the marked graphic 2, as well as the alignment and extension lengths of the ends of the first straight line segment 211, second straight line segment 212, third straight line segment 221, and fourth straight line segment 222, can be adjusted according to measurement requirements and are not limited to this embodiment.

[0041] As a preferred example, the first straight line segment 211 and the third straight line segment 221 are arranged alternately with their edges aligned, and the second straight line segment 212 and the fourth straight line segment 222 are arranged alternately with their edges aligned. The first straight line segment 211 and the third straight line segment 221 have the same width, and the second straight line segment 212 and the fourth straight line segment 222 have the same width. The widths of the first straight line segment 211, the second straight line segment 212, the third straight line segment 221, and the fourth straight line segment 222 can be adjusted in the design according to measurement requirements, and are not limited to this embodiment.

[0042] This embodiment also provides a mask pattern 3, such as Figure 3 As shown, the mask pattern 3 includes several of the marker patterns 2 described in the above embodiments. This embodiment illustrates this by showing that the mask pattern 3 includes four marker patterns 2, with the four marker patterns 2 located at the four opposite corners of the functional area 33. The number and placement of the marker patterns 2 can be adjusted according to actual design requirements and the needs of both sides, and are not limited to this embodiment.

[0043] The mask pattern in this embodiment includes multiple marker patterns capable of simultaneously performing CD measurement and overlay error measurement. By integrating the previous layer pattern with the current pattern, this marker pattern simplifies the marker pattern structure, reduces the area occupied by the layout, saves dicing space, and can measure overlay errors in the X and Y directions within the mask plane. Furthermore, it makes the CD and overlay error measurement methods simpler and faster, improving the overall accuracy and efficiency of integrated circuit manufacturing.

[0044] This embodiment also provides a measurement method, such as Figure 4 As shown, the measurement method includes:

[0045] S1, Reference Figure 5 A substrate 30 is provided, on which a front layer pattern 21, a current layer 31 and a photoresist layer 32 are sequentially formed, and the photoresist layer 32 is photolithographically patterned based on the mask pattern 3 described in the above embodiment.

[0046] S2, Reference Figure 5 The CD of the front layer pattern 21 and the patterned photoresist layer 32 is measured, and the overlay error of the front layer pattern 21 and the patterned photoresist layer 32 is measured, for example, by an overlay machine.

[0047] S3, Reference Figure 6 The current pattern 22 is obtained by etching the current layer 31 based on the patterned photoresist layer 32.

[0048] S4, Reference Figure 6 The CD of the current pattern 22 is measured by means of a scanning electron microscope (CDSEM) including but not limited to a critical dimension microscope, and the overlay error between the current pattern 22 and the previous pattern 21 is measured by means of a scanning electron microscope (CDSEM) including but not limited to a CDSEM.

[0049] The measurement method of this embodiment involves sequentially forming a front layer pattern, a current layer, and a photoresist layer on a substrate, and then using the mask pattern described in the previous embodiment to photolithographically pattern the photoresist layer. Subsequently, the critical dimensions of the front layer pattern and the patterned photoresist layer are measured, as well as the overlay error between them. Next, the current layer is etched based on the patterned photoresist layer to form the current pattern, and the critical dimensions of the current pattern and its overlay error with the front layer pattern are further measured. In existing technologies, only the overlay error between the front layer pattern and the patterned photoresist layer is typically measured. When measuring the overlay error at the site where the current pattern is etched, TEM is usually used to confirm whether there is an overlay misalignment, a very time-consuming verification process. The measurement method of this embodiment can measure the overlay error simultaneously with the measurement of the critical dimensions of the current pattern, which helps to accelerate the development process of new products, improve the response speed and flexibility of the production line, and achieve higher production efficiency.

[0050] Specifically, in step S4, the method for measuring the overlay error between the current pattern 22 and the previous pattern 21 includes the following steps:

[0051] Measure the first center position 213 of the first straight line segment 211 of all the previous layer graphics 21, measure the second center position 223 of the third straight line segment 221 of all the current graphics 22, and calculate the offset between the first center position 213 and the second center position 223, that is, obtain the overlay error between the previous layer graphics 21 and the current graphics 22 in the X direction.

[0052] The third center position of the second straight line segment 212 of all the previous layer patterns 21 is measured, the fourth center position of the fourth straight line segment 222 of all the current patterns 22 is measured, and the offset between the third center position and the fourth center position is calculated, that is, the overlay error between the previous layer pattern 21 and the current pattern 22 in the Y direction is obtained.

[0053] As a preferred example, the measurement method further includes a step of comparing and analyzing the measured overlay error between the current pattern 22 and the previous pattern 21 with the measured overlay error between the previous pattern 21 and the patterned photoresist layer 32. The overlay error between the previous pattern 21 and the patterned photoresist layer 32 reflects the accuracy of pattern transfer during photolithography, i.e., whether the photoresist layer 32 can accurately replicate the pattern design on the mask during photolithography. The overlay error between the current pattern 22 and the previous pattern 21 reflects the stability of pattern alignment throughout the entire manufacturing process, including photolithography, etching, and other process steps that may affect the pattern position. This is of great significance for evaluating the accuracy and reliability of the entire production process. Through this comparative analysis, a more comprehensive understanding of the factors that may affect overlay accuracy during production can be obtained, helping to promptly identify and correct potential problems in the production process, thereby taking corresponding measures for optimization and improving the quality and performance of integrated circuit products.

[0054] In summary, the marking pattern, mask pattern, and measurement method of this invention innovatively design multiple L-shaped front-layer patterns and current patterns, arranging them alternately to form a marking pattern capable of simultaneously measuring critical dimensions and overlay errors. This design not only solves the problems in existing technologies where pattern damage caused by processes, low-contrast images due to light source issues, and unstable IBO parameters affect measurement accuracy and repeatability, but also simplifies the marking pattern structure, reduces the layout area occupied, and saves dicing space by integrating the front-layer and current patterns. Furthermore, this marking pattern can also measure overlay errors in the X and Y directions within the mask plane, making CD and overlay error measurement methods simpler and faster, thereby improving the overall accuracy and efficiency of integrated circuit manufacturing. The measurement method of this invention involves sequentially forming a previous layer pattern, a current layer, and a photoresist layer on a substrate, and then using a mask pattern to photolithographically pattern the photoresist layer. Subsequently, the critical dimensions of the previous layer pattern and the patterned photoresist layer are measured, as well as the overlay error between them. Next, the current layer is etched based on the patterned photoresist layer to form the current pattern, and the critical dimensions of the current pattern and its overlay error with the previous layer pattern are further measured. This method can measure the overlay error simultaneously with the measurement of the critical dimensions of the current pattern, avoiding the time-consuming verification process of confirming overlay misalignment using TEM, which is typically required in existing technologies. This helps to accelerate the development of new products, improve the response speed and flexibility of the production line, and achieve higher production efficiency. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A marking pattern, characterized in that The mark pattern comprises: a plurality of L-shaped front layer patterns, each of the L-shaped front layer patterns comprising a first straight line segment extending along an X direction and a second straight line segment extending along a Y direction, and all the first straight line segments being spaced apart along the Y direction and all the second straight line segments being spaced apart along the X direction, wherein the X direction and the Y direction are perpendicular to each other in a mask plane; a plurality of L-shaped current patterns, each of the L-shaped current patterns comprising a third straight line segment extending along the X direction and a fourth straight line segment extending along the Y direction, wherein all the third straight line segments are spaced apart along the Y direction and all the fourth straight line segments are spaced apart along the X direction, and the first straight line segments and the third straight line segments are alternately arranged, and the second straight line segments and the fourth straight line segments are alternately arranged, and none of the front layer patterns and the current patterns forms an overlapping area.

2. Marking pattern according to claim 1, characterized in that: The first straight line segments of two adjacent front layer patterns have different lengths, the second straight line segments of two adjacent front layer patterns have different lengths, the third straight line segments of two adjacent current patterns have different lengths, the fourth straight line segments of two adjacent current patterns have different lengths, and the third straight line segment is flush with the end of the first straight line segment on the adjacent side, and the fourth straight line segment is flush with the end of the second straight line segment on the adjacent side.

3. The marking graphic of claim 1, wherein: The mark pattern comprises N+1 front layer patterns and N current patterns, wherein N is a positive integer, each of the third straight line segments is located between two adjacent first straight line segments, and each of the fourth straight line segments is located between two adjacent second straight line segments.

4. The marking pattern of claim 3, wherein: The mark pattern comprises 6 front layer patterns and 5 current patterns, the first straight line segment and the second straight line segment of the same front layer pattern have equal lengths, and the third straight line segment and the fourth straight line segment of the same current pattern have equal lengths; all the first straight line segments are sequentially a first segment, a second segment, a third segment, a fourth segment, a fifth segment and a sixth segment along the Y direction; all the third straight line segments are sequentially a seventh segment, an eighth segment, a ninth segment, a tenth segment and an eleventh segment along the Y direction; wherein the ends of the first segment, the fifth segment, the sixth segment, the seventh segment and the eleventh segment are flush, the ends of the second segment, the fourth segment, the eighth segment and the tenth segment are flush, the ends of the third segment and the ninth segment are flush; and the lengths of the third segment, the first segment and the second segment sequentially decrease.

5. The marking graphic of claim 1, wherein: The first straight line segments and the third straight line segments are alternately arranged in edge-to-edge alignment, and the second straight line segments and the fourth straight line segments are alternately arranged in edge-to-edge alignment.

6. The marking graphic of claim 1, wherein: The first straight line segments and the third straight line segments have equal widths, and the second straight line segments and the fourth straight line segments have equal widths.

7. A mask pattern, characterized by: The mask pattern comprises a plurality of mark patterns as claimed in any one of claims 1 to 6.

8. A metrology method, characterized by, The measurement method comprises: providing a substrate, sequentially forming a front layer pattern, a current layer and a photoresist layer on the substrate, and performing photoetching patterning on the photoresist layer based on the mask pattern as claimed in claim 7; measuring critical dimensions of the front layer pattern and the patterned photoresist layer, and measuring overlay error of the front layer pattern and the patterned photoresist layer; etching the current layer based on the patterned photoresist layer to obtain a current pattern; measuring critical dimensions of the current pattern, and measuring overlay error of the current pattern and the front layer pattern.

9. The metrology method of claim 8, wherein: measuring critical dimensions of the current pattern by a CDSEM machine, and measuring overlay error of the current pattern and the front layer pattern by the CDSEM machine.

10. The metrology method of claim 8, wherein: The measurement method further comprises a step of comparing and analyzing the measured overlay error of the current pattern and the front layer pattern with the measured overlay error of the front layer pattern and the patterned photoresist layer.

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