Operation component, operation method and chip

Abstract

The embodiment of the invention discloses an operation component, an operation method and a chip. Wherein the data processing module comprises M operation paths, a serial processing unit of the control module is used for splitting current input data into N vectors, and a time sequence control unit is used for controlling the serial processing unit to send one vector to a preprocessing unit of at least one operation path in each period in a plurality of continuous periods; a pre-processing unit of the operation path is used for pre-processing a vector, an iterative calculation unit is used for carrying out iterative calculation on the vector to obtain a first calculation result, a post-processing unit is used for post-processing the first calculation result to obtain a second calculation result, and the second calculation result is sent to a result cache unit; and a result cache unit of the control module is used for caching the second calculation results and outputting a final calculation result according to all the second calculation results of the current input data. According to the method, hardware resources can be reused and the area overhead and the power consumption can be reduced while the calculation performance of division and extraction calculation is relatively good.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a computing unit, computing method and chip. Background Technology

[0002] In computationally intensive fields such as deep learning training and inference, real-time graphics rendering, and high-performance scientific computing, computing architectures are shifting from simply pursuing peak computing power to optimizing designs that prioritize energy efficiency. Compared to traditional FP32 / FP64 data formats, narrow bit-width data not only reduces data bandwidth requirements but also doubles the computational throughput within the same chip area, reducing chip power consumption and better meeting current design needs.

[0003] In floating-point computing unit design, division and square root operations are among the most computationally complex operations. In existing division and square root calculations, each input data is split into multiple vectors, and all vectors are computed in parallel. Taking FP16 division and square root calculations with a bit width of 128 bits as an example... Figure 1 As shown, the input data is split into vectors 0 to 7. The computing unit includes 8 complete and independent computing units. Each vector is sent to a computing unit to perform parallel computing on the 8 vectors, so as to realize the simultaneous processing of 8 independent FP16 data elements.

[0004] The inventors discovered that the above design uses narrow bit-width data FP16, and all vectors are computed in parallel, resulting in high computational throughput in a single cycle, but also in high area overhead and significantly increased hardware resource consumption. Summary of the Invention

[0005] In view of this, the present disclosure provides a computing unit, computing method and chip that can achieve good computing performance in division and square root calculations while reusing hardware resources, reducing area overhead and power consumption.

[0006] In a first aspect, the present disclosure provides a computing unit, which adopts the following technical solution: The arithmetic unit is used to perform division and / or square root operations. The arithmetic unit includes a data processing module and a control module. The data processing module includes M computation paths, each of which includes a preprocessing unit, an iterative calculation unit, and a postprocessing unit; the control module includes a serial processing unit, a timing control unit, and a result buffer unit; M is a positive integer less than N, and N is a positive integer determined based on the bit width of the current input data and the algorithm type; The serial processing unit is used to split the current input data into N vectors; the timing control unit is used to control the serial processing unit to send one vector to the preprocessing unit of at least one computing path in each of multiple consecutive cycles. The preprocessing unit is used to preprocess the vector; the iterative calculation unit is used to perform iterative calculation on the vector to obtain a first calculation result; the postprocessing unit is used to postprocess the first calculation result to obtain a second calculation result, and send it to the result caching unit. The result caching unit is used to cache the second calculation result and output the final calculation result based on all the second calculation results of the current input data.

[0007] Optionally, M=1, and the timing control unit is specifically used to control the serial processing unit to send the first to N vectors of the current input data to the preprocessing unit in N consecutive cycles starting from t1, where t1 is the start cycle of the current input data operation.

[0008] Optionally, the timing control unit is further configured to control the serial processing unit to send the first to Nth vectors of the next input data to the preprocessing unit in the N+1th to 2Nth cycles starting from t1.

[0009] Optionally, M > 1, and M is a divisor of N; the serial processing unit is further configured to distribute N vectors equally among M operation paths; the timing control unit is specifically configured to control the serial processing unit to send the N / M vectors corresponding to each operation path to the corresponding preprocessing unit in a continuous N / M cycle starting from t1, where t1 is the start cycle of the current input data operation.

[0010] Optionally, the timing control unit is further configured to control the serial processing unit to send the N / M vectors allocated to each operation path of the next input data to the corresponding preprocessing unit in the N / M+1 to 2N / Mth cycles starting from t1.

[0011] Optionally, the iterative calculation unit includes cascaded multi-level calculation sub-units; the preprocessing unit, the various levels of calculation sub-units of the iterative calculation unit, and the postprocessing unit process the same vector sequentially in multiple consecutive cycles.

[0012] Optionally, the timing control unit is further configured to control the preprocessing unit to send the preprocessed vector's preprocessing information to the corresponding postprocessing unit.

[0013] Optionally, the timing control unit is specifically used to control the preprocessing unit to send preprocessing information to the corresponding postprocessing unit during the period of postprocessing the vector.

[0014] Optionally, the preprocessing of the vector includes: when the operands represented by the vector are non-special data, determining whether they are non-standard numbers; if they are non-standard numbers, converting them into standard numbers; preprocessing the converted standard numbers to make them meet the conditions for iterative calculation; if they are standard numbers, preprocessing them to make them meet the conditions for iterative calculation.

[0015] Optionally, the preprocessing of the vector further includes: when the operands represented by the vector are special data, obtaining a third calculation result, and sending the third calculation result to the result caching unit for caching; The result caching unit is specifically used to cache the second calculation result and the third calculation result, and output the final calculation result based on the second calculation result and / or the third calculation result of all N vectors of the current input data.

[0016] Optionally, the preprocessing unit is further configured to report an exception when an exception occurs, and the postprocessing unit is further configured to report an exception when an exception occurs. The control module further includes an exception handling unit, which is configured to receive the exception reported by the preprocessing unit and the exception reported by the postprocessing unit, and output the final exception status.

[0017] Secondly, this disclosure provides a calculation method, which adopts the following technical solution: The calculation method is used to perform division and / or square root operations, the calculation method applies the calculation unit described in any of the above claims, and the calculation method includes: The serial processing unit splits the current input data into N vectors; The timing control unit controls the serial processing unit to send a vector to the preprocessing unit of at least one computing path in each of multiple consecutive cycles. The preprocessing unit performs preprocessing on the vector; The iterative calculation unit performs iterative calculations on the vector to obtain a first calculation result; The post-processing unit performs post-processing on the first calculation result to obtain a second calculation result, which is then sent to the result caching unit. The result caching unit caches the second calculation result and outputs the final calculation result based on all the second calculation results of the current input data.

[0018] Optionally, the current input data has a bit width of 128 bits, the algorithm type is FP16, and the serial processing unit splits the input data into 8 vectors.

[0019] Thirdly, embodiments of this disclosure provide a chip, the chip including any of the computing components described above.

[0020] When the arithmetic unit provided in this embodiment performs division and / or square root operations, the current input data is split into N vectors by a serial processing unit. A timing control unit controls the serial processing unit to send one vector to the preprocessing unit of at least one arithmetic path in each of several consecutive cycles. The preprocessing unit preprocesses the vectors. An iterative calculation unit iteratively calculates the vectors to obtain a first calculation result. A post-processing unit post-processes the first calculation result to obtain a second calculation result, which is then sent to a result buffer unit. The result buffer unit buffers the second calculation result and outputs the final calculation result based on all the second calculation results of the current input data. Since the timing control unit controls the serial processing unit to send one vector to the preprocessing unit of at least one arithmetic path in each of several consecutive cycles, at least one arithmetic path can perform operations without waiting for the post-processing of the previous vector to complete before preprocessing the next vector. As soon as the preprocessing of the previous vector is finished, the preprocessing unit can receive the next vector and preprocess it. This allows at least one arithmetic path to be reused during the operation, thereby achieving good computational performance in division and square root calculations while reusing hardware resources, reducing area overhead, and reducing power consumption.

[0021] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A structural diagram of the computing unit provided for the prior art; Figure 2 This is a structural diagram of the first type of computing unit provided in an embodiment of the present disclosure; Figure 3 This is a structural diagram of a second type of computing unit provided in an embodiment of this disclosure; Figure 4 A timing diagram of the operation of a first type of computing unit provided in this embodiment of the present disclosure; Figure 5 This is a timing diagram of the operation of the second type of computing unit provided in an embodiment of this disclosure; Figure 6 A schematic diagram of the computational path provided in the embodiments of this disclosure; Figure 7 A schematic diagram of the preprocessing procedure provided in the embodiments of this disclosure; Figure 8 A schematic diagram of the iterative calculation process provided in the embodiments of this disclosure. Figure 1 ; Figure 9 A schematic diagram of the iterative calculation process provided in the embodiments of this disclosure. Figure 2 ; Figure 10 Timing diagrams of the computing unit provided for existing technologies; Figure 11 A flowchart of the calculation method provided in the embodiments of this disclosure; Figure 12 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0024] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0025] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0026] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0027] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0029] This disclosure provides an arithmetic unit for performing division and / or square root operations, specifically, as shown in the following embodiments. Figure 2 and Figure 3 As shown, the computing unit includes a data processing module 10 and a control module 20, wherein, The data processing module includes M operation paths, each of which includes a pre-processing unit 11, an iterative calculation unit 12, and a post-processing unit 13; the control module 20 includes a serial processing unit 21, a timing control unit 22, and a result buffer unit 23; M is a positive integer less than N, and N is a positive integer determined based on the bit width of the current input data and the algorithm type; The serial processing unit 21 is used to split the current input data into N vectors; the timing control unit 22 is used to control the serial processing unit 21 to send one vector to the preprocessing unit 11 of at least one computing path in each of multiple consecutive cycles. The preprocessing unit 11 is used to preprocess the vector; the iterative calculation unit 12 is used to perform iterative calculation on the vector to obtain a first calculation result; the postprocessing unit 13 is used to postprocess the first calculation result to obtain a second calculation result and send it to the result cache unit 23. The result caching unit 23 is used to cache the second calculation result and output the final calculation result based on all the second calculation results of the current input data.

[0030] In this embodiment of the disclosure, M can take multiple values. For example, M is 1, which means that the data processing module 10 includes one operation path. Or, M is greater than 1, which means that the data processing module 10 includes multiple operation paths. The following will illustrate the relevant details of the operation component when M takes different values.

[0031] In one example, such as Figure 2 As shown, the data processing module 10 in this embodiment includes only one operation path, i.e., M=1. The timing control unit 22 is specifically used to control the serial processing unit 21 to send the first to N vectors of the current input data to the preprocessing unit 11 in N consecutive cycles starting from t1. t1 is the start cycle of the operation of the current input data. Figure 2 The computing unit shown has only one computing path, with the highest degree of hardware resource reuse, the smallest area overhead, and the lowest power consumption. Through the above-mentioned control of the timing control unit 22, it can still have good computing performance.

[0032] against Figure 2 The arithmetic unit shown takes FP16 division or square root operation on current input data with a bit width of 128 bits as an example. Figure 4 As shown, the serial processing unit 21 splits the current input data (the input data corresponding to the division instruction 0) into 8 vectors, namely vector 0, vector 1, vector 2, vector 3, vector 4, vector 5, vector 6 and vector 7. The timing control unit 22 controls the serial processing unit 21 to send vectors 0 to 7 to the preprocessing unit 11 in sequence from the first cycle to the 8th cycle.

[0033] Furthermore, in the embodiments of this disclosure, Figure 2 The timing control unit 22 in the shown arithmetic unit is also used to control the serial processing unit 21 to send the first to Nth vectors of the next input data to the preprocessing unit 11 sequentially in the (N+1)th to 2Nth cycles starting from t1. This configuration allows for the reuse of computation paths between vectors corresponding to the same computation instruction, and also allows for the reuse of computation paths between vectors corresponding to adjacent computation instructions. This enables pipelined processing of computation instructions, improves the utilization rate of the computation path, and further reduces area overhead and power consumption.

[0034] Continuing with the example of performing FP16 division or square root operations on the current input data with a bit width of 128 bits, as follows... Figure 4As shown, the serial processing unit 21 splits the next input data (the input data corresponding to the division instruction 1) into 8 vectors, namely vector 0, vector 1, vector 2, vector 3, vector 4, vector 5, vector 6 and vector 7. The timing control unit 22 controls the serial processing unit 21 to send vectors 0 to 7 to the preprocessing unit 11 in sequence from the 9th cycle to the 16th cycle.

[0035] In yet another example, in an embodiment of this disclosure, such as Figure 3 As shown, the data processing module 10 includes M processing paths, where 1 < M < N, and M is a divisor of N. For example, if N is 8, M can be 2 or 4. Figure 3 In the example, M is 2; the serial processing unit 21 is also used to distribute N vectors equally to M operation paths, with each operation path being allocated N / M vectors; the timing control unit 22 is specifically used to control the serial processing unit 21 to send the N / M vectors corresponding to each operation path to the corresponding preprocessing unit 11 in a continuous N / M cycle starting from t1, where t1 is the start cycle of the current input data operation. Figure 3 The computing unit shown in the example has M computing paths. During the processing of the current input data, each computing path is reused, resulting in high hardware resource reuse, small area overhead, and low power consumption. Through the parallel computing of multiple computing paths and the aforementioned control of the timing control unit 22, the computing unit can achieve better computing performance.

[0036] against Figure 3 The arithmetic unit shown takes FP16 division or square root operation on current input data with a bit width of 128 bits as an example. Figure 5 As shown, the serial processing unit 21 splits the current input data (the input data corresponding to division instruction 0) into 8 vectors, namely vector 0, vector 1, vector 2, vector 3, vector 4, vector 5, vector 6, and vector 7. Four vectors are allocated to each of the two operation paths. The timing control unit 22 controls the serial processing unit 21 to send vectors 0 to 3 sequentially to the pre-processing unit 11 of one operation path in cycles 1 to 4, and to send vectors 4 to 7 sequentially to the pre-processing unit 11 of the other operation path in cycles 1 to 4. Of course, the above vector allocation method is only an example; those skilled in the art can choose according to actual needs.

[0037] Furthermore, in the embodiments of this disclosure, Figure 3The timing control unit 22 in the shown arithmetic unit is also used to control the serial processing unit 21 to send the N / M vectors allocated to each arithmetic path of the next input data to the corresponding preprocessing unit 11 in the N / M+1 to 2N / Mth cycles starting from t1. This configuration allows for the reuse of arithmetic paths between vectors corresponding to the same arithmetic instruction, and also allows for the reuse of arithmetic paths between vectors corresponding to adjacent arithmetic instructions. This enables pipelined processing of arithmetic instructions, greatly improving computational throughput, increasing the utilization of arithmetic paths, further reducing area overhead, and lowering power consumption.

[0038] Continuing with the example of data processing module 10, which includes two arithmetic paths, performing FP16 division or square root operations on the current input data with a bit width of 128 bits, as follows: Figure 5 As shown, the serial processing unit 21 splits the next input data (the input data corresponding to the division instruction 1) into 8 vectors, namely vector 0, vector 1, vector 2, vector 3, vector 4, vector 5, vector 6 and vector 7. Four vectors are allocated to each of the two operation paths. The timing control unit 22 controls the serial processing unit 21 to send vectors 0 to 3 to the pre-processing unit 11 of one operation path in cycles 5 to 8, and to send vectors 4 to 7 to the pre-processing unit 11 of the other operation path in cycles 5 to 8.

[0039] In another example, the data processing module 10 includes M processing paths, where 1 < M < N, and M is not a divisor of N. The serial processing unit 21 is also used to allocate N vectors to the M processing paths, with the specific allocation method determined according to actual needs. The timing control unit 22 is specifically used to control the serial processing unit 21 to send the allocated vectors to the corresponding preprocessing unit 11 one per cycle for each processing path within a continuous period. In the above example, although it is difficult to achieve full-cycle reuse of all processing paths, reuse is still achieved within a certain period. Compared with existing technologies, this can improve the degree of hardware resource reuse, reduce area overhead and power consumption, and maintain good computing performance at the same time.

[0040] Optionally, the iterative calculation unit 12 in this embodiment includes cascaded multi-level calculation sub-units; the preprocessing unit 11, the various levels of calculation sub-units of the iterative calculation unit 12, and the postprocessing unit 13 process the same vector sequentially in multiple consecutive cycles.

[0041] For example, the iterative calculation unit 12 in this embodiment includes P-level cascaded calculation sub-units, where P is a positive integer determined according to the algorithm type. Specifically, the pre-processing unit 11, the various calculation sub-units of the iterative calculation unit 12, and the post-processing unit 13 process the same vector sequentially over multiple consecutive cycles. This includes: for the i-th vector of the current input data transmitted to a computation path, in the (t1+i-1)th to (t1+i+P)th cycles, the pre-processing unit 11, the various calculation sub-units of the iterative calculation unit 12, and the post-processing unit 13 process the i-th vector sequentially, where t1 is the start cycle of the current input data computation. This configuration ensures that not only does the computation path receive vectors pipelinedly from the control path, but the processing of vectors within the computation path is also completely pipelined. Within the same cycle, the various calculation sub-units of the same iterative calculation unit 12 can simultaneously perform iterative calculations on different vectors, which helps to further improve the reuse of hardware resources, reduce area overhead, lower power consumption, and improve computational performance.

[0042] It should be noted that, for the value of i, when the arithmetic unit includes one arithmetic path, i can take any integer value between 1 and N. When the arithmetic unit includes M arithmetic paths, i can take any integer value between 1 and the total number of vectors assigned to one arithmetic path.

[0043] like Figure 6 As shown, the iterative calculation unit 12 includes four cascaded calculation subunits, combined with... Figure 2 , Figure 4 and Figure 6 As shown, FP16 division or square root operations are performed on the current input data with a bit width of 128 bits. From the perspective of a single vector, for the first vector of the current input data transmitted to the operation path, the preprocessing unit 11, the four-level calculation subunit of the iterative calculation unit 12, and the postprocessing unit 13 process the first vector sequentially from the 1st to the 6th cycle. For the second vector of the current input data transmitted to the operation path, the preprocessing unit 11, the four-level calculation subunit of the iterative calculation unit 12, and the postprocessing unit 13 process the second vector sequentially from the 2nd to the 7th cycle, and so on for other vectors. From the perspective of a single cycle, taking the 6th cycle as an example, in the 6th cycle, the preprocessing unit 11 preprocesses vector 5, the four-level calculation subunit of the iterative calculation unit 12 performs iterative calculations on vectors 4, 3, 2, and 1 respectively, and the postprocessing unit 13 performs postprocessing on the first calculation result of vector 0.

[0044] Optionally, such as Figure 2 and Figure 3As shown, in this embodiment of the present disclosure, the timing control unit 22 is also used to control the preprocessing unit 11 to send the preprocessing information of the preprocessed vector to the corresponding postprocessing unit 13, so that the postprocessing unit 13 can directly determine the preprocessing-related details based on the preprocessing information and perform corresponding postprocessing operations accordingly, which is more efficient.

[0045] Furthermore, in this embodiment, the timing control unit 22 is specifically used to control the preprocessing unit 11. During the postprocessing cycle of the vector, the preprocessing information is sent to the corresponding postprocessing unit 13, so that the first calculation result of the vector and its corresponding preprocessing information arrive at the postprocessing unit 13 synchronously. The postprocessing unit 13 directly performs postprocessing based on the preprocessing information and the first calculation result to obtain the second calculation result, without the need to perform additional operations such as matching the first calculation result with the preprocessing information. The above preprocessing information may be the result sign bit, rounding mode, etc., which are specifically determined according to the specific content of the preprocessing.

[0046] Optionally, such as Figure 7 As shown, in this embodiment, the preprocessing unit 11 performs preprocessing on the vector in the following specific manner: when the operand represented by the vector (in the figure, the first operand is non-special data) is determined to be an unnormalized number; if it is an unnormalized number, it is converted into a normalized number, and the converted normalized number is preprocessed to meet the conditions for iterative calculation; if it is a normalized number, it is preprocessed to meet the conditions for iterative calculation. Further, as... Figure 7 As shown, in this embodiment, the preprocessing unit 11 further includes the following method for preprocessing vectors: when the operands represented by the vector are special data, a third calculation result is obtained, and the third calculation result is sent to the result caching unit 23 for caching. Based on the above specific design of the preprocessing unit 11, the result caching unit 23 in this embodiment is specifically used to cache the second and third calculation results, and output the final calculation result based on the second and / or third calculation results of all N vectors of the current input data.

[0047] In summary, the preprocessing unit 11 is responsible for determining special data, converting non-standard numbers, and preprocessing before calculation. Special data refers to input data that does not require calculation and yields a direct result. Examples include divisors or dividends containing 0, Not a Number (NaN), or Infinity (INF). If the operand represented by the vector is not special data, it is first determined whether it is a non-standard number. If so, it needs to be converted to a standard number before preprocessing to meet the conditions required for iterative calculation. Iterative calculation requires the following conditions: division requires the dividend to be greater than or equal to the divisor; square root calculation requires the exponent of the radicand to be even. If the division calculation does not meet the conditions, the mantissa of the dividend needs to be shifted left by 1 bit and the exponent decremented by 1 during preprocessing; similarly, if the square root calculation does not meet the conditions, the mantissa of the radicand needs to be shifted left by 1 bit and the exponent decremented by 1 during preprocessing.

[0048] In addition, when an exception occurs in the current processing unit 11, the exception can be reported as needed, such as invalidity exception, division by zero exception, denormalization exception, etc. Figure 7 As shown, when the operands in the vector representation are special data, an exception can be checked first. If an exception exists, the exception is reported first and then the third calculation result is obtained. If no exception exists, the third calculation result can be obtained directly.

[0049] Optionally, the iterative algorithm used by the iterative calculation unit 12 in this embodiment of the present disclosure can be a remainder recovery algorithm, a non-recovery remainder algorithm, an SRT algorithm, or a Goldschmidt algorithm, etc. When different iterative algorithms are used, the iterative calculation unit 12 has different implementation forms, which are illustrated below with examples.

[0050] In the first example, the iterative algorithm is the recovery remainder algorithm, such as... Figure 8 As shown, initialization is performed first. During initialization, the remainder w[0] = dividend, d = divisor, and counter j = 0. In each iteration, it is first determined whether the iteration number j is less than n. If j is less than n, the remainder w[0] is shifted left by 1 bit and subtracted from the divisor d. If the subtraction result w[j+1] ≥ 0, the quotient q[j] = 1 for this iteration, and the subtraction result is output for the next iteration. If the subtraction result w[j+1] < 0, the quotient q[j] = 0 for this iteration, and the next iteration is performed. The result of shifting the remainder left by 1 bit for this iteration is output for the next iteration. When j is not less than n, the iteration ends, and the quotient = q and the remainder = w[j+1] are output. The number of iterations n is related to the current data type of the division square root, n = floating-point decimal width + 2. After n iterations, the first calculation result including the quotient and the remaining remainder can be obtained and output to the post-processing unit 13.

[0051] In the second example, the iterative algorithm is a non-recovery remainder algorithm, such as... Figure 9 As shown, initialization is performed first. During initialization, the remainder w[0] = dividend, d = divisor, and counter j = 0. In each iteration, it is first determined whether the iteration number j is less than n. When j is less than n, it is determined whether w[j] ≥ 0. If w[j] ≥ 0, the remainder w[0] is shifted left by 1 bit and subtracted from the divisor d to obtain w[j+1]. If w[j] < 0, the remainder w[0] is shifted left by 1 bit and subtracted from the divisor d to obtain w[j+1]. The addition yields w[j+1]. Further checks if w[j+1] ≥ 0. If w[j+1] ≥ 0, the quotient q[j] = 1. If w[j+1] < 0, the quotient q[j] = 0. The iteration ends when j is not less than n. At this point, if w[j+1] < 0, the output quotient = q - 1 and the partial remainder = w[j+1] + d. If w[j+1] ≥ 0, the output quotient = q and the partial remainder = w[j+1].

[0052] Compared with the recovery remainder algorithm, the main difference is that the non-recovery remainder algorithm supports the partial remainder w[j] of each iteration being negative. If it is negative, the partial remainder w[j+1] of the next iteration will be w[j]+d. Moreover, after the iteration ends, the quotient and remainder will be corrected according to the sign of the last partial remainder w[j+1], and the quotient will be q or q-1.

[0053] In the third example, the iterative algorithm is the SRT algorithm. The overall process is similar to the non-recovery remainder algorithm, except that in each iteration, the quotient of the non-recovery remainder algorithm is 0 or 1, while in the SRT algorithm, the range of quotients that can be selected is larger depending on the radix. This allows multiple bits to be obtained in one iteration. For example, in radix 2-SRT, the quotient can be -1, 0, or 1; in radix 4-SRT, the quotient can be -2, -1, 0, 1, or 2. However, a larger radix makes the calculation more complex in each iteration, and the quotient is usually obtained by looking up a table.

[0054] Optionally, the post-processing unit 13 in this embodiment is specifically used for rounding the first calculation result, converting non-standard numbers, and judging three types of exceptions: overflow, underflow, and inaccuracy. For example, the post-processing unit 13 first shifts the first calculation result based on the shift amount obtained in the pre-processing unit 11 to convert the non-standard number to a standard number, obtaining an intermediate result. If the operands in the pre-processing are directly standard numbers, no further shifting is needed, and the first calculation result is directly used as the intermediate result. Then, the intermediate result is rounded to obtain the final result. The final result is then judged for inaccuracy and overflow. If the final result exceeds the representable range of standard numbers, an overflow or underflow exception is reported. If the final result is inaccurate, an inaccuracy exception is reported. Optionally, the post-processing unit 13 supports four rounding modes: rounding to nearest, rounding towards zero, rounding towards positive infinity, and rounding towards negative infinity.

[0055] It should be noted that the timing of the serial processing unit 21 performing vector splitting on the input data in this embodiment is not limited, as long as it is completed before the first vector of the input data is preprocessed, ensuring that it can be sent to the preprocessing unit 11 for preprocessing in the corresponding period.

[0056] Optionally, the timing control unit 22 in this embodiment includes a state machine, which controls the serial processing unit 21 to send each vector in the input data to the preprocessing unit 11 in a set timing sequence, and / or to send the preprocessing information of the vectors to the corresponding postprocessing unit 13 in a set timing sequence.

[0057] Optionally, the result caching unit 23 in this embodiment of the present disclosure has two sets of inputs. The first set is the third calculation result generated by the preprocessing unit 11 based on special data, at which point iterative calculation is not required. The second set is the second calculation result obtained after iterative calculation and post-processing. After all the results (second calculation result and / or third calculation result) for a given input data have been cached, all results are integrated and output to obtain the final calculation result.

[0058] Optionally, such as Figure 2 , Figure 3As shown, the preprocessing unit 11 is also used to report exceptions when they occur, and the postprocessing unit 13 is also used to report exceptions when they occur. The control module 20 also includes an exception handling unit 24, which receives the exceptions reported by the preprocessing unit 11 and the postprocessing unit 13, and outputs the final exception status. For example, when the preprocessing unit 11 can report three types of calculation exceptions and the postprocessing unit 13 can report three types of calculation exceptions, a 6-bit exception flag is configured for each operation instruction. The exception handling unit 24 selectively enables or masks specific exceptions based on the exception mask configuration of the flag bits corresponding to each exception, and finally outputs the final exception status.

[0059] When the arithmetic unit provided in this embodiment performs division and / or square root operations, the current input data is split into N vectors by the serial processing unit 21; the timing control unit 22 controls the serial processing unit 21 to send one vector to the preprocessing unit 11 of at least one arithmetic path in each of multiple consecutive cycles; the preprocessing unit 11 performs preprocessing on the vectors; the iterative calculation unit 12 performs iterative calculation on the vectors to obtain a first calculation result; the postprocessing unit 13 performs postprocessing on the first calculation result to obtain a second calculation result, which is sent to the result buffer unit 23; the result buffer unit 23 buffers the second calculation result and outputs the final calculation result based on all the second calculation results of the current input data. In this process, since the timing control unit 22 controls the serial processing unit 21 to send a vector to the preprocessing unit 11 of at least one operation path in each of multiple consecutive cycles, the operation path does not need to wait for the post-processing of the previous vector to be completed before the pre-processing of the next vector. As soon as the pre-processing of the previous vector is completed, the pre-processing unit 11 can receive the next vector and pre-process it, thus realizing pipelined processing of vectors. This enables the at least one operation path to be reused during the operation process, thereby achieving good computational performance in division and square root calculations while reusing hardware resources, reducing area overhead, and reducing power consumption.

[0060] To more clearly illustrate the technical advantages of the computing unit in this embodiment compared with the prior art, a comparative explanation is given using the same division operation as an example.

[0061] In this embodiment of the disclosure, Figure 2 When the arithmetic unit shown performs FP16 division or square root operations on the current input data with a bit width of 128 bits, it pipelines eight vectors through a single arithmetic path. The timing sequence of the arithmetic unit is as follows: Figure 4As shown, for the input data corresponding to division instruction 0, the process from preprocessing starting with the first vector 0 to processing after vector 7 and outputting the final calculation result lasts for 14 cycles (1~14). For the input data corresponding to division instruction 1, the process from preprocessing starting with the first vector 0 to processing after vector 7 and outputting the final calculation result lasts for 14 cycles (9~22). Multiple cycles simultaneously process both division instructions 0 and 1, allowing the execution of both division instructions (0 and 1) to be completed in only 22 cycles through a single computation path. In this computation process, the arithmetic unit achieves a throughput of 0.125 and realizes pipelined execution between computation instructions.

[0062] In existing technologies, Figure 1 When the arithmetic unit shown performs FP16 division or square root operations on the current input data with a bit width of 128 bits, such as Figure 10 As shown, for the input data corresponding to division instruction 0, 8 vectors are processed in parallel, and the processing of division instruction 0 lasts for 7 cycles (1~7). For the input data corresponding to division instruction 1, 8 vectors are processed in parallel, and the processing of division instruction 1 lasts for 7 cycles (8~14). In the prior art, although the execution of two division instructions, division instruction 0 and division instruction 1, can be completed in 14 cycles, it requires parallel processing by 8 arithmetic units.

[0063] Furthermore, this disclosure provides an arithmetic method for performing division and / or square root operations. The arithmetic method utilizes any of the arithmetic components described above, specifically, as shown in... Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 11 As shown, the calculation methods include: Step S1: The serial processing unit 21 splits the current input data into N vectors; Step S2: The timing control unit 22 controls the serial processing unit 21 to send a vector to the preprocessing unit 11 of at least one computing path in each of multiple consecutive cycles. Step S3: Preprocessing unit 11 performs preprocessing on the vector; Step S4: Iterative calculation unit 12 performs iterative calculations on the vector to obtain the first calculation result; Step S5: Post-processing unit 13 performs post-processing on the first calculation result to obtain the second calculation result, and sends it to the result cache unit 23; Step S6: The result caching unit 23 caches the second calculation result and outputs the final calculation result based on all the second calculation results of the current input data.

[0064] If there is no explicit input-output relationship between the above steps, the order can be adjusted according to actual needs.

[0065] Optionally, the operation method in this embodiment further includes: reporting an exception when an exception occurs in the preprocessing unit 11, and / or, when the postprocessing unit 13 reports an exception when an exception occurs, the exception handling unit 24 receives the exception reported by the preprocessing unit 11 and the exception reported by the postprocessing unit 13, and outputs the final exception status.

[0066] Optionally, in this embodiment of the disclosure, the current input data has a bit width of 128 bits, the algorithm type is FP16, and the serial processing unit 21 splits the input data into 8 vectors. The above is only an example of a 128-bit FP16 data division and square root operation unit. For other bit widths, such as 64 bits, or other data types, such as FP8, only the number of vectors and the number of iterations differ; the overall implementation idea is the same. FP16, FP8, BF16, INT8, and INT4 are also mentioned.

[0067] It should be noted that the details of the computing components in the embodiments of this disclosure are applicable to the corresponding computing methods, and will not be repeated here.

[0068] Furthermore, this disclosure provides a chip including the computing components described in any of the above embodiments. With the continuous expansion of integrated circuit design scale and the ongoing evolution of chip manufacturing processes, hardware resource overhead has become a key indicator in modern processor architecture design. Especially in applications such as high-performance computing and embedded systems, the chip in this disclosure can fully reuse computing paths while ensuring the performance of narrow-bit-width data division / square root instructions, thus greatly reducing hardware area.

[0069] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0070] The processor may be a central processing unit (CPU) or other processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the arithmetic methods described in the foregoing embodiments of this disclosure.

[0071] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0072] like Figure 12 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 4 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0073] like Figure 12 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0074] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 12 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0075] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processor, all or part of the steps of the operational methods of embodiments of this disclosure are performed.

[0076] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0077] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the arithmetic methods described in the foregoing embodiments of the present disclosure are performed.

[0078] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0079] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0080] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0081] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0082] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0083] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0084] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0085] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0086] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. An arithmetic unit for performing division and / or square root operations, characterized in that, The operation component comprises a data processing module and a control module, wherein, The data processing module comprises M operation channels, the operation channel comprises a pre-processing unit, an iterative calculation unit and a post-processing unit; the control module comprises a serial processing unit, a timing control unit and a result cache unit; M is a positive integer less than N, N is a positive integer determined according to the bit width of the current input data and the algorithm type; The serial processing unit is used for splitting the current input data into N vectors; the timing control unit is used for controlling the serial processing unit to send one vector to the pre-processing unit of at least one operation channel every cycle in continuous multiple cycles; The pre-processing unit is used for pre-processing the vector; the iterative calculation unit is used for iterative calculation on the vector to obtain a first calculation result; the post-processing unit is used for post-processing the first calculation result to obtain a second calculation result and sending the second calculation result to the result cache unit; The result cache unit is used for caching the second calculation result and outputting a final calculation result according to all second calculation results of the current input data.

2. The operation member according to claim 1, characterized in that, M=1, and the timing control unit is specifically configured to control the serial processing unit to send the 1st to Nth vectors of the current input data to the pre-processing unit in turn in continuous N cycles from t1, t1 being an operation start cycle of the current input data.

3. The operation component according to claim 2, wherein The timing control unit is further configured to control the serial processing unit to send the 1st to Nth vectors of the next input data to the pre-processing unit in turn in the N+1th to 2Nth cycles from t1.

4. The operation component according to claim 1, wherein M>1, and M is a divisor of N; the serial processing unit is further configured to evenly distribute the N vectors to the M operation channels; and the timing control unit is specifically configured to control the serial processing unit to send the N / M vectors corresponding to each operation channel to the corresponding pre-processing unit in turn in continuous N / M cycles from t1, t1 being an operation start cycle of the current input data.

5. The arithmetic unit according to claim 4, wherein The timing control unit is further configured to control the serial processing unit to send the N / M vectors of the next input data distributed to each operation channel to the corresponding pre-processing unit in turn in the N / M+1th to 2N / Mth cycles from t1.

6. The arithmetic unit according to claim 1, wherein The iterative calculation unit comprises a plurality of cascade-connected calculation subunits; the pre-processing unit, each calculation subunit of the iterative calculation unit and the post-processing unit process the same vector in turn in continuous multiple cycles.

7. The operation component according to claim 1, wherein The timing control unit is further configured to control the pre-processing unit to send pre-processing information of the pre-processed vector to the corresponding post-processing unit.

8. The arithmetic unit according to claim 7, wherein The timing control unit is specifically configured to control the pre-processing unit to send the pre-processing information to the corresponding post-processing unit in a cycle of post-processing the vector.

9. The operation component according to claim 1, wherein The pre-processing of the vector comprises: when an operand represented by the vector is non-special data, judging whether it is a non-standard number, if it is a non-standard number, converting it into a standard number, pre-processing the converted standard number to make it meet the condition of iterative calculation, and if it is a standard number, pre-processing it to make it meet the condition of iterative calculation.

10. The arithmetic unit according to claim 9, wherein The pre-processing of the vector further includes: when the operand of the vector representation is special data, obtaining a third calculation result, and sending the third calculation result to the result cache unit for caching; The result cache unit is specifically configured to cache the second calculation result and the third calculation result, and output a final calculation result according to the second calculation result and / or the third calculation result of all N vectors of the current input data.

11. The arithmetic unit according to claim 1, wherein The pre-processing unit is further configured to report an exception when the exception occurs, the post-processing unit is further configured to report an exception when the exception occurs, and the control module further includes an exception processing unit configured to receive the exception reported by the pre-processing unit and the exception reported by the post-processing unit, and output a final exception state.

12. An operation method for performing division and / or square root operation, the operation method applying the operation member according to any one of claims 1 to 11, characterized by The operation method includes: The serial processing unit splits the current input data into N vectors; The timing control unit controls the serial processing unit to send one vector to the pre-processing unit of at least one operation path every cycle in a plurality of consecutive cycles; The pre-processing unit pre-processes the vector; The iteration calculation unit performs iteration calculation on the vector to obtain a first calculation result; The post-processing unit post-processes the first calculation result to obtain a second calculation result, and sends the second calculation result to the result cache unit; The result cache unit caches the second calculation result, and outputs a final calculation result according to all second calculation results of the current input data.

13. The operation method according to claim 12, wherein The bit width of the current input data is 128 bits, the algorithm type is FP16, and the serial processing unit splits the input data into 8 vectors.

14. A chip, characterized by The operation component includes any one of claims 1-11. The operation component includes any one of claims 1-11.

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