Instruction processing device and method, processor and electronic equipment

Abstract

The invention relates to the technical field of processors, and provides an instruction processing device and method, a processor and electronic equipment. The device comprises a merging module and a renaming module, and the merging module is used for merging the current microinstruction as a subordinate microinstruction to a previous microinstruction and outputting the subordinate microinstruction to the renaming module when an execution result of the current microinstruction is known; when the execution result of the current microinstruction is unknown, outputting the previous microinstruction to the renaming module; the renaming module is used for recording an identifier indicating an execution result of a subordinate microinstruction when the execution result of the subordinate microinstruction of the received microinstruction is known to be a constant; the microinstruction output by the merging module is a microinstruction expected to be executed, and when a source operand of the microinstruction output by the merging module is an execution result of any subordinate microinstruction and the execution result is known to be a constant, the numerical value of the source operand is determined according to the identifier recorded by the renaming module. The device can reduce the number of to-be-executed microinstructions and improve the execution efficiency of the microinstructions.

Description

Technical Field

[0001] This disclosure relates to the field of processor technology, and more particularly to an instruction processing apparatus, method, processor, and electronic device. Background Technology

[0002] In x86 architecture processors, the instruction execution flow is as follows: The decoding module decodes the instruction to obtain a micro-operation (μop) sequence; the renaming module allocates physical registers for the operands of the micro-instructions, issues the micro-instruction to the reservation station (RS) for source operand preparation, and sends the micro-instruction to the reorder buffer (ROB) to await its retirement; once the reservation station confirms that the micro-instruction has completed source operand preparation, it dispatches the micro-instruction to the execution module for execution; after the execution module executes the micro-instruction, it stores the execution result in the physical register allocated for the destination operand of the micro-instruction and notifies the reorder buffer that the micro-instruction is awaiting retirement. The reorder buffer ensures that each micro-instruction exits in the order it appears in the micro-instruction sequence.

[0003] In the existing technology, each microinstruction in the microinstruction sequence needs to be executed by the execution module, which makes the execution efficiency of the instructions low. Summary of the Invention

[0004] In view of the above, this disclosure provides an instruction processing apparatus, method, processor, and electronic device. The instruction processing apparatus using embodiments of this disclosure can reduce the number of microinstructions to be executed and improve the execution efficiency of microinstructions.

[0005] According to one aspect of this disclosure, an instruction processing apparatus is provided, the apparatus comprising a merging module and a renaming module. The merging module is configured to: acquire a microinstruction sequence; when the execution result of the current microinstruction is known, merge the current microinstruction as a subordinate microinstruction of the previous microinstruction into the previous microinstruction, and then output the previous microinstruction to the renaming module; when the execution result of the current microinstruction is unknown, directly output the previous microinstruction to the renaming module. The renaming module is configured to: when a received microinstruction has a subordinate microinstruction and the execution result of the subordinate microinstruction is known to be a constant, record an identifier indicating the execution result of the subordinate microinstruction; wherein the microinstruction output by the merging module is the microinstruction to be executed, and when the source operand of the microinstruction output by the merging module is the execution result of any subordinate microinstruction and the execution result of the subordinate microinstruction is known to be a constant, the value of the source operand is determined according to the identifier recorded by the renaming module.

[0006] In one possible implementation, the merging module is specifically used to: when the execution result of the current microinstruction is known, determine whether the current microinstruction should be executed sequentially after the previous microinstruction has been executed; and when the current microinstruction is executed sequentially after the previous microinstruction has been executed, merge the current microinstruction into the previous microinstruction.

[0007] In one possible implementation, some microinstructions in the microinstruction sequence include a first destination operand. The merging module is specifically used to, when the execution result of the current microinstruction is known to be a constant, add a second destination operand and an identifier indicating the execution result of the current microinstruction to the previous microinstruction, and then output the previous microinstruction to the renaming module. The second destination operand is equal to the first destination operand of the current microinstruction. When the execution result of the current microinstruction is known and the value of the first destination operand remains unchanged before and after the execution of the current microinstruction, or when the current microinstruction does not include a first destination operand, the execution result of the current microinstruction is known, and the execution of the current microinstruction does not affect the data storage of the physical registers, the previous microinstruction remains unchanged before and after merging.

[0008] In one possible implementation, the renaming module includes a control unit, an allocation unit, and a register alias table. The register alias table includes multiple entries. The control unit is configured to, upon receiving any microinstruction, control the allocation unit to allocate a physical register for the first destination operand of the microinstruction; write the index of the allocated physical register into the register alias table corresponding to the first destination operand of the microinstruction; and, if the microinstruction includes an identifier indicating the execution result of a subordinate microinstruction, write the identifier into the register alias table corresponding to the second destination operand of the microinstruction.

[0009] In one possible implementation, the apparatus further includes a reservation station and an execution module. The renaming module is further configured to: output received microinstructions to the reservation station; and, for each received microinstruction, search the register alias table for an entry corresponding to each source operand of the microinstruction; if any entry corresponding to a source operand stores an identifier indicating the execution result of a subordinate microinstruction, use that identifier as a first parameter carried by the source operand and output it to the reservation station along with the microinstruction; if any entry corresponding to a source operand does not store an identifier indicating the execution result of a subordinate microinstruction, use the index of the physical register stored in that entry as a second parameter carried by the source operand and output it to the reservation station along with the microinstruction. The microinstruction is output to the reservation station; the reservation station is used to store the received microinstructions, wherein each microinstruction is stored in an entry in the reservation station; for any microinstruction stored in an entry, if any source operand included in the microinstruction carries a first parameter, the value indicated by the first parameter is assigned to the source operand; if any source operand included in the microinstruction does not carry a first parameter, the value stored in the physical register allocated to the source operand is obtained according to the second parameter carried by the source operand, and the value is assigned to the source operand; after any microinstruction is output to the execution module for execution, in response to the completion of the microinstruction execution, the entry storing the microinstruction is cleared.

[0010] In one possible implementation, the apparatus further includes a reordering buffer, and the renaming module is further configured to output received microinstructions to the reordering buffer, the reordering buffer being configured to: store received microinstructions, wherein each microinstruction is stored in an entry in the reordering buffer; and, in response to the completion of execution of the microinstruction, cause the microinstruction to enter a waiting exit state.

[0011] According to another aspect of this disclosure, an instruction processing method is provided, the method being applied to an instruction processing apparatus, the apparatus including a merging module and a renaming module, the method comprising: the merging module acquiring a microinstruction sequence; when the execution result of the current microinstruction is known, merging the current microinstruction as a subordinate microinstruction of a previous microinstruction into the previous microinstruction, and then outputting the previous microinstruction to the renaming module; when the execution result of the current microinstruction is unknown, directly outputting the previous microinstruction to the renaming module; the renaming module, when a received microinstruction has a subordinate microinstruction and the execution result of the subordinate microinstruction is known to be a constant, recording an identifier indicating the execution result of the subordinate microinstruction; wherein, the microinstruction output by the merging module is the microinstruction to be executed, and when the source operand of the microinstruction output by the merging module is the execution result of any subordinate microinstruction and the execution result of the subordinate microinstruction is known to be a constant, the value of the source operand is determined according to the identifier recorded by the renaming module.

[0012] In one possible implementation, merging the current microinstruction as a subordinate microinstruction of the previous microinstruction into the previous microinstruction includes: when the execution result of the current microinstruction is known, determining whether the current microinstruction should be executed sequentially after the previous microinstruction has been executed; and when the current microinstruction is executed sequentially after the previous microinstruction has been executed, merging the current microinstruction into the previous microinstruction.

[0013] In one possible implementation, some microinstructions in the microinstruction sequence include a first destination operand. Merging the current microinstruction as a subordinate microinstruction of the previous microinstruction into the previous microinstruction includes: when the execution result of the current microinstruction is known to be constant, adding a second destination operand and an identifier indicating the execution result of the current microinstruction to the previous microinstruction, and then outputting the previous microinstruction to the renaming module, where the second destination operand is equal to the first destination operand of the current microinstruction; when the execution result of the current microinstruction is known and the value of the first destination operand remains unchanged before and after the execution of the current microinstruction, or when the current microinstruction does not include a first destination operand, the execution result of the current microinstruction is known, and the execution of the current microinstruction does not affect the data storage of physical registers, the previous microinstruction remains unchanged before and after merging.

[0014] In one possible implementation, the renaming module includes a control unit, an allocation unit, and a register alias table. The register alias table includes multiple entries. The step of recording an identifier indicating the execution result of a subordinate microinstruction when the received microinstruction has a dependent microinstruction and the execution result of the dependent microinstruction is known to be a constant includes: when the control unit receives any microinstruction, it controls the allocation unit to allocate a physical register for the first destination operand of the microinstruction; the control unit writes the index of the allocated physical register into the register alias table corresponding to the first destination operand of the microinstruction; when the microinstruction includes an identifier indicating the execution result of a subordinate microinstruction, the control unit writes the identifier into the register alias table corresponding to the second destination operand of the microinstruction.

[0015] In one possible implementation, the apparatus further includes a reservation station and an execution module, and the method further includes: the renaming module outputting received microinstructions to the reservation station; and, for each received microinstruction, searching in a register alias table for an entry corresponding to each source operand of the microinstruction; if any entry corresponding to a source operand stores an identifier indicating the execution result of a subordinate microinstruction, the identifier is used as a parameter carried by the source operand and output to the reservation station along with the microinstruction; if any entry corresponding to a source operand does not store an identifier indicating the execution result of a subordinate microinstruction, the index of the physical register stored in the entry is used as a second parameter carried by the source operand and output along with the microinstruction. The microinstructions are stored at the reserved station; each microinstruction is stored in an entry at the reserved station; for any microinstruction stored in an entry, if any source operand included in the microinstruction carries a first parameter, the reserved station assigns the value indicated by the first parameter to the source operand; if any source operand included in the microinstruction does not carry a first parameter, the reserved station obtains the value stored in the physical register allocated to the source operand according to the second parameter carried by the source operand, and assigns the value to the source operand; after any microinstruction is output to the execution module for execution, the reserved station clears the entry storing the microinstruction in response to the completion of the microinstruction execution.

[0016] In one possible implementation, the apparatus further includes a reordering buffer, and the method further includes: the renaming module outputting received microinstructions to the reordering buffer, the reordering buffer storing the received microinstructions, wherein each microinstruction is stored in an entry in the reordering buffer; in response to the completion of execution of the microinstruction, the reordering buffer puts the microinstruction into a waiting exit state.

[0017] According to another aspect of this disclosure, a processor is provided, including the instruction processing means described above.

[0018] According to another aspect of this disclosure, an electronic device is provided, including the processor described above.

[0019] According to the instruction processing apparatus of this disclosure, a microinstruction sequence is obtained through a merging module. When the execution result of the current microinstruction is known, the current microinstruction is merged into the previous microinstruction as a subordinate microinstruction, and then the previous microinstruction is output to a renaming module. When the execution result of the current microinstruction is unknown, the previous microinstruction is directly output to the renaming module. The microinstruction output by the merging module is the microinstruction to be executed, thereby reducing the number of microinstructions to be executed. The renaming module records the execution result of the received microinstruction when there is a subordinate microinstruction and the execution result of the subordinate microinstruction is known to be constant. The identifier indicating the execution result of the subordinate microinstruction is equivalent to the execution of the subordinate microinstruction being completed in the renaming module, and the execution result of the subordinate microinstruction is reflected in the renaming module. When the source operand of the microinstruction output by the merging module is the execution result of any subordinate microinstruction and the execution result of that subordinate microinstruction is known to be a constant, the value of the source operand is determined according to the identifier recorded by the renaming module. In this way, it is ensured that even when the merging module does not output the execution result of a microinstruction as a source operand, the source operand can still be successfully prepared, thereby ensuring that each microinstruction can be executed smoothly. In summary, the instruction processing device using the embodiments of this disclosure can reduce the number of microinstructions to be executed and improve the execution efficiency of microinstructions.

[0020] Because fewer microinstructions are required to be executed, the hardware resource usage of the reordering buffer and reservation station can be reduced.

[0021] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0023] Figure 1 This illustrates an exemplary application scenario of an instruction processing apparatus according to embodiments of the present disclosure.

[0024] Figure 2 A schematic diagram showing the structure of an instruction processing apparatus according to an embodiment of the present disclosure is provided.

[0025] Figure 3 A schematic diagram illustrating the effect of merging microinstructions according to an embodiment of the present disclosure.

[0026] Figure 4 A schematic diagram of the merged microinstructions according to an embodiment of this disclosure is shown.

[0027] Figure 5 A schematic diagram showing the structure of a renaming module according to an embodiment of the present disclosure is provided.

[0028] Figure 6 A schematic diagram illustrating the flow of an instruction processing method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0029] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0030] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0031] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0032] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0033] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0034] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0035] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0036] In existing technologies, each microinstruction in a microinstruction sequence needs to be executed by the execution module, resulting in low execution efficiency. Furthermore, each microinstruction requires an entry in both the reordering buffer and the reservation station, leading to excessive hardware resource consumption in these areas when there are many microinstructions.

[0037] In view of the above, this disclosure provides an instruction processing apparatus, method, processor, and electronic device. The instruction processing apparatus using embodiments of this disclosure can reduce the number of microinstructions to be executed and improve the execution efficiency of microinstructions.

[0038] Furthermore, the reduced number of microinstructions to be executed reduces the hardware resource occupancy of the reordering buffer and the reservation station.

[0039] Figure 1 This illustrates an exemplary application scenario of an instruction processing apparatus according to embodiments of the present disclosure.

[0040] like Figure 1 As shown, the processor 10 includes a decoding module 101, an instruction processing device 102, a reservation station 103, a reordering buffer 104, an execution module 105, and a physical register file 106.

[0041] The decoding module receives instructions and decodes them to obtain a microinstruction sequence. This microinstruction sequence enters the instruction processing unit, where microinstructions are merged and allocated physical registers from the physical register file. The instruction processing unit can output microinstructions to a reservation station and a reordering buffer. After the reservation station determines that the microinstruction has completed source operand preparation, it dispatches the microinstruction to the execution module for execution. After executing the microinstruction, the execution module writes the execution result to the allocated physical register and notifies the reordering buffer and reservation station that the microinstruction has been executed. The reordering buffer then exits the queue of executed microinstructions according to their write order. The reservation station clears the queue of executed microinstructions.

[0042] It should be understood that the decoding module, the holding station, the reordering buffer, and the execution module can also be integrated into the instruction processing device. This disclosure does not limit whether the instruction processing device includes a decoding module, a holding station, a reordering buffer, and an execution module.

[0043] Figure 2 A schematic diagram showing the structure of an instruction processing apparatus according to an embodiment of the present disclosure is provided.

[0044] like Figure 2 As shown, in one possible implementation, the instruction processing device 102 includes a merging module 1021 and a renaming module 1022.

[0045] The merging module 1021 is used to obtain the microinstruction sequence. When the execution result of the current microinstruction is known, the current microinstruction is merged into the previous microinstruction as a subordinate microinstruction and then the previous microinstruction is output to the renaming module 1022. When the execution result of the current microinstruction is unknown, the previous microinstruction is directly output to the renaming module 1022.

[0046] The renaming module 1022 is used to record an identifier indicating the execution result of a subordinate microinstruction when the received microinstruction has a subordinate microinstruction and the execution result of the subordinate microinstruction is known to be a constant.

[0047] Among them, the microinstruction output by the merging module 1021 is the microinstruction to be executed. When the source operand of the microinstruction output by the merging module 1021 is the execution result of any subordinate microinstruction and the execution result of the subordinate microinstruction is known to be a constant, the value of the source operand is determined according to the identifier recorded by the renaming module 1022.

[0048] For example, a merging module can be used to obtain a microinstruction sequence. The merging module can be connected to a decoding module to obtain the microinstruction sequence decoded by the decoding module. The merging module itself can also implement decoding functionality; in this case, the merging module can receive instructions, decode the instructions, and obtain the microinstruction sequence. This disclosure does not limit the specific implementation method of the merging module obtaining the microinstruction sequence.

[0049] A microinstruction sequence consists of multiple microinstructions. An example of a microinstruction is given below.

[0050] Microinstruction 1: ADD RAX RDX;

[0051] Microinstruction 2: MUL RBX IMM;

[0052] Microinstruction 3: SUB RAX RBX;

[0053] Microinstruction 4: MOV RCX RBX;

[0054] Microinstruction 5: AND RCX RCX;

[0055] Microinstruction 1 is an addition microinstruction. RDX is the source operand of microinstruction 1, and RAX is the first destination operand of microinstruction 1. Executing microinstruction 1 adds the value of RDX to the value of RAX, and assigns the result to RAX.

[0056] Microinstruction 2 is a multiplication microinstruction. IMM is the source operand of microinstruction 2, and RBX is the first destination operand of microinstruction 2. Executing microinstruction 2 multiplies the value of IMM and the value of RBX, and assigns the result to RBX.

[0057] Microinstruction 3 is a subtraction microinstruction. RBX is the source operand of microinstruction 3, and RAX is the first destination operand of microinstruction 3. Executing microinstruction 3 subtracts the value of RAX from the value of RBX, and assigns the result to RAX.

[0058] Microinstruction 4 is a move microinstruction. RBX is the source operand of microinstruction 4, and RCX is the first destination operand of microinstruction 4. Executing microinstruction 4 assigns the value of RBX to RCX.

[0059] Microinstruction 5 is a logical AND microinstruction, with RCX serving as both the source operand and the first destination operand. Executing microinstruction 5 performs a logical AND operation between RCX and itself, assigning the result to RCX.

[0060] Some microinstructions can produce results without being dispatched to the execution module. In the example above, assuming IMM is an immediate value of 0, the execution results of microinstructions 1, 3, and 4 are unknown, while the execution results of microinstructions 2 and 5 are known. Specifically, the execution result of microinstruction 2 is the constant 0. The execution result of microinstruction 5 is equal to its source operand RCX.

[0061] The merging module analyzes the current microinstruction to determine if its execution result is known. If the result is known, the current microinstruction is merged into the previous microinstruction as a subordinate microinstruction, and then the previous microinstruction is output to the renaming module. If the result is unknown, the merging module can directly output the previous microinstruction to the renaming module.

[0062] Figure 3 A schematic diagram illustrating the effect of merging microinstructions according to an embodiment of the present disclosure.

[0063] like Figure 3 As shown, the merging module receives microinstructions 1 through 5 sequentially. It is assumed that the merging module can receive one microinstruction per cycle and issue one microinstruction per cycle.

[0064] In the first cycle, the merging module receives microinstruction 1. Microinstruction 1 is the current microinstruction. The execution result of microinstruction 1 is unknown, and there is no previous microinstruction for microinstruction 1. Therefore, microinstruction 1 is not processed.

[0065] In the second cycle, the merging module receives microinstruction 2 and uses it as the current microinstruction. The execution result of microinstruction 2 is known, and microinstruction 1 is the preceding microinstruction. Therefore, microinstruction 2 can be merged into microinstruction 1. Microinstruction 2 becomes a subordinate microinstruction of microinstruction 1. The merged microinstruction 1 can then be output to the renaming module.

[0066] In the third cycle, the merging module receives microinstruction 3 and uses it as the current microinstruction. The execution result of microinstruction 3 is unknown. Since microinstruction 2 has been merged into microinstruction 1 and microinstruction 1 has already been output, there is no preceding microinstruction for microinstruction 3, and therefore microinstruction 3 is not processed.

[0067] In the fourth cycle, the merging module receives microinstruction 4 and uses it as the current microinstruction. The execution result of microinstruction 4 is unknown. Microinstruction 3 is the preceding microinstruction of microinstruction 4, and microinstruction 3 can be output to the renaming module. Microinstruction 4 is not processed.

[0068] In the 5th cycle, the merging module receives microinstruction 5 and uses it as the current microinstruction. The execution result of microinstruction 5 is known, and microinstruction 4 is the preceding microinstruction. Therefore, microinstruction 5 can be merged into microinstruction 4. Microinstruction 5 becomes a subordinate microinstruction of microinstruction 4. The merged microinstruction 4 can then be output to the renaming module.

[0069] For microinstructions whose execution result is constant, there are no restrictions on the execution result of the preceding microinstruction when merging it into the previous microinstruction. That is, the preceding microinstruction can be an instruction whose execution result is constant, an instruction whose execution result is unknown, or an instruction whose execution result is known but not constant.

[0070] As can be seen, after processing by the merging module, the number of microinstructions is reduced from 5 to 3.

[0071] For the renaming module, when a received microinstruction has a subordinate microinstruction and the execution result of that subordinate microinstruction is known to be a constant, an identifier indicating the execution result of that subordinate microinstruction can be recorded. For example, when the renaming module receives microinstruction 1, it can record an identifier indicating the execution result (constant 0) of microinstruction 2 (a subordinate microinstruction of microinstruction 1). In this case, it is equivalent to the renaming module completing the execution of the subordinate microinstruction, and the execution result of the subordinate microinstruction is reflected in the renaming module.

[0072] In this scenario, only the microinstructions output by the merging module are the microinstructions expected to be executed by the execution module. Because the number of microinstructions output by the merging module is reduced, the number of microinstructions that need to be executed is also reduced, thus improving microinstruction execution efficiency.

[0073] When the source operand of a microinstruction output by the merging module is the execution result of any subordinate microinstruction, and the execution result of that subordinate microinstruction is known to be a constant, the value of the source operand can be determined according to the identifier recorded by the renaming module. For example, if the source operand RBX of microinstruction 3 is the execution result of microinstruction 2, and microinstruction 2 is a subordinate microinstruction, the renaming module will record an identifier indicating the execution result of microinstruction 2 (constant 0). The value 0 indicated by this identifier can be assigned to the source operand RBX of microinstruction 3. In this way, it is ensured that even if the merging module does not output the execution result of a microinstruction as a source operand, the source operand can still be successfully prepared, thus ensuring that each microinstruction can be executed smoothly.

[0074] Those skilled in the art will understand that, in practical applications, the microinstruction sequence may include more instruction types than those listed above, such as logical OR microinstructions, division microinstructions, etc. This disclosure does not limit the types of instructions that a microinstruction sequence may include.

[0075] Those skilled in the art should understand that, in practical applications, the microinstructions whose execution results are known are not limited to the examples described above. The conditions for determining whether the execution result of a microinstruction is known and whether it is a constant can be set according to the type of the microinstruction. For example, when the microinstruction is a logical AND / OR microinstruction, if the source operand and the first destination operand are the same, the execution result is known and not a constant; when the microinstruction is an addition / subtraction microinstruction and the source operand is a constant 0, the execution result is known and not a constant; when the microinstruction is a multiplication instruction and the source operand is a constant 0, the execution result is known and is a constant 0. Specific judgment conditions can be set by the operator, and this embodiment does not limit the specific setting method of the judgment conditions for whether the execution result of a microinstruction is known and whether it is a constant.

[0076] Those skilled in the art should understand that the merging module can make more detailed judgments on the execution result of the microinstruction, such as judging whether the value of the first target operand remains unchanged before and after the execution of the microinstruction. The embodiments of this disclosure do not limit the specific judgment method of the merging module on the execution result of the microinstruction.

[0077] According to the instruction processing apparatus of this disclosure, a microinstruction sequence is obtained through a merging module. When the execution result of the current microinstruction is known, the current microinstruction is merged into the previous microinstruction as a subordinate microinstruction, and then the previous microinstruction is output to a renaming module. When the execution result of the current microinstruction is unknown, the previous microinstruction is directly output to the renaming module. The microinstruction output by the merging module is the microinstruction to be executed, thereby reducing the number of microinstructions to be executed. The renaming module records the execution result of the received microinstruction when there is a subordinate microinstruction and the execution result of the subordinate microinstruction is known to be constant. The identifier indicating the execution result of the subordinate microinstruction is equivalent to the execution of the subordinate microinstruction being completed in the renaming module, and the execution result of the subordinate microinstruction is reflected in the renaming module. When the source operand of the microinstruction output by the merging module is the execution result of any subordinate microinstruction and the execution result of that subordinate microinstruction is known to be a constant, the value of the source operand is determined according to the identifier recorded by the renaming module. In this way, it is ensured that even when the merging module does not output the execution result of a microinstruction as a source operand, the source operand can still be successfully prepared, thereby ensuring that each microinstruction can be executed smoothly. In summary, the instruction processing device using the embodiments of this disclosure can reduce the number of microinstructions to be executed and improve the execution efficiency of microinstructions.

[0078] In one possible implementation, the merging module is specifically used for,

[0079] When the execution result of the current microinstruction is known, determine whether to execute the current microinstruction sequentially after the previous microinstruction has been executed;

[0080] When executing the current microinstruction sequentially after the previous microinstruction has been completed, the current microinstruction is merged into the previous microinstruction.

[0081] For example, the execution of some microinstructions may involve jumps, raising exceptions, or generating interrupts. In this case, the microinstruction following that microinstruction will not be executed sequentially.

[0082] Therefore, when the execution result of the current microinstruction is known, the merging module can further determine whether the current microinstruction should be executed sequentially after the previous microinstruction has finished. If the current microinstruction is executed sequentially after the previous microinstruction has finished, then the current microinstruction can be merged into the previous microinstruction. This method can reduce the waste of computational resources in the merging module and the waste of storage resources in the renaming module.

[0083] The following describes an exemplary implementation of the merging module for merging microinstructions.

[0084] In one possible implementation, some microinstructions in the microinstruction sequence include a first destination operand, and the merging module is specifically used for...

[0085] When the execution result of the current microinstruction is known to be a constant, after adding a second destination operand and an identifier indicating the execution result of the current microinstruction to the previous microinstruction, the previous microinstruction is output to the renaming module, and the second destination operand is equal to the first destination operand of the current microinstruction.

[0086] When the execution result of the current microinstruction is known and the value of the first destination operand remains unchanged before and after the execution of the current microinstruction, or when the current microinstruction does not include the first destination operand, the execution result of the current microinstruction is known, and the execution of the current microinstruction does not affect the data storage of the physical registers, the previous microinstruction remains unchanged before and after merging.

[0087] For example, some microinstructions in a microinstruction sequence include a first destination operand, while others do not. If both the previous and current microinstructions include a first destination operand, and the merging module determines that the execution result of the current microinstruction is known to be constant, it can add a second destination operand to the previous microinstruction. The second destination operand is equal to the first destination operand of the current microinstruction.

[0088] Since it is possible to determine whether the execution result of a microinstruction is a constant, and the value of a constant can also be determined, possible constant values ​​can be anticipated, and a corresponding flag can be set for each possible constant value. For example, assuming there are three possible constant values: constant 0, constant 1, and constant 0xF, the bit width of the flag indicating the execution result of the current microinstruction can be set to 3, with the flag corresponding to constant 0 being 100, the flag corresponding to constant 1 being 010, and the flag corresponding to constant 0xF being 001. This embodiment of the present disclosure does not limit the specific number of flags or the specific setting method of the flags. When both the previous microinstruction and the current microinstruction include a first destination operand, and it is determined that the execution result of the current microinstruction is known to be a constant, a flag indicating the execution result of the current microinstruction can be added to the previous microinstruction.

[0089] Figure 4 A schematic diagram of the merged microinstructions according to an embodiment of this disclosure is shown.

[0090] like Figure 4 As shown, both microinstruction 1 and microinstruction 2 include a first destination operand. Since the execution result of microinstruction 2 is known to be a constant 0, when merging microinstruction 2 into microinstruction 1, a second destination operand can be added to microinstruction 1. The second destination operand of microinstruction 1 is equal to the first destination operand of microinstruction 2. The flag 100 can be added to microinstruction 1.

[0091] The merging module can output the previous microinstruction to the renaming module. When the renaming module detects that a microinstruction includes a second destination operand, it can determine that the microinstruction has a dependent microinstruction, and determine that the identifier included in the microinstruction indicates the execution result of the dependent microinstruction. The renaming module can record this identifier. For example, if microinstruction 1, which includes the identifier 100, is output to the renaming module, the renaming module can record the identifier 100. An exemplary method for the renaming module to record identifiers is given later.

[0092] When the current microinstruction includes a first destination operand, if the execution result of the current microinstruction is known, and the value of the first destination operand remains unchanged before and after the execution of the current microinstruction, then the previous microinstruction remains unchanged before and after the merge. For example, if the execution result of microinstruction 5 is known and the value of the first destination operand is RCX before and after the execution of microinstruction 5, then microinstruction 5 is actually redundant. Whether or not microinstruction 5 is executed has no impact on the execution effect of the microinstruction sequence. Therefore, there is no need to change microinstruction 4, and microinstruction 4 remains unchanged before and after the merge.

[0093] If the current microinstruction does not include the first destination operand, and the merging module determines that the execution result of the current microinstruction is known, then if the execution of the current microinstruction does not affect the data storage of the physical registers, the previous microinstruction remains unchanged before and after merging.

[0094] For example, a No Operation (NOP) instruction is a microinstruction with no destination operand, no source operand, a known result, and no impact on the data storage of physical registers before or after execution. This microinstruction can be used to consume clock cycles to implement delays, as a placeholder for debugging, to fill pipelines, and to align instruction boundaries. When this microinstruction is a subordinate microinstruction to a preceding microinstruction, the preceding microinstruction remains unchanged before and after merging.

[0095] In this way, the changes to the micro-instructions output by the merging module are smaller, saving the data processing cost of the merging module.

[0096] The following describes an exemplary implementation of the storage identifier for the renaming module. Figure 5 A schematic diagram showing the structure of a renaming module according to an embodiment of the present disclosure is provided.

[0097] In one possible implementation, the renaming module includes a control unit, an allocation unit, and a Register Alias ​​Table (RAT). The RAT contains multiple entries, and the control unit is used for...

[0098] Upon receiving any microinstruction, the control allocation unit allocates a physical register for the first destination operand of that microinstruction;

[0099] Write the index of the allocated physical register into the register alias table for the entry corresponding to the first destination operand of the microinstruction;

[0100] When the microinstruction includes an identifier indicating the execution result of a subordinate microinstruction, the identifier is written into the entry in the register alias table corresponding to the second destination operand of the microinstruction.

[0101] For example, such as Figure 5 As shown, the renaming module includes a control unit, an allocation unit, and a register alias table. The register alias table contains multiple entries. Figure 5 The example shows entries 1-5 of the register alias table, each entry having multiple bit fields used to store the index of the physical register and each data bit identified. Figure 5 In the example, each entry has 4 bit fields: 1 bit field stores the index, and the other 3 bit fields store the first data bit cnst0, the second data bit cnst1, and the third data bit cnstF of the identifier, respectively.

[0102] The microinstructions output by the merging module are received by the control unit. When the control unit receives any microinstruction, it controls the allocation unit to allocate a physical register for the first destination operand (such as dst1) of that microinstruction.

[0103] The allocation unit can access the physical register file, obtain the index (e.g., preg1) of the physical register allocated for the first destination operand of the microinstruction, and output the index to the register alias table. The control unit can select a free entry (e.g., entry 2) from the register alias table as the entry corresponding to the first destination operand of the microinstruction, write the index to the selected entry, and clear the bit field of the data bits storing the identifier in the entry, that is, make cnst0, cnst1, and cnstF all 0. The control unit can determine the previous physical register allocated to the first destination operand according to the register alias table, pre-reclaim the physical register, so that the reclaimed physical register can re-participate in physical register allocation. Pre-reclaim can be implemented based on existing technology, which will not be elaborated here.

[0104] If the microinstruction includes a second destination operand (e.g., dst2), and an entry corresponding to the second destination operand exists in the register alias table (e.g., entry 5), then the identifier indicating the execution result of the subordinate microinstruction included in the microinstruction can be written into the entry in the register alias table corresponding to the second destination operand of the microinstruction. For example, when the identifier is 100, cnst0 can be updated to 1, while cnst1 and cnstF remain 0. At this time, the bit field storing the index in the entry corresponding to the second destination operand of the microinstruction is invalid; this bit field is not updated, nor is the physical register corresponding to the index stored in this bit field pre-reclaimed.

[0105] If the microinstruction includes a second destination operand, and there is no corresponding entry for the second destination operand in the register alias table, the control unit may select a free entry in the register alias table as the entry for the second destination operand corresponding to the microinstruction. The control unit may write the identifier included in the microinstruction, indicating the execution result of the subordinate microinstruction, into the entry in the register alias table corresponding to the second destination operand of the microinstruction. In this case, it is not necessary to allocate a physical register for the second destination operand, and the entry corresponding to the second destination operand of the microinstruction does not store the index of the physical register.

[0106] In this way, the storage of the second destination operand does not require a new physical register, thus saving storage resources.

[0107] In one possible implementation, the device further includes a retention station and an execution module.

[0108] The renaming module is also used to output the received microinstructions to the reservation station; and, for each received microinstruction, to look up the entry corresponding to each source operand of the microinstruction in the register alias table; when any entry corresponding to a source operand stores an identifier indicating the execution result of the subordinate microinstruction, the identifier is used as a parameter carried by the source operand and output to the reservation station along with the microinstruction; when any entry corresponding to a source operand does not store an identifier indicating the execution result of the subordinate microinstruction, the index of the physical register stored in the entry is used as a second parameter carried by the source operand and output to the reservation station along with the microinstruction;

[0109] The reservation station is used for: storing received microinstructions, wherein each microinstruction is stored in an entry in the reservation station; for any microinstruction stored in an entry, if any source operand included in the microinstruction carries a first parameter, assigning the value indicated by the first parameter to the source operand; if any source operand included in the microinstruction does not carry a first parameter, obtaining the value stored in the physical register allocated to the source operand according to the second parameter carried by the source operand, and assigning the value to the source operand; after any microinstruction is output to the execution module for execution, clearing the entry storing the microinstruction in response to the completion of the microinstruction execution.

[0110] For example, the instruction processing unit further includes a reservation station and an execution module. After the renaming module completes the allocation of physical registers and the update of the register alias table based on the received microinstructions, it can output the microinstructions to the reservation station.

[0111] For each received microinstruction, the renaming module also searches the register alias table for the entry corresponding to each source operand of that microinstruction. When an entry corresponding to any source operand stores an identifier indicating the execution result of the subordinate microinstruction, this identifier is used as the first parameter carried by that source operand and output to the reservation station along with the microinstruction.

[0112] For example, the microinstruction 1 received by the renaming module is a merged microinstruction, including a first destination operand RAX and a second destination operand RBX. Based on microinstruction 1, the renaming module can add entries corresponding to operand RAX and operand RBX to the register alias table. The entry corresponding to operand RBX stores an identifier indicating the execution result of microinstruction 2.

[0113] The renaming module receives microinstruction 3, whose source operand is RBX. The renaming module can look up the entry corresponding to operand RBX in the register alias table. Since this entry stores an identifier indicating the execution result of microinstruction 2, the renaming module can use this identifier as the first parameter carried by operand RBX and output it to the reserved station along with microinstruction 3.

[0114] If the entry corresponding to any source operand does not store an identifier indicating the execution result of the subordinate microinstruction, the index of the physical register where the entry is stored is used as the second parameter carried by the source operand and output to the reserved station along with the microinstruction.

[0115] For example, microinstruction 1 received by the renaming module includes the source operand RDX. If the entry in the register alias table corresponding to operand RDX does not store an identifier indicating a constant, the renaming module can use the index of the physical register stored in that entry as the second parameter carried by operand RDX, and output it to the reserved station along with microinstruction 1.

[0116] The retention station can store received microinstructions, with each microinstruction stored in an entry within the retention station. The microinstructions stored in the retention station are those that have not yet been issued. The retention station is responsible for determining whether the microinstruction has completed operand preparation. After confirming that the microinstruction has completed operand preparation, it can issue (output) the microinstruction to the execution module for execution. Subsequently, in response to the completion of the microinstruction execution, the entry storing the microinstruction in the retention station is cleared.

[0117] The reserved station determines whether the microinstruction has completed operand preparation as follows:

[0118] Determine whether each source operand in the microinstruction carries a first parameter or a second parameter. If any source operand in the microinstruction carries a first parameter, assign the value indicated by the first parameter to the source operand and confirm that the source operand has completed its source operand preparation.

[0119] For example, when the reservation station determines whether microinstruction 3 "SUB RAX RBX" has completed source operand preparation, since the renaming module has already used the identifier of the execution result of microinstruction 2 (e.g., 100, indicating constant 0) as the first parameter carried by operand RBX and output it to the reservation station along with microinstruction 3, the constant 0 indicated by the first parameter can be assigned to RBX. At this time, RBX is ready, and microinstruction 3 has completed source operand preparation.

[0120] When any source operand in a microinstruction carries a second parameter (i.e., the index of the physical register allocated to that source operand), the value stored in the physical register allocated to that source operand can be obtained according to the second parameter, and the obtained value can be assigned to that source operand to complete the preparation of the source operand.

[0121] For example, when the reserved station determines whether microinstruction 1 "ADD RAX RDX" has completed operand preparation, since the renaming module has already used the index preg1 of the physical register allocated to the source operand RDX as the second parameter carried by the operand RDX, it can determine that the physical register allocated to the source operand is preg1 based on preg1, obtain the value stored in the physical register preg1, and assign the obtained value to the source operand RDX, so that the source operand RDX can complete preparation, and microinstruction 1 completes the source operand preparation.

[0122] In this way, the retention station can prepare the source operands for microinstructions even when microinstructions are merged. Furthermore, subordinate microinstructions do not consume retention station resources, thus improving the retention station's resource utilization.

[0123] In one possible implementation, the apparatus further includes a reordering buffer, and the renaming module is also configured to output received microinstructions to the reordering buffer.

[0124] The reorder buffer is used for:

[0125] The received microinstructions are stored, with each microinstruction stored in an entry in the reordering buffer;

[0126] Upon completion of the microinstruction, the microinstruction enters a waiting exit state.

[0127] For example, the instruction processing unit further includes a reordering buffer. After the renaming module completes the allocation of physical registers and the update of the register alias table based on the received microinstructions, it can output the microinstructions to the reordering buffer.

[0128] The reorder buffer stores received microinstructions, with each microinstruction stored as an entry in the reorder buffer. The microinstructions stored in the reorder buffer are those that have not yet exited. The reorder buffer is responsible for putting a microinstruction into a waiting-to-exit state when it has finished executing, and clearing the entry for that microinstruction in the reorder buffer after it has exited.

[0129] If a microinstruction has a dependent microinstruction, both the microinstruction and its dependent microinstruction occupy only one entry in the reordering buffer. When the microinstruction exits, the dependent microinstruction also exits. In this case, hardware resources occupied by the reordering buffer can be saved, improving the resource utilization of the reordering buffer.

[0130] This disclosure also proposes an instruction processing method. Figure 6 A schematic diagram illustrating the flow of an instruction processing method according to an embodiment of the present disclosure is shown.

[0131] In one possible implementation, such as Figure 6 As shown, the method is applied to an instruction processing device, which includes a merging module and a renaming module. The method includes:

[0132] Step S61: The merging module obtains the microinstruction sequence;

[0133] Step S62: When the execution result of the current microinstruction is known, the merging module merges the current microinstruction as a subordinate microinstruction of the previous microinstruction into the previous microinstruction and then outputs the previous microinstruction to the renaming module; when the execution result of the current microinstruction is unknown, the previous microinstruction is directly output to the renaming module.

[0134] Step S63: When the received microinstruction has a subordinate microinstruction and the execution result of the subordinate microinstruction is known to be a constant, the renaming module records an identifier indicating the execution result of the subordinate microinstruction.

[0135] The microinstruction output by the merging module is the microinstruction to be executed. When the source operand of the microinstruction output by the merging module is the execution result of any subordinate microinstruction and the execution result of the subordinate microinstruction is known to be a constant, the value of the source operand is determined according to the identifier recorded by the renaming module.

[0136] In one possible implementation, merging the current microinstruction as a subordinate microinstruction of the previous microinstruction into the previous microinstruction includes: when the execution result of the current microinstruction is known, determining whether the current microinstruction should be executed sequentially after the previous microinstruction has been executed; and when the current microinstruction is executed sequentially after the previous microinstruction has been executed, merging the current microinstruction into the previous microinstruction.

[0137] In one possible implementation, some microinstructions in the microinstruction sequence include a first destination operand. Merging the current microinstruction as a subordinate microinstruction of the previous microinstruction into the previous microinstruction includes: when the execution result of the current microinstruction is known to be constant, adding a second destination operand and an identifier indicating the execution result of the current microinstruction to the previous microinstruction, and then outputting the previous microinstruction to the renaming module, where the second destination operand is equal to the first destination operand of the current microinstruction; when the execution result of the current microinstruction is known and the value of the first destination operand remains unchanged before and after the execution of the current microinstruction, or when the current microinstruction does not include a first destination operand, the execution result of the current microinstruction is known, and the execution of the current microinstruction does not affect the data storage of physical registers, the previous microinstruction remains unchanged before and after merging.

[0138] In one possible implementation, the renaming module includes a control unit, an allocation unit, and a register alias table. The register alias table includes multiple entries. The step of recording an identifier indicating the execution result of a subordinate microinstruction when the received microinstruction has a dependent microinstruction and the execution result of the dependent microinstruction is known to be a constant includes: when the control unit receives any microinstruction, it controls the allocation unit to allocate a physical register for the first destination operand of the microinstruction; the control unit writes the index of the allocated physical register into the register alias table corresponding to the first destination operand of the microinstruction; when the microinstruction includes an identifier indicating the execution result of a subordinate microinstruction, the control unit writes the identifier into the register alias table corresponding to the second destination operand of the microinstruction.

[0139] In one possible implementation, the apparatus further includes a reservation station and an execution module, and the method further includes: the renaming module outputting received microinstructions to the reservation station; and, for each received microinstruction, searching in a register alias table for an entry corresponding to each source operand of the microinstruction; if any entry corresponding to a source operand stores an identifier indicating the execution result of a subordinate microinstruction, the identifier is used as a parameter carried by the source operand and output to the reservation station along with the microinstruction; if any entry corresponding to a source operand does not store an identifier indicating the execution result of a subordinate microinstruction, the index of the physical register stored in the entry is used as a second parameter carried by the source operand and output along with the microinstruction. The microinstructions are stored at the reserved station; each microinstruction is stored in an entry at the reserved station; for any microinstruction stored in an entry, if any source operand included in the microinstruction carries a first parameter, the reserved station assigns the value indicated by the first parameter to the source operand; if any source operand included in the microinstruction does not carry a first parameter, the reserved station obtains the value stored in the physical register allocated to the source operand according to the second parameter carried by the source operand, and assigns the value to the source operand; after any microinstruction is output to the execution module for execution, the reserved station clears the entry storing the microinstruction in response to the completion of the microinstruction execution.

[0140] In one possible implementation, the apparatus further includes a reordering buffer, and the method further includes: the renaming module outputting received microinstructions to the reordering buffer, the reordering buffer storing the received microinstructions, wherein each microinstruction is stored in an entry in the reordering buffer; in response to the completion of execution of the microinstruction, the reordering buffer puts the microinstruction into a waiting exit state.

[0141] This disclosure also proposes a processor, including the instruction processing apparatus described above. A schematic diagram of the processor's structure can be found [link to schematic diagram]. Figure 1 The processor can be a central processing unit, a graphics processing unit, or a microcontroller, etc. The embodiments disclosed herein do not limit the specific implementation of the processor.

[0142] This disclosure also proposes an electronic device including the processor described above. The electronic device may be a terminal device or a server; this disclosure does not limit the specific type of electronic device.

[0143] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0144] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An instruction processing apparatus, characterized by, The apparatus comprises a merging module and a renaming module, The merging module is configured to acquire a microinstruction sequence, when an execution result of a current microinstruction is known, merge the current microinstruction as a dependent microinstruction of a previous microinstruction to the previous microinstruction, and output the previous microinstruction to the renaming module; when the execution result of the current microinstruction is unknown, directly output the previous microinstruction to the renaming module; The renaming module is configured to, when a dependent microinstruction exists in the received microinstruction and an execution result of the dependent microinstruction is known as a constant, record an identifier indicating the execution result of the dependent microinstruction. The microinstruction output by the merging module is an expected execution microinstruction, and when a source operand of the microinstruction output by the merging module is an execution result of any dependent microinstruction and the execution result of the dependent microinstruction is known as a constant, a value of the source operand is determined according to the identifier recorded by the renaming module.

2. The apparatus of claim 1, wherein, The merging module is specifically configured to, when the execution result of the current microinstruction is known, determine whether the current microinstruction is sequentially executed after the previous microinstruction is executed; when the current microinstruction is sequentially executed after the previous microinstruction is executed, merge the current microinstruction to the previous microinstruction.

3. The apparatus of claim 1, wherein, Part of the microinstructions in the microinstruction sequence comprises a first destination operand, and the merging module is specifically configured to, when the execution result of the current microinstruction is known as a constant, add a second destination operand and an identifier indicating the execution result of the current microinstruction to the previous microinstruction, and output the previous microinstruction to the renaming module, the second destination operand being equal to the first destination operand of the current microinstruction; when the execution result of the current microinstruction is known and a value of the first destination operand is unchanged before and after the execution of the current microinstruction, or when the current microinstruction does not comprise the first destination operand, the execution result of the current microinstruction is known, and the execution of the current microinstruction does not affect data storage of a physical register, the previous microinstruction is unchanged before and after the merging.

4. The apparatus of claim 3, wherein, The renaming module comprises a control unit, an allocation unit, and a register alias table, the register alias table comprises a plurality of entries, and the control unit is configured to, when any microinstruction is received, control the allocation unit to allocate a physical register for a first destination operand of the microinstruction; write an index of the allocated physical register into an entry corresponding to the first destination operand of the microinstruction in the register alias table; when the microinstruction comprises an identifier indicating an execution result of a dependent microinstruction, write the identifier into an entry corresponding to a second destination operand of the microinstruction in the register alias table.

5. The apparatus of claim 4, wherein, The apparatus further comprises a reservation station and an execution module, The renaming module is further configured to output the received micro-instructions to the reservation station, and for each received micro-instruction, search the register alias table for an entry corresponding to each source operand of the micro-instruction; when the entry corresponding to any source operand stores an identifier indicating an execution result of a dependent micro-instruction, output the identifier as a first parameter carried by the source operand along with the micro-instruction to the reservation station; when the entry corresponding to any source operand does not store an identifier indicating an execution result of a dependent micro-instruction, output an index of a physical register stored in the entry as a second parameter carried by the source operand along with the micro-instruction to the reservation station; The reservation station is configured to store the received micro-instructions, wherein each micro-instruction is stored in a corresponding entry; for any micro-instruction stored in any entry, when any source operand included in the micro-instruction carries a first parameter, assign a value indicated by the first parameter to the source operand; when any source operand included in the micro-instruction does not carry a first parameter, obtain a value stored in a physical register assigned to the source operand according to a second parameter carried by the source operand, and assign the value to the source operand; and in response to execution of any micro-instruction, clear the entry storing the micro-instruction.

6. The apparatus of claim 5, wherein, The apparatus further comprises a reorder buffer, and the renaming module is further configured to output the received micro-instructions to the reorder buffer, The reorder buffer is configured to: store the received micro-instructions, wherein each micro-instruction is stored in a corresponding entry; and in response to execution of the micro-instruction, make the micro-instruction enter a wait-for-exit state.

7. An instruction processing method, characterized by, The method is applied to an instruction processing apparatus comprising a merging module and a renaming module, and the method comprises: The merging module obtains a sequence of micro-instructions, and when an execution result of a current micro-instruction is known, merges the current micro-instruction as a dependent micro-instruction of a previous micro-instruction to the previous micro-instruction, and then outputs the previous micro-instruction to the renaming module; when the execution result of the current micro-instruction is unknown, directly outputs the previous micro-instruction to the renaming module; The renaming module records an identifier indicating an execution result of a dependent micro-instruction when the received micro-instruction exists and the execution result of the dependent micro-instruction is known to be a constant; The micro-instruction output by the merging module is an expected execution micro-instruction, and when a source operand of the micro-instruction output by the merging module is an execution result of any dependent micro-instruction and the execution result of the dependent micro-instruction is known to be a constant, a value of the source operand is determined according to the identifier recorded by the renaming module.

8. The method of claim 7, wherein, The apparatus further comprises a reservation station and an execution module, and the method further comprises: The renaming module outputs the received micro-instructions to the reservation station; and for each received micro-instruction, looks up an entry corresponding to each source operand of the micro-instruction in a register alias table; when the entry corresponding to any source operand stores an identifier indicating an execution result of a dependent micro-instruction, outputs the identifier as a first parameter carried by the source operand along with the micro-instruction to the reservation station; when the entry corresponding to any source operand does not store an identifier indicating an execution result of a dependent micro-instruction, outputs an index of a physical register stored in the entry as a second parameter carried by the source operand along with the micro-instruction to the reservation station; The reservation station stores the received micro-instructions, wherein each micro-instruction is stored in one entry of the reservation station; For any micro-instruction stored in an entry, when any source operand included in the micro-instruction carries a first parameter, the reservation station assigns a value indicated by the first parameter to the source operand; when any source operand included in the micro-instruction does not carry a first parameter, the reservation station acquires a value stored in a physical register assigned to the source operand according to a second parameter carried by the source operand, and assigns the value to the source operand; After any micro-instruction is output to the execution module for execution, the reservation station clears the entry storing the micro-instruction in response to completion of execution of the micro-instruction.

9. The method of claim 8, wherein, The apparatus further comprises a reorder buffer, and the method further comprises: The renaming module outputs the received micro-instructions to the reorder buffer; The reorder buffer stores the received micro-instructions, wherein each micro-instruction is stored in one entry of the reorder buffer; In response to completion of execution of the micro-instruction, the reorder buffer enters the micro-instruction into a wait-for-exit state.

10. A processor, comprising: An instruction processing apparatus according to any one of claims 1-6.

11. An electronic device, comprising: A processor according to claim 10.

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