Chip management network configuration method, chip management network system, computing device, storage medium and computer program product

Abstract

Provided in the embodiments of the present disclosure are a chip management network configuration method, a chip management network system, a computing device, a storage medium and a computer program product, which are applied to a target chip. The target chip comprises a plurality of different types of chiplets, each chiplet containing one or more modules and being configured with a management network configuration serial number, and the management network configuration serial number being configured on the basis of the type of the chiplet and its encapsulation position in the target chip. The chip management network configuration method comprises: acquiring architecture information of the target chip, at least comprising the management network configuration serial numbers configured for the chiplets; on the basis of the architecture information of the target chip, dividing a preset address space into a plurality of sub-configuration spaces; and, on the basis of the management network configuration serial numbers, allocating corresponding sub-configuration spaces among the plurality of sub-configuration spaces to the target chip and each chiplet in the target chip, wherein the sub-configuration spaces allocated to the modules contained in each chiplet are different.

Description

Chip management network configuration methods, chip management network systems, computing devices, storage media, and computer program products

[0001] This application claims priority to Chinese Patent Application No. 202411425746.7, filed on October 12, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of this disclosure relate to a chip management network configuration method, a chip management network system, a computing device, a storage medium, and a computer program product. Background Technology

[0003] A chip is a unit chip that can perform certain functions and contains interconnect interfaces. Multiple chips can be packaged into a chip group by means of 2D, 2.5D, 3D and other packaging technologies. Interconnection and communication between different chips can be achieved based on the interconnect interfaces, thereby forming a chip with the expected function, such as a SOC (System on Chip) chip.

[0004] When designing a chip, different specifications can be obtained by adjusting the number of chips in a chip group. Furthermore, in addition to determining the chip group information, a management network configuration is also required. The management network connects the modules within the chip that require address space configuration and management. The chip manages each module within the chip through the management network, and each module can also report interrupt and error information through the management network. Therefore, the chip's management network configuration is crucial for achieving network connectivity and dynamic interaction between the various chips, and for realizing the chip's intended functionality.

[0005] However, the chips configured using the chip management network configuration method have high requirements for software compatibility. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a chip management network configuration method, a chip management network system, a computing device, a storage medium, and a computer program product to reduce the requirements for software compatibility.

[0007] In a first aspect, embodiments of this disclosure provide a chip management network configuration method applied to a target chip. The target chip includes multiple dies of different types, each die containing one or more modules, and each die is configured with a management network configuration number. The management network configuration number is obtained based on the type of die and its packaging position in the target chip, and includes:

[0008] Obtain the architecture information of the target chip, wherein the architecture information includes at least the management network configuration number of the chip configuration;

[0009] Based on the architecture information of the target chip, the preset address space is divided into multiple sub-configuration spaces;

[0010] Based on the management network configuration sequence number, a corresponding sub-configuration space is allocated for the target chip and each chip in the target chip in multiple sub-configuration spaces, wherein the sub-configuration spaces allocated to the modules contained in each chip are different.

[0011] Optionally, dividing the preset address space into multiple sub-configuration spaces according to the architecture information of the target chip specifically involves dividing the preset address space into multiple sub-configuration spaces that satisfy predetermined rules according to the architecture information of the target chip; wherein the predetermined rules are associated with the address space of each chip in the target chip.

[0012] Optionally, the predetermined rules include:

[0013] Different types of chips correspond to different address spaces, and the modules contained in a chip also correspond to different address spaces.

[0014] Optionally, the architecture information of the target chip may also include the type of the target chip;

[0015] The step of dividing the preset address space into multiple sub-configuration spaces that satisfy predetermined rules based on the architecture information of the target chip includes:

[0016] Based on the type of the target chip, the preset address space is divided into multiple configuration spaces, and different configuration spaces correspond to different functional implementations of the target chip;

[0017] Based on the number of cores in the target chip, the types and number of chips that make up the target chip, and the number and functions of modules contained in each chip in the target chip, the corresponding configuration space is divided into multiple sub-configuration spaces.

[0018] Optionally, the plurality of configuration spaces include at least a core configuration space, a system management configuration space, and an I / O management configuration space;

[0019] The core configuration space corresponds to the core task execution of the target chip; the system management configuration space corresponds to the state control of the target chip; and the I / O management configuration space corresponds to the information interaction of the target chip.

[0020] Optionally, the sub-configuration space includes: sub-core configuration space, sub-system configuration space, and sub-IO configuration space;

[0021] The configuration space is divided into multiple sub-configuration spaces based on the number of cores in the target chip, the types and numbers of chips that make up the target chip, and the types and numbers of modules contained in each chip, including:

[0022] Based on the number of cores in the target chip, the core configuration space is divided into multiple corresponding sub-core configuration spaces, wherein the number of the sub-core configuration spaces is greater than or equal to the number of cores in the target chip.

[0023] Based on the type and number of chips that make up the target chip, the system management configuration space is divided into multiple corresponding subsystem configuration spaces, wherein the number of the divided subsystem configuration spaces is greater than or equal to the number of chips contained in the target chip.

[0024] Based on the number and function of modules contained in each chip in the target chip, the IO management configuration space is divided into multiple corresponding sub-IO configuration spaces, wherein the number of the sub-IO configuration spaces is greater than or equal to the sum of the number of modules contained in each chip in the target chip.

[0025] Optionally, the step of allocating corresponding sub-configuration spaces for the target chip and each chip within the target chip in multiple sub-configuration spaces according to the management network configuration sequence number includes:

[0026] Based on the management network configuration number, a sub-core configuration space is allocated to the target chip in multiple sub-core configuration spaces according to the number of cores of the target chip;

[0027] In the multiple subsystem configuration spaces, a subsystem management configuration space is allocated to the target chip chips based on the type and quantity of the target chip chips;

[0028] In the plurality of sub-IO configuration spaces, a sub-IO configuration space is allocated to the modules contained in each chip in the target chip based on the number of modules and the module functions.

[0029] Optionally, the configuration space also includes a reserved address space, which is used to adapt to the address expansion requirements of target chips of different specifications, or to meet the different address expansion requirements of target chips.

[0030] Optionally, the architecture information of the target chip may also include a routing table corresponding to the target chip. The routing table is used to indicate the routing information of the routing unit in the target chip, and the routing information is used to determine the data transmission path corresponding to the module contained in the chip in the target chip.

[0031] The step of allocating corresponding sub-configuration spaces for each chip in the target chip within multiple sub-configuration spaces according to the management network configuration sequence number also includes:

[0032] Based on the management network configuration number, corresponding routing units are assigned to the modules contained in each chip in the target chip in the routing table.

[0033] Optionally, the target chip further includes an interface unit corresponding to the module contained in each chip, the interface unit being used for communication maintenance of the corresponding module;

[0034] The step of allocating corresponding routing units to the modules contained in each chip of the target chip in the routing table according to the management network configuration sequence number also includes: allocating corresponding interface units to the modules contained in each chip of the target chip.

[0035] Optionally, the target chip further includes a relay unit disposed in each chip in the target chip, the relay unit being used for signal transmission between the chip and the peer chip;

[0036] The step of allocating corresponding routing units to the modules contained in each chip of the target chip in the routing table according to the management network configuration sequence number also includes: allocating corresponding relay units to the modules contained in each chip of the target chip.

[0037] Secondly, embodiments of this disclosure provide a chip management network system applied to a target chip, the target chip comprising multiple dies of different types, each die containing one or more modules, and each die configured with a management network configuration number, the management network configuration number being configured based on the type of die and its packaging position in the target chip; the chip management network system includes:

[0038] An acquisition module is used to acquire the architecture information of the target chip, wherein the architecture information includes at least the management network configuration number of the chip configuration;

[0039] The configuration module is used to divide a preset address space into multiple sub-configuration spaces according to the architecture information of the target chip; and to allocate corresponding sub-configuration spaces for the target chip and each chip in the target chip in the multiple sub-configuration spaces according to the management network configuration sequence number, wherein the sub-configuration spaces allocated to the modules contained in each chip are different.

[0040] Thirdly, embodiments of this disclosure provide a computing device including the chip management network system as described in the third aspect above.

[0041] Fourthly, embodiments of this disclosure provide a storage medium that stores one or more computer-executable instructions, which, when executed, implement the chip management network configuration method as described in the first aspect above.

[0042] Fifthly, embodiments of this disclosure provide a computer program product, characterized in that it includes one or more computer-executable instructions, which, when executed, implement the chip management network configuration method described in the first aspect.

[0043] In the chip management network configuration method, chip management network system, and related devices provided in this disclosure, the chip management network configuration method obtains the architecture information of a target chip, the architecture information of the target chip including at least the management network configuration sequence number of the chip configuration; then, based on the architecture information of the target chip, a preset address space is divided into multiple sub-configuration spaces, and based on the management network configuration sequence number, a corresponding sub-configuration space is allocated to the target chip and each chip in the target chip in the multiple sub-configuration spaces, wherein the sub-configuration spaces allocated to the modules contained in each chip are different.

[0044] As can be seen, the embodiments of this disclosure allocate corresponding sub-configuration spaces to the chips within a preset address space divided into multiple sub-configuration spaces. This allows multiple chips in the target chip to share the preset address space, making it applicable to chip groups with different types of chips. Furthermore, because the sub-configuration spaces allocated to the modules contained in each chip are different, the preset address space of this disclosure is also applicable to chip groups with different specifications, such as a chip group constituting a 32-core CPU or a chip group constituting a 64-core CPU. Therefore, the preset address space of the embodiments of this disclosure can be understood as a shared address space with uniform configuration provided by the software system for each chip in the chip group. This eliminates the need for specific software-matched address spaces for each chip in the chip group, improving the applicability of this disclosure and reducing the software compatibility requirements of the target chip. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0046] Figure 1 is a schematic diagram of an optional structure of a chip;

[0047] Figures 2 and 3 are schematic diagrams of optional architectures for a CPU chip composed of multiple chips;

[0048] Figure 4 is a schematic diagram of the module address space configuration of a core containing 16 modules;

[0049] Figure 5 is a schematic diagram of module routing configuration for a core containing 16 modules;

[0050] Figure 6 is a schematic diagram of the internal structure of CPU chip 1;

[0051] Figure 7 is a schematic diagram of the internal structure of CPU chip 2;

[0052] Figure 8 is a schematic diagram of an optional process of the chip management network configuration method provided in an embodiment of this disclosure;

[0053] Figure 9 is a schematic diagram of another optional process of the chip management network configuration method provided in an embodiment of this disclosure;

[0054] Figure 10 is a schematic diagram of the internal structure of a core provided in an embodiment of this disclosure;

[0055] Figure 11 is a schematic diagram of the interconnection structure of different cores provided in the embodiments of this disclosure;

[0056] Figure 12 is a schematic diagram of the optional internal structure of a 32-core CPU chip provided in an embodiment of this disclosure;

[0057] Figure 13 is a schematic diagram of the optional internal structure of a 64-core CPU chip provided in an embodiment of this disclosure;

[0058] Figure 14 is a schematic diagram of the partitioning of a 64MB preset address space provided in an embodiment of this disclosure; and

[0059] Figure 15 is a schematic diagram of an optional structure of the chip management network system provided in an embodiment of this disclosure. Detailed Implementation

[0060] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0061] To facilitate understanding of the chip's structure, Figure 1 illustrates an exemplary schematic diagram of an optional chip structure. As shown in Figure 1, the chip may include multiple chips (chip 1, chip 2, chip 3, and chip 4 are shown as examples in the figure). Chips 1, 2, 3, and 4 can be the same type of chip with the same function, or they can be different types of chips with different functions. Chips 1, 2, 3, and 4 are packaged and integrated using a substrate to obtain the chip shown in Figure 1.

[0062] It's important to note that during the chip design phase, the overall chip architecture can be decomposed according to the different computing units or functional units required to achieve the chip's intended function. One or more chips corresponding to different computing units or functional units are then designed according to this architecture decomposition scheme. These chips are interconnected and packaged together to achieve the chip's intended function as a whole. Since a chip is a unit chip capable of performing a specific function and containing interconnect interfaces, multiple chips constituting the same computing unit or functional unit can be called a chiplet. The chips in a chiplet group can be identical or different. Furthermore, based on the interconnect communication between different modules, chips in the same chiplet group can also be used to form different chiplet groups. Moreover, with the continuous development of semiconductor technology, a single chiplet can contain various functional blocks to achieve effects such as computation. Therefore, in certain specific scenarios, this single chiplet can be regarded as a special chiplet group.

[0063] In an alternative example, taking a CPU chip as an example, Figures 2 and 3 show schematic diagrams of alternative architectures of different CPU chips consisting of multiple cores. Figure 2 shows a CPU chip 1 with 32 cores, and Figure 3 shows a CPU chip 2 with 64 cores.

[0064] As shown in Figure 2, the 32-core CPU chip 1 may include two I / O chips (IO chip m1 and IO chip m2, respectively) and two CPU chips (CPU chip n1 and CPU chip n2, respectively). The two I / O chips and the two CPU chips can be considered as a single chipset, such as chipset A. The two I / O chips are used to handle input / output (I / O) tasks; the two CPU chips are used to implement the 32-core CPU.

[0065] As shown in Figure 3, the 64-core CPU chip 2 may include two I / O chips (IO chip M1 and IO chip M2) and four CPU chips (CPU chip N1, CPU chip N2, CPU chip N3, and CPU chip N4). The two I / O chips and four CPU chips can be considered as a chipset, such as chipset B. The two I / O chips are used for input / output (I / O) tasks; the four CPU chips are used to implement the 64-core CPU.

[0066] Once the chip's component information is determined (as shown in Figure 2 or Figure 3, the types of chips included in the CPU chip and the quantity of each type of chip), management network configuration is required. The management network connects the modules within the chips that require address space configuration and management. The chip manages each module within the chip through the management network, and each module can also report interrupt and error information to the CPU through the management network. This enables network connectivity and dynamic interaction between the chips, thereby achieving the chip's intended functionality.

[0067] It should be further explained that, since each chip in the chip group can function as a unit chip, the configuration space of each chip can be designed independently. Therefore, to achieve the complete chip functionality of the chip group, the management networks (i.e., control buses) of the individual chips in the chip group can be interconnected through inter-chip interconnection technology. The interconnected management networks within the chip group can be considered as a complete chip management network. The chip management network configuration includes management address space configuration, data routing configuration, and permission and priority configuration, etc.

[0068] As an optional implementation, when configuring the management network, based on the independent design of the configuration space of each core, a fixed address space allocation and fixed routing can be used for each core. That is, the address space allocation and routing in each core are pre-designed by the manufacturer based on the hardware specifications and are fixed. Taking a core containing 16 modules as an example, the management network configuration is illustrated in Figures 4 and 5. Figure 4 shows the module address space configuration of this core, and Figure 5 shows the module routing configuration. The management network configuration space corresponding to this core containing 16 modules is a 16-bit address space. Modules 1 to 16 are configured to each occupy 4KB of address space, and the address spaces of each module do not overlap. Furthermore, while configuring the address spaces of the 16 modules of this core, the corresponding routes in the management network must also be configured. Each module is configured with a corresponding route to determine the information transmission path of that module. The configured routes constitute a routing table. The configured routes can be static or dynamic routes according to design requirements, and the routing methods can include, for example, source routing and distributed routing.

[0069] Therefore, when configuring chip management networks on a per-chip basis, chips of different specifications packaged from chip groups with varying numbers of chips, even if their internal configurations (e.g., controllers) are identical, will be designed with different configuration spaces. This reduces the flexibility of later chip development and usage. In other words, different chips have configuration spaces unique to that chip type and specification. This means that chips built in this way require software adapted to their internal chip configuration spaces; different specifications of chips require different software systems, placing high demands on software adaptability.

[0070] The following explanation uses CPU chip 1 and CPU chip 2 shown in Figures 2 and 3 as examples. Figures 6 and 7, corresponding to Figures 2 and 3, respectively, show schematic diagrams of the internal structures of CPU chip 1 and CPU chip 2. As shown in Figure 6, in CPU chip 1 with 32 cores, both CPU cores n1 and n2 are equipped with two sets of DDR (Double Data Rate) controllers, meaning CPU chip 1 has a total of four DDR controllers. As shown in Figure 7, in CPU chip 2 with 64 cores, CPU cores N1, N2, N3, and N4 are each equipped with one set of DDR controllers, meaning CPU chip 2 also has a total of four DDR controllers.

[0071] As can be seen, both CPU chip 1 and CPU chip 2, which have different product specifications, are equipped with 4 sets of DDR controllers. However, since the number of CPU chips packaged in CPU chip 1 and CPU chip 2 is different, and the DDR controllers configured in the packaged CPU chips are also different, the address spaces configured in the 4 sets of DDR controllers in CPU chip 1 and CPU chip 2 are different when the manufacturer pre-designs the address space allocation and routing in the chips based on the hardware specifications. Therefore, different software systems are required to match CPU chip 1 and CPU chip 2 when they are used and developed in the later stage, which increases the requirements for software adaptability.

[0072] In view of this, the present disclosure proposes an improved solution, which allocates a sub-configuration space to the chip and each chip in the chip based on a preset address space, so that multiple chips in the chip can share the preset address space. In this way, the preset address space can be applied to chip groups with different types of chips, and also to chip groups with different specifications. Thus, it is not necessary to match the address space of the chips in the chip group with specific software, which effectively improves the applicability of the solution and reduces the software compatibility requirements of the target chip.

[0073] Based on the above ideas, as an optional implementation, this disclosure provides a chip management network configuration method. By allocating corresponding sub-configuration spaces to chips within a preset address space divided into multiple sub-configuration spaces, multiple chips in the target chip can share the preset address space. This allows the preset address space to be applicable to chip groups with different types of chips. Furthermore, because the sub-configuration spaces allocated to the modules contained in each chip are different, the preset address space of this disclosure is also applicable to chip groups with different specifications, such as a chip group constituting a 32-core CPU or a chip group constituting a 64-core CPU. Therefore, the preset address space of this disclosure can be understood as a shared address space with uniform configuration provided by the software system for each chip in the chip group. This eliminates the need for specific software-matched address spaces for each chip in the chip group, improving the applicability of this disclosure and reducing the software compatibility requirements of the target chip.

[0074] Figure 8 illustrates an optional flowchart of a chip management network configuration method according to an embodiment of this disclosure. As shown in Figure 8, the method may include the following steps:

[0075] Step S100: Obtain the architecture information of the target chip.

[0076] The target chip refers to any pre-designed chip for implementing the expected function. The target chip includes multiple chips of different types, each chip contains one or more modules, and each chip is configured with a management network configuration number, which is obtained based on the type of chip and its packaging position in the target chip.

[0077] The architecture information of the target chip includes at least the management network configuration number of the chip configuration. This management network configuration number can be configured based on the type of chip and its packaging location within the target chip, and is used to coordinate and identify routing rules and interconnection relationships during data packet or connection processes between different chips.

[0078] Step S200: Based on the architecture information of the target chip, the preset address space is divided into multiple sub-configuration spaces.

[0079] The preset address space can be understood as a pre-defined address range that can meet the address space configuration requirements of target chips of different specifications. By obtaining the architecture information of the target chip, the preset address space can be divided into multiple sub-configuration spaces according to the architecture information of the target chip, so as to allocate corresponding addresses to the target chip and each chip in the target chip.

[0080] Step S300: Based on the management network configuration sequence number, allocate corresponding sub-configuration spaces for the target chip and each chip in the target chip in multiple sub-configuration spaces.

[0081] The sub-configuration spaces allocated to the modules contained in each core are different.

[0082] It is understood that the management network configuration number in this embodiment is configured based on the type of chip and its packaging position in the target chip. Therefore, for different chips with different packaging positions in the target chip, the management configuration network number is different. Furthermore, when allocating corresponding sub-configuration spaces for the target chip and each chip within the target chip in the plurality of sub-configuration spaces according to the management network configuration number, multiple chips in the target chip can share the preset address space, making the preset address space applicable to chip groups with different types of chips. Simultaneously, the different sub-configuration spaces allocated to the modules contained in each chip also allow the sub-configuration space obtained by this disclosure based on the preset address space to be simultaneously applicable to chip groups with different specifications, such as a chip group constituting a 32-core CPU, or a chip group constituting a 64-core CPU. Therefore, the preset address space in this embodiment can be understood as a shared address space with a unified configuration provided by the software system for each chip in the chip group. This eliminates the need for the chip in the chip group to match the address space with specific software, thereby improving the applicability of the chip management network configuration and reducing the software compatibility requirements of the target chip.

[0083] In some embodiments, to organize and manage the efficient use of memory and I / O resources, the allocation of the configuration space of the target chip can meet certain rule requirements. Thus, given that different target chips have corresponding architecture information, predetermined rules can be set based on the architecture information to associate the address spaces of each chip within the target chip. As an optional implementation, when dividing the preset address space into multiple sub-configuration spaces according to the target chip's architecture information, specifically, the preset address space can be divided into multiple sub-configuration spaces that satisfy predetermined rules based on the target chip's architecture information.

[0084] Regarding the architecture information of the target chip, in one optional example, the predetermined rules for associating the address spaces of each chip within the target chip with the target chip's architecture information may include different types of chips corresponding to different address spaces, and different address spaces for the modules contained within a chip. In other words, when configuring the network for managing the target chip, it is necessary to ensure that the address spaces of any module configuration within any chip do not overlap.

[0085] In some embodiments, to ensure that the designed system makes full use of resources while meeting functional requirements and expected performance, the architecture information of the target chip may also include the type of the target chip, such as a 32-core CPU chip or a 64-core CPU chip.

[0086] Therefore, based on the architecture information of the target chip, when dividing the preset address space into multiple sub-configuration spaces that satisfy predetermined rules according to the architecture information of the target chip, the preset address space can first be divided into multiple configuration spaces according to the type of the target chip, with different configuration spaces corresponding to different functional implementations of the target chip. Furthermore, based on the number of cores in the target chip, the types and number of chips that make up the target chip, and the number and functions of modules contained in each chip of the target chip, the corresponding configuration space can be divided into multiple sub-configuration spaces.

[0087] It should be noted that the target chip contains multiple functional units. To enable the software system to customize hardware behavior according to the target chip's environment, and to ensure that the preset address space meets the configuration requirements of different types of target chips, providing higher performance and adaptability, the preset address space can be divided into multiple configuration spaces based on the target chip type. This achieves the purpose of managing and optimizing the target chip. Furthermore, each chip in the target chip can be configured with corresponding modules, thereby dynamically determining the enabled parts of the chip and enabling the collaborative work of different modules and chips. Therefore, to prevent mutual interference between the functional units of the target chip, meet the configuration requirements of target chips of different specifications, improve the chip's resource management efficiency, and ensure the flexibility and reliability of the chip management network configuration, the configuration space corresponding to the functional implementation of the target chip can be further divided into multiple sub-configuration spaces.

[0088] In one optional example, for different functional implementations of the target chip, the multiple configuration spaces of the preset address space can include at least the core configuration space, the system management configuration space, and the IO management configuration space.

[0089] The core configuration space corresponds to the core task execution of the target chip. The system management configuration space corresponds to the state control of the target chip. The I / O management configuration space corresponds to the information interaction of the target chip.

[0090] In another optional example, in addition to the core configuration space, system management configuration space and IO management configuration space of the preset address space, the multiple configuration spaces of the preset address space can also reserve address space. The reserved address space is used to adapt to the address expansion requirements of target chips of different specifications, or to meet the different address expansion requirements of target chips.

[0091] It should be noted that the preset address space disclosed herein can meet the address space configuration requirements of chips of different specifications. Therefore, the address range of the preset address space is larger than the address range requirement of the target chip. Thus, when the preset address space is divided into multiple configuration spaces, a corresponding reserved address space can be allocated to adapt to the address expansion requirements of target chips of different specifications.

[0092] In some embodiments, based on the type of configuration space partitioning, sub-configuration spaces may include sub-core configuration spaces, sub-system configuration spaces, and sub-IO configuration spaces.

[0093] Therefore, when dividing the corresponding configuration space into multiple sub-configuration spaces based on the number of cores in the target chip, the types and number of chips that make up the target chip, and the types and number of modules contained in each chip, specifically, the core configuration space can be divided into multiple corresponding sub-core configuration spaces based on the number of cores in the target chip, wherein the number of the divided sub-core configuration spaces can be greater than or equal to the number of cores in the target chip; the system management configuration space can be divided into multiple corresponding subsystem configuration spaces based on the types and number of chips that make up the target chip, wherein the number of the divided subsystem configuration spaces can be greater than or equal to the number of chips contained in the target chip; and the I / O management configuration space can be divided into multiple corresponding sub-IO configuration spaces based on the number and function of modules contained in each chip in the target chip, wherein the number of the divided sub-IO configuration spaces can be greater than or equal to the sum of the number of modules contained in each chip in the target chip.

[0094] It should be noted that the preset address space disclosed herein can meet the address space configuration requirements of chips of different specifications. Therefore, when dividing the corresponding configuration space into multiple sub-configuration spaces, the number of configuration spaces and the number of sub-configuration spaces obtained can be greater than or equal to the number of corresponding partitioning conditions to meet the different address expansion requirements of the target chip. Furthermore, after allocating the sub-configuration spaces to the core of the corresponding target chip, the chips contained in the target chip, and the modules contained in each chip in the target chip based on the corresponding conditions, the remaining sub-configuration spaces can be used as reserved address spaces.

[0095] In some embodiments, when allocating corresponding sub-configuration spaces for the target chip and each chip in the target chip in multiple sub-configuration spaces based on the classification of sub-configuration spaces and according to the management network configuration sequence number, specifically, based on the management network configuration sequence number, sub-core configuration spaces are allocated to the target chip in multiple sub-core configuration spaces according to the number of cores of the target chip; sub-system management configuration spaces are allocated to the chips of the target chip in multiple sub-system configuration spaces according to the type and number of chips of the target chip; and sub-IO configuration spaces are allocated to the modules contained in each chip in multiple sub-IO configuration spaces according to the number and function of modules contained in each chip in the target chip.

[0096] In some embodiments, in order to perform data transmission in the target chip and realize the expected function of the target chip, the architecture information of the target chip may also include a routing table. The routing table contains routing information for indicating routing units in the target chip, and the routing information is used to determine the data transmission path corresponding to the modules contained in the chip in the target chip.

[0097] Therefore, when configuring the management network for the target chip, corresponding routing configuration also needs to be performed. Referring to Figure 9, which shows another optional flowchart of the chip management network configuration method of this embodiment, while performing step S300, step S400 can also be performed to allocate corresponding routing units to the modules contained in each chip in the target chip in the routing table according to the management network configuration sequence number.

[0098] It should be noted that the routing unit can be a static route (i.e., when a data packet is sent, the routing unit will forward it directly according to the preset path) or a dynamic route (i.e., the route is dynamically calculated according to changes in network status). The routing table can be source routing, distributed routing, etc., and this disclosure does not limit this.

[0099] In some embodiments, based on the communication and cooperation between modules contained in each chip within the target chip, the target chip may further include interface units corresponding to the modules contained in each chip. These interface units are used for communication maintenance of the corresponding modules. For example, Figure 10 shows a schematic diagram of the internal structure of a chip containing eight modules, from module 01 to module 08. Each module has a corresponding interface unit, namely interface unit 01, interface unit 02, interface unit 03, and so on up to interface unit 08. Furthermore, based on the function of the interface units, each module's interface unit can connect to its corresponding routing unit, transmitting corresponding communication information through the information transmission path defined by the routing unit. The communication information can be the address space information configured for that module.

[0100] Accordingly, while allocating corresponding routing units to the modules contained in each chip of the target chip in the routing table according to the management network configuration sequence number, corresponding interface units can also be allocated to the modules contained in each chip of the target chip at the same time.

[0101] In some embodiments, based on communication and cooperation between different chips in the target chip, the target chip may further include relay units set in each chip of the target chip. These relay units are used for signal transmission between the chip and the peer chip. In the schematic diagram of the interconnection structure of different chips shown in Figure 11, both chip A and chip B are equipped with relay units (relay unit Aa and relay unit Bb, respectively). Chip A establishes transmission and communicates with chip B through its relay unit Aa. Taking chip A as an example, relay unit Aa can connect to the routing unit of chip A, and then connect to the interface unit to send the corresponding communication information transmitted by chip B to the corresponding module of chip A. The communication information includes, for example, data signals transmitted between chip A and chip B.

[0102] Accordingly, while allocating corresponding routing units to the modules contained in each chip of the target chip in the routing table according to the management network configuration sequence number, corresponding relay units can also be allocated to the modules contained in each chip of the target chip at the same time.

[0103] It should be noted that the interface units and relay units in the target chip can be set according to actual design requirements. When the communication protocol of the module is relatively simple, each module may not need to set an interface unit. When the data transmission between chips is relatively simple, each chip may not need to set a relay unit. This disclosure does not impose any restrictions on this.

[0104] To facilitate understanding of the chip management network configuration method of this disclosure, a 32-core CPU chip and a 64-core CPU chip are used as target chips for explanation and description of the chip management network configuration method of this disclosure. The CPU chip's preset address space can be pre-set to 64MB to allocate corresponding address space for the 32-core and 64-core CPU chips.

[0105] Figure 12 illustrates an exemplary internal optional structure diagram of a 32-core CPU chip. As shown in Figure 12, the 32-core CPU chip includes IO chip 1, IO chip 2, CPU chip 1, and CPU chip 2. Furthermore, both IO chip 1 and IO chip 2 contain two PCIe modules (shown as PCIe11, PCIe12, PCIe13, and PCIe14 in Figure 12), and both CPU chip 1 and CPU chip 2 contain two DDR modules (shown as DDR21, DDR22, DDR23, and DDR24 in Figure 12).

[0106] Figure 13 illustrates an exemplary internal optional structure diagram of a 64-core CPU chip. As shown in Figure 13, the 64-core CPU chip includes IO core 1', IO core 2', CPU core 1', CPU core 2', CPU core 3', and CPU core 4'. Furthermore, IO core 1' and IO core 2' each contain two PCIe modules (shown as PCIe11', PCIe12', PCIe13', and PCIe14' in Figure 13), and CPU cores 1 through 4 each contain one DDR module (shown as DDR21', DDR22', DDR23', and DDR24' in Figure 13).

[0107] Figure 14 illustrates an exemplary diagram of the partitioning of a 64MB preset address space.

[0108] If the target chip is a 64-core CPU chip as shown in Figure 13, based on the type of 64-core CPU chip, the 64MB preset address space can be first divided into 16MB CPU core configuration space, 16MB IO management configuration space, and 16MB system management configuration space. Among them, 16MB of address space remains unallocated and can be reserved as a reserve address space for use when needed.

[0109] Secondly, based on the fact that the 64-core CPU chip has 64 cores, the 16MB CPU core configuration space can be divided into 64 sub-core configuration spaces of 256KB each (shown in Figure 14 as 256KB CPU1 configuration space, 256KB CPU2 configuration space, ..., 256KB CPU64 configuration space).

[0110] Based on the types and number of chips that make up this 64-core CPU chip, the 16MB system management configuration space can be divided into four CPU chip system management configuration spaces (shown in Figure 14 as 2MB CPU chip 1 system management configuration space to 2MB CPU chip 4 system management configuration space) and two I / O chip system management configuration spaces (shown in Figure 14 as 2MB I / O chip 1 system management configuration space and 2MB I / O chip 2 system management configuration space). Of these, 4MB of address space remains unallocated within the 16MB system management configuration space, which can be reserved as address space for use when needed.

[0111] Based on this 64-core CPU chip, each CPU core contains one DDR module, and each I / O core contains two PCIe modules. The 16MB I / O management configuration space can be divided into a 4MB DDR configuration space and a 4MB PCIe configuration space. Specifically, the 4MB DDR configuration space can be defined as 4 IMB of DDR configuration space (shown in Figure 14 as 1MB DDR1 to 1MB DDR4 configuration space), and the 4MB PCIe configuration space can be defined as 4 IMB of PCIe configuration space (shown in Figure 14 as 1MB PCIe1 to 1MB PCIe4 configuration space).

[0112] It should be noted that since CPU chips inevitably need to use low-speed I / O, in order to enable the 64-core CPU chip to use low-speed I / O, when allocating the 16MB I / O management configuration space, a low-speed I / O configuration space needs to be allocated. The capacity of this low-speed I / O configuration space can be 4MB.

[0113] Of the 16MB IO management configuration space, 4MB of address space remains unallocated and can be reserved for use when needed.

[0114] Similarly, if the target chip is a 32-core CPU chip as shown in Figure 12, the 64MB preset address space can be divided as shown in Figure 14. Since the 32-core CPU chip has 32 cores, the 16MB CPU core configuration space can be divided into 32 sub-core configuration spaces of 256KB each (i.e., 256KB CPU1 configuration space to 256KB CPU32 configuration space). At this point, 8MB of address space remains unallocated within the 16MB preset address space. This 8MB can be reserved as address space for use when needed, such as when allocating CPU core configuration space for a 64-core CPU.

[0115] Based on the partitioning diagram shown in Figure 14, when allocating corresponding sub-configuration spaces for the target chip and each chip in the target chip according to the management network configuration sequence number, if the target chip is a 64-core CPU chip as shown in Figure 13, in this 64-core CPU, the management network configuration sequence number of CPU chip 1' is set to 1 through the substrate connection. Among them, the number of cores provided by CPU chip 1 is 16. Then, the core configuration space configured for CPU chip 1' is 256KB CPU1 configuration space to 256KB CPU16 configuration space, and the system management configuration space is 2MB CPU chip 1 system management configuration space. Correspondingly, CPU chip 1' contains a DDR21' module, and the IO management configuration space configured for the DDR21' module in CPU chip 1' is 1MB DDR1 configuration space.

[0116] In this 64-core CPU, the management network configuration number of CPU core 2' is set to 2 via the substrate connection. The core configuration space configured for CPU core 2' is 256KB CPU17 configuration space to 256KB CPU32 configuration space, and the system management configuration space is 2MB CPU core 2 system management configuration space. Correspondingly, CPU core 2' contains a DDR21' module, and the IO management configuration space configured for the DDR22' module in CPU core 2' is 1MB DDR2 configuration space.

[0117] In this 64-core CPU, the management network configuration number of CPU core 3' is set to 3 via the substrate connection. The core configuration space configured for CPU core 3' is 256KB CPU33 configuration space to 256KB CPU48 configuration space, and the system management configuration space is 2MB CPU core 3 system management configuration space. Correspondingly, CPU core 3' contains a DDR23' module, and the IO management configuration space configured for the DDR23' module in CPU core 3' is 1MB DDR3 configuration space.

[0118] In this 64-core CPU, the management network configuration number of CPU core 4' is set to 4 via the substrate connection. The core configuration space configured for CPU core 4' is 256KB CPU49 configuration space to 256KB CPU64 configuration space, and the system management configuration space is 2MB CPU core 4 system management configuration space. The CPU core 4' contains a DDR24' module, and the IO management configuration space configured for the DDR24' module in CPU core 4' is 1MB DDR4 configuration space.

[0119] It should be noted that since 64-core CPU chips require the use of low-speed I / O, in order to enable the use of low-speed I / O by 64-core CPU chips, when configuring the I / O management configuration space for CPU chips, the 4MB low-speed I / O configuration space can be allocated to any CPU chip in the 64-core CPU chip, such as CPU chip 1'.

[0120] Similarly, if the target chip is the 32-core CPU chip shown in Figure 12, in this 32-core CPU, the management network configuration number of CPU chip 1 is set to 11 through the substrate connection. Here, the number of cores provided by CPU chip 1 is 16. Then, the core configuration space configured for CPU chip 1 is 256KB CPU1 configuration space to 256KB CPU16 configuration space, and the system management configuration space is 2MB CPU chip 1 system management configuration space. Correspondingly, CPU chip 1 contains DDR21 module and DDR22 module. The IO management configuration space configured for DDR21 module and DDR22 module in CPU chip 1 is 1MB DDR1 configuration space and 1MB DDR2 configuration space, respectively.

[0121] In this 32-core CPU, the management network configuration number of CPU core 2 is set to 22 via the substrate connection. The core configuration space configured for CPU core 2 is 256KB, CPU17 configuration space to 256KB, and CPU32 configuration space is 2MB. The system management configuration space is 2MB. The CPU core 2 contains DDR23 and DDR24 modules. The IO management configuration space configured for the DDR23 and DDR24 modules in the CPU core 2 is 1MB for DDR3 and 1MB for DDR4, respectively.

[0122] It should be noted that since 32-core CPU chips require the use of low-speed I / O, in order to enable the use of low-speed I / O by 32-core CPU chips, when configuring the I / O management configuration space for CPU chips, the 4MB low-speed I / O configuration space can be allocated to any CPU chip in the 32-core CPU chip, such as CPU chip 1.

[0123] Furthermore, when performing management network configuration on the CPU chip based on the management network configuration sequence number, each interface module contained in each chip of the CPU chip can obtain the management network configuration sequence number accordingly, so that the interface module can select the configuration space and routing table of the route according to the management network configuration sequence number. The routing method can be source routing or distributed routing.

[0124] As can be seen, the chip management network configuration method of this disclosure allocates corresponding sub-configuration spaces to chips within a preset address space divided into multiple sub-configuration spaces. This allows multiple chips in the target chip to share the preset address space, making the preset address space applicable to chip groups with different types of chips. Furthermore, based on the different sub-configuration spaces allocated to the modules contained in each chip, the configuration space can simultaneously apply to chip groups with different specifications, such as a chip group constituting a 32-core CPU or a chip group constituting a 64-core CPU. Therefore, the preset address space provided for the software system can be understood as a space shared by the chips in the chip group with a unified configuration, without requiring specific software to be configured to match it, thereby improving its applicability and reducing the software compatibility requirements of the resulting target chip.

[0125] This disclosure also provides a chip management network system applicable to a target chip. The target chip may include multiple dies of different types, each die containing one or more modules. Each die is configured with a management network configuration number, which is obtained based on the die type and its packaging location within the target chip. In an optional implementation, FIG15 exemplarily illustrates an optional structural diagram of the chip management network system according to an embodiment of this disclosure, in conjunction with the foregoing description. This chip management network system may include an acquisition module 151 and a configuration module 152. The functions and detailed structures of the acquisition module and the configuration module can be found in the corresponding descriptions above.

[0126] The acquisition module 151 is used to acquire the architecture information of the target chip, and the architecture information includes at least the management network configuration number of the chip configuration;

[0127] The configuration module 152 is used to divide the preset address space into multiple sub-configuration spaces according to the architecture information of the target chip; and to allocate corresponding sub-configuration spaces for the target chip and each chip in the target chip in the multiple sub-configuration spaces according to the management network configuration sequence number, wherein the sub-configuration spaces allocated to the modules contained in each chip are different.

[0128] Optionally, the configuration module 152 is used to divide the preset address space into multiple sub-configuration spaces according to the architecture information of the target chip. Specifically, the preset address space is divided into multiple sub-configuration spaces that satisfy predetermined rules according to the architecture information of the target chip. The predetermined rules are associated with the address space of each chip in the target chip.

[0129] Optionally, the predetermined rules include:

[0130] Different types of chips correspond to different address spaces, and the modules contained in a chip also correspond to different address spaces.

[0131] Optionally, the architecture information of the target chip acquired by the acquisition module 151 may also include the type of the target chip;

[0132] The configuration module 152 is used to divide the preset address space into multiple sub-configuration spaces that satisfy predetermined rules according to the architecture information of the target chip, including:

[0133] Based on the type of the target chip, the preset address space is divided into multiple configuration spaces, and different configuration spaces correspond to different functional implementations of the target chip;

[0134] Based on the number of cores in the target chip, the types and number of chips that make up the target chip, and the number and functions of modules contained in each chip in the target chip, the corresponding configuration space is divided into multiple sub-configuration spaces.

[0135] Optionally, the plurality of configuration spaces include at least a core configuration space, a system management configuration space, and an I / O management configuration space;

[0136] The core configuration space corresponds to the core task execution of the target chip; the system management configuration space corresponds to the state control of the target chip; and the I / O management configuration space corresponds to the information interaction of the target chip.

[0137] Optionally, the sub-configuration space includes: sub-core configuration space, sub-system configuration space, and sub-IO configuration space;

[0138] The configuration module 152 is used to divide the corresponding configuration space into multiple sub-configuration spaces based on the number of cores of the target chip, the types and numbers of chips that make up the target chip, and the types and numbers of modules contained in each chip, including:

[0139] Based on the number of cores in the target chip, the core configuration space is divided into multiple corresponding sub-core configuration spaces, wherein the number of the sub-core configuration spaces is greater than or equal to the number of cores in the target chip.

[0140] Based on the type and number of chips that make up the target chip, the system management configuration space is divided into multiple corresponding subsystem configuration spaces, wherein the number of the divided subsystem configuration spaces is greater than or equal to the number of chips contained in the target chip.

[0141] Based on the number and function of modules contained in each chip in the target chip, the IO management configuration space is divided into multiple corresponding sub-IO configuration spaces, wherein the number of the sub-IO configuration spaces is greater than or equal to the sum of the number of modules contained in each chip in the target chip.

[0142] Optionally, the configuration module 152 is used to allocate corresponding sub-configuration spaces for the target chip and each chip in the target chip in multiple sub-configuration spaces according to the management network configuration sequence number, including:

[0143] Based on the management network configuration number, a sub-core configuration space is allocated to the target chip in multiple sub-core configuration spaces according to the number of cores of the target chip;

[0144] In the multiple subsystem configuration spaces, a subsystem management configuration space is allocated to the target chip chips based on the type and quantity of the target chip chips;

[0145] In the plurality of sub-IO configuration spaces, a sub-IO configuration space is allocated to the modules contained in each chip in the target chip based on the number of modules and the module functions.

[0146] Optionally, the configuration module 152 may further include a reserved address space in the partitioned configuration space. The reserved address space is used to adapt to the address expansion requirements of target chips of different specifications, or to meet the different address expansion requirements of target chips.

[0147] Optionally, the architecture information of the target chip acquired by the acquisition unit 151 may further include a routing table corresponding to the target chip. The routing table contains multiple routing units, and the routing units are used to determine the data transmission paths corresponding to the modules contained in the chips of the target chip.

[0148] The configuration module 152 is used to allocate corresponding sub-configuration spaces for each chip in the target chip in multiple sub-configuration spaces according to the management network configuration sequence number, and is also used to:

[0149] Based on the management network configuration number, corresponding routing units are assigned to the modules contained in each chip in the target chip in the routing table.

[0150] Optionally, the target chip further includes an interface unit corresponding to the module contained in each chip, the interface unit being used for communication maintenance of the corresponding module;

[0151] The configuration module 152 is used to allocate corresponding routing units to the modules contained in each chip of the target chip in the routing table according to the management network configuration sequence number, and also includes allocating corresponding interface units to the modules contained in each chip of the target chip.

[0152] Optionally, the target chip may further include relay units configured in each chip of the target chip, the relay units being used for signal transmission between the chip and the peer chip.

[0153] The configuration module 152 is used to allocate corresponding routing units to the modules contained in each chip of the target chip in the routing table according to the management network configuration sequence number, and also includes allocating corresponding relay units to the modules contained in each chip of the target chip.

[0154] As can be seen, the chip management network configuration device of this disclosure embodiment can provide a space with unified configuration shared by chips in a chip group, without the need to configure specific software to match it, thereby improving its applicability and reducing the software compatibility requirements of the obtained target chip.

[0155] This disclosure also provides a computing device, such as a server device or a terminal device, which may include a chip management network system as provided in this disclosure.

[0156] This disclosure also provides a storage medium that stores one or more computer-executable instructions, which, when executed, implement the chip management network configuration method provided in this disclosure.

[0157] This disclosure also provides a computer program product, which includes one or more computer-executable instructions. When the one or more computer-executable instructions are executed, they implement the chip management network configuration method provided in this disclosure.

[0158] The foregoing describes multiple embodiment schemes provided by the present disclosure. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and made public by the present disclosure.

[0159] While the embodiments disclosed herein are as described above, this disclosure is not limited thereto. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A chip management network configuration method, applied to a target chip, wherein, The target chip includes multiple dies of different types, each die containing one or more modules, and each die is configured with a management network configuration number. The management network configuration number is obtained based on the type of die and its packaging position within the target chip, and includes: Obtain the architecture information of the target chip, wherein the architecture information includes at least the management network configuration number of the chip configuration; Based on the architecture information of the target chip, the preset address space is divided into multiple sub-configuration spaces; Based on the management network configuration sequence number, a corresponding sub-configuration space is allocated for the target chip and each chip in the target chip in multiple sub-configuration spaces, wherein the sub-configuration spaces allocated to the modules contained in each chip are different.

2. The method according to claim 1, wherein, The step of dividing the preset address space into multiple sub-configuration spaces according to the architecture information of the target chip includes: dividing the preset address space into multiple sub-configuration spaces that satisfy predetermined rules according to the architecture information of the target chip; wherein the predetermined rules are associated with the address space of each chip in the target chip.

3. The method according to claim 2, wherein, The predetermined rules include: Different types of chips correspond to different address spaces, and the modules contained in a chip also correspond to different address spaces.

4. The method according to claim 3, wherein, The architecture information of the target chip also includes the type of the target chip; The step of dividing the preset address space into multiple sub-configuration spaces that satisfy predetermined rules based on the architecture information of the target chip includes: Based on the type of the target chip, the preset address space is divided into multiple configuration spaces, and different configuration spaces correspond to different functional implementations of the target chip; Based on the number of cores in the target chip, the types and number of chips that make up the target chip, and the number and functions of modules contained in each chip in the target chip, the corresponding configuration space is divided into multiple sub-configuration spaces.

5. The method according to claim 4, wherein, The multiple configuration spaces include at least a core configuration space, a system management configuration space, and an I / O management configuration space; The core configuration space corresponds to the core task execution of the target chip; the system management configuration space corresponds to the state control of the target chip; and the I / O management configuration space corresponds to the information interaction of the target chip.

6. The method according to claim 5, wherein, The sub-configuration space includes: sub-core configuration space, sub-system configuration space, and sub-IO configuration space; The configuration space is divided into multiple sub-configuration spaces based on the number of cores in the target chip, the types and numbers of chips that make up the target chip, and the types and numbers of modules contained in each chip, including: Based on the number of cores in the target chip, the core configuration space is divided into multiple corresponding sub-core configuration spaces, wherein the number of the sub-core configuration spaces is greater than or equal to the number of cores in the target chip. Based on the type and number of chips that make up the target chip, the system management configuration space is divided into multiple corresponding subsystem configuration spaces, wherein the number of the divided subsystem configuration spaces is greater than or equal to the number of chips contained in the target chip. Based on the number and function of modules contained in each chip in the target chip, the IO management configuration space is divided into multiple corresponding sub-IO configuration spaces, wherein the number of the sub-IO configuration spaces is greater than or equal to the sum of the number of modules contained in each chip in the target chip.

7. The method according to claim 6, wherein, The step of allocating corresponding sub-configuration spaces for the target chip and each chip within the target chip in multiple sub-configuration spaces according to the management network configuration sequence number includes: Based on the management network configuration number, a sub-core configuration space is allocated to the target chip in multiple sub-core configuration spaces according to the number of cores of the target chip; In the multiple subsystem configuration spaces, a subsystem management configuration space is allocated to the target chip chips based on the type and quantity of the target chip chips; In the plurality of sub-IO configuration spaces, a sub-IO configuration space is allocated to the modules contained in each chip in the target chip based on the number of modules and the module functions.

8. The method according to any one of claims 5-7, wherein, The configuration space also includes a reserved address space, which is used to adapt to the address expansion requirements of target chips of different specifications, or to meet the different address expansion requirements of target chips.

9. The method according to any one of claims 1-8, wherein, The architecture information of the target chip also includes a routing table corresponding to the target chip. The routing table is used to indicate the routing information of the routing unit in the target chip. The routing information is used to determine the data transmission path corresponding to the module contained in the chip in the target chip. The step of allocating corresponding sub-configuration spaces for each chip in the target chip within multiple sub-configuration spaces according to the management network configuration sequence number also includes: Based on the management network configuration number, corresponding routing units are assigned to the modules contained in each chip in the target chip in the routing table.

10. The method according to any one of claims 1-9, wherein, The target chip also includes interface units corresponding to the modules contained in each chip, and the interface units are used for communication maintenance of the corresponding modules; The step of allocating corresponding routing units to the modules contained in each chip of the target chip in the routing table according to the management network configuration sequence number also includes: allocating corresponding interface units to the modules contained in each chip of the target chip.

11. The method according to any one of claims 1-10, wherein, The target chip also includes relay units set in each chip in the target chip, and the relay units are used for signal transmission between the chip and the peer chip; The step of allocating corresponding routing units to the modules contained in each chip of the target chip in the routing table according to the management network configuration sequence number also includes: allocating corresponding relay units to the modules contained in each chip of the target chip.

12. A chip management network system, applied to a target chip, wherein, The target chip includes multiple dies of different types. Each die contains one or more modules, and each die is configured with a management network configuration number. The management network configuration number is obtained based on the type of die and its packaging position in the target chip. The chip management network system includes: The acquisition module is configured to acquire the architecture information of the target chip, the architecture information including at least the management network configuration number of the chip configuration; The configuration module is configured to divide a preset address space into multiple sub-configuration spaces according to the architecture information of the target chip; and to allocate corresponding sub-configuration spaces for the target chip and each chip in the target chip in the multiple sub-configuration spaces according to the management network configuration sequence number, wherein the sub-configuration spaces allocated to the modules contained in each chip are different.

13. A computing device comprising the chip management network system as described in claim 12.

14. A storage medium storing one or more computer-executable instructions, wherein, When one or more computer-executable instructions are executed, the chip management network configuration method as described in any one of claims 1 to 11 is implemented.

15. A computer program product comprising one or more computer-executable instructions, wherein, When one or more computer-executable instructions are executed, the chip management network configuration method as described in any one of claims 1 to 11 is implemented.

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