Distribution method and device from unselectable scheduling queue to multi-scheduling queue

Abstract

The embodiment of the invention discloses a distribution method and device from an unselectable scheduling queue to a multi-scheduling queue. The method comprises the following steps: firstly, acquiring all microinstruction information read out by an unselectable scheduling queue, then, for each microinstruction, acquiring effective slot quantity and idle slot quantity of a first type of scheduling queue and a second type of scheduling queue, and calculating a difference value of the effective slot quantity of the two types of queues; meanwhile, the effective microinstruction number of the corresponding sub PIPE of each scheduling queue is obtained, and the difference value of the effective microinstruction number of the corresponding sub PIPE is calculated; the number of the idle slots and the three difference values are synthesized to determine unbalance types, and the unbalance types are classified carefully; and calling a corresponding allocation strategy to dynamically allocate the microinstruction according to different unbalance types. According to the method, the imbalance condition of the system can be comprehensively and accurately judged, and the throughput rate from an unselectable scheduling queue to a multi-scheduling queue when the scheduling queues are relatively idle or SQ or PIPE imbalance does not occur is effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method and apparatus for allocating from a non-selectable scheduling queue to a multi-scheduling queue. Background Technology

[0002] To improve instruction set parallelism, CPU design employs pipelining. During microinstruction execution, after being renamed in registers, microinstructions first enter the non-pickable schedule queue (NSQ), and then sequentially enter the multi-schedule queue (MSQ). The multi-schedule queue contains multiple schedule queues (SQ), each corresponding to a different execution PIPE. Microinstructions in the SQ then undergo a preparation process before being fetched and passed to the execution unit for execution.

[0003] The allocation mechanism from non-selectable scheduling queues to multiple scheduling queues mainly depends on the current balance between SQs and PIPEs. Microinstructions to be allocated will go to the corresponding SQ or an SQ with fewer PIPEs.

[0004] In existing technologies, the allocation devices from non-pickable queues to multiple queues suffer from several drawbacks. Due to physical limitations or design constraints of the data storage location for each microinstruction, some microinstructions can only be allocated to a specific PIPE, i.e., only to the SQ corresponding to that specific PIPE (i.e., single-select microinstructions). Furthermore, since the number of write ports for each SQ is limited by resource constraints, a batch of microinstructions read from the NSQ must enter the SQ in sequence. As a result, when selecting which SQ to allocate multiple-select microinstructions to based solely on the balance of SQs or PIPEs, the limited number of write ports for the SQs leads to a loss in throughput from the NSQ to the SQ, thus degrading performance. Summary of the Invention

[0005] In view of this, the present disclosure provides a method and apparatus for allocating from a non-selectable scheduling queue to a multi-scheduling queue, which can solve the problem of reduced throughput during allocation caused by single-selection microinstructions in the prior art.

[0006] In a first aspect, embodiments of this disclosure provide a method for allocating tasks from a non-selectable scheduling queue to multiple scheduling queues, including: Retrieve all microinstruction information read from the currently unselectable scheduling queue; Get the number of valid slots and the number of idle slots in the first type of scheduling queue and the second type of scheduling queue, and get the first difference between the number of valid slots in the two types of queues; Obtain the effective micro-instruction counts of the first sub-PIPE and the second sub-PIPE corresponding to the first type of scheduling queue, and the effective micro-instruction counts of the third sub-PIPE and the fourth sub-PIPE corresponding to the second type of scheduling queue, respectively. Obtain a second difference in the number of effective microinstructions between the first sub-PIPE and the third sub-PIPE, and a third difference in the number of effective microinstructions between the second sub-PIPE and the fourth sub-PIPE; Based on the number of idle slots, the first difference, the second difference, and the third difference, the imbalance type is determined, and the corresponding allocation strategy is invoked according to the imbalance type to dynamically allocate each microinstruction in the microinstruction information.

[0007] Secondly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform any of the above-described allocation methods from non-selectable scheduling queues to multiple scheduling queues.

[0008] Thirdly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions for causing a computer to perform any of the above-described allocation methods from non-selectable scheduling queues to multiple scheduling queues.

[0009] Fourthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0010] The allocation method disclosed in this application from a non-selectable scheduling queue to multiple scheduling queues first obtains all micro-instruction information read from the currently non-selectable scheduling queue, providing basic data for subsequent allocation; then, it obtains the number of valid slots and the number of idle slots in the current first-type scheduling queue and the second-type scheduling queue, and obtains the first difference in the number of valid slots between the two types of queues, which can clearly understand the current balance and load of the two types of scheduling queues; next, it obtains the number of valid micro-instructions for the first sub-PIPE and the second sub-PIPE corresponding to the first-type scheduling queue, and the number of valid micro-instructions for the third sub-PIPE and the fourth sub-PIPE corresponding to the second-type scheduling queue; and obtains the second difference in the number of valid micro-instructions between the first and third sub-PIPEs and the third difference in the number of valid micro-instructions between the second and fourth sub-PIPEs, which can provide a deeper understanding of each sub-PIPE. The system monitors the working status of the system; finally, based on the number of idle slots, the first difference, the second difference, and the third difference, it determines the imbalance type and calls the corresponding allocation strategy to dynamically allocate each microinstruction in the microinstruction information according to the imbalance type. By comprehensively considering multiple aspects of queue and PIPE information, it can comprehensively and accurately judge the imbalance status of the system, classify the imbalance type in detail, and adopt different allocation methods for different imbalance types. This effectively improves the throughput from non-selectable scheduling queues to multiple scheduling queues when the scheduling queue is relatively idle or there is no imbalance of SQ or PIPE.

[0011] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating the allocation method from a non-selectable scheduling queue to multiple scheduling queues provided in an embodiment of this disclosure.

[0014] Figure 2 A flowchart illustrating a method for determining the type of imbalance provided in an embodiment of this disclosure.

[0015] Figure 3This is a flowchart illustrating a method for dynamically allocating corresponding microinstructions based on a first-type strategy, as provided in an embodiment of this disclosure.

[0016] Figure 4 This is a flowchart illustrating a method for dynamically allocating corresponding microinstructions based on a second type of strategy, as provided in an embodiment of this disclosure.

[0017] Figure 5 This is a flowchart illustrating a method for dynamically allocating corresponding microinstructions based on a third-class strategy, as provided in an embodiment of this disclosure.

[0018] Figure 6 This is a flowchart illustrating a method for dynamically allocating corresponding microinstructions based on a fourth type of strategy, as provided in an embodiment of this disclosure.

[0019] Figure 7 This is a block diagram of the structure of a general-purpose CPU, from microinstruction renaming through registers to execution unit.

[0020] Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0021] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0022] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0023] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0024] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0025] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0026] Reference Figure 1 This application discloses a method for allocating from a non-selectable scheduling queue to multiple scheduling queues, including: S100: Obtain all microinstruction information read from the currently unselectable scheduling queue.

[0027] Each microinstruction is a multiplication, addition, or store type. Each scheduling queue typically writes a maximum of 6 microinstructions at a time. Multiple scheduling queues generally include a first type scheduling queue (SQ0), a second type scheduling queue (SQ1), and a store scheduling queue (Store SQ). The corresponding non-selectable scheduling queue (NSQ) typically reads 6 microinstructions at a time. In this embodiment, all microinstruction information includes 6 microinstructions and their corresponding types. The dynamic allocation of each microinstruction is as follows.

[0028] S200: Obtain the number of valid slots and the number of idle slots in the current first type of scheduling queue and the second type of scheduling queue, and obtain the difference between the number of valid slots in the two types of queues, which is recorded as the first difference.

[0029] S300: Obtain the effective microinstruction counts of the first sub-PIPE and the second sub-PIPE corresponding to the first type of scheduling queue, and the effective microinstruction counts of the third sub-PIPE and the fourth sub-PIPE corresponding to the second type of scheduling queue.

[0030] In this embodiment, the PIPE corresponding to the first type of scheduling queue is the first sub-PIPE and the second sub-PIPE, and the PIPE corresponding to the second type of scheduling queue is the third sub-PIPE and the fourth sub-PIPE; the first sub-PIPE and the third sub-PIPE constitute the first type of PIPE, and the second sub-PIPE and the fourth sub-PIPE constitute the second type of PIPE. More preferably, the first type of PIPE corresponds to micro-instructions that can execute multiplication, and the second type of PIPE corresponds to micro-instructions that can execute addition.

[0031] S400: Obtain the difference in the number of valid microinstructions between the first sub-PIPE and the third sub-PIPE, and record it as the second difference; obtain the difference in the number of valid microinstructions between the second sub-PIPE and the fourth sub-PIPE, and record it as the third difference.

[0032] S500 determines the imbalance type based on the number of idle slots, the first difference, the second difference, and the third difference.

[0033] It should be noted that as long as the number of free slots, the first difference, the second difference, and the third difference are obtained before determining the type of imbalance, the order of S100-S400 is only a preferred embodiment and does not limit the scope of protection of this application.

[0034] S600 invokes the corresponding allocation strategy based on the imbalance type to dynamically allocate each microinstruction in the microinstruction information.

[0035] In this embodiment, the first difference, the second difference, and the third difference all refer to absolute values.

[0036] The allocation method disclosed in this application from a non-selectable scheduling queue to multiple scheduling queues obtains all micro-instruction information read from the non-selectable scheduling queue in S100, providing basic data for subsequent allocation; while in S200, the effective slot count, the idle slot count, and their difference (first difference) of the two types of scheduling queues corresponding to each micro-instruction are obtained respectively. This can clearly understand the current balance and load status of the two types of scheduling queues. The effective slot count reflects the resources occupied by the queue, the idle slot count reflects the remaining processing capacity of the queue, and the first difference is used to measure the degree of load difference between the two types of queues; S300 obtains the effective micro-instruction count of each sub-PIPE, and S400 calculates the difference (second difference and third difference) between the corresponding sub-PIPEs. Since different scheduling queues may correspond to different... The S500 analyzes the load of different sub-pipelines (PIPEs) in detail, providing a deeper understanding of the working status of each sub-pipeline and helping to identify which sub-pipelines are experiencing load imbalances. This provides a more accurate basis for subsequent allocation decisions. The S500 determines the imbalance type based on the number of idle slots, the first difference, the second difference, and the third difference. By comprehensively considering multiple aspects of queue and pipeline information, it can accurately and comprehensively judge the system's imbalance status and classify the imbalance type in detail, such as queue-level imbalance and pipeline-level imbalance. The S600 dynamically allocates resources by calling the corresponding allocation strategy based on the determined imbalance type. Different allocation methods are used for different imbalance types, enabling more targeted solutions to system problems and improving the rationality and efficiency of resource allocation.

[0037] This method, while maintaining timing friendliness, effectively improves throughput when switching from a non-selectable scheduling queue (NSQ) to multiple scheduling queues (MSQ) when the scheduling queue (SQ) is relatively idle or there is no imbalance in the SQ or PIPE. Through precise load assessment and flexible allocation strategies, it can more rationally distribute micro-instructions to different scheduling queues and sub-PIPEs, avoiding resource idleness and waste, enabling the system to process micro-instructions more efficiently, thereby improving overall throughput. Because it adopts a dynamic allocation method, adjusting the allocation strategy in real time according to different imbalance types, the system can better adapt to different workloads and changing conditions. It maintains good performance under both light and heavy queue loads, enhancing system stability and reliability. In summary, this method of switching from a non-selectable scheduling queue to multiple scheduling queues provides an efficient and reliable solution for computer system scheduling and resource allocation through precise load assessment, flexible imbalance handling, performance improvement and optimization, and device improvements.

[0038] Reference Figure 2The S500 method of "determining the imbalance type based on the number of idle slots, the first difference, the second difference, and the third difference" specifically includes the following methods for determining the imbalance type: S510 determines the queue's balance and load status based on the first difference and the number of idle slots; S520, determine the queue PIPE difference status based on the second difference and the third difference; S530 determines the imbalance type based on the queue's balance, load status, and queue PIPE difference status.

[0039] Specifically, when the proportion of the number of idle slots in the corresponding call queue is greater than a preset proportion threshold (i.e., the proportion of the number of idle slots in the current first type of scheduling queue in the first type of call queue is greater than the preset proportion threshold and the proportion of the number of idle slots in the current second type of scheduling queue in the second type of call queue is greater than the preset proportion threshold), or when the first difference is not greater than the first preset threshold, the second difference is not greater than the second preset threshold and the third difference is not greater than the third preset threshold, the imbalance type is determined to be the first type of imbalance.

[0040] The phrase "when the proportion of idle slots in the corresponding call queue is greater than the preset proportion threshold" means that when the proportion of idle slots in the first type of scheduling queue is greater than the preset proportion threshold and the proportion of idle slots in the second type of scheduling queue is greater than the preset proportion threshold, it indicates that there are enough idle slots in both types of scheduling queues.

[0041] If the conditions "the first difference is not greater than the first preset threshold, the second difference is not greater than the second preset threshold, and the third difference is not greater than the third preset threshold" are met, it indicates that there is no imbalance in the scheduling queue or the PIPE.

[0042] When a single microinstruction corresponds to a type 1 imbalance, a type 1 strategy invocation instruction is generated based on the type 1 imbalance; the type 1 strategy is invoked in response to the type 1 strategy invocation instruction; and the dynamic allocation of the corresponding microinstruction is executed based on the type 1 strategy.

[0043] In this embodiment, the first type of strategy refers to the strategy of allocating all resources that should be allocated.

[0044] The first type of strategy mainly includes two implementation examples, as follows.

[0045] Example 1 Reference Figure 3 The method of "dynamic allocation of corresponding microinstructions based on the first type of strategy" includes: A100 configures a target queue list based on the PIPE corresponding to the microinstruction information. The target queue list includes several sub-elements.

[0046] Each sub-element is the target scheduling queue for a single microinstruction (any one of the six categories: SQ0, SQ1, SQ0 / SQ1, Store SQ, and empty), and the order of all sub-elements is consistent with the order of the microinstructions in the microinstruction information.

[0047] Specifically, scheduling queues generally include first-class scheduling queues (SQ0), second-class scheduling queues (SQ1), and store scheduling queues (Store SQ). The target scheduling queue can be any one of the six categories: SQ0, SQ1, SQ0 / SQ1, Store SQ, or empty. That is, there are six possible scenarios for microinstructions to be allocated: only SQ0, only SQ1, both SQ0 and SQ1, only Store SQ, and no queue available for allocation (i.e., empty).

[0048] Table 1: List of Target Teams In Table 1, a0, a1, a2, a3, a4, and a5 are sub-elements arranged in the order of the 6 micro-instructions read from the currently unselectable scheduling queue. It can be understood that a0 corresponds to the older micro-instruction, and a5 corresponds to the younger micro-instruction.

[0049] A200 obtains the initial position table corresponding to the target queue list based on all target scheduling queues. Each position in the initial position table corresponds to a rule value.

[0050] The rule value for each location is determined according to preset rules. Specifically, if the target scheduling queue in a single location is SQ0, SQ1, Store SQ, or empty, the corresponding rule value in the initial location table is the first value; if the target scheduling queue in a single location is SQ0 / SQ1, the corresponding rule value in the initial location table is the second value. Further, the first value is preferably 0, and the second value is preferably 1. Table 2: Initial Location Table Assuming that in a specific embodiment, the obtained initial position table is [1,0,1,0,1,0], it means that a0, a2, and a4 correspond to multi-select micro-instructions (i.e., SQ0 / 1), and a1, a3, and a4 correspond to single-select micro-instructions. Specifically, a1 corresponds to the single-select SQ0 micro-instruction, a3 corresponds to the single-select Store SQ micro-instruction, and a5 corresponds to the single-select SQ1 micro-instruction.

[0051] A300, determine the multiple-choice position table based on the initial position table.

[0052] In the position multiple choice table, each position corresponds to one multiple choice.

[0053] When the rule value is the first value, and 0 is preferred, the corresponding number of multiple selections is 0; When the rule value is the second value, preferably 1, the number of multiple choices at the i-th position = the rule value at the i-th position + the sum of all rule values ​​at the first i-1 positions.

[0054] In this embodiment, the maximum value of i is 6, which is consistent with the total number of microinstructions read from the currently unselectable scheduling queue.

[0055] Table 3: Multiple Choice Table for Positions Referring to Table 3, the position multiple selection numbers in the position multiple selection table corresponding to the example above are [1,0,2,0,3,0], indicating that the microinstruction corresponding to a0 is the first multiple selection microinstruction, the microinstruction corresponding to a2 is the second multiple selection microinstruction, and the microinstruction corresponding to a4 is the third multiple selection microinstruction.

[0056] The A400 determines and executes the dynamic allocation strategy for each microinstruction based on the position selection table and the target queue list.

[0057] Specifically, the A400 includes: A410, if the target queue list meets the first type of condition, call the first sub-strategy to execute the dynamic allocation of the corresponding single micro-instruction; A420: If the target queue list meets the second type of condition, the second sub-strategy is invoked to execute the dynamic allocation of the corresponding single micro-instruction; A430: If the target queue list meets the third type of condition, the third sub-strategy is invoked to execute the dynamic allocation of the corresponding single micro-instruction.

[0058] For the A410, specifically including: A411, get the total number of third-type scheduling queues in the first 4 child elements of the target queue list, denoted as the total number of StoreSQs; A412, if the total number of Store SQ is 0, 3 or 4, obtain the total number of single-selection first-type scheduling queues and the total number of single-selection second-type scheduling queues in the first 4 child elements of the target queue list, and record them as the first-type single-selection number (i.e., CntSQ0) and the second-type single-selection number (i.e., CntSQ1) respectively. A413, retrieve the maximum number of selections among the first 4 selections in the position selection table; A414, based on the maximum number of multiple selections and the first and second types of single selections, calls the corresponding first sub-strategy to execute the dynamic allocation of the corresponding single micro-instruction.

[0059] Specifically, if the maximum number of multiple selections is 0, the corresponding single micro-instruction enters the multiple scheduling queue in sequence; If the maximum number of selections is 1, the corresponding single microinstruction will be assigned to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1. If the maximum number of multiple selections is 2, these two multiple selection micro-instructions will be assigned to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1. If the maximum number of multiple selections is 3 or 4, the first two multiple selection micro-instructions are assigned to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1; the remaining multiple selection micro-instructions are assigned to the scheduling queue corresponding to the larger value of CntSQ0 and CntSQ1.

[0060] For the A420, specifically including: A421, retrieve the first 5 child elements in the target list; A422, among the current 4 child elements, there is only one Store SQ and the 5th child element is not a Store SQ. Get the total number of single selections of the first type of scheduling queue and the total number of single selections of the second type of scheduling queue among the first 5 child elements, and record them as the first type single selection number (i.e., CntSQ0) and the second type single selection number (i.e., CntSQ1) respectively. A423 retrieves the maximum number of multiple selections from the top 5 multiple selections in the position multiple selection table, and based on the number of the maximum multiple selections, the first type of single selections, and the second type of single selections, calls the corresponding second sub-strategy to execute the dynamic allocation of the corresponding single micro-instruction.

[0061] The specific steps for "dynamically allocating the corresponding single microinstruction by calling the corresponding second sub-policy" include: If the maximum number of selections is 0, the corresponding single microinstruction enters the multi-scheduling queue in sequence. If the maximum number of selections is 1, the corresponding single microinstruction is allocated to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1. If the maximum number of selections is 2, the two multi-select microinstructions are allocated to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1. If the maximum number of selections is 3 or 4, the first two multi-select microinstructions are allocated to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1; the remaining multi-select microinstructions are allocated to the scheduling queue corresponding to the larger value of CntSQ0 and CntSQ1.

[0062] For the A430, specifically including: A431, retrieve the first 6 child elements in the target list; A432, if there is only one Store SQ among the current 4 child elements and the 5th child element is a Store SQ, or if there are two Store SQs among the first 4 child elements, obtain the total number of single selections of the first type of scheduling queue and the total number of single selections of the second type of scheduling queue among the first 6 child elements, and record them as the first type single selection number (i.e., CntSQ0) and the second type single selection number (i.e., CntSQ1) respectively. A433 retrieves the maximum number of multiple selections from the first 6 multiple selections in the position selection table, and based on the number of the maximum number of multiple selections, the first type of single selections, and the second type of single selections, calls the corresponding third sub-strategy to execute the dynamic allocation of the corresponding single micro-instruction.

[0063] The specific steps for "dynamically allocating the corresponding single microinstruction by calling the corresponding third sub-policy" include: If the maximum number of selections is 0, the corresponding single microinstruction enters the multi-scheduling queue in sequence. If the maximum number of selections is 1, the corresponding single microinstruction is allocated to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1. If the maximum number of selections is 2, the two multi-select microinstructions are allocated to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1. If the maximum number of selections is 3 or 4, the first two multi-select microinstructions are allocated to the scheduling queue corresponding to the smaller value of CntSQ0 and CntSQ1; the remaining multi-select microinstructions are allocated to the scheduling queue corresponding to the larger value of CntSQ0 and CntSQ1.

[0064] The method disclosed in this application for "dynamic allocation of corresponding microinstructions based on the first type of strategy" specifically includes the above three cases, and executes the first sub-strategy, the second sub-strategy, or the third sub-strategy according to different cases. In this embodiment, since the scheduling queue corresponding to the Store SQ is a single-selection microinstruction, the analysis mainly focuses on non-Store SQs. The method provided by this application covers all cases in this scenario, realizes intelligent allocation of multi-selection microinstructions, improves system throughput, and increases execution efficiency.

[0065] Example 2 Dynamic allocation of corresponding microinstructions based on the first type of strategy includes: 1) Configure a target queue list according to the PIPE corresponding to the microinstruction information. The target queue list includes several sub-elements, and each sub-element is the target scheduling queue of a single microinstruction.

[0066] The order of all sub-elements is consistent with the order of the micro-instructions in the micro-instruction information.

[0067] 2) Based on all target scheduling queues, obtain the type initial table corresponding to the target queue list. Each position in the type initial table corresponds to a type of scheduling queue that can be accessed.

[0068] Each type can be any of the following: store SQ, SQ0, SQ1, SQ0 / 1, or air.

[0069] 3) Based on the initial type table, determine the location multi-selection table, Store number table, first type target queue number table (i.e., the number of items that only go to the first type scheduling queue), second type target queue number table (i.e., the number of items that only go to the second type scheduling queue), and multi-selection cumulative table.

[0070] In the position multiple choice table, each position corresponds to a multiple choice number; in the position multiple choice table: when the type of the accessible scheduling queue is not SQ0 / 1, the corresponding multiple choice number is 0; when the type of the accessible scheduling queue is SQ0 / 1, the multiple choice number of the i-th position is equal to the total number of accessible scheduling queues of type SQ0 / 1 in the first i positions.

[0071] Each position in the Store count table corresponds to a Store count; in the Store count table, the Store count at the i-th position is equal to the number of Store SQs among all the types of dispatch queues that can be accessed from the first i positions.

[0072] In the table of first-class target queues, the number of first-class target queues at position i is equal to the number of SQ0 queues among all accessible scheduling queues at the first i positions.

[0073] In the table of second-class target queues, the number of second-class target queues at position i is equal to the number of SQ1 queues among all accessible scheduling queues at the first i positions.

[0074] In the multi-selection cumulative table, each position corresponds to a multi-selection cumulative number; the multi-selection cumulative number of the i-th position is equal to the number of all accessible scheduling queues of type SQ0 / 1 for the first i positions.

[0075] It should be noted that in this embodiment, the first type of scheduling queue preferably refers to SQ0, and the second type of scheduling queue preferably refers to SQ1; in addition, if the first type of scheduling queue refers to SQ1, then the second type of scheduling queue refers to SQ0, both of which are within the protection scope of this application.

[0076] 4) Starting from the second position in the target queue list, find the first target position that meets the preset allocation position conditions according to the multi-select cumulative table 1, the first type of target queue number table 0, the second type of target queue number table 0, and the Store number table, and set the position before the target position as the endpoint of the position to be allocated.

[0077] 5) If there is no position that meets the preset allocation position conditions, then set the position of the last micro-instruction as the endpoint of the position to be allocated.

[0078] 6) Determine and execute the dynamic allocation strategy for each microinstruction based on the position selection table, the endpoint of the position to be assigned, and the target team list.

[0079] The method of "finding the first target position that meets the preset allocation position conditions based on the multi-select cumulative table, the first type of target queue number table, the second type of target queue number table, and the Store number table, and setting the position before the target position as the endpoint of the position to be allocated" includes: 1) Based on the multiple-selection cumulative table, the first type of target queue number table, and the second type of target queue number table 0, determine the information corresponding to each microinstruction position. The information includes the total number of microinstructions written in a single allocation of non-Store class SQ, the number of Stores, the number of first type of target queues, and the number of second type of target queues. 2) If the information corresponding to all micro-instructions satisfies at least two of the first, second, third, and fourth conditions, select the position preceding the first position from the target positions that satisfy at least two conditions and set it as the endpoint of the position to be assigned. 3) If the information corresponding to all micro-instructions satisfies any one of the first, second, third, or fourth conditions, determine the first target position that satisfies the preset allocation position condition starting from the second position in the target queue list, and set the position before the target position as the endpoint P of the position to be allocated. 4) If the first, second, third, and fourth conditions are not met, set the position of the last microinstruction as the endpoint of the position to be allocated.

[0080] The first condition is that the total number of microinstructions written in a single allocation of a non-Store type SQ for each microinstruction position is greater than 2n. In this embodiment, the "total number of microinstructions written in a single allocation of a non-Store type SQ" is the sum of multiple selections, the number of the first type of target queue, and the number of the second type of target queue, where n is the maximum number of microinstructions that can be written to each scheduling queue at one time. The second condition is that the number of Stores is greater than n; the third condition is that the number of the first type of target queue is greater than n; and the fourth condition is that the number of the second type of target queue is greater than n.

[0081] It should be noted that the order of judgment of the first, second, third, and fourth conditions is not restricted, and all are within the scope of protection of this application.

[0082] The method of "determining and executing the dynamic allocation strategy for each microinstruction based on the type initialization table, the endpoint P of the position to be allocated, and the target queue list" includes: 1) Extract all micro-instructions corresponding to the endpoint of the position to be assigned and the positions before it in the target queue list to obtain the target queue to be assigned; 2) Obtain the target initial table corresponding to the target queue to be assigned based on the type initial table; obtain the target multiple selection table corresponding to the target queue to be assigned based on the position multiple selection table; 3) Obtain the total number of single-selection first-type scheduling queues and the total number of single-selection second-type scheduling queues in the target initial table, and record them as the first-type single-selection number and the second-type single-selection number, respectively; 4) All micro-instructions with multiple selections in the target multiple selection table are assigned to the multi-scheduling queue in the order they appear in the target queue list; Assign the microinstructions corresponding to the multi-selection number in the target multi-selection table that is no greater than (n - the first type of single selection number) to the first type of scheduling queue; where n is the maximum number of microinstructions that can be written to each scheduling queue at one time. The remaining micro-instructions in the target queue to be assigned are assigned to the second type of scheduling queue.

[0083] Specifically, we will take the target team list in Example 1 as an example for a detailed description.

[0084] Table 4 Initial Table of Types In this table, the characters are arranged in ascending order as follows: a0 corresponds to SQ0 / 1 (i.e., multi-select micro-instruction), a1 corresponds to single-select SQ0 micro-instruction, a2 corresponds to SQ0 / 1 (i.e., multi-select micro-instruction), a3 corresponds to single-select Store SQ micro-instruction, a4 corresponds to SQ0 / 1 (i.e., multi-select micro-instruction), and a5 corresponds to single-select SQ1 micro-instruction.

[0085] Table 5. Multiple Choice Table for Positions In the position multiple-choice table, when the type of the accessible scheduling queue is not SQ0 / 1, the corresponding multiple-choice number is 0; when the type of the accessible scheduling queue is SQ0 / 1, the multiple-choice number of the i-th position is equal to the total number of accessible scheduling queues of type SQ0 / 1 in the first i positions. Therefore, in this embodiment, the multiple-choice numbers corresponding to positions a0, a1, a2, a3, a4, and a5 are 1, 0, 2, 0, 3, and 0, respectively.

[0086] Table 6 Store Count Table In the Store count table, since the Store count at position i is equal to the number of Store SQs among all the dispatch queue types that can be accessed at the previous i positions, in this embodiment, the multiple selection numbers corresponding to positions a0, a1, a2, a3, a4, and a5 are 0, 0, 0, 1, 1, and 1, respectively.

[0087] Table 7 Number of Queues for the First Type of Target In the first type of target queue number table, since the number of first type target queues at the i-th position is equal to the number of SQ0 types among all the go-to scheduling queues at the first i positions, in this embodiment, the multiple selection numbers corresponding to positions a0, a1, a2, a3, a4, and a5 are 0, 1, 1, 1, 1, and 1, respectively.

[0088] Table 8. Number of Second-Class Target Queues In the second type of target queue number table, since the number of second type target queues at the i-th position is equal to the number of SQ1 types among all the go-to scheduling queues at the first i positions, in this embodiment, the multiple selection numbers corresponding to positions a0, a1, a2, a3, a4, and a5 are 0, 0, 0, 0, 0, and 1, respectively.

[0089] Table 9 Multiple Choice Cumulative Table In the multi-select cumulative table, since the multi-select cumulative number of the i-th position is equal to the number of all accessible scheduling queues of type SQ0 / 1 for the first i positions, in this embodiment, the multi-select numbers corresponding to positions a0, a1, a2, a3, a4, and a5 are 1, 1, 2, 2, 3, and 3, respectively.

[0090] For example, for the microinstruction at position a0, the "total number of microinstructions written in a single allocation of non-Store class SQ" at the corresponding position is (1+0+0=1). In this embodiment, n is 2, so the first condition is not satisfied. Then, we analyze whether the second condition is satisfied. Since the number of Stores at the corresponding position is 0, which is less than 2, the second condition is also not satisfied. Next, we analyze whether the third condition is satisfied. Since the number of first-class target queues at the corresponding position is 0, which is less than 2, the third condition is also not satisfied. Finally, we analyze whether the fourth condition is satisfied. Since the number of second-class target queues at the corresponding position is 0, which is less than 2, the fourth condition is also not satisfied.

[0091] For the microinstruction at position a1, the total number of microinstructions written in a single allocation of non-Store class SQ at the corresponding position is (1+1+0=2), which is not greater than 2n, so the first condition is not satisfied. Then we analyze whether the second condition is satisfied, because the number of Stores at the corresponding position is 0, which is less than 2, so the second condition is not satisfied either. Next, we analyze whether the third condition is satisfied, because the number of first-class target queues at the corresponding position is 1, which is less than 2, so the third condition is not satisfied either. Finally, we analyze whether the fourth condition is satisfied, because the number of second-class target queues at the corresponding position is 0, which is less than 2, so the fourth condition is not satisfied either.

[0092] For the microinstruction at position a2, the total number of microinstructions written in a single allocation of non-Store class SQ at the corresponding position is (2+1+0=3), which is not greater than 2n, so the first condition is not met. Then, we analyze whether the second condition is met, because the number of Stores at the corresponding position is 0, which is less than 2, so the second condition is not met either. Next, we analyze whether the third condition is met, because the number of first-class target queues at the corresponding position is 1, which is less than 2, so the third condition is not met either. Finally, we analyze whether the fourth condition is met, because the number of second-class target queues at the corresponding position is 0, which is less than 2, so the fourth condition is not met either.

[0093] For the microinstruction at position a3, the total number of microinstructions written in a single allocation of non-Store class SQ at the corresponding position is (2+1+0=3), which is not greater than 2n, so the first condition is not met. Then, we analyze whether the second condition is met, because the number of Stores at the corresponding position is 1, which is less than 2, so the second condition is not met either. Next, we analyze whether the third condition is met, because the number of first-class target queues at the corresponding position is 1, which is less than 2, so the third condition is not met either. Finally, we analyze whether the fourth condition is met, because the number of second-class target queues at the corresponding position is 0, which is less than 2, so the fourth condition is not met either.

[0094] For the microinstruction at position a4, the total number of microinstructions written in a single allocation of non-Store class SQ at the corresponding position is (3+1+0=4), which is not greater than 2n, so the first condition is not met. Then, we analyze whether the second condition is met, because the number of Stores at the corresponding position is 1, which is less than 2, so the second condition is not met either. Next, we analyze whether the third condition is met, because the number of first-class target queues at the corresponding position is 1, which is less than 2, so the third condition is not met either. Finally, we analyze whether the fourth condition is met, because the number of second-class target queues at the corresponding position is 0, which is less than 2, so the fourth condition is not met either.

[0095] For the microinstruction at position a5, the total number of microinstructions written in a single allocation of non-Store type SQ at the corresponding position is (3+1+1=5), which is greater than 2n, thus satisfying the first condition. Next, we analyze whether the second condition is satisfied. Since the number of Stores at the corresponding position is 1, which is less than 2, the second condition is also not satisfied. Then, we analyze whether the third condition is satisfied. Since the number of first-type target queues at the corresponding position is 1, which is less than 2, the third condition is also not satisfied. Finally, we analyze whether the fourth condition is satisfied. Since the number of second-type target queues at the corresponding position is 1, which is less than 2, the fourth condition is also not satisfied. Because the microinstruction at position a5 satisfies the first condition of the first, second, third, and fourth conditions, and there is only one target position satisfying the preset allocation position condition starting from the second position in the target queue list (i.e., the first one), we set the position preceding the target position (i.e., position a5) (i.e., position a4) as the endpoint of the position to be allocated (i.e., position a4).

[0096] Next, “extract all micro-instructions corresponding to the endpoint of the target queue and the positions before it in the target queue list to obtain the target queue to be assigned”. In this embodiment, the target queue to be assigned includes [a0,a1,a2,a3,a4], and the corresponding target initial table is [SQ0 / 1,SQ0,SQ0 / 1,Store SQ,SQ0 / 1]; the corresponding target multi-select table is [1,0,2,0,3].

[0097] Obtain the total number of single-selection first-type scheduling queues and the total number of single-selection second-type scheduling queues in the target initial table, and record them as the first-type single-selection number (i.e., 1) and the second-type single-selection number (i.e., 0), respectively.

[0098] All micro-instructions with a multi-selection value of 0 in the target multi-selection table are assigned to the multi-scheduling queue in the order of the target queue list; Microinstructions with a multi-selection number not greater than (n - first-type single-selection number) in the target multi-selection table are assigned to the first-type scheduling queue. The remaining microinstructions in the target queue to be assigned are assigned to the second-type scheduling queue. In this embodiment, n - first-type single-selection number is 1, so the multi-selection numbers corresponding to a0, a1, a2, a3, and a4 are 1, 0, 2, 0, and 3 respectively. The microinstruction corresponding to a0 is assigned to the multi-scheduling queue according to the order in the target queue list (preferably assigned to SQ0 in this embodiment). The multi-selection number corresponding to a1 is 0, and the microinstruction corresponding to a1 is assigned to the first-type scheduling queue (SQ0 in this embodiment). The multi-selection number corresponding to a2 is greater than (n - first-type single-selection number), so the microinstruction corresponding to a2 is assigned to the second-type scheduling queue. The multi-selection number corresponding to a3 is 0, so the microinstruction corresponding to a3 is assigned to the Store SQ scheduling queue. The multi-selection number corresponding to a4 is greater than (n - first-type single-selection number), so the microinstruction corresponding to a4 is assigned to the second-type scheduling queue. Since a5 is not in the target queue to be assigned, it is not assigned. In this embodiment, this method can successfully distribute a total of 5 microinstructions to multiple scheduling queues at once.

[0099] If the first difference is greater than the first preset threshold, the second difference is not greater than the second preset threshold, and the third difference is not greater than the third preset threshold, the imbalance type is determined to be the second type of imbalance. This type of imbalance represents that only the imbalance between SQ0 and SQ1 has occurred.

[0100] When a single microinstruction corresponds to a type 2 imbalance, a type 2 strategy invocation instruction is generated based on the type 2 imbalance; the type 2 strategy is invoked in response to the type 2 strategy invocation instruction; and the dynamic allocation of the corresponding microinstruction is executed based on the type 2 strategy.

[0101] In this embodiment, the second type of strategy refers to the SQ-first allocation strategy (i.e., the scheduling queue priority strategy).

[0102] Reference Figure 4 The method of "dynamic allocation of corresponding microinstructions based on the second type of strategy" includes: B100, determines the microinstruction to be allocated, denoted as the target microinstruction; After allocating a microinstruction, B200 updates the queue corresponding to the smaller number of valid slots in the current first-class scheduling queue and second-class scheduling queue corresponding to the target microinstruction in real time, which is denoted as the target queue. B300, if the target microinstruction is a multi-select microinstruction, assign the target microinstruction to the target queue; If the target microinstruction is a single-selection microinstruction, it will be entered into the multi-schedule queue in sequence.

[0103] It should be noted that when analyzing each microinstruction, it is necessary to obtain the number of valid slots in the corresponding current first-type scheduling queue and second-type scheduling queue in real time for calculation, that is, to obtain the latest data after real-time updates.

[0104] If the first difference is not greater than the first preset threshold, the second difference is greater than the second preset threshold, and the third difference is greater than the third preset threshold, the imbalance type is determined to be the third type of imbalance, which is an imbalance that only occurs between PIPEs.

[0105] When a single microinstruction corresponds to a third type of imbalance, a third type of strategy invocation instruction is generated based on the third type of imbalance; the third type of strategy is invoked in response to the third type of strategy invocation instruction; and the dynamic allocation of the corresponding microinstruction is executed based on the third type of strategy.

[0106] In this embodiment, the third type of strategy refers to the PIPE-first allocation strategy (i.e., the PIPE priority allocation strategy).

[0107] Reference Figure 5 The method of "dynamic allocation of corresponding microinstructions based on the third type of strategy" includes: C100 determines the microinstruction to be allocated, denoted as the target microinstruction; C200 can obtain in real time the number of valid micro-instructions for the first sub-PIPE and the second sub-PIPE corresponding to the current first type of scheduling queue for the target micro-instruction, as well as the number of valid micro-instructions for the third sub-PIPE and the fourth sub-PIPE corresponding to the second type of scheduling queue. C300, if the target microinstruction is a multiplication type, obtain the scheduling queue corresponding to the smaller number of valid microinstructions in the first sub-PIPE and the third sub-PIPE, and denote it as the target queue; C400: If the target microinstruction is an addition type, obtain the scheduling queue corresponding to the smaller number of valid microinstructions in the second sub-PIPE and the fourth sub-PIPE, and denote it as the target queue. C500: If the target microinstruction is a multi-select microinstruction, the target microinstruction is assigned to the target queue; if the target microinstruction is a single-select microinstruction, it is entered into the multi-scheduling queue in sequence.

[0108] In this embodiment, the number of valid microinstructions for each sub-PIPE is obtained in real time in C200, providing an accurate basis for subsequent allocation. For multiplication microinstructions (C300) and addition microinstructions (C400), the scheduling queue with the smaller number of valid microinstructions in the corresponding sub-PIPE is selected as the target queue. This allows microinstructions to be allocated to queues with lighter loads, avoiding some queues being overloaded while others are idle, resulting in more balanced utilization of system resources and improving overall resource utilization. By allocating microinstructions to queues with lighter loads, the waiting time of microinstructions can be reduced. For example, multiplication microinstructions can be allocated to queues with lighter loads in the first or third sub-PIPE, and addition microinstructions can be allocated to queues with lighter loads in the second or fourth sub-PIPE, allowing microinstructions to be processed faster, thereby improving the overall performance and processing speed of the system.

[0109] Different allocation methods are employed for different types of microinstructions (multiplication, addition, multi-select, and single-select). Multi-select microinstructions are allocated to the target queue, while single-select microinstructions enter the multi-scheduling queue sequentially. This flexible allocation strategy better adapts to the characteristics and requirements of different microinstructions, making allocation more rational and efficient. The entire allocation process emphasizes real-time acquisition of the effective number of microinstructions for each sub-PIPE, enabling dynamic allocation based on the current system load. When system load changes, the allocation strategy can be adjusted promptly to ensure the system always operates at high efficiency.

[0110] If the first difference is greater than the first preset threshold, the second difference is greater than the second preset threshold, and the third difference is greater than the second preset threshold, the imbalance type is determined to be the fourth type of imbalance, which is an imbalance between SQ and PIPE occurring simultaneously.

[0111] When a single microinstruction corresponds to a type 4 imbalance, a type 4 strategy invocation instruction is generated based on the type 4 imbalance; the type 4 strategy is invoked in response to the type 4 strategy invocation instruction; and the dynamic allocation of the corresponding microinstruction is executed based on the type 4 strategy.

[0112] In this embodiment, the fourth type of strategy refers to the Diff-compare allocation strategy (i.e., the difference comparison allocation strategy).

[0113] Reference Figure 6 The method of "dynamic allocation of corresponding microinstructions based on the fourth type of strategy" includes: D100 determines the microinstruction to be allocated, denoted as the target microinstruction; D200, real-time acquisition of the maximum difference among the first, second, and third differences corresponding to the target micro-instruction; D300, if the maximum difference is the first difference, execute the dynamic allocation of the corresponding microinstruction based on the second type of strategy; If the maximum difference is the second or third difference, the corresponding microinstruction will be dynamically allocated based on the third type of strategy.

[0114] In this embodiment, the maximum difference among the first, second, and third differences is acquired in real time during step D200, and this difference is used to determine the main source of imbalance in the system. The first difference represents the difference in the number of effective slots between the two types of scheduling queues, reflecting the load imbalance at the queue level; the second and third differences reflect the difference in the number of effective micro-instructions at different sub-PIPEs, reflecting the load imbalance at the pipeline level; by identifying the maximum difference, the most prominent imbalance problem in the system can be accurately located; different allocation strategies are adopted in steps D300 and D400 according to the different situations of the maximum difference. If the maximum difference is the first difference, allocation based on the second strategy can focus on solving the load imbalance at the queue level; if the maximum difference is the second or third difference, allocation based on the third strategy can effectively handle the load imbalance at the pipeline (PIPE) level. This targeted allocation method makes the micro-instruction allocation more in line with the actual system situation and improves the rationality of resource allocation.

[0115] By accurately locating and resolving the main imbalances in the system, resource waste and idleness can be avoided. For example, when the imbalance at the queue level is severe, the second type of strategy can achieve a more rational allocation of resources in the scheduling queue; when the imbalance at the pipeline level is prominent, the third type of strategy can make fuller use of the processing capacity of sub-pipes, thereby improving the overall resource utilization of the system. Reasonable micro-instruction allocation can reduce the waiting time of micro-instructions in queues and sub-pipes, enabling micro-instructions to be processed faster, thereby reducing system processing latency and improving system response speed and overall performance. This method emphasizes real-time acquisition of the maximum difference and timely adjustment of the allocation strategy based on dynamic changes in the system. Regardless of changes in system load, selecting an appropriate allocation strategy can ensure efficient system operation, enhancing the system's adaptability to different workloads and changing conditions. By effectively resolving system imbalances, system performance degradation or even crashes caused by excessive local loads can be avoided, enabling the system to operate more stably and reducing the probability of failures.

[0116] Reference Figure 7In this embodiment, the Multi-Schedule Queue (MSQ) includes three types of scheduling queues: the first type of scheduling queue SQ0, the second type of scheduling queue SQ1, and the third type of scheduling queue StoreSQ. The first type of scheduling queue SQ0 corresponds to the execution of PIPE0 and PIPE1, the second type of scheduling queue SQ1 corresponds to the execution of PIPE2 and PIPE3, and the third type of scheduling queue StoreSQ corresponds to the execution of PIPE4 and PIPE5.

[0117] Each SQ corresponds to a different execution PIPE, meaning that different tasks, requests, or events need to be completed through different processing flows; each specific SQ has a matching, specially designed execution steps and operation sequence to ensure that the SQ can be processed correctly and efficiently.

[0118] The NSQ reads 6 micro-instructions and assigns them to the corresponding SQ at a time. Each SQ can write a maximum of 2 micro-instructions at a time. Micro-instruction types are mainly divided into several categories: addition micro-instructions are executed in PIPE1 or PIPE3, multiplication micro-instructions in PIPE0 or PIPE2, and store micro-instructions in PIPE4 or PIPE5. Micro-instructions destined for PIPE4 or PIPE5 cannot be executed simultaneously in PIPE0 through PIPE3; the allocation of multiple micro-instructions will be decided between SQ0 and SQ1.

[0119] In practical applications, it is usually necessary to consider the imbalance of SQ and PIPE to prevent an SQ or PIPE from becoming too crowded, which would block the allocation process from NSQ to SQ and cause performance degradation due to uneven allocation of execution units.

[0120] Due to physical constraints or design limitations of the data storage location for each microinstruction, some microinstructions can only access a specific PIPE, i.e., the SQ corresponding to that specific PIPE. The NSQ must be read and allocated to the SQ sequentially, and each SQ has a limited number of write ports. Therefore, the way the allocation device allocates microinstructions will affect the speed at which they enter the SQ at certain times. For example, among the six microinstructions read from the NSQ, the possible SQs are: Microinstruction 0: StoreSQ, Microinstruction 1: SQ0; Microinstruction 2: SQ0, Microinstruction 3: SQ0 or SQ1, Microinstruction 4: SQ0 or SQ1, Microinstruction 5: StoreSQ, where Microinstruction 0 is the oldest microinstruction, simply referred to as the sequence [St, 0, 0, 0 / 1, 0 / 1, St].

[0121] If a conventional allocation device (i.e., the method disclosed in the prior art) is used to allocate microinstructions, under the condition that there is no imbalance in SQ or PIPE, allocation is generally carried out in a round-robin manner. Multi-select microinstructions may be allocated as [St, 0, 0, 1, 0, St] or [St, 0, 0, 0, 1, St]. Due to the two read ports of each SQ, only a total of 4 or 3 microinstructions can be allocated to MSQ at one time.

[0122] The method disclosed in this application can be used to allocate a sequence as [St, 0, 0, 1, 1, St], which can be allocated to a total of 6 microinstructions in the MSQ, significantly increasing throughput. This effectively solves the problem that the SQ-first or PIPE-first allocation strategy cannot achieve optimal throughput because each microinstruction can only go to a specific SQ.

[0123] In this context, "PIPE" usually refers to a pipe. In the field of computer science, a pipe is a data transmission mechanism that allows the output of one program to be used as the input of another program, thus connecting different processing steps. Executing a PIPE can be understood as a series of processing steps or operation flows executed in a specific order.

[0124] Furthermore, the method disclosed in this application can be used not only for multiple selections of SQ0 / SQ1, but also for more SQs, using the idea of ​​allocating as much as possible (for example, the difference in the number of effective micro-instructions between three SQs can be compared simultaneously for selection). The purpose is to solve the problem that the SQ-first or PIPE-first allocation strategy cannot achieve the optimal throughput because each micro-instruction can only go to a specific SQ. All of these are within the protection scope of this application.

[0125] Secondly, this application discloses an allocation system from a non-selectable scheduling queue to multiple scheduling queues, for executing the allocation method from a non-selectable scheduling queue to multiple scheduling queues disclosed in the first aspect of this application. The system includes: The read module is used to obtain all microinstruction information read from the currently unselectable scheduling queue; The slot dimension acquisition module is used to obtain the number of valid slots and the number of idle slots in the current first type of scheduling queue and the second type of scheduling queue, and to obtain the difference between the number of valid slots in the two types of queues, which is denoted as the first difference. The effective microinstruction count acquisition module is used to acquire the effective microinstruction counts of the first sub-PIPE and the second sub-PIPE corresponding to the first type of scheduling queue, as well as the effective microinstruction counts of the third sub-PIPE and the fourth sub-PIPE corresponding to the second type of scheduling queue; wherein the first sub-PIPE and the third sub-PIPE constitute the first type of PIPE, and the second sub-PIPE and the fourth sub-PIPE constitute the second type of PIPE. The PIPE dimension information acquisition module is used to obtain the difference in the number of effective micro-instructions between the first sub-PIPE and the third sub-PIPE, and the difference in the number of effective micro-instructions between the second sub-PIPE and the fourth sub-PIPE, and record them as the second difference and the third difference respectively. The imbalance type determination module is used to determine the imbalance type based on the number of idle slots, the first difference, the second difference, and the third difference. The dynamic allocation module is used to dynamically allocate each microinstruction in the microinstruction information by calling the corresponding allocation strategy according to the imbalance type.

[0126] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0127] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the allocation method from a non-selectable scheduling queue to a multiple scheduling queue described in the foregoing embodiments of this disclosure.

[0128] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0129] like Figure 8 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 8The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0130] like Figure 8 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0131] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 8 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0132] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from ROM. When the computer program is executed by a processor, all or part of the steps of the allocation method from a non-selectable scheduling queue to a multiple scheduling queue according to embodiments of this disclosure are performed.

[0133] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0134] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When these non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the allocation method from a non-selectable scheduling queue to multiple scheduling queues described in the foregoing embodiments of the present disclosure are performed.

[0135] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0136] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0137] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0138] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0139] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0140] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0141] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0142] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0143] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method of allocating from a non-selectable dispatch queue to a multiple dispatch queue, characterized by, The method comprises: acquiring all microinstruction information read out by a current non-selectable scheduling queue; acquiring the number of effective slots and the number of idle slots in a first type of scheduling queue and a second type of scheduling queue, and obtaining a first difference value of the number of effective slots in the two types of queues; acquiring the number of effective microinstructions in a first sub-PIPE corresponding to the first type of scheduling queue, the number of effective microinstructions in a second sub-PIPE, the number of effective microinstructions in a third sub-PIPE corresponding to the second type of scheduling queue, and the number of effective microinstructions in a fourth sub-PIPE; obtaining a second difference value of the number of effective microinstructions in the first sub-PIPE and the third sub-PIPE, and a third difference value of the number of effective microinstructions in the second sub-PIPE and the fourth sub-PIPE; determining an imbalance type according to the number of idle slots, the first difference value, the second difference value, and the third difference value, and performing dynamic allocation of each microinstruction in the microinstruction information according to a corresponding allocation strategy of the imbalance type.

2. The method of claim 1, wherein, The determination of the imbalance type according to the number of idle slots, the first difference value, the second difference value, and the third difference value comprises: determining the balance condition and the load state of the queue according to the first difference value and the number of idle slots; determining the queue PIPE difference state according to the second difference value and the third difference value; determining the imbalance type according to the balance condition and the load state of the queue and the queue PIPE difference state.

3. The method of claim 2, wherein, The determination of the imbalance type according to the number of idle slots, the first difference value, the second difference value, and the third difference value, and the performance of dynamic allocation of each microinstruction in the microinstruction information according to a corresponding allocation strategy of the imbalance type comprises: if the proportion of the number of idle slots in the corresponding calling queue is greater than a preset proportion threshold, or the first difference value is not greater than a first preset threshold, the second difference value is not greater than a second preset threshold, and the third difference value is not greater than a third preset threshold, determining that the imbalance type is a first type of imbalance, and performing a first type of strategy according to the first type of imbalance; if the first difference value is greater than the first preset threshold, the second difference value is not greater than the second preset threshold, and the third difference value is not greater than the third preset threshold, determining that the imbalance type is a second type of imbalance, and performing a second type of strategy according to the second type of imbalance; if the first difference value is not greater than the first preset threshold, the second difference value is greater than the second preset threshold, and the third difference value is greater than the third preset threshold, determining that the imbalance type is a third type of imbalance, and performing a third type of strategy according to the third type of imbalance; if the first difference value is greater than the first preset threshold and the second difference value is greater than the second preset threshold, or the first difference value is greater than the first preset threshold and the third difference value is greater than the second preset threshold, determining that the imbalance type is a fourth type of imbalance, and performing a fourth type of strategy according to the fourth type of imbalance.

4. The method of claim 3, wherein, The performance of the first type of strategy according to the first type of imbalance comprises: A target queue list is configured according to a PIPE corresponding to the microinstruction information, the target queue list comprising a plurality of sub-elements, each of the sub-elements being a target scheduling queue of a single microinstruction, wherein the order of all the sub-elements is consistent with the order of the microinstructions in the microinstruction information; A position initial table corresponding to the target queue list is obtained according to all the target scheduling queues, each position in the position initial table corresponding to a rule value; A position multiple selection number table is determined according to the position initial table, each position in the position multiple selection number table corresponding to a multiple selection number; When the rule value is a first value, the corresponding multiple selection number is 0; When the rule value is a second value, the multiple selection number of the ith position = the rule value of the ith position + the sum of all the rule values of the previous i-1 positions; The dynamic allocation strategy of each microinstruction is determined and executed according to the position multiple selection number table and the target queue list.

5. The method of claim 4, wherein, The dynamic allocation strategy of each microinstruction is determined and executed according to the position multiple selection number table and the target queue list, comprising: if the target queue list satisfies a first type of condition, a first sub-strategy is called to execute the dynamic allocation of the corresponding single microinstruction; The dynamic allocation strategy of each microinstruction is determined and executed according to the position multiple selection number table and the target queue list, comprising: if the target queue list satisfies a second type of condition, a second sub-strategy is called to execute the dynamic allocation of the corresponding single microinstruction; The first type of condition is satisfied when the total number of third type scheduling queues existing in the first four sub-elements in the target queue list is 0, 3 or 4, the total number of single-selected first type scheduling queues in the first four sub-elements in the target queue list is obtained, and the total number of single-selected second type scheduling queues in the first four sub-elements in the target queue list is obtained, and the total number of single-selected first type scheduling queues is recorded as a first type of single selection number, and the total number of single-selected second type scheduling queues is recorded as a second type of single selection number; The maximum multiple selection number in the first five multiple selection numbers in the position multiple selection number table is obtained, and the dynamic allocation of the corresponding single microinstruction is executed according to the number of the maximum multiple selection number and the first type of single selection number and the second type of single selection number. The second type of condition is satisfied when the first five sub-elements in the target queue list are obtained, only one Store SQ exists in the first four sub-elements, and the fifth sub-element is not a Store SQ, the total number of single-selected first type scheduling queues in the first five sub-elements is obtained, the total number of single-selected second type scheduling queues in the first five sub-elements is obtained, and the total number of single-selected first type scheduling queues is recorded as a first type of single selection number, and the total number of single-selected second type scheduling queues is recorded as a second type of single selection number. The maximum multiple selection number in the first five multiple selection numbers in the position multiple selection number table is obtained, and the dynamic allocation of the corresponding single microinstruction is executed according to the number of the maximum multiple selection number and the first type of single selection number and the second type of single selection number.

6. The method of claim 4, wherein, ​ ​ ​ ​ ​ 7. The method of claim 4, wherein, The dynamic allocation strategy of each micro instruction is determined according to the position multi-selection number table and the target queue list, and the dynamic allocation strategy is executed, and the method comprises the following steps of: if the target queue list meets a third type condition, a third sub-strategy is called to execute the dynamic allocation of a corresponding single micro instruction. The dynamic allocation strategy of each micro instruction is determined according to the position multi-selection number table and the target queue list, and the dynamic allocation strategy is executed, and the method comprises the following steps of: if the target queue list meets a third type condition, a third sub-strategy is called to execute the dynamic allocation of a corresponding single micro instruction. The maximum multi-selection number in the first six multi-selection numbers in the position multi-selection number table is obtained, and the dynamic allocation of the corresponding single micro instruction is executed according to the number of the maximum multi-selection number and the first type single selection number and the second type single selection number by calling the corresponding third sub-strategy. The dynamic allocation strategy of each micro instruction is determined according to the position multi-selection number table and the target queue list, and the dynamic allocation strategy is executed, and the method comprises the following steps of: if the target queue list meets a third type condition, a third sub-strategy is called to execute the dynamic allocation of a corresponding single micro instruction. The dynamic allocation strategy of each micro instruction is determined according to the position multi-selection number table and the target queue list, and the dynamic allocation strategy is executed, and the method comprises the following steps of: if the target queue list meets a third type condition, a third sub-strategy is called to execute the dynamic allocation of a corresponding single micro instruction.

8. The method of claim 3, wherein, A target queue list is configured according to the corresponding PIPE of the micro instruction information, the target queue list comprises a plurality of sub-elements, each of the sub-elements is a target scheduling queue of a single micro instruction, and the order of all the sub-elements is consistent with the order of the micro instructions in the micro instruction information. A type initial table corresponding to the target queue list is obtained according to all the target scheduling queues, each position in the type initial table corresponds to a type of a schedulable queue, and each type is any one of a store SQ, an SQ0, an SQ1, an SQ0 / 1 and a null. A position multi-selection number table, a store number table, a first type target queue number table, a second type target queue number table and a multi-selection cumulative table are determined according to the type initial table. A first target position meeting a preset allocation position condition is found from a second position in the target queue list according to the multi-selection cumulative table, the first type target queue number table, the second type target queue number table and the store number table, a position before the target position is set as an end of a to-be-allocated position. If there is no position meeting the preset allocation position condition, a position of a last micro instruction is set as the end of the to-be-allocated position. A dynamic allocation strategy of each micro instruction is determined according to the type initial table, the end of the to-be-allocated position and the target queue list, and the dynamic allocation strategy is executed. The first target position meeting the preset allocation position condition is found from the second position in the target queue list according to the multi-selection cumulative table, the first type target queue number table, the second type target queue number table and the store number table, and a position before the target position is set as the end of the to-be-allocated position.

9. The method of claim 8, wherein, Information of a position corresponding to each micro instruction is determined according to the multi-selection cumulative table, the first type target queue number table and the second type target queue number table, the information comprising a total number of micro instructions written in a non-Store type SQ one-time allocation, a store number, a first type target queue number and a second type target queue number. ​ If the information of all micro-instruction corresponding positions satisfies at least two of the first condition, the second condition, the third condition, and the fourth condition, the position one place before the most front position in the target positions satisfying the at least two conditions is set as the to-be-allocated position end point; If the information of all micro-instruction corresponding positions satisfies any one of the first condition, the second condition, the third condition, and the fourth condition, the first target position satisfying the preset allocation position condition from the second position in the target queue list is determined, and the position one place before the target position is set as the to-be-allocated position end point; If none of the first condition, the second condition, the third condition, and the fourth condition is satisfied, the position of the last micro-instruction is set as the to-be-allocated position end point; The first condition is that the total number of micro-instructions written in the non-Store SQ one-time allocation of a single micro-instruction corresponding position is greater than 2n, and n is the maximum number of micro-instructions that can be written in each scheduling queue at a time; The second condition is that the Store number of a single micro-instruction corresponding position is greater than n; The third condition is that the number of first-type target queues of a single micro-instruction corresponding position is greater than n; The fourth condition is that the number of second-type target queues of a single micro-instruction corresponding position is greater than n.

10. The method of claim 9, wherein, The determining of the dynamic allocation strategy of each micro-instruction according to the type initial table, the to-be-allocated position end point, and the target queue list and the execution thereof include: All micro-instructions corresponding to the to-be-allocated position end point and the positions before the to-be-allocated position end point in the target queue list are intercepted to obtain a to-be-allocated target queue; A target initial table corresponding to the to-be-allocated target queue is obtained according to the type initial table, and a target multiple number table corresponding to the to-be-allocated target queue is obtained according to the position multiple number table; The total number of single-selected first-type scheduling queues in the target initial table is obtained, and is recorded as a first-type single selection number; The micro-instructions with all multiple numbers being 0 in the target multiple number table are entered into a multi-scheduling queue allocation according to the order in the target queue list; The micro-instructions with multiple numbers not greater than (n-first-type single selection number) in the target multiple number table are allocated to the first-type scheduling queue; The remaining micro-instructions in the to-be-allocated target queue are allocated to the second-type scheduling queue.

11. The method of claim 3, wherein, The execution of the second-type strategy according to the second-type imbalance includes: A to-be-allocated micro-instruction is determined and is recorded as a target micro-instruction; A queue corresponding to the smaller effective slot number in the current first-type scheduling queue and the second-type scheduling queue corresponding to the target micro-instruction is obtained in real time, and is recorded as a target queue; If the target micro-instruction is a multiple selection micro-instruction, the target micro-instruction is allocated to the target queue; If the target micro-instruction is a single selection micro-instruction, the target micro-instruction is entered into a multi-scheduling queue according to the order.

12. The method of claim 3, wherein, The execution of the third-type strategy according to the third-type imbalance includes: A to-be-allocated micro-instruction is determined and is recorded as a target micro-instruction; acquire, in real time, the number of valid microinstructions of the first sub-PIPE corresponding to the current first-type scheduling queue of the target microinstruction, the number of valid microinstructions of the second sub-PIPE, the number of valid microinstructions of the third sub-PIPE corresponding to the second-type scheduling queue, and the number of valid microinstructions of the fourth sub-PIPE; if the target microinstruction is a multiplication type, acquire the scheduling queue corresponding to the smaller number of valid microinstructions in the first sub-PIPE and the third sub-PIPE, and record the scheduling queue as a target queue; if the target microinstruction is an addition type, acquire the scheduling queue corresponding to the smaller number of valid microinstructions in the second sub-PIPE and the fourth sub-PIPE, and record the scheduling queue as a target queue; if the target microinstruction is a multiple selection microinstruction, allocate the target microinstruction to the target queue; if the target microinstruction is a single selection microinstruction, sequentially enter a plurality of scheduling queues.

13. The method of claim 3, wherein, The fourth-type strategy is executed according to the fourth-type imbalance, including: determining a microinstruction to be allocated, recorded as a target microinstruction; acquiring, in real time, the maximum difference value among the first difference value, the second difference value, and the third difference value corresponding to the target microinstruction; if the maximum difference value is the first difference value, performing dynamic allocation of the corresponding microinstruction based on a second-type strategy; if the maximum difference value is the second difference value or the third difference value, performing dynamic allocation of the corresponding microinstruction based on a third-type strategy.

14. A computer apparatus, comprising: The computer device includes: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the allocation method from the non-selectable scheduling queue to the multiple scheduling queue according to any one of claims 1-13.

15. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for causing a computer to perform the allocation method from the non-selectable scheduling queue to the multiple scheduling queue according to any one of claims 1-13.

16. A computer program product comprising computer instructions, characterized in that, The computer instructions, when executed by a processor, implement the steps of the method according to any one of claims 1-13.

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