Interrupt sending control method, hardware interrupt controller and virtual machine system

Abstract

The invention provides an interrupt sending control method, a hardware interrupt controller and a virtual machine system. The method is applied to the hardware interrupt controller provided with a local specific peripheral interrupt controller, a virtual local specific peripheral interrupt controller and an interrupt management controller. The method comprises the following steps: when a local specific peripheral interrupt controller and a virtual local specific peripheral interrupt controller simultaneously request to send interrupt to a target processor core, and a target storage space corresponding to the target processor core does not have an idle storage space; if the lowest priority interrupt in the target storage space is the local specific peripheral interrupt, the interrupt management controller sends the highest priority information to a virtual local specific peripheral interrupt controller; and if the lowest priority interrupt stored in the target storage space is the virtual local specific peripheral interrupt, the interrupt management controller sends the highest priority information to a local specific peripheral interrupt controller. The method can reduce the power consumption waste of transmission interruption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computers, and in particular to an interrupt sending control method, a hardware interrupt controller and a virtual machine system. BACKGROUND

[0002] In a PICD (Phytium Interrupt Controller Distributor) of a hardware interrupt controller of a virtual machine system, a local-specific peripheral interrupt controller, a virtual local-specific peripheral interrupt controller and an interrupt management controller are arranged. The local-specific peripheral interrupt controller is used to control sending of a LPI (Locality-specific Peripheral Interrupt); the virtual local-specific peripheral interrupt controller is used to control sending of a VLPI (Virtul Locality-specific Peripheral Interrupt); and the interrupt management controller is internally arranged with a storage space corresponding to each processor core, and is used to store an interrupt sent to the corresponding processor core.

[0003] When the local-specific peripheral interrupt controller needs to send a LPI interrupt or the virtual local-specific peripheral interrupt controller needs to send a VLPI interrupt, an interrupt request signal needs to be first sent to the interrupt management controller, and the target processor core receiving the interrupt is carried in the interrupt request signal. When the interrupt management controller receives the interrupt request signal sent by the local-specific peripheral interrupt controller or the virtual local-specific peripheral interrupt controller, the occupation of the target storage space corresponding to the target processor core carried in the interrupt request signal and the lowest priority information of the stored interrupt are queried, and the occupation of the target storage space and the lowest priority information are fed back to the local-specific peripheral interrupt controller or the virtual local-specific peripheral interrupt controller. If the target storage space has free storage space, the local-specific peripheral interrupt controller or the virtual local-specific peripheral interrupt controller determines that the interrupt can be sent to the interrupt management controller. Alternatively, the target storage space has no free storage space, but the priority of the interrupt to be sent is higher than the lowest priority of the interrupt stored in the target storage space, and the type of the interrupt to be sent is the same as the type of the lowest priority interrupt stored in the target storage space, then the local-specific peripheral interrupt controller or the virtual local-specific peripheral interrupt controller also determines that the interrupt can be sent to the interrupt management controller, and at this time, the newly sent interrupt will replace the same type of lowest priority interrupt stored in the target storage space.

[0004] However, when the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the same target processor core, and the storage space corresponding to the target processor core has no free storage space, according to the above processing mechanism, only the interrupt of the same type as the lowest priority interrupt stored in the storage space corresponding to the target processor core can be successfully sent, and the interrupt sent by the other cannot be received by the interrupt management controller, thereby causing waste of interrupt sending power consumption. SUMMARY

[0005] Based on the above technical problems, the present application provides an interrupt sending control method, a hardware interrupt controller and a virtual machine system, which can reduce the waste of interrupt sending power consumption when the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the same target processor core, and the storage space corresponding to the target processor core has no free storage space.

[0006] The first aspect of the present application provides an interrupt sending control method applied to a hardware interrupt controller of a virtual machine system, wherein a local specific peripheral interrupt controller, a virtual local specific peripheral interrupt controller and an interrupt management controller are arranged in an interrupt controller distributor of the hardware interrupt controller; the interrupt management controller is arranged with a storage space corresponding to each processor core, for storing an interrupt sent to the corresponding processor core. The method comprises: When the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to a target processor core, and the target storage space corresponding to the target processor core has no free storage space, the interrupt management controller determines the type of the lowest priority interrupt stored in the target storage space. When the lowest priority interrupt stored in the target storage space is a local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the virtual local specific peripheral interrupt controller to the highest priority, and sets the priority information sent to the local specific peripheral interrupt controller to the priority of the lowest priority interrupt stored in the target storage space. Alternatively, When the lowest priority interrupt stored in the target storage space is a virtual local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the local specific peripheral interrupt controller to the highest priority, and sets the priority information sent to the virtual local specific peripheral interrupt controller to the priority of the lowest priority interrupt stored in the target storage space.

[0007] In some implementations, the method further comprises: The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller based on the received priority information.

[0008] In some implementations, the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller based on the received priority information, including: The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller compare the priority of the interrupt to be sent with the received priority information, respectively. When the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller determine that the priority of the interrupt to be sent is higher than the received priority information, they determine to send the interrupt to be sent to the interrupt management controller. or, If the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller determine that the priority of the interrupt to be sent is not higher than the priority information received, they will decide not to send the interrupt to be sent to the interrupt management controller.

[0009] In some implementations, the method further includes: The interrupt management controller sends the target storage space occupancy information to both the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller.

[0010] In some implementations, the occupancy information of the target storage space includes a status identifier of the target storage space; when the value of the status identifier is a first value, it indicates that the target storage space has free storage space, or when the value of the status identifier is a second value, it indicates that the target storage space has no free storage space.

[0011] In some implementations, the method further includes: The interrupt management controller receives a first interrupt request signal sent by the local specific peripheral interrupt controller and a second interrupt request signal sent by the virtual local specific peripheral interrupt controller; the interrupt request signal includes the identifier of the target processor core receiving the interrupt; If the first interrupt request signal and the second interrupt request signal include the same target processor core identifier, the interrupt management controller determines that the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core.

[0012] The second aspect of this application provides a hardware interrupt controller, wherein the interrupt controller dispatcher of the hardware interrupt controller is provided with a local specific peripheral interrupt controller, a virtual local specific peripheral interrupt controller, and an interrupt management controller; the interrupt management controller is provided with a storage space corresponding to each processor core for storing interrupts sent to the corresponding processor core; When both the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core, and the target memory space corresponding to the target processor core has no free memory space, the interrupt management controller determines the type of the lowest priority interrupt stored in the target memory space; If the lowest priority interrupt stored in the target storage space is a local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the virtual local specific peripheral interrupt controller to the highest priority, and sets the priority information sent to the local specific peripheral interrupt controller to the priority of the lowest priority interrupt stored in the target storage space. or, If the lowest priority interrupt stored in the target storage space is a virtual local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the local specific peripheral interrupt controller to the highest priority, and sets the priority information sent to the virtual local specific peripheral interrupt controller to the priority of the lowest priority interrupt stored in the target storage space.

[0013] In some implementations, the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller based on the received priority information.

[0014] In some implementations, the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller based on the received priority information, including: The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller compare the priority of the interrupt to be sent with the received priority information, respectively. When the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller determine that the priority of the interrupt to be sent is higher than the received priority information, they determine to send the interrupt to be sent to the interrupt management controller. or, If the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller determine that the priority of the interrupt to be sent is not higher than the priority information received, they will decide not to send the interrupt to be sent to the interrupt management controller.

[0015] A third aspect of this application provides a virtual machine system including the aforementioned hardware interrupt controller.

[0016] In the interrupt transmission control scheme provided in this application, when both the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core, and the target memory space corresponding to the target processor core has no free memory space, the interrupt management controller further determines the type of the lowest priority interrupt stored in the target memory space. If the lowest priority interrupt stored in the target memory space is a local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the virtual local specific peripheral interrupt controller to the highest priority; if the lowest priority interrupt stored in the target memory space is a virtual local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the local specific peripheral interrupt controller to the highest priority. This process ensures that when the interrupt to be transmitted by the local specific peripheral interrupt controller or the virtual local specific peripheral interrupt controller is of a different type than the lowest priority interrupt stored in the target memory space, the highest priority information is received. This allows the local specific peripheral interrupt controller or the virtual local specific peripheral interrupt controller to recognize that the priority of the interrupt to be transmitted is not higher than the priority of the lowest priority interrupt stored in the target memory space and cancel the transmission interrupt, thereby avoiding wasted power consumption due to the interrupt being unable to be received by the interrupt management controller. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a hardware interrupt controller provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the instruction translation process of the instruction translation service module provided in this application embodiment.

[0020] Figure 3 This is a schematic diagram of the internal structure and interrupt sending process of the interrupt controller dispatcher provided in the embodiments of this application.

[0021] Figure 4 This is a flowchart illustrating the interrupt transmission control method provided in an embodiment of this application. Detailed Implementation

[0022] In virtual machine systems, the traditional method of injecting Virtual Locality-specific Peripheral Interrupt (VLPI) into a vPE (Virtual Processing Element) requires the following five steps: (1) The hardware interrupt controller sends a physical interrupt to the physical CPU interface.

[0023] (2) A physical interrupt is received.

[0024] (3) The Hypervisor sends interrupts to the running vPE.

[0025] (4) Hypervisor writes to registers to send a VLPI interrupt.

[0026] (5) The VLPI interrupt is received and reaches vPE.

[0027] In the above process, the involvement of the hypervisor is called a trap, requiring the software to perform a significant amount of work to save the current state, which greatly consumes system time. VLPI interrupt direct injection avoids trapping the hypervisor, directly injecting virtual interrupts into the virtual CPU interface, thus greatly improving system efficiency. VLPI interrupt direct injection only requires the following two steps: (1) The interrupt controller sends a VLPI interrupt to the virtual CPU interface.

[0028] (2) The VLPI interrupt is received by the vPE.

[0029] Figure 1 The internal structure of the hardware interrupt controller is shown.

[0030] See Figure 1 As shown, the hardware interrupt controller includes an Interrupt Translation Service (ITS) module, an Interrupt Controller Distributor (PICD), and a Redistributor (RD).

[0031] The main function of ITS is to receive the device ID and event ID sent by the device, and translate the device ID and event ID into LPI interrupt (Locality-specific Peripheral Interrupt) or VLPI interrupt by looking up three interrupt translation tables.

[0032] like Figure 2 As shown, there are three interrupt translation tables: Device table, InterruptTranslation Table (ITT table, or instruction translation table), and vPE table (virtual processing unit table). DeviceTable uses deviceID for addressing and stores the entry address of the ITT table; the ITT table stores vPEID (virtual processing unit ID) and INTID (interrupt number); vPE table uses vPEID as the address and stores the entry address (vpt_addr) of the VLPI pending table and the interrupt target core number (RDbase).

[0033] The entry address of the Device table is stored in the GITS_BASER0 register, and the entry address of the vPE table is stored in the GITS_BASER2 register.

[0034] The following is a basic VLPI interrupt translation process: The interrupt source device sends its DeviceID and EventID to the ITS. The Device table uses GITS_BASER0 + DeviceID as the address to read the Device table and obtain the entry address of the ITT table. Then, it uses the ITT table entry address + EventID to obtain vPEID and INTID. Finally, it uses GITS_BASER2 + vPEID as the address to read the vPE table and obtain vpt_addr and RDbase.

[0035] Ultimately, the VLPI interrupt carries the following information: interrupt number INTID, the pending table entry address of the target vPE (vpt_addr), and the target core number (RDbase).

[0036] The PICD is the core component of the hardware interrupt controller, which controls and distributes LPI and VLPI interrupts. The RD receives interrupt information sent by the PICD and sends LPI interrupts to the physical CPU interface and VLPI interrupts to the virtual CPU interface.

[0037] Figure 3 A schematic diagram of the internal structure of the interrupt controller dispatcher (PICD) is shown.

[0038] See Figure 3 As shown, the PICD contains a local specific peripheral interrupt controller lpi_ctrl, a virtual local specific peripheral interrupt controller vlpi_ctrl, an interrupt management controller dest_ctrl, and an arbitration routing module dest_switch.

[0039] Among them, the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl are modules used to control and process LPI interrupts and VLPI interrupts, respectively. The arbitration routing module dest_switch is a module based on the Roundrobin arbitrator. When LPI interrupts and VLPI interrupts arrive at dest_switch at the same time, it will poll to select one of them and send it to the dest_ctrl module.

[0040] The interrupt management controller dest_ctrl is an internal module of PICD that interacts with RD. It receives interrupts sent by the lpi_ctrl and vlpi_ctrl modules, maintains a state machine to control the state of each interrupt, and interacts with RD.

[0041] The interrupt management controller, dest_ctrl, contains dedicated memory spaces for each processor core to store interrupts sent to that core. For example, dest_ctrl has five slots built into each processor core, which can store LPI and VLPI interrupts destined for that core.

[0042] See also Figure 3 As shown, when the local specific peripheral interrupt controller lpi_ctrl needs to send an LPI interrupt or the virtual local peripheral interrupt controller vlpi_ctrl needs to send a VLPI interrupt, it needs to first send an interrupt request signal to the interrupt management controller dest_ctrl. This interrupt request signal includes... Figure 3 In the interrupt request signal, ①valid and ②tgt carry the identifier of the target processor core receiving the interrupt, which is ②tgt. This interrupt request signal indicates that it wants to obtain two pieces of information about the memory slot corresponding to the processor core number of tgt. Figure 3The diagram shows ③space information and ④priority information. ③space information indicates the memory space occupancy of the processor core corresponding to tgt, i.e., whether there are empty slots in the slot; ④priority information indicates the priority information of the lowest priority interrupt among all interrupts stored in the memory space of the processor core corresponding to tgt.

[0043] When the interrupt management controller dest_ctrl receives interrupt request signals (signals ① and ②) sent by the local specific peripheral interrupt controller lpi_ctrl or the virtual local specific peripheral interrupt controller vlpi_ctrl, it queries the target memory space occupancy status and the lowest priority information of the stored interrupt corresponding to the target processor core carried in the interrupt request signal, and feeds back the target memory space occupancy status and the lowest priority information to the local specific peripheral interrupt controller lpi_ctrl or the virtual local specific peripheral interrupt controller vlpi_ctrl through signals ③ and ④.

[0044] If there is free storage space in the target storage space, the local specific peripheral interrupt controller lpi_ctrl or the virtual local specific peripheral interrupt controller vlpi_ctrl determines that an interrupt can be sent to the interrupt management controller dest_ctrl.

[0045] Meanwhile, the interrupt management controller dest_ctrl has a rejection mechanism. That is, when the memory space of a processor core in the interrupt management controller dest_ctrl is full, if a new interrupt is received for that processor core, the interrupt management controller dest_ctrl will compare the priority of the new interrupt with the priority of the lowest priority interrupt stored in the memory space of that processor core. If the priority of the new interrupt is higher than the priority of the stored lowest priority interrupt, and the type of the new interrupt (such as LPI interrupt or VLPI interrupt) is the same as the type of the stored lowest priority interrupt, then the interrupt management controller dest_ctrl will accept the new interrupt, replace the lowest priority interrupt stored in the memory space of that processor core with the new interrupt, and reject the lowest priority interrupt back to the controller that sent the lowest priority interrupt.

[0046] When the memory space of a processor core in the interrupt management controller dest_ctrl is full, if a new interrupt is received destined for that processor core, and the priority of the new interrupt is not higher than the priority of the lowest priority interrupt stored in the memory space of that processor core, or although the priority of the new interrupt is higher than the priority of the lowest priority interrupt stored in the memory space of that processor core, the type of the new interrupt is different from the type of the lowest priority interrupt stored in the memory space of that processor core, then the interrupt management controller dest_ctrl will return the new interrupt to the controller that sent the new interrupt.

[0047] However, when the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl simultaneously request to send an interrupt to the same target processor core, and the memory space corresponding to the target processor core has no free memory space, according to the above-mentioned fallback mechanism, since the lowest priority interrupt stored in the memory space corresponding to the target processor core is either an LPI interrupt or a VLPI interrupt, in this case, only the interrupt sent that is of the same type as the lowest priority interrupt stored in the memory space corresponding to the target processor core can be successfully sent. The interrupt sent by the other party cannot be received by the interrupt management controller, thus causing wasted power consumption for sending interrupts.

[0048] To address the aforementioned technical problems and avoid the power consumption waste caused by the transmission interrupt in the PICD, this application provides an interrupt transmission control method that can be executed in the interrupt controller dispatcher (PICD) of the hardware interrupt controller.

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] This embodiment first provides an interrupt transmission control method, see [link to previous section]. Figure 4 As shown, the method includes: S101, when the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core, and the target memory space corresponding to the target processor core has no free memory space, the interrupt management controller determines the type of the lowest priority interrupt stored in the target memory space.

[0051] For details, see Figure 3As shown, when the interrupt management controller dest_ctrl receives interrupt request signals (including signal ① and signal ②) from both the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl, it first determines whether the interrupt request signal is a request to send an interrupt to the same target processor core.

[0052] For example, the interrupt management controller dest_ctrl receives a first interrupt request signal sent by the local specific peripheral interrupt controller lpi_ctrl and a second interrupt request signal sent by the virtual local specific peripheral interrupt controller vlpi_ctrl. The tgt signal of the first interrupt request signal and the second interrupt request signal respectively carry the identifier of the target processor core receiving the interrupt, such as carrying the ID of the target processor core.

[0053] The interrupt management controller dest_ctrl compares the target processor core identifier carried in the first interrupt request signal and the second interrupt request signal. If the first interrupt request signal and the second interrupt request signal carry the same target processor core identifier, the interrupt management controller dest_ctrl can determine that the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl simultaneously request to send an interrupt to the target processor core.

[0054] When the interrupt management controller dest_ctrl determines that both the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl request to send an interrupt to the target processor core, the interrupt management controller dest_ctrl checks whether there is free storage space in the target memory space corresponding to the target processor core, which is used to store interrupts sent to the target processor core. For example, it checks whether there is a free slot in the target memory space.

[0055] If the target storage space has free storage space and the free storage space is sufficient to store 2 interrupts, the interrupt management controller dest_ctrl can send response information allowing interrupts to be sent to the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl, respectively, so that the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl can send interrupts respectively.

[0056] If the target storage space has free storage space but the free storage space can only store 1 interrupt, the interrupt management controller dest_ctrl can choose either the local specific peripheral interrupt controller lpi_ctrl or the virtual local specific peripheral interrupt controller vlpi_ctrl to allow interrupts to be sent, or only allow interrupts with higher priority to be sent.

[0057] If there is no free storage space in the target storage space, the interrupt management controller dest_ctrl further detects whether the type of the lowest priority interrupt stored in the target storage space is an LPI interrupt or a VLPI interrupt.

[0058] S102. If the lowest priority interrupt stored in the target storage space is a local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the virtual local specific peripheral interrupt controller to the highest priority, and sets the priority information sent to the local specific peripheral interrupt controller to the priority of the lowest priority interrupt stored in the target storage space.

[0059] Specifically, if the lowest priority interrupt stored in the target memory space corresponding to the target processor core is an LPI interrupt, then according to the rejection mechanism of the interrupt management controller dest_ctrl, when a new interrupt sent to the target processor core is an LPI interrupt and the priority of the new interrupt is higher than that of the lowest priority LPI interrupt, the interrupt management controller dest_ctrl can accept the new LPI interrupt and store it in the target memory space corresponding to the target processor core, while rejecting the lowest priority LPI interrupt stored in the target memory space. If the received new interrupt is a VLPI interrupt, the interrupt management controller dest_ctrl will reject the new VLPI interrupt.

[0060] As can be seen, if the lowest priority interrupt stored in the target memory space corresponding to the target processor core is an LPI interrupt, the interrupt management controller dest_ctrl may still receive new LPI interrupts, but it is impossible to receive new VLPI interrupts.

[0061] Therefore, in this embodiment, when the interrupt management controller dest_ctrl determines that the lowest priority interrupt stored in the target memory space corresponding to the target processor core is an LPI interrupt, the interrupt management controller sets the priority information sent to the virtual local specific peripheral interrupt controller vlpi_ctrl to the highest priority, and sets the priority information sent to the local specific peripheral interrupt controller lpi_ctrl to the priority of the lowest priority interrupt stored in the target memory space.

[0062] In other words, the interrupt management controller dest_ctrl sets the priority information sent to the virtual local specific peripheral interrupt controller vlpi_ctrl to the highest priority, for example, setting the value of the priority signal sent to the virtual local specific peripheral interrupt controller vlpi_ctrl to a value representing the highest priority; at the same time, it sets the priority information sent to the local specific peripheral interrupt controller lpi_ctrl to the priority of the lowest priority interrupt stored in the target memory space, that is, setting the value of the priority signal sent to the local specific peripheral interrupt controller lpi_ctrl to the priority of the lowest priority interrupt stored in the target memory space.

[0063] or, S103. If the lowest priority interrupt stored in the target storage space is a virtual local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the local specific peripheral interrupt controller to the highest priority, and sets the priority information sent to the virtual local specific peripheral interrupt controller to the priority of the lowest priority interrupt stored in the target storage space.

[0064] Specifically, if the lowest priority interrupt stored in the target memory space corresponding to the target processor core is a VLPI interrupt, then according to the rejection mechanism of the interrupt management controller dest_ctrl, when a new interrupt sent to the target processor core is a VLPI interrupt and the priority of the new interrupt is higher than that of the lowest priority VLPI interrupt, the interrupt management controller dest_ctrl can accept the new VLPI interrupt and store it in the target memory space corresponding to the target processor core, while rejecting the lowest priority VLPI interrupt stored in the target memory space. If the received new interrupt is an LPI interrupt, the interrupt management controller dest_ctrl will reject the new LPI interrupt.

[0065] It is evident that if the lowest priority interrupt stored in the target memory space corresponding to the target processor core is a VLPI interrupt, the interrupt management controller dest_ctrl may still receive new VLPI interrupts, but it is impossible to receive new LPI interrupts.

[0066] Therefore, in this embodiment, when the interrupt management controller dest_ctrl determines that the lowest priority interrupt stored in the target memory space corresponding to the target processor core is a VLPI interrupt, the interrupt management controller sets the priority information sent to the local specific peripheral interrupt controller lpi_ctrl to the highest priority, and sets the priority information sent to the virtual local specific peripheral interrupt controller vlpi_ctrl to the priority of the lowest priority interrupt stored in the target memory space.

[0067] In other words, the interrupt management controller dest_ctrl sets the priority information sent to the local specific peripheral interrupt controller lpi_ctrl to the highest priority, for example, setting the value of the priority signal sent to the local specific peripheral interrupt controller lpi_ctrl to a value representing the highest priority; at the same time, it sets the priority information sent to the virtual local specific peripheral interrupt controller vlpi_ctrl to the priority of the lowest priority interrupt stored in the target memory space, that is, setting the value of the priority signal sent to the virtual local specific peripheral interrupt controller vlpi_ctrl to the priority of the lowest priority interrupt stored in the target memory space.

[0068] Based on the above settings, the interrupt management controller dest_ctrl sends the target memory space occupancy information and priority information to the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl, respectively.

[0069] The interrupt management controller dest_ctrl sends the same occupancy information to both the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl, indicating that there is no free storage space in the target memory. However, the priority information sent by the interrupt management controller dest_ctrl to both the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl differs as described above.

[0070] In another embodiment, the interrupt management controller dest_ctrl sends target memory space occupancy information to the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl, which is represented by a target memory space status flag. A first value for the status flag indicates that the target memory space has free memory space, and a second value indicates that the target memory space has no free memory space.

[0071] For example, through Figure 3The space value is used to represent the occupancy information of the target storage space. When the space value is 1, it means that there is free storage space in the target storage space. When the space value is 0, it means that there is free storage space in the target storage space.

[0072] In another embodiment, it is disclosed that when the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl each receive priority information sent by the interrupt management controller dest_ctrl, the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl determine whether to send an interrupt to the interrupt management controller dest_ctrl according to the received priority information.

[0073] Specifically, when the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl each receive the priority information sent by the interrupt management controller dest_ctrl, they each perform the following operations: The priority of the interrupt to be sent is compared with the priority information received.

[0074] If the priority of the interrupt to be sent is higher than the priority information received, then it is determined that the interrupt to be sent can be sent to the interrupt management controller dest_ctrl.

[0075] If the priority of the interrupt to be sent is not higher than the priority information received, then it is determined not to send the interrupt to be sent to the interrupt management controller dest_ctrl.

[0076] Based on the above processing method, since the party whose interrupt type is different from the lowest priority interrupt type stored in the target memory space receives the highest priority information, this party will abandon sending the interrupt to the interrupt management controller dest_ctrl after the priority comparison and judgment described above. Therefore, in the above scenario, only one of the local specific peripheral interrupt controller lpi_ctrl and the virtual local specific peripheral interrupt controller vlpi_ctrl ultimately sends the interrupt to the interrupt management controller dest_ctrl, thereby reducing interrupt transmission power consumption.

[0077] As described above, in the interrupt transmission control scheme provided in this application embodiment, when both the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core, and the target memory space corresponding to the target processor core has no free memory space, the interrupt management controller further determines the type of the lowest priority interrupt stored in the target memory space. If the lowest priority interrupt stored in the target memory space is a local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the virtual local specific peripheral interrupt controller to the highest priority; if the lowest priority interrupt stored in the target memory space is a virtual local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the local specific peripheral interrupt controller to the highest priority. This process ensures that when the interrupt to be transmitted by the local specific peripheral interrupt controller or the virtual local specific peripheral interrupt controller is of a different type than the lowest priority interrupt stored in the target memory space, the highest priority information is received. This allows the local specific peripheral interrupt controller or the virtual local specific peripheral interrupt controller to recognize that the priority of the interrupt to be transmitted is not higher than the priority of the lowest priority interrupt stored in the target memory space and cancel the transmission interrupt, thereby avoiding wasted power consumption due to the interrupt being unable to be received by the interrupt management controller.

[0078] Another embodiment of this application provides a hardware interrupt controller, wherein the interrupt controller dispatcher of the hardware interrupt controller is provided with a local specific peripheral interrupt controller, a virtual local specific peripheral interrupt controller, and an interrupt management controller; the interrupt management controller is provided with a storage space corresponding to each processor core for storing interrupts sent to the corresponding processor core; When both the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core, and the target memory space corresponding to the target processor core has no free memory space, the interrupt management controller determines the type of the lowest priority interrupt stored in the target memory space; If the lowest priority interrupt stored in the target storage space is a local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the virtual local specific peripheral interrupt controller to the highest priority, and sets the priority information sent to the local specific peripheral interrupt controller to the priority of the lowest priority interrupt stored in the target storage space. or, If the lowest priority interrupt stored in the target storage space is a virtual local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the local specific peripheral interrupt controller to the highest priority, and sets the priority information sent to the virtual local specific peripheral interrupt controller to the priority of the lowest priority interrupt stored in the target storage space.

[0079] In some embodiments, the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller based on the received priority information.

[0080] In some embodiments, the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller based on received priority information, including: The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller compare the priority of the interrupt to be sent with the received priority information, respectively. When the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller determine that the priority of the interrupt to be sent is higher than the received priority information, they determine to send the interrupt to be sent to the interrupt management controller. or, If the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller determine that the priority of the interrupt to be sent is not higher than the priority information received, they will decide not to send the interrupt to be sent to the interrupt management controller.

[0081] In some embodiments, the interrupt management controller also sends the target storage space occupancy information to the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller, respectively.

[0082] In some embodiments, the occupancy information of the target storage space includes a status identifier of the target storage space; when the value of the status identifier is a first value, it indicates that the target storage space has free storage space, or when the value of the status identifier is a second value, it indicates that the target storage space has no free storage space.

[0083] In some embodiments, the interrupt management controller further receives a first interrupt request signal sent by the local specific peripheral interrupt controller and a second interrupt request signal sent by the virtual local specific peripheral interrupt controller; the interrupt request signal includes an identifier of the target processor core receiving the interrupt; If the first interrupt request signal and the second interrupt request signal include the same target processor core identifier, the interrupt management controller determines that the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core.

[0084] The hardware interrupt controller provided in this embodiment belongs to the same concept as the interrupt transmission control method provided in the above embodiments of this application. It can execute the interrupt transmission control method provided in any of the above embodiments of this application and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment can be found in the specific processing content of the interrupt transmission control method provided in the above embodiments of this application, and will not be repeated here.

[0085] Another embodiment of this application provides a virtual machine system that includes the aforementioned hardware interrupt controller, thereby enabling the execution of the interrupt transmission control method provided in any of the above embodiments through the hardware interrupt controller, and achieving the beneficial effects of executing the interrupt transmission control method.

[0086] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0087] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0088] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0089] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0090] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0091] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0092] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0093] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0095] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0096] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A transmission interrupt control method characterized by comprising: A hardware interrupt controller applied to a virtual machine system, wherein a local specific peripheral interrupt controller, a virtual local specific peripheral interrupt controller and an interrupt management controller are arranged in an interrupt controller distributor of the hardware interrupt controller; The interrupt management controller is arranged with a storage space corresponding to each processor core, and is used to store an interrupt sent to a corresponding processor core; The method comprises: In a case where the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to a target processor core, and a target storage space corresponding to the target processor core has no idle storage space, the interrupt management controller determines a type of a lowest priority interrupt stored in the target storage space; In a case where the lowest priority interrupt stored in the target storage space is a local specific peripheral interrupt, the interrupt management controller sets priority information sent to the virtual local specific peripheral interrupt controller as a highest priority, and sets priority information sent to the local specific peripheral interrupt controller as a priority of the lowest priority interrupt stored in the target storage space; Or, In a case where the lowest priority interrupt stored in the target storage space is a virtual local specific peripheral interrupt, the interrupt management controller sets priority information sent to the local specific peripheral interrupt controller as a highest priority, and sets priority information sent to the virtual local specific peripheral interrupt controller as a priority of the lowest priority interrupt stored in the target storage space.

2. The method of claim 1, wherein, The method further comprises: The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller according to received priority information.

3. The method of claim 2, wherein, The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller according to received priority information, comprising: The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller respectively compare a priority of a to-be-sent interrupt with received priority information; In a case where the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller determine that the priority of the to-be-sent interrupt is higher than the received priority information, it is determined that the to-be-sent interrupt is sent to the interrupt management controller; Or, In a case where the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller determine that the priority of the to-be-sent interrupt is not higher than the received priority information, it is determined that the to-be-sent interrupt is not sent to the interrupt management controller.

4. The method of claim 1, wherein, The method further comprises: The interrupt management controller sends occupation information of the target storage space to the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller respectively.

5. The method of claim 4, wherein, The occupancy information of the target storage space includes a state identifier of the target storage space; when the value of the state identifier is a first value, it indicates that the target storage space has free storage space, or when the value of the state identifier is a second value, it indicates that the target storage space has no free storage space.

6. The method according to any one of claims 1 to 5, characterized in that, The method further comprises: The interrupt management controller receives a first interrupt request signal sent by the local specific peripheral interrupt controller and a second interrupt request signal sent by the virtual local specific peripheral interrupt controller; the interrupt request signal includes the identifier of the target processor core receiving the interrupt; In the case that the first interrupt request signal and the second interrupt request signal include the same target processor core identifier, the interrupt management controller determines that the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core.

7. A hardware interrupt controller, characterized by The interrupt controller distributor of the hardware interrupt controller is provided with the local specific peripheral interrupt controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller; the interrupt management controller is provided with a storage space corresponding to each processor core, for storing the interrupt sent to the corresponding processor core; In the case that the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller simultaneously request to send an interrupt to the target processor core, and the target storage space corresponding to the target processor core has no free storage space, the interrupt management controller determines the type of the lowest priority interrupt stored in the target storage space; In the case that the lowest priority interrupt stored in the target storage space is a local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the virtual local specific peripheral interrupt controller as the highest priority, and sets the priority information sent to the local specific peripheral interrupt controller as the priority of the lowest priority interrupt stored in the target storage space. Or, In the case that the lowest priority interrupt stored in the target storage space is a virtual local specific peripheral interrupt, the interrupt management controller sets the priority information sent to the local specific peripheral interrupt controller as the highest priority, and sets the priority information sent to the virtual local specific peripheral interrupt controller as the priority of the lowest priority interrupt stored in the target storage space.

8. The hardware interrupt controller of claim 7, wherein, The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller according to the received priority information.

9. The hardware interrupt controller of claim 8, wherein, The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller each determine whether to send an interrupt to the interrupt management controller according to the received priority information, comprising: The local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller respectively compare the priority of the interrupt to be sent with the received priority information; determining, by the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller, to send the pending interrupt to the interrupt management controller if it is determined that the priority of the pending interrupt is higher than the received priority information; or alternatively, determining, by the local specific peripheral interrupt controller and the virtual local specific peripheral interrupt controller, not to send the pending interrupt to the interrupt management controller if it is determined that the priority of the pending interrupt is not higher than the received priority information.

10. A virtual machine system, characterized by a hardware interrupt controller as claimed in any one of claims 7 to 9.

Images