Program energy efficiency optimization method and system based on stage division and multi-stage cooperation

Abstract

The application discloses a program energy efficiency optimization method and system based on stage division and multi-stage cooperation, and the method comprises the following steps: obtaining a profiling call tree of a target program, and initializing a current level as a maximum level of the profiling call tree; extracting a node set of the current level, extracting effective nodes, extracting features, and determining a stage type of the effective nodes; adding a binary tuple formed by a node name of each effective node and the stage type into a selected stage set S; constructing a stage feature matrix for the selected stage set S of the profiling call tree, and predicting an optimal frequency combination of the target program by using a pre-trained multi-stage cooperative energy efficiency optimization model. The application aims to realize optimal processor frequency configuration of each stage of a program under the condition that the global performance constraint is met, and significantly optimize the total processor energy consumption of the program under the premise that the execution performance is not lost.

Description

Technical Field

[0001] This invention belongs to the field of computer program optimization, specifically relating to a program energy efficiency optimization method and system based on stage division and multi-stage collaboration. Background Technology

[0002] With the continuous development of CPU dynamic frequency adjustment technology in modern computer systems, the characteristics of program execution stages are becoming increasingly differentiated, and the complexity of performance monitoring indicators is constantly increasing, leading to more pronounced differentiation in program execution stage characteristics. Achieving a synergistic balance between program performance improvement and processor energy consumption optimization based on processor dynamic frequency adjustment strategies has become an important research topic. However, traditional methods for program performance improvement and processor energy consumption optimization often fail to incorporate the program type characteristic into processor frequency settings, resulting in room for improvement in both the magnitude of program performance improvement and the effectiveness of processor energy consumption control. Furthermore, existing technologies often apply the same or similar energy efficiency optimization goals (such as minimizing processor energy consumption) to code segments belonging to different program types, ignoring the type-specific differences in program code segments. Processor frequency settings typically do not consider the coordination between program stages, making it difficult to achieve a dynamic balance between program performance and processor energy consumption. Summary of the Invention

[0003] The technical problem this invention aims to solve is to address the issues of neglecting stage differences and failing to consider stage coordination in existing technologies. This invention provides a program energy efficiency optimization method and system based on stage division and multi-stage coordination. The goal is to achieve the optimal processor frequency configuration with minimum processor energy consumption that satisfies global performance constraints at each stage of the program, significantly optimizing the total processor energy consumption during program execution without sacrificing program performance.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A process energy efficiency optimization method based on stage division and multi-stage collaboration includes the following steps:

[0006] S1, obtain the parsing call tree of the target program, wherein the nodes in the parsing call tree are function call instances of the target program, the edges are one-time call relationships of the function call instances, and the current level is initialized to the maximum level of the parsing call tree;

[0007] S2, extract the set of nodes at the current level;

[0008] S3, extract valid nodes from the current level's node set;

[0009] S4. Extract the features of each valid node and determine the stage type of the valid node based on the features.

[0010] S5, add the tuple consisting of the node name and stage type of each valid node to the selected stage set S;

[0011] S6, determine whether the traversal of all levels of the parsing call tree has been completed. If the traversal of all levels of the parsing call tree has not been completed, decrease the current level and jump to step S2; otherwise, jump to step S7.

[0012] S7. Construct a stage feature matrix for the selected stage set S, and use a pre-trained multi-stage collaborative energy efficiency optimization model to predict the optimal frequency combination corresponding to the selected stage set S, which satisfies the performance constraints and minimizes the total processor energy consumption. The multi-stage collaborative energy efficiency optimization model is pre-trained to establish a mapping relationship between the input stage feature matrix and the output optimal frequency combination.

[0013] Optionally, step S3, which involves extracting valid nodes from the current level's node set, includes filtering out nodes that are in a preset prohibited set B, as well as invalid nodes whose ratio of the execution time Tj of the sub-function to the total execution time Ttotal of the target program is less than a preset threshold, and using the remaining nodes as the extracted valid nodes.

[0014] Optionally, when the remaining node is used as the extracted valid node, all ancestor functions of the remaining node are added to the forbidden set B to prevent stage overlap. The ancestor function refers to the function instance that is earlier in the parsing call tree.

[0015] Optionally, when extracting the features of each valid node in step S4, the features of the valid nodes are represented by the vector shown in the following formula:

[0016] (AI, Tj, dj);

[0017] Where AI is the arithmetic strength of the node, Tj is the execution time of the node's sub-functions, and dj is the call depth of the node. The function expression for calculating the arithmetic strength of the node is:

[0018] AI = FLOPs count / Bytes count ;

[0019] Among them, FLOPs count For floating-point operands during node execution, Bytes count This represents the number of bytes accessed from the node's main memory.

[0020] Optionally, determining the stage type of a valid node based on features in step S4 includes: comparing the node's arithmetic strength AI with a preset Roofline model inflection point threshold AI_ridge; if the node's arithmetic strength AI is greater than or equal to the preset Roofline model inflection point threshold AI_ridge, then the stage type of the valid node is determined to be a computationally intensive stage; otherwise, the stage type of the valid node is determined to be a memory-intensive stage. The calculation function expression of the preset Roofline model inflection point threshold AI_ridge is: AI_ridge=π / β, where π is the processor's peak computing performance and β is the memory bandwidth.

[0021] Optionally, when constructing the stage feature matrix for the selected stage set S in step S7, the stage features adopted for each stage in the selected stage set S include program features of computation, memory access, and communication. The program features of computation include some or all of computation efficiency and instructions per cycle (IPC). The program features of memory access include some or all of memory access efficiency, cache utilization, L3 cache miss rate, and DRAM bandwidth. The program features of communication include network bandwidth.

[0022] Optionally, during training, the multi-stage collaborative energy efficiency optimization model generates labels for the optimal frequency combination used for the input stage feature matrix samples, including: for each computationally intensive stage i in the stage feature matrix samples, within a preset frequency range [f base ,f max [Iterate through each frequency f with a step size Δf] C Recording frequency f C Processor power consumption E C (f C ) and execution time T C (f C For each memory-intensive stage j in the stage feature matrix sample, within the preset frequency range [f] min ,f base [Iterate through each frequency f with a step size Δf] M Record the processor power consumption E at this frequency. M (f M ) and execution time T M (f M ), where f min and f max f is the preset minimum and maximum frequency. base The frequency boundary values ​​are shared by the preset compute-intensive and memory-intensive stages; the candidate frequency combinations F={f1,f2,...,f...} of all stages in the stage feature matrix sample are generated. n}, where f1~f nFor each candidate frequency combination F in stages 1 to n, calculate the total execution time T. total =ΣT i (f i ), where T is i (f i Let be the execution time of the candidate frequencies in the i-th stage, and verify the total execution time T. total For candidate frequency combinations F that meet the preset performance constraints, calculate the total processor power consumption E. total= ΣE i (f i ), where E i (f i Let E be the processor energy consumption of the candidate frequencies in the i-th stage, and select the total processor energy consumption E. total The smallest candidate frequency combination F is used as the label f ​​of the optimal frequency combination adopted by the feature matrix samples in this stage. .

[0023] The present invention also provides a program energy efficiency optimization system based on stage division and multi-stage collaboration, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the program energy efficiency optimization method based on stage division and multi-stage collaboration.

[0024] The present invention also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute the program energy efficiency optimization method based on phase division and multi-phase collaboration by a processor.

[0025] The present invention also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the program energy efficiency optimization method based on phase division and multi-phase collaboration via a processor.

[0026] Compared with existing technologies, this invention mainly achieves the following beneficial effects: Addressing the problems of large differences in optimal frequency distribution across different program execution stages, traditional frequency setting methods neglecting the trade-off between global program performance and processor energy consumption, and sacrificing program execution performance for processor energy consumption, this embodiment's program energy efficiency optimization method based on stage division and multi-stage collaboration includes two core stages: a stage division and classification stage based on a program classification model (referred to as the PhaseDivis-Alg stage, i.e., steps S1-S6) and a multi-stage collaborative frequency control stage based on a deep learning model (referred to as the PhaseColla-Alg stage, i.e., step S7). Through the PhaseDivis-Alg stage, this invention achieves precise division of program stages based on call tree analysis and a program classification model, clearly identifying the characteristic differences of computation / memory-intensive stages, greatly improving the targeting of processor energy consumption control. With the help of the PhaseColla-Alg stage, a deep learning model models the resource competition relationship between stages, combining differentiated frequency strategies and constrained exhaustive search to achieve the minimum processor energy consumption configuration while satisfying global performance constraints. This invention adopts a "static feature profiling + dynamic collaborative optimization" model to avoid the problems of inaccurate stage identification and neglect of performance coupling effects in traditional optimization. It achieves zero runtime overhead through secondary instrumentation, significantly improving optimization efficiency and energy efficiency ratio. It is particularly suitable for application scenarios with strict requirements for energy efficiency and performance balance, such as high-performance computing and heterogeneous computing. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0029] like Figure 1 As shown, the program energy efficiency optimization method based on stage division and multi-stage collaboration in this embodiment includes the following steps:

[0030] S1, obtain the parsing call tree of the target program. The nodes in the parsing call tree are the function call instances of the target program, and the edges are the call relationships of the function call instances. Initialize the current level currentLevel to the maximum level m of the parsing call tree.

[0031] S2, extract the set of nodes Nodes_current of the current level currentLevel;

[0032] S3, extract valid nodes from the node set Nodes_current of the current level;

[0033] S4. Extract the features of each valid node and determine the stage type of the valid node based on the features.

[0034] S5, add the tuple consisting of the node name and stage type of each valid node to the selected stage set S, that is:

[0035] S={(f i type i )};

[0036] Among them, (f i type i f is the node name of the i-th valid node. i and its stage type i The binary tuple formed;

[0037] S6, determine whether the traversal of all levels of the parsing call tree has been completed. If the traversal of all levels of the parsing call tree has not been completed, decrement the current level currentLevel.

[0038] currentLevel= currentLevel-1;

[0039] Jump to step S2; otherwise, jump to step S7.

[0040] S7. Construct a stage feature matrix for the selected stage set S. Use a pre-trained multi-stage collaborative energy efficiency optimization model to predict the optimal frequency combination corresponding to the selected stage set S, which satisfies the performance constraints and minimizes the total processor energy consumption. The multi-stage collaborative energy efficiency optimization model is pre-trained to establish a mapping relationship between the input stage feature matrix and the output optimal frequency combination.

[0041] This embodiment is based on a program energy efficiency optimization method that uses stage division and multi-stage collaboration. It obtains a set of selected stages S by accurately dividing the program into stages, constructs a stage feature matrix for the selected stage set S, and uses a pre-trained multi-stage collaborative energy efficiency optimization model to predict the global optimization mechanism of the optimal frequency combination corresponding to the selected stage set S. This method can significantly reduce the total processor energy consumption and improve the energy efficiency ratio without sacrificing program execution performance, thus achieving a dynamic balance between program performance and processor energy consumption.

[0042] In step S1 of this embodiment, the call tree is analyzed as an m×n hierarchical tree structure, where m is the maximum nesting depth of the call chain and n is the average number of nodes per level. Any node in the call tree contains the execution time Tj of the sub-function (inclusive), the call depth dj, and the performance data of the performance counter PMC, where Tj>0 indicates the effective execution time of the node.

[0043] Step S3 involves extracting valid nodes from the current level's node set, including filtering out nodes in the preset prohibited set B from the current level's node set Nodes_current, as well as invalid nodes whose ratio Tj / Ttotal of the execution time Tj of the sub-function to the total execution time Ttotal of the target program is less than a preset threshold τ (default 5%), and using the remaining nodes as the extracted valid nodes.

[0044] When the remaining node is selected as the extracted valid node, all ancestor functions of that remaining node are simultaneously added to the forbidden set B to prevent stage overlap. The ancestor function refers to an earlier function instance in the parsing call tree, including parent functions, grandparent functions, etc. In this embodiment, the forbidden set B is initialized as follows: This is used to record the parent nodes of processed nodes and valid nodes to avoid redundant analysis and control the time complexity of the algorithm. Then, when the remaining nodes are extracted as valid nodes, all ancestor functions of the remaining nodes are added to the forbidden set B to prevent stage overlap.

[0045] In step S4, when extracting features from each valid node, the arithmetic strength AI can be calculated based on the node PMC data (including FLOPs, Bytes, and Cycles) to construct a stage feature quantification model. Specifically, in this embodiment, the features of valid nodes are represented by the vector shown in the following formula:

[0046] (AI, Tj, dj);

[0047] Where AI is the arithmetic strength of the node, Tj is the execution time of the node including its sub-functions (including inclusive execution time), and dj is the call depth of the node. The function expression for calculating the arithmetic strength of the node is:

[0048] AI = FLOPs count / Bytes count ;

[0049] Among them, FLOPs count For floating-point operands during node execution, Bytes countThis refers to the number of bytes accessed from the main memory of the node. In this embodiment, when extracting key performance indicators from the node's performance counter (PMC) data, the PMC data acquisition process for any node is as follows: The performance counters are started at the beginning of node execution; the initial value of the floating-point operation counter (FP_OPS) is recorded; the initial value of the main memory access counter (MEM_BYTES) is recorded; the initial value of the cycle counter (CYCLES) is recorded; the final values ​​of each counter are read at the end of node execution; and the increment is calculated.

[0050] FLOPs count =FP_OPS_end-FP_OPS_start;

[0051] Bytes count =MEM_BYTES_end-MEM_BYTES_start;

[0052] Cycles count =CYCLES_end-CYCLES_start;

[0053] This method yields the complete PMC data set for each node. Among these, FLOPs... count For floating-point operands during node execution, Bytes count Cycles represents the number of bytes accessed from the main memory of a node. count This represents the number of cycles. FP_OPS_end and FP_OPS_start are the end and start times of the floating-point counter, respectively. MEM_BYTES_end and MEM_BYTES_start are the final and initial values ​​of the main memory access counter MEM_BYTES, respectively. CYCLES_end and CYCLES_start are the final and initial values ​​of the cycle counter CYCLES, respectively.

[0054] In step S4, the phase types of determining valid nodes according to features include: comparing the arithmetic intensity AI of a node with the preset Roofline model turning point threshold AI_ridge. If the arithmetic intensity AI of the node is greater than or equal to the preset Roofline model turning point threshold AI_ridge, it is determined that the phase type of the valid node is a compute-intensive phase; otherwise, it is determined that the phase type of the valid node is a memory-intensive phase. The calculation function expression of the preset Roofline model turning point threshold AI_ridge is: AI_ridge = π / β, where π is the peak computing performance of the processor (GFLOP / s), and β is the memory bandwidth (GB / s). In this embodiment, determining whether a node is a compute-intensive or memory-intensive phase in combination with the Roofline model threshold includes: comparing the size relationship between the node arithmetic intensity AI and the Roofline model turning point threshold AI_ridge = π / β, where π is the peak computing performance of the processor (such as 1000 G FLOPS), and β is the memory bandwidth (such as 100 GB / s); when AI ≥ AI_ridge, it is determined that the node is in the compute-intensive phase, and type i is set to C; when AI < AI_ridge, it is determined that the node is in the memory-intensive phase, and type i is set to M; the pair (f i , type i ) is stored in the selected phase set S.

[0055] In this embodiment, two types of compute-intensive phases and memory-intensive phases are divided. The different types of nodes and their phase types in this embodiment are as follows:

[0056] Matrix multiplication node: Compute-intensive phase. This node contains a large number of floating-point operation operations and has a high arithmetic intensity.

[0057] Data loading node: Memory-intensive phase. This node mainly reads main memory data and has frequent memory access.

[0058] Loop unrolling node: Compute-intensive phase. This node improves instruction-level parallelism through loop unrolling technology.

[0059] Cache prefetch node: Memory-intensive phase. This node is responsible for data prefetching to reduce cache misses.

[0060] Vectorized computing node: Compute-intensive phase. This node uses SIMD instructions for parallel computing.

[0061] Taking the matrix multiplication node as an example, AI_ridge = π / β = 1000 / 100 = 10. If the arithmetic intensity AI of the matrix multiplication node is:

[0062] AI = 1000 FLOPs / 10 Bytes = 100;

[0063] Then, if AI > AI_ridge, it is determined that the matrix multiplication node is a compute-intensive stage.

[0064] If the arithmetic intensity AI of the data loading node is:

[0065] AI = 10 FLOPs / 1000 Bytes = 0.01;

[0066] Then, if AI < AI_ridge, it is determined that the matrix multiplication node is a memory-intensive stage.

[0067] When constructing the stage feature matrix for the selected stage set S in step S7, the stage features adopted for each stage in the selected stage set S include the program features of computing, memory access, and communication. The program features of computing include some or all of the computing efficiency and the instructions per cycle IPC. The program features of memory access include some or all of the memory access efficiency, cache utilization rate, L3 cache miss rate, and DRAM bandwidth. The program features of communication include the network bandwidth.

[0068] When training the multi-stage collaborative energy efficiency optimization model, the generation of the labels of the optimal frequency combinations for the input stage feature matrix samples includes: for each compute-intensive stage i in the stage feature matrix sample, traversing each frequency f within the preset frequency range [f base , f max with a step size of Δf, and recording the processor energy consumption E C at frequency f C and the execution time T C (f C ); for each memory-intensive stage j in the stage feature matrix sample, traversing each frequency f within the preset frequency range [f C , f C with a step size of Δf, and recording the processor energy consumption E min at this frequency and the execution time T base (f M ), where f M and f M are the preset minimum and maximum frequencies, and f M is the preset frequency boundary value shared by the compute-intensive stage and the memory-intensive stage; generating the candidate frequency combinations F = {f1, f2,..., f M} for all stages in the stage feature matrix sample, where f1 to f min and f max are the preset minimum and maximum frequencies, and f base is the preset frequency boundary value shared by the compute-intensive stage and the memory-intensive stage; generating the candidate frequency combinations F = {f1, f2,..., f n} for all stages in the stage feature matrix sample, where f1 to f nFor each candidate frequency combination F in stages 1 to n, calculate the total execution time T. total =ΣT i (f i ), where T is i (f i Let be the execution time of the candidate frequencies in the i-th stage, and verify the total execution time T. total Does it meet the preset performance constraints (e.g., T)? total ≤T origin ×(1+1%), where T origin Given the total execution time at the base frequency, calculate the total processor power consumption E for candidate frequency combinations F that satisfy the performance constraints. total= ΣE i (f i ), where E i (f i Let E be the processor energy consumption of the candidate frequencies in the i-th stage, and select the total processor energy consumption E. total The smallest candidate frequency combination F is used as the label f ​​of the optimal frequency combination adopted by the feature matrix samples in this stage. Taking the dynamic frequency adjustment of an Intel Core i7 processor as an example, the processor's base frequency f... base =2.4GHz, maximum frequency f max =4.2GHz, minimum frequency f min =1.2GHz, frequency adjustment step size Δf=0.1GHz; during the optimization program execution, the optimal frequency combination f is output based on the multi-stage collaborative energy efficiency optimization model. Assign target frequencies to each stage: the optimal frequency for computationally intensive stages is adapted to their computational characteristics to ensure performance, while the optimal frequency for memory-intensive stages is matched to their memory access characteristics to reduce inefficient processor power consumption; taking frequency optimization of a program with 5 stages as an example: obtain the type of each stage. i ∈{C,M} (In this embodiment, Type=[C,M,C,C,M]); the frequency ranges for each stage are defined according to a differentiated strategy, with the C-type stage being [2.4GHz, 4.2GHz] and the M-type stage being [1.2GHz, 2.4GHz]; the optimal frequency combination prediction and processor energy consumption evaluation process for each stage are as follows: In this embodiment, the stage type is... i The distribution is an n×1 vector, where n is the total number of stages in the program, and each element is type. i ∈{C,M} represents the type of the i-th stage; the energy efficiency evaluation matrix is ​​an n×k analysis table (k is the number of legal frequency points for the corresponding stage), with each row recording the processor energy consumption and execution time for each frequency point in the corresponding stage, used to filter the optimal frequency combination that satisfies the global constraints. The label f ​​of the optimal frequency combination is obtained. Then, by labeling the optimal frequency combination f The secondary instrumentation is solidified into a static frequency modulation command, achieving zero-overhead execution.

[0069] The multi-stage collaborative energy efficiency optimization model can employ the required machine learning model, such as the Transformer model, as needed. In this embodiment, training the Transformer model and validating its prediction performance includes dividing the training dataset into a training set and a validation set in a 7:3 ratio, training the model using the Adam optimizer, setting the learning rate to 1e-4 to 1e-3, and the number of iterations to 100 to 200 rounds; during validation, the frequency combination f predicted by the model is checked. The total execution time corresponding to _pred is checked to ensure that slowdown ≤ 1%, and the deviation between the total processor energy consumption and the optimal solution is less than the tolerance threshold η (η = 5% in this embodiment). When the deviation exceeds η or the performance constraints are not met, the model structure is optimized (e.g., the number of encoder layers is adjusted to 3-6, and the number of attention heads is adjusted to 8-16), or the sample size of the training dataset is expanded. After optimization, the model is retrained until the validation set meets the constraints and the processor energy consumption deviation is ≤ η. In this embodiment, when optimizing the Transformer model parameters to improve prediction accuracy, a grid search method is used to traverse key parameter combinations: the number of encoder layers is 3-6, the number of attention heads is 8-16, the hidden layer dimension is 128-512, and the cross-validation folds are set to 5 folds. By monitoring the training set loss and the energy efficiency deviation of the validation set, the optimal parameter combination is determined to ensure the stability and accuracy of the model in generalization scenarios. It should be noted that the multi-stage collaborative energy efficiency optimization algorithm based on Transformer is an innovative algorithm of this invention. Through long-range dependency modeling of stage sequence and global constraint optimization, it achieves the minimum processor energy consumption frequency configuration that meets performance requirements, and achieves a global collaborative balance between processor energy consumption and program performance.

[0070] To verify the program energy efficiency optimization method based on stage division and multi-stage collaboration in this embodiment, experiments were conducted on a supercomputing cluster (processor model: Intel(R) Xeon(R) Platinum 8358P CPU) using typical benchmark tests (HPCC, HPCG, Graph500 and LULESH), and the program was run at the benchmark frequency as the baseline. The comparison results with the baseline are shown in Table 1.

[0071] Table 1: Performance constraint satisfaction and energy consumption reduction of the method in this embodiment compared to the baseline in typical benchmark tests.

[0072]

[0073] As shown in Table 1, the method in this embodiment achieves an average energy consumption reduction of 18.29% compared to the baseline in four typical benchmark tests: HPCC, HPCG, Graph500, and LULESH, while meeting performance constraints (the optimized execution time is less than or equal to the unoptimized execution time). This embodiment's method enables the minimum energy consumption and optimal processor frequency configuration at each stage of the program to meet global performance constraints, significantly optimizing the total energy consumption of program execution without sacrificing execution performance.

[0074] In summary, the program energy efficiency optimization method based on stage division and multi-stage collaboration in this embodiment includes two core stages: the stage division and classification stage based on the program classification model (referred to as the PhaseDivis-Alg stage, i.e., steps S1 to S6) and the multi-stage collaborative frequency regulation stage based on the deep learning model (referred to as the PhaseColla-Alg stage, i.e., step S7). The PhaseDivis-Alg stage collects source code instrumentation to analyze the call tree and function dynamic feature data (including PMC data such as FLOPs, Bytes, and Cycles), and combines it with the inflection point threshold AI_ridge=π / β of the program classification model (such as Roofline). Through filtering hot code segments, bottom-up hierarchical traversal, and program stage type determination, it accurately identifies computationally intensive (C) and memory-intensive (M) key code stages. The PhaseColla-Alg stage is based on the self-attention mechanism of deep learning (such as Transformer) models. It learns the long-range dependencies and resource competition relationships of the stage sequence. By constructing an n×(s+1) feature matrix (containing s dynamic feature data and 1 type label) and exhaustively filtering the optimal frequency combination that satisfies global performance constraints, it achieves cross-stage collaborative processor frequency configuration optimization. This embodiment of the program energy efficiency optimization method based on stage division and multi-stage collaboration accurately identifies the characteristics of program stages, establishes differentiated frequency control strategies, and combines the Transformer model to accurately model the resource competition between stages. This achieves the goal of significantly reducing the total processor energy consumption while ensuring global performance constraints. Thus, the method of this embodiment can effectively solve the problems of ignoring stage coupling effects and fragmented energy efficiency optimization in traditional optimization, and can make up for the shortcomings of existing dynamic frequency adjustment technology, which lacks global decision-making capabilities and has limited optimization effects.

[0075] Those skilled in the art will understand that the technical solutions provided by this invention can take the form of a method, a system, or a computer program product. For example, this invention can provide a program energy efficiency optimization system based on stage partitioning and multi-stage collaboration, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the program energy efficiency optimization method based on stage partitioning and multi-stage collaboration. This invention can provide a computer-readable storage medium storing a computer program or instructions programmed or configured to execute the program energy efficiency optimization method based on stage partitioning and multi-stage collaboration via a processor. This invention can provide a computer program product including a computer program or instructions programmed or configured to execute the program energy efficiency optimization method based on stage partitioning and multi-stage collaboration via a processor. Furthermore, this invention can also take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, this invention can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0076] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A program energy efficiency optimization method based on stage division and multi-stage collaboration, characterized in that, Includes the following steps: S1, obtain the parsing call tree of the target program, wherein the nodes in the parsing call tree are function call instances of the target program, the edges are one-time call relationships of the function call instances, and the current level is initialized to the maximum level of the parsing call tree; S2, extract the set of nodes at the current level; S3, extract valid nodes from the current level's node set; S4. Extract the features of each valid node and determine the stage type of the valid node based on the features. S5, add the tuple consisting of the node name and stage type of each valid node to the selected stage set S; S6, determine whether the traversal of all levels of the parsing call tree has been completed. If the traversal of all levels of the parsing call tree has not been completed, decrease the current level and jump to step S2. Otherwise, proceed to step S7; S7. Construct a stage feature matrix for the selected stage set S. Use a pre-trained multi-stage collaborative energy efficiency optimization model to predict the optimal frequency combination corresponding to the selected stage set S. Optimal means that the total execution time meets the performance constraints and the total processor energy consumption is minimized. The multi-stage collaborative energy efficiency optimization model is pre-trained to establish a mapping relationship between the input stage feature matrix and the output optimal frequency combination. During training, the multi-stage collaborative energy efficiency optimization model generates labels for the optimal frequency combination used in the input stage feature matrix samples, including: for each computationally intensive stage i in the stage feature matrix samples, within a preset frequency range [f base ,f max [Iterate through each frequency f with a step size Δf] C Recording frequency f C Processor power consumption E C (f C ) and execution time T C (f C For each memory-intensive stage j in the stage feature matrix sample, within the preset frequency range [f] min ,f base [Iterate through each frequency f with a step size Δf] M Record the processor power consumption E at this frequency. M (f M ) and execution time T M (f M ), where f min and f max f is the preset minimum and maximum frequency. base The frequency baseline values ​​are shared by the pre-defined compute-intensive and memory-intensive stages; the candidate frequency combinations F={f1,f2,...,f...} of all stages in the stage feature matrix sample are generated. n }, where f1~f n For each candidate frequency combination F in stages 1 to n, calculate the total execution time T. total =ΣT i (f i ), where T i (f i Let be the execution time of the program in the i-th stage at the candidate frequency, and verify the total execution time T. total For candidate frequency combinations F that meet the preset performance constraints, calculate the total processor power consumption E. total= ΣE i (f i ), where E i (f i Let E be the processor energy consumption of the program running at the candidate frequency in the i-th stage. The total processor energy consumption E is then selected. total The smallest candidate frequency combination F is used as the label f ​​of the optimal frequency combination adopted by the feature matrix samples in this stage. .

2. The program energy efficiency optimization method based on stage division and multi-stage collaboration according to claim 1, characterized in that, Step S3 involves extracting valid nodes from the current level's node set, which includes filtering out nodes that are in the preset prohibited set B, as well as invalid nodes whose ratio of the execution time Tj of the sub-function to the total execution time Ttotal of the target program is less than a preset threshold. The remaining nodes are then used as the extracted valid nodes.

3. The program energy efficiency optimization method based on stage division and multi-stage collaboration according to claim 2, characterized in that, When the remaining nodes are used as the extracted valid nodes, all ancestor functions of the remaining nodes are added to the forbidden set B to prevent stage overlap. The ancestor function refers to the function instance that is earlier in the parsing call tree.

4. The program energy efficiency optimization method based on stage division and multi-stage collaboration according to claim 1, characterized in that, In step S4, when extracting the features of each valid node, the features of the valid nodes are represented by the vector shown in the following formula: (AI, Tj, dj); Where AI is the arithmetic strength of the node, Tj is the execution time of the node's sub-functions, and dj is the call depth of the node. The function expression for calculating the arithmetic strength of the node is: AI=FLOPs count / Bytes count ; Among them, FLOPs count For floating-point operands during node execution, Bytes count This represents the number of bytes accessed from the node's main memory.

5. The program energy efficiency optimization method based on stage division and multi-stage collaboration according to claim 4, characterized in that, Step S4, determining the stage type of a valid node based on features, includes: comparing the node's arithmetic strength AI with a preset Roofline model inflection point threshold AI_ridge. If the node's arithmetic strength AI is greater than or equal to the preset Roofline model inflection point threshold AI_ridge, then the stage type of the valid node is determined to be a computationally intensive stage; otherwise, the stage type of the valid node is determined to be a memory-intensive stage. The calculation function expression of the preset Roofline model inflection point threshold AI_ridge is: AI_ridge = π / β, where π is the processor's peak computing performance and β is the memory bandwidth.

6. The program energy efficiency optimization method based on stage division and multi-stage collaboration according to claim 1, characterized in that, In step S7, when constructing the stage feature matrix for the selected stage set S, the stage features adopted for each stage in the selected stage set S include program features of computation, memory access, and communication. The program features of computation include some or all of computation efficiency and instructions per cycle (IPC). The program features of memory access include some or all of memory access efficiency, cache utilization, L3 cache miss rate, and DRAM bandwidth. The program features of communication include network bandwidth.

7. A program energy efficiency optimization system based on stage division and multi-stage collaboration, comprising interconnected microprocessors and memory, characterized in that, The microprocessor is programmed or configured to execute the program energy efficiency optimization method based on stage division and multi-stage collaboration as described in any one of claims 1 to 6.

8. A computer-readable storage medium storing a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute the program energy efficiency optimization method based on phase division and multi-phase collaboration as described in any one of claims 1 to 6 via a processor.

9. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute the program energy efficiency optimization method based on phase division and multi-phase collaboration as described in any one of claims 1 to 6 via a processor.

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