Data management control system and method, storage medium and electronic equipment

Abstract

The invention relates to a data management control system and method, a storage medium and electronic equipment, and relates to the technical field of ship communication, and the system comprises an interface chip controller which is used for receiving a to-be-transmitted data stream sent by an interface, and writing the to-be-transmitted data stream into a data cache region; the dynamic random access memory is in communication connection with the interface chip controller, and the dynamic random access memory comprises a data cache region, a dynamic random controller and a data controller; wherein the data cache region is used for caching the data stream to be transmitted; the data controller is used for dynamically adjusting a data transmission channel for the data stream to be transmitted; and the dynamic random controller is used for reading a to-be-transmitted data stream from the data cache region and transmitting the to-be-transmitted data stream based on the data transmission channel. The data transmission efficiency is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of ship communication, and in particular, to a data management control system, a data management control method, a computer readable storage medium, and an electronic device. BACKGROUND

[0002] In the prior method, the data transmission channel cannot be dynamically adjusted, and thus the data transmission efficiency is low.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and thus can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to provide a data management control system, a data management control method, a computer readable storage medium, and an electronic device, thereby at least partially overcoming the problem of low data transmission efficiency caused by the limitations and defects of the related art.

[0005] According to one aspect of the present disclosure, a data management control system is provided, comprising:

[0006] An interface chip controller configured to receive a to-be-transmitted data stream transmitted by an interface and write the to-be-transmitted data stream into a data cache area;

[0007] A dynamic random access memory in communication connection with the interface chip controller, the dynamic random access memory comprising a data cache area, a dynamic random controller, and a data controller; wherein:

[0008] The data cache area is configured to cache the to-be-transmitted data stream;

[0009] The data controller is configured to dynamically adjust a data transmission channel for the to-be-transmitted data stream;

[0010] The dynamic random controller is configured to read the to-be-transmitted data stream from the data cache area and transmit the to-be-transmitted data stream based on the data transmission channel.

[0011] In an exemplary embodiment of the present disclosure, the interface chip controller comprises a serial interface chip controller and a USB interface chip controller; wherein:

[0012] The serial interface chip controller is configured to receive a first to-be-transmitted data stream transmitted through a serial data interface; and

[0013] Determine whether the first data stream to be transmitted includes interface management configuration information, and if it is determined that the first data stream to be transmitted includes the interface management configuration information, extract the interface management configuration information from the first data stream to be transmitted; and

[0014] When it is determined that the first data stream to be transmitted does not contain interface management configuration information, the first data stream to be transmitted is written into the data buffer area;

[0015] The USB interface chip controller is used to receive a second data stream to be transmitted via the USB data interface and write the second data stream to be transmitted into the data buffer.

[0016] In one exemplary embodiment of this disclosure, the first data stream to be transmitted includes interface management configuration information and / or navigation signal logs; the second data stream to be transmitted includes data information transmitted by the base station.

[0017] In one exemplary embodiment of this disclosure, the serial interface chip controller is further configured to:

[0018] Obtain the serial port data frame from the first data stream to be transmitted, and obtain the frame data type from the serial port data frame;

[0019] Determine whether the serial port data frame is interface management configuration information based on the frame data type.

[0020] In one exemplary embodiment of this disclosure, the data controller includes a controller configuration unit, a serial interface management structure, and a USB interface management structure; wherein:

[0021] The controller configuration unit is used to receive interface management configuration information sent by the serial interface chip controller, and extract the first management configuration information corresponding to the serial interface and the second management configuration information corresponding to the USB interface from the interface management configuration information; and

[0022] Based on the first management configuration information, the first original configuration information in the serial interface management structure is updated to obtain the first configuration information update result; and based on the second configuration information, the second original configuration information in the USB interface management structure is updated to obtain the second configuration information update result; and

[0023] The first data transmission channel of the first data stream to be transmitted is determined based on the first configuration information update result, and the second data transmission channel of the second data stream to be transmitted is determined based on the second configuration information update result.

[0024] In one exemplary embodiment of this disclosure, the first data transmission channel includes a first sub-transmission channel: data buffer → embedded multimedia storage card, or a second sub-transmission channel: data buffer → direct memory access → programmable array logic;

[0025] The second data transmission channel includes a second sub-transmission channel: data buffer → direct memory access → programmable array logic, or a first sub-transmission channel: data buffer → embedded multimedia memory card.

[0026] In one exemplary embodiment of this disclosure, the controller configuration unit is further configured to:

[0027] The first original configuration information in the serial interface management structure is updated based on the first data priority, first data path, first starting address of the data buffer, and first address offset in the first management configuration information to obtain the first configuration information update result; and

[0028] The second original configuration information in the USB interface management structure is updated based on the second data priority, second data path, second starting address and second address offset of the data buffer in the second management configuration information to obtain the second configuration information update result.

[0029] In one exemplary embodiment of this disclosure, the data controller further includes a data arbitrator, which is used to update the first cache information address in the serial interface chip controller and the second cache information address in the USB interface chip controller in response to a data overflow signal emitted by the data buffer.

[0030] The serial interface chip controller is used to write the first data stream to be transmitted into the dynamic random access memory (DRAM) in other memory spaces besides the data cache area, based on the updated first cache information address.

[0031] The USB interface chip controller is used to write the second data stream to be transmitted into the memory space other than the data cache area in the dynamic random access memory based on the updated second cache information address.

[0032] In one exemplary embodiment of this disclosure, the arbitrator is further configured to update the first address offset in the serial interface management structure after the first data stream to be transmitted has been written; and

[0033] After the second data stream to be transmitted is written, the second address offset in the USB interface management structure is updated.

[0034] In one exemplary embodiment of this disclosure, the dynamic random controller is further configured to store the first data stream to be transmitted and / or the second data stream to be transmitted to an embedded multimedia memory card; and / or

[0035] The first data stream to be transmitted and / or the second data stream to be transmitted are transmitted to direct memory access, so as to transmit the first data stream to be transmitted and / or the second data stream to be transmitted to the programmable array logic via the direct memory access.

[0036] According to one aspect of this disclosure, a data management and control method is provided, configured in a dynamic random access memory (DRAM), the DRAM including a data buffer, a DRAM controller, and a data controller, the data management and control method comprising:

[0037] The data stream to be transmitted is received through the data buffer, and the data stream to be transmitted is buffered.

[0038] The data controller dynamically adjusts the data transmission channel for the data stream to be transmitted.

[0039] The dynamic random controller reads the data stream to be transmitted from the data buffer and transmits the data stream based on the data transmission channel.

[0040] In one exemplary embodiment of this disclosure, the data controller includes a controller configuration unit, a serial interface management structure, and a USB interface management structure;

[0041] Adjusting the data transmission channel for the data stream to be transmitted includes:

[0042] The controller configuration unit receives interface management configuration information sent by the serial interface chip controller, and extracts the first management configuration information corresponding to the serial interface and the second management configuration information corresponding to the USB interface from the interface management configuration information.

[0043] The first original configuration information in the serial interface management structure is updated based on the first management configuration information to obtain the first configuration information update result, and the second original configuration information in the USB interface management structure is updated based on the second configuration information to obtain the second configuration information update result.

[0044] The first data transmission channel of the first data stream to be transmitted is determined based on the first configuration information update result, and the second data transmission channel of the second data stream to be transmitted is determined based on the second configuration information update result.

[0045] In one exemplary embodiment of this disclosure, the first data transmission channel includes a first sub-transmission channel: data buffer → embedded multimedia storage card, or a second sub-transmission channel: data buffer → direct memory access → programmable array logic;

[0046] The second data transmission channel includes a second sub-transmission channel: data buffer → direct memory access → programmable array logic, or a first sub-transmission channel: data buffer → embedded multimedia memory card.

[0047] In one exemplary embodiment of this disclosure, updating the first original configuration information in the serial interface management structure based on the first management configuration information to obtain a first configuration information update result includes:

[0048] The first original configuration information in the serial interface management structure is updated based on the first data priority, the first data path, the first starting address and the first address offset of the data buffer in the first management configuration information to obtain the first configuration information update result.

[0049] According to one aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the data management and control method described in any of the preceding claims.

[0050] According to one aspect of this disclosure, an electronic device is provided, comprising:

[0051] Processor; and

[0052] Memory for storing the executable instructions of the processor;

[0053] The processor is configured to execute the data management and control method described above by executing the executable instructions.

[0054] This disclosure provides a data management and control system. On one hand, it caches the data stream to be transmitted through a data buffer; then, it dynamically adjusts the data transmission channel for the data stream to be transmitted through a data controller; finally, it reads the data stream to be transmitted from the data buffer through a dynamic random controller and transmits the data stream based on the data transmission channel. Because the data transmission channel can be dynamically adjusted for the data stream to be transmitted, it solves the problem of low data transmission efficiency in the prior art due to the inability to dynamically adjust the data transmission channel. On the other hand, because the data transmission channel can be dynamically adjusted for the data stream to be transmitted, and the data stream to be transmitted can be transmitted based on the data transmission channel, the memory utilization of the data buffer is improved.

[0055] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0056] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0057] Figure 1 The diagram schematically illustrates an example structure of a data management and control system according to an exemplary embodiment of the present disclosure.

[0058] Figure 2 The diagram illustrates an example application scenario of a data management and control system according to an exemplary embodiment of the present disclosure.

[0059] Figure 3 This diagram schematically illustrates an example data structure for managing configuration information for an interface according to an exemplary embodiment of this disclosure.

[0060] Figure 4 The diagram schematically illustrates a specific structural example of a data controller according to an exemplary embodiment of the present disclosure.

[0061] Figure 5 The diagram illustrates a scenario example of a data transmission channel according to an exemplary embodiment of the present disclosure.

[0062] Figure 6 The diagram illustrates a method flowchart of a data management control method according to an example embodiment of the present disclosure.

[0063] Figure 7 The diagram schematically illustrates a block diagram of a data management control device according to an exemplary embodiment of the present disclosure.

[0064] Figure 8 An electronic device for implementing a data management control method is illustrated according to an example embodiment of the present disclosure. Detailed Implementation

[0065] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0066] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0067] In current shipboard communication systems, different types of data information need to be transmitted through limited data interfaces at different communication phases. For example, during the signal traversal and search phase, the information acquisition system can adjust the strength of the search signal by collecting input information from the serial port, and the serial port information only needs to be stored in local flash memory as a navigation signal log. Furthermore, during the rapid signal locking phase, the input information collected by the information acquisition system through the serial port needs to be analyzed using the logic of the PL-side algorithm on the ZYNQ platform. Under these circumstances, with limited interfaces, the data acquired by the interface needs to have its transmission path adjusted according to the data type. Simultaneously, the serial port also needs to record the module's operation log into the EMMC, which involves multiple processing units interacting with the same interface, potentially leading to waiting conflicts and other issues. Therefore, to meet the requirement of real-time switching of data processing methods according to application scenarios, a new data path and corresponding memory management scheme need to be constructed, reusing the interface's data management system through real-time switching of the data path.

[0068] Based on this, this example implementation first provides a data management and control system. Specifically, refer to... Figure 1As shown, the data management and control system may include an interface chip controller 110 and a dynamic random access memory (DRAM) 120; wherein, the interface chip controller is communicatively connected to the DRAM; and in practical applications, the interface chip controller is used to receive data to be transmitted from the interface and write the data to be transmitted into a data buffer; further, the DRAM may include a data buffer 121, a dynamic random access controller 122, and a data controller 123; wherein, the data buffer is used to buffer the data stream to be transmitted; the data controller is used to dynamically adjust the data transmission channel for the data stream to be transmitted; and the dynamic random access controller is used to read the data stream to be transmitted from the data buffer and transmit the data stream to be transmitted based on the data transmission channel.

[0069] In the aforementioned data management and control system, on the one hand, the data stream to be transmitted is buffered through a data buffer; then, the data controller dynamically adjusts the data transmission channel for the data stream to be transmitted; finally, the dynamic random controller reads the data stream to be transmitted from the data buffer and transmits it based on the data transmission channel. Because the data transmission channel can be dynamically adjusted for the data stream to be transmitted, the problem of low data transmission efficiency in existing technologies due to the inability to dynamically adjust the data transmission channel can be solved. On the other hand, because the data transmission channel can be dynamically adjusted for the data stream to be transmitted, and the data stream to be transmitted can be transmitted based on the data transmission channel, the memory utilization rate of the data buffer is improved.

[0070] The data management and control system described in the exemplary embodiments of this disclosure will now be explained and described in detail with reference to the accompanying drawings.

[0071] First, the terms used in the exemplary embodiments of this disclosure will be explained and described.

[0072] ZYNQ platform: It is a scalable processing platform designed to provide the processing and computing performance required for high-end embedded applications such as video surveillance, automotive driver assistance, and factory automation. In practical applications, ZYNQ can be divided into two parts: ARM (Advanced RISC Machines, RISC microprocessors) and FPGA (Field Programmable Gate Array).

[0073] PS: (Processing System) refers to the SOC (System on Chip) part, which corresponds to the ARM part in ZYNQ, and is also the data processor in the example embodiment of this disclosure.

[0074] PL: (Programmable Logic), which corresponds to the FPGA part in ZYNQ.

[0075] DDR3: (Double-data-rate 3synchronous dynamic RAM), also known as third-generation double-data-rate synchronous dynamic random access memory; DDR3 is a widely used memory chip due to its advantages such as large capacity, high speed, and low power consumption.

[0076] EMMC (Embedded Multi-Media Card) is an embedded, non-volatile storage system that mainly consists of flash memory, a flash memory controller, and the EMMC protocol structure, packaged together in the form of a BGA (Ball Grid Array).

[0077] DMA (Direct Memory Access) is a technology that allows certain hardware subsystems (CPU peripherals) to exchange data directly with system memory without the direct involvement of the CPU. This method can significantly improve system data throughput and, in some cases, reduce CPU load.

[0078] FIFO (First-In-First-Out) is a data buffer that ensures the order of data.

[0079] Secondly, the technical implementation principles of the exemplary embodiments of this disclosure will be explained and described. Specifically, the data management and control system described in the exemplary embodiments of this disclosure is implemented based on the ZYNQ platform. Furthermore, the data management and control system described in the exemplary embodiments of this disclosure can include two complete data paths; the first data path is: from the input interface to DDR3, then through DMA to send data to the PL side, mainly for data that needs further processing by the PL side; the second data path is: from the input interface to DDR3, then through the eMMC write FIFO and finally written to the eMMC unit, used to store debugging and other related log information; furthermore, in practical applications, the data controller in the system can dynamically switch the transmission channel of data input from different input interfaces, improving the system's interface reuse rate and memory utilization efficiency in this scenario, and reducing the difficulty of data management. Furthermore, the data management and control system described in the exemplary embodiments of this disclosure, by setting up data monitoring, memory management, and data paths within the ZYNQ platform, solves the technical problem of multiple data reuse interfaces under limited interface conditions, improves interface utilization and memory utilization efficiency, and reduces the difficulty of data management.

[0080] The following will be about Figure 1 The data management and control system shown will be further explained and described. Specifically:

[0081] In one example embodiment, reference is made to... Figure 2 As shown, the interface chip controller described above may include a serial interface chip controller 201 and a USB interface chip controller 202. That is, in practical applications, the data to be received and transmitted can come from either a serial data interface or a USB data interface. Under this premise, the serial interface chip controller can be used to receive a first data stream to be transmitted via the serial data interface; the USB interface chip controller is used to receive a second data stream to be transmitted via the USB data interface and write the second data stream to be transmitted into the data buffer. Simultaneously, the first data stream to be transmitted may include interface management configuration information and / or navigation signal logs; the second data stream to be transmitted includes data information transmitted by the base station. The interface management configuration information may be manually entered by ship maintenance personnel through corresponding terminal equipment (such as a computer equipped with a ship maintenance system); the navigation signal log includes the ship's mileage, speed, signal status, fuel consumption, etc., during navigation; the data information transmitted by the base station may include corresponding operating instructions, weather signals, etc., which are not specifically limited in this example.

[0082] In one example embodiment, the serial interface chip controller described above can also be used to: determine whether the first data stream to be transmitted includes interface management configuration information, and when it is determined that the first data stream to be transmitted includes the interface management configuration information, extract the interface management configuration information from the first data stream to be transmitted; further, when it is determined that the first data stream to be transmitted does not include interface management configuration information, write the first data stream to be transmitted into the data buffer; that is, in practical applications, in order to dynamically configure data transmission channels for the first data stream to be transmitted and / or the second data stream to be transmitted, it is necessary to determine in real time whether the first data stream to be transmitted transmitted through the serial data interface includes interface management configuration information; in practical applications, the specific data presentation format of the serial port data frame transmitted by the serial data interface can be referred to Figure 3 As shown; further, in Figure 3The serial port data frame (301) shown adds a frame header, frame trailer, and frame data type to the collected module information and the user-defined configuration information. This data frame is used to dynamically modify the data path (i.e., data transmission channel) of the interface online through the data controller, thereby simplifying the modification process. The frame consists of a frame header (0x55 0xA5) + 5 bytes of data + a frame trailer (0xF0). Furthermore, if the first data stream to be transmitted includes interface management configuration information, the interface management configuration information is extracted from the first data stream to be transmitted. The specific information format of the interface management configuration information can be found in [reference needed]. Figure 3 As shown in 302, the parameter information in the interface management configuration information can be referenced. Figure 3 As shown in 303; the parameter information recorded here may include priority, data transmission channel, and cache address, etc.

[0083] In one example embodiment, the serial interface chip controller described above is further configured to: acquire serial port data frames from the first data stream to be transmitted, and acquire the frame data type in the serial port data frames; determine whether the serial port data frame is interface management configuration information based on the frame data type. That is, in practical applications, it can be determined according to... Figure 3 The data type of the serial port data frame shown indicates whether it includes interface management configuration information. In practical applications, the flag in the serial port data frame can be used to determine whether it contains interface management configuration information.

[0084] In one example embodiment, the data controller described above is a module implemented using a programming language (e.g., C, or other programming languages) and running on the bare metal PS side of the ZYNQ. It can be used to control the matching of two input interfaces (serial data interface and USB data interface) with two output channels: one for writing to the eMMC module and the other for communication with the PL side, thereby forming a data processing path. Furthermore, externally to the data controller, DDR3 serves as a data transfer center, providing DMA-mapped addresses and eMMC for writing data. Even further, in practical applications, since writing the first and / or second data streams to be transmitted into the data buffer requires implementation based on the data input channels, therefore, [further details are needed]. Figure 2As shown, in this data management and control system, a first data input channel 203 and a second data input channel 204 also need to be set. The first data input channel may include a serial interface channel data FIFO and a serial interface channel address FIFO; the second data input channel may include a USB interface channel data FIFO and a USB interface channel address FIFO. Furthermore, the data bit width of the serial interface channel data FIFO, the serial interface channel address FIFO, the USB interface channel data FIFO, and the USB interface channel address FIFO is consistent with the data bit width of the DDR3 controller. Moreover, the serial interface channel address FIFO and the USB interface channel address FIFO are managed by the data controller and allocated independent address spaces in memory.

[0085] In one example embodiment, reference is made to... Figure 4 As shown, the data controller described above may include a controller configuration unit 401, a serial interface management structure 402, and a USB interface management structure 403. The serial interface management structure and the USB interface management structure may each include a data transmission channel, a starting address, an address offset, and a priority. In practical applications, the controller configuration unit receives interface management configuration information sent by the serial interface chip controller and extracts the first management configuration information corresponding to the serial data interface and the second management configuration information corresponding to the USB interface from the interface management configuration information. Further, it can update the first original configuration information in the serial interface management structure based on the first management configuration information to obtain a first configuration information update result, and update the second original configuration information in the USB interface management structure based on the second configuration information to obtain a second configuration information update result. Even further, it can determine the first data transmission channel of the first data stream to be transmitted based on the first configuration information update result, and determine the second data transmission channel of the second data stream to be transmitted based on the second configuration information update result.

[0086] In one example embodiment, reference continues to... Figure 4As shown, in practical applications, if it is determined that interface management configuration information exists in the first data stream to be transmitted, this interface management configuration information can be passed to the controller configuration unit. The controller configuration unit then updates the data transmission channel, start address, address offset, and priority in the serial interface management structure and the USB interface management structure. In the specific update process, the first original configuration information in the serial interface management structure can be updated based on the first data priority, first data path, first start address, and first address offset of the data buffer in the first management configuration information, resulting in a first configuration information update result. Furthermore, the second original configuration information in the USB interface management structure can also be updated based on the second data priority, second data path, second start address, and second address offset of the data buffer in the second management configuration information, resulting in a second configuration information update result.

[0087] It's worth noting that by setting the starting address and address offset, the storage space for the serial data interface and USB data interface in the data buffer can be dynamically allocated. For example, if the serial data interface is only used to receive configuration and log information from the detection module, while the USB data interface needs to receive information transmitted by the base station, then the occupancy rate of the serial data interface in the data buffer needs to be reduced, while the occupancy rate of the USB data interface needs to be increased. This approach improves the efficiency of the data buffer and alleviates the transmission pressure caused by the asynchronous data production and consumption on the PS side. Further explanation is needed here: setting the priorities of the serial and USB data interfaces ensures the order of data processing. The starting address and address offset can determine whether there is any backlogged data in the data buffer. For example, if high-priority data exists, it needs to be processed first and transmitted to the corresponding data transmission channel. Of course, if the first and second data streams to be transmitted for the serial and USB data interfaces need to be transmitted through different data transmission channels, the impact of data priority can be ignored, and the data transmission tasks can be executed according to their order in the data buffer.

[0088] In one example embodiment, the first data transmission channel described above may include a first sub-transmission channel: a data buffer (FIFO) → an embedded multimedia memory card (EMMC unit), or a second sub-transmission channel: a data buffer (FIFO) → direct memory access (DMA) → programmable array logic (PL); the second data transmission channel described here includes a second sub-transmission channel: a data buffer → direct memory access → programmable array logic, or a first sub-transmission channel: a data buffer → an embedded multimedia memory card. Under this premise, when transmitting the data stream to be transmitted through the dynamic random controller, it can be achieved as follows: storing the first data stream to be transmitted and / or the second data stream to be transmitted to the embedded multimedia memory card; transmitting the first data stream to be transmitted and / or the second data stream to be transmitted to direct memory access, so as to transmit the first data stream to be transmitted and / or the second data stream to be transmitted to the programmable array logic through the direct memory access. The first sub-transmission channel described here can be referred to... Figure 5 As shown in 501, the second sub-transmission channel can be referenced. Figure 5 As shown in 502; whether it needs to be transmitted through the first or second sub-transmission channel is determined by the interface management configuration information. Furthermore, after the data controller receives the DMA transmission completion interrupt signal and the EMMC write completion signal, it also needs to modify the address offset information in the management structure to overwrite the old data (i.e., the data that has been transmitted) based on the validity of the data.

[0089] In one example embodiment, reference continues to... Figure 4As shown, the data controller described above may further include a data arbitrator 404. This data arbitrator is used to update the first cache information address in the serial interface chip controller and the second cache information address in the USB interface chip controller in response to a data overflow signal emitted by the data buffer. That is, in practical applications, if too much data is cached in the data buffer, a data overflow signal needs to be triggered and transmitted to the data arbitrator. Upon receiving the data overflow signal, the data arbitrator can respond to it and perform specific data arbitration. Furthermore, during the specific data arbitration process, higher-priority data transmission channels can be prioritized and modified... The DMA mapping method; under this premise, the aforementioned serial interface chip controller can be used to write the first data stream to be transmitted into the memory space other than the data buffer area in the dynamic random access memory based on the updated first cache information address; the aforementioned USB interface chip controller is used to write the second data stream to be transmitted into the memory space other than the data buffer area in the dynamic random access memory based on the updated second cache information address; furthermore, after the first data stream to be transmitted is written, the first address offset in the serial interface management structure is updated; and after the second data stream to be transmitted is written, the second address offset in the USB interface management structure is updated. In other words, in practical applications, if the data in the data buffer FIFO exceeds the FIFO threshold, a data overflow signal will be triggered and transmitted to the data arbitrator. After receiving the data overflow signal, the data arbitrator can update the write address cache information in the data input channel according to the priority, so that the interface chip controller can write the data stream to be transmitted into the specified memory space in DDR3 based on the updated write address cache information. After the data is written, the address offset information in the serial interface management structure 402 and the USB interface management structure 403 also needs to be updated.

[0090] Thus, the data management and control system described in the exemplary embodiments of this disclosure has been fully implemented. Furthermore, the exemplary embodiments of this disclosure also provide a data management and control method, configured in a dynamic random access memory (DRAM), wherein the DRAM includes a data buffer, a DRAM controller, and a data controller. Further, refer to... Figure 6 As shown, the data management and control method may include the following steps:

[0091] Step S610: Receive the data stream to be transmitted through the data buffer and buffer the data stream to be transmitted;

[0092] Step S620: The data transmission channel is dynamically adjusted for the data stream to be transmitted by the data controller;

[0093] Step S630: Read the data stream to be transmitted from the data buffer through the dynamic random controller, and transmit the data stream to be transmitted based on the data transmission channel.

[0094] In one exemplary embodiment, adjusting the data transmission channel for the data stream to be transmitted can be achieved as follows: First, the controller configuration unit receives interface management configuration information sent by the serial interface chip controller, and extracts the first management configuration information corresponding to the serial interface and the second management configuration information corresponding to the USB interface from the interface management configuration information; second, the first original configuration information in the serial interface management structure is updated based on the first management configuration information to obtain a first configuration information update result, and the second original configuration information in the USB interface management structure is updated based on the second configuration information to obtain a second configuration information update result; then, the first data transmission channel of the first data stream to be transmitted is determined based on the first configuration information update result, and the second data transmission channel of the second data stream to be transmitted is determined based on the second configuration information update result.

[0095] In one exemplary embodiment, the first data transmission channel includes a first sub-transmission channel: data buffer → embedded multimedia memory card, or a second sub-transmission channel: data buffer → direct memory access → programmable array logic; the second data transmission channel includes a second sub-transmission channel: data buffer → direct memory access → programmable array logic, or a first sub-transmission channel: data buffer → embedded multimedia memory card.

[0096] In one exemplary embodiment, updating the first original configuration information in the serial interface management structure based on the first management configuration information to obtain the first configuration information update result can be achieved in the following way: updating the first original configuration information in the serial interface management structure based on the first data priority, the first data path, the first starting address of the data buffer, and the first address offset in the first management configuration information to obtain the first configuration information update result.

[0097] The data management and control methods described above will be further explained and illustrated below. Specifically, in practical applications, they can be implemented in the following ways:

[0098] First, receive the first or second data stream to be transmitted via the serial data interface / USB data interface. Second, determine whether the first data stream to be transmitted contains interface management configuration information. Since the data path needs to be dynamically set, interface management configuration information is required for adjustment. Then, if interface management configuration information exists, the serial port and USB priority, starting address, and corresponding address offset need to be modified according to the frame data. At the same time, the corresponding data transmission channel selection scheme is as follows: When the system powers on, the serial port defaults to the memory starting address and data length of DMA mapping, and the write data address and total data buffer length of eMMC are set during system initialization. If the serial port chooses to transmit data to the PL side via DMA in this configuration, the memory space starting address in the serial port management structure can be modified to the DMA corresponding mapping address. The path matching method is changed by modifying the correspondence of memory spaces. Furthermore, if the serial port data does not contain configuration information and is a data frame, the relevant data is read into the corresponding channel buffer FIFO. When the set FIFO threshold is exceeded, a FIFO overflow signal is triggered, and the data processing continues. Further still, the data arbitrator responds to the data processing flow, updating the write address buffer information in the input channel according to priority and the memory address information in the data controller, and then sequentially writes it to the specified DDR3 memory space. After the write is complete, the address offset information in the management structure of the data controller is updated. Finally, after the DDR3 write is complete, it needs to wait for the data transmission to be further transmitted to the specified chip, waiting for the DMA transmission end interrupt signal and the eMMC write end signal. After the transmission is completed, the address offset information in the management structure is modified to overwrite the old data based on the validity of the data.

[0099] Thus, the data management and control method described in the exemplary embodiments of this disclosure has been fully implemented. Based on the foregoing description, it can be understood that the data management and control method described in the exemplary embodiments of this disclosure, on the one hand, improves memory utilization; in scenarios where platform memory is limited, data priority settings improve the efficiency of parallel access to memory by multiple data channels; on the other hand, it improves data processing efficiency; specific data path encapsulation ensures data processing efficiency and switching efficiency, simplifies repetitive development work for data path switching, and improves interface reusability.

[0100] The following are embodiments of the apparatus disclosed herein, which can be used to execute embodiments of the method disclosed herein. For details not disclosed in the apparatus embodiments of this disclosure, please refer to the embodiments of the method disclosed herein.

[0101] This disclosure also provides a data management and control device configured in a dynamic random access memory (DRAM), the DRAM including a data buffer, a DRAM controller, and a data controller. Specifically, refer to... Figure 7As shown, the data management and control device may include a data stream buffer module 710, a data transmission channel adjustment module 720, and a data stream transmission module 730. Wherein:

[0102] The data stream buffer module 710 can be used to receive the data stream to be transmitted through the data buffer area and to buffer the data stream to be transmitted.

[0103] The data transmission channel adjustment module 720 can be used to dynamically adjust the data transmission channel for the data stream to be transmitted through the data controller;

[0104] The data stream transmission module 730 can be used to read the data stream to be transmitted from the data buffer through the dynamic random controller, and transmit the data stream to be transmitted based on the data transmission channel.

[0105] In one exemplary embodiment of this disclosure, the data controller includes a controller configuration unit, a serial interface management structure, and a USB interface management structure; wherein, adjusting the data transmission channel for the data stream to be transmitted includes: receiving interface management configuration information sent by a serial interface chip controller through the controller configuration unit, and extracting first management configuration information corresponding to the serial interface and second management configuration information corresponding to the USB interface from the interface management configuration information; updating the first original configuration information in the serial interface management structure based on the first management configuration information to obtain a first configuration information update result, and updating the second original configuration information in the USB interface management structure based on the second configuration information to obtain a second configuration information update result; determining a first data transmission channel for the first data stream to be transmitted based on the first configuration information update result, and determining a second data transmission channel for the second data stream to be transmitted based on the second configuration information update result.

[0106] In one exemplary embodiment of this disclosure, the first data transmission channel includes a first sub-transmission channel: data buffer → embedded multimedia memory card, or a second sub-transmission channel: data buffer → direct memory access → programmable array logic; the second data transmission channel includes a second sub-transmission channel: data buffer → direct memory access → programmable array logic, or a first sub-transmission channel: data buffer → embedded multimedia memory card.

[0107] In one exemplary embodiment of this disclosure, updating the first original configuration information in the serial interface management structure based on the first management configuration information to obtain a first configuration information update result includes: updating the first original configuration information in the serial interface management structure based on the first data priority, the first data path, the first starting address of the data buffer, and the first address offset in the first management configuration information to obtain a first configuration information update result.

[0108] The specific details of each module in the aforementioned data management and control device have been described in detail in the corresponding data management and control methods, so they will not be repeated here.

[0109] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0110] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0111] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0112] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0113] The following reference Figure 8 To describe an electronic device 800 according to such an embodiment of the present disclosure. Figure 8 The electronic device 800 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0114] like Figure 8As shown, the electronic device 800 is manifested in the form of a general-purpose computing device. The components of the electronic device 800 may include, but are not limited to: at least one processing unit 810, at least one storage unit 820, a bus 830 connecting different system components (including storage unit 820 and processing unit 810), and a display unit 840.

[0115] The storage unit stores program code that can be executed by the processing unit 810, causing the processing unit 810 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 810 can perform actions such as... Figure 1 The steps shown are as follows: Step S110: Receive the data stream to be transmitted through the data buffer and buffer the data stream to be transmitted; Step S120: Dynamically adjust the data transmission channel for the data stream to be transmitted through the data controller; Step S130: Read the data stream to be transmitted from the data buffer through the dynamic random controller and transmit the data stream to be transmitted based on the data transmission channel.

[0116] Storage unit 820 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 8201 and / or cache memory 8202, and may further include a read-only memory (ROM) 8203.

[0117] The storage unit 820 may also include a program / utility 8204 having a set (at least one) of program modules 8205, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0118] Bus 830 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0119] Electronic device 800 can also communicate with one or more external devices 900 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 800, and / or with any device that enables electronic device 800 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 850. Furthermore, electronic device 800 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 via bus 830. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0120] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0121] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible implementations, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of this disclosure described in the "Exemplary Methods" section above.

[0122] The program product for implementing the above-described method according to embodiments of the present disclosure may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0123] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0124] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0125] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0126] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0127] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0128] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention described herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not invented by this disclosure. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A data management control system, characterized by, The application relates to an interface chip controller for receiving a data stream to be transmitted sent by an interface and writing the data stream to be transmitted into a data buffer area. The application relates to a dynamic random memory in communication connection with the interface chip controller, wherein the dynamic random memory comprises a data buffer area, a dynamic random controller and a data controller. The data buffer area is used for buffering the data stream to be transmitted. The data controller is used for dynamically adjusting a data transmission channel for the data stream to be transmitted. The dynamic random controller is used for reading the data stream to be transmitted from the data buffer area and transmitting the data stream to be transmitted based on the data transmission channel. The interface chip controller comprises a serial interface chip controller and a USB interface chip controller.

2. The data management control system of claim 1, wherein, The serial interface chip controller is used for receiving a first data stream to be transmitted transmitted through a serial data interface. The serial interface chip controller is further used for: The data controller comprises a controller configuration unit, a serial interface management structure and a USB interface management structure. The controller configuration unit is used for receiving interface management configuration information sent by the serial interface chip controller and extracting first management configuration information corresponding to the serial interface and second management configuration information corresponding to the USB interface in the interface management configuration information. The data controller is used for dynamically adjusting a data transmission channel for the data stream to be transmitted.

3. The data management control system of claim 2, wherein, The dynamic random controller is used for reading the data stream to be transmitted from the data buffer area and transmitting the data stream to be transmitted based on the data transmission channel. The serial interface chip controller is further used for: The data controller comprises a controller configuration unit, a serial interface management structure and a USB interface management structure.

4. The data management control system of claim 1, wherein, The controller configuration unit is used for receiving interface management configuration information sent by the serial interface chip controller and extracting first management configuration information corresponding to the serial interface and second management configuration information corresponding to the USB interface in the interface management configuration information. The first data transmission channel comprises a first sub-transmission channel: data buffer area -> embedded multimedia memory card, or a second sub-transmission channel: data buffer area -> direct memory access -> programmable array logic. The second data transmission channel comprises a second sub-transmission channel: data buffer area -> direct memory access -> programmable array logic, or a first sub-transmission channel: data buffer area -> embedded multimedia memory card. The controller configuration unit is further used for:

5. The data management control system of claim 4, wherein, ​ ​ 6. The data management control system of claim 4, wherein, ​ updating first original configuration information in the serial interface management structure based on a first data priority, a first data path, a first start address and a first address offset of the data buffer area in the first management configuration information, to obtain a first configuration information updating result; and updating second original configuration information in the USB interface management structure based on a second data priority, a second data path, a second start address and a second address offset of the data buffer area in the second management configuration information, to obtain a second configuration information updating result.

7. The data management control system of claim 1, wherein, The data controller further comprises a data arbitrator, which is configured to update a first buffer information address in the serial interface chip controller and a second buffer information address in the USB interface chip controller in response to a data overflow signal sent by the data buffer area; The serial interface chip controller is configured to write the first to-be-transmitted data stream into a memory space other than the data buffer area in the dynamic random access memory based on the updated first buffer information address; The USB interface chip controller is configured to write the second to-be-transmitted data stream into a memory space other than the data buffer area in the dynamic random access memory based on the updated second buffer information address.

8. The data management control system of claim 7, wherein, The arbitrator is further configured to update the first address offset in the serial interface management structure after the writing of the first to-be-transmitted data stream is completed; and update the second address offset in the USB interface management structure after the writing of the second to-be-transmitted data stream is completed.

9. The data management control system of claim 1, wherein, The dynamic random controller is further configured to store the first to-be-transmitted data stream and / or the second to-be-transmitted data stream to an embedded multimedia memory card; and / or transmit the first to-be-transmitted data stream and / or the second to-be-transmitted data stream to a direct memory access, so as to transmit the first to-be-transmitted data stream and / or the second to-be-transmitted data stream to a programmable array logic through the direct memory access.

10. A data management control method characterized by comprising: The dynamic random memory is configured to include a data buffer area, a dynamic random controller and a data controller, and the data management control method comprises: receiving a to-be-transmitted data stream through the data buffer area and buffering the to-be-transmitted data stream; dynamically adjusting a data transmission path for the to-be-transmitted data stream through the data controller; reading the to-be-transmitted data stream from the data buffer area through the dynamic random controller and transmitting the to-be-transmitted data stream based on the data transmission path.

11. The data management control method according to claim 10, wherein The data controller comprises a controller configuration unit, a serial interface management structure and a USB interface management structure; wherein adjusting the data transmission path for the to-be-transmitted data stream comprises: receiving interface management configuration information sent by a serial interface chip controller through the controller configuration unit, and extracting first management configuration information corresponding to the serial interface and second management configuration information corresponding to the USB interface in the interface management configuration information; update first original configuration information in the serial interface management structure based on the first management configuration information to obtain a first configuration information update result, and update second original configuration information in the USB interface management structure based on second configuration information to obtain a second configuration information update result; determine a first data transmission channel of a first to-be-transmitted data stream based on the first configuration information update result, and determine a second data transmission channel of a second to-be-transmitted data stream based on the second configuration information update result.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the data management control method of claim 10 or 11.

13. An electronic device, comprising: comprise: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the data management control method of claim 10 or 11 by executing the executable instructions.

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