Chip BootLoader dual-mode configuration system

Abstract

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.

Description

Technical Field

[0001] This application belongs to the field of chip bootloader technology, and more specifically, relates to a dual-mode configuration system for chip bootloader. Background Technology

[0002] As the core boot component after the chip is powered on, the BootLoader plays a crucial role in chip initialization, program loading, and basic configuration, and is widely used in various embedded chips such as microcontrollers (MCUs) and digital signal processors (DSPs).

[0003] The existing BootLoader technology generally has the following defects. (1) Insufficient security: The communication layer mostly uses UART channel to transmit data, and only relies on simple mechanisms such as parity check to ensure data integrity. The data field is not encrypted, and the data is easily intercepted and tampered with. During the program loading process, the code in the external Flash (such as QSPI-Flash) is directly read without being encrypted in combination with the chip's unique identifier (such as device ID, management ID). There is a risk that the code in the Flash can be illegally read and reused. (2) Poor flexibility and compatibility: The working mode is single and only supports the program loading and booting function. If it is necessary to configure the chip registers or RAM, it is necessary to connect additional debugging tools such as J-Link. It cannot be completed by the BootLoader itself interacting with the host computer. The Flash configuration parameters (such as read command, page size, communication rate) are fixed in the BootLoader code. When changing to different models of Flash, the BootLoader code needs to be modified and recompiled, and it cannot be dynamically adapted. (3) Low reliability: Integrity verification only targets the program code and lacks an independent verification mechanism for configuration parameters such as boot address and program length. If the parameters are incorrect, the program may fail to load. The program loading process only performs a single verification and has no multi-layer verification protection. Data transmission errors may cause boot abnormalities. (4) Low operation efficiency: Chip configuration depends on external debugging tools and the operation steps are cumbersome. Mode switching needs to be achieved through hardware plugging and unplugging, which cannot quickly respond to different scenario requirements. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a dual-mode configuration system for a chip bootloader, which can achieve secure, flexible and reliable chip booting and configuration through dynamic switching between dual modes and encryption based on the chip's unique information.

[0005] In a first aspect, this application provides a dual-mode configuration system for a chip bootloader, integrated into the chip's internal ROM, including an OTP storage module, a dual-mode control module, a UART communication module, a key generation module, a CRC32 verification module, a QSPI interface module, and a command processing module; The OTP storage module is used to store the chip's unique information and SPI_FLASH parameters; The dual-mode control module is used to trigger the corresponding working mode through the level state of the Boot pin; wherein, when the Boot pin is low, the configuration mode is triggered, and when it is high, the program loading and booting mode is triggered. The UART communication module is used to transmit command frames and response frames with the host computer in configuration mode and to report error logs in program loading and booting mode. The key generation module is used to generate a communication key through a first key generation logic in configuration mode, and to generate a program encryption key through a second key generation logic in program loading and booting mode. The CRC32 verification module is used to verify the plaintext of the data field of the UART communication frame in configuration mode and to verify the data in the QSPI-Flash in program loading and boot mode. The QSPI interface module is configured to read data from the QSPI-Flash in single-wire mode according to the SPI_FLASH parameters loaded by the OTP storage module in the program loading boot mode. The command processing module is used to parse the host computer command in configuration mode, execute the corresponding operation, and return the corresponding response frame.

[0006] In some embodiments, in configuration mode: The OTP storage module synchronously transmits the stored chip unique information and SPI_FLASH parameters to the UART communication module, CRC32 verification module, and command processing module via the internal bus for initialization. The host computer sends a version read command via the UART communication module. The command processing module retrieves the version data from the OTP storage module and then sends it back to the host computer via the UART communication module. The key generation module generates a communication key based on the version data provided by the OTP storage module and transmits it to the UART communication module. The host computer encrypts the command frame it sends and transmits it to the UART communication module. The UART communication module decrypts the command frame using the communication key and transmits the decrypted data to the CRC32 verification module for verification. Data that passes the verification is then sent to the command processing module to execute the corresponding command. The execution result is encrypted by the UART communication module and fed back to the host computer in the form of a response frame.

[0007] In some embodiments, the command frames issued by the host computer include read / write register, read / write SRAM, software reset, and program boot.

[0008] In some embodiments, under program loading boot mode: The OTP storage module synchronously transmits the stored chip unique information and SPI_FLASH parameters to the QSPI interface module, CRC32 verification module and UART communication module via the internal bus for initialization. After the QSPI interface module completes the communication mode configuration according to the SPI_FLASH parameters, it sends a command to the QSPI-Flash to make it exit the low-power mode, and reads data from it and transmits it to the CRC32 verification module through the chip's internal bus. After the CRC32 verification module verifies the received data, it writes it into SRAM, and the chip core retrieves the data and executes the program.

[0009] In some embodiments, the QSPI interface module reads the data in the Code_Info area and the Code area from the QSPI-Flash and transmits it to the CRC32 verification module via the chip's internal bus. The CRC32 verification module first verifies the data in the Code_Info area. If it fails, the UART communication module reports the log and terminates the process. After the verification passes, it verifies the Code area. If it fails, the UART communication module reports the log and terminates the process. If it succeeds, the data in the Code area is written to the SRAM, and the chip core retrieves the data and executes the program.

[0010] In some embodiments, the key generation module generates a program encryption key based on the chip unique information provided by the OTP storage module and transmits it to the QSPI interface module. The QSPI interface module uses the program encryption key to decrypt and read the program code read from the QSPI-Flash. The program code in the SPI-Flash is encrypted and stored based on the chip unique information.

[0011] In some embodiments, the chip's unique information includes a 32-bit CHIP_ID, a 16-bit CHIP_VERSION, and a 192-bit SID; the SPI_FLASH parameters include read ID command, read data command, read start address, page size, clock phase / polarity, and communication rate.

[0012] In some embodiments, the key generation module combines the 16-bit CHIP_VERSION high byte with the 16-bit BootLoader version to form a 32-bit version information, XORs it with the 32-bit CHIP_ID, and then XORs it with the constant 0xA55A5AA5 to generate a 32-bit communication key.

[0013] In some embodiments, the key generation module divides the 192-bit SID into six groups of 4-bit data, XORs them sequentially, and then XORs them with the constant 0xA55A5AA5 to generate a 32-bit program encryption key.

[0014] Secondly, this application also provides a chip that integrates the chip BootLoader dual-mode configuration system described in any one of the first aspects.

[0015] This application describes a dual-mode configuration system for a chip bootloader. By flexibly switching between configuration and program loading modes using boot pin levels, it adapts to diverse scenarios, significantly optimizing compatibility and flexibility. Furthermore, based on the chip's unique information, a dual-key differentiation mechanism generates a communication key and a program encryption key, significantly enhancing security and preventing unauthorized intrusion and data leakage. This achieves secure, flexible, and reliable chip booting and configuration, meeting the application needs of embedded chips in industrial control, automotive electronics, and the Internet of Things. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This illustration shows a schematic diagram of how the system in this application triggers the corresponding operating mode through the Boot pin level state; Figure 2 This illustration shows a schematic diagram of the system's workflow in configuration mode according to an embodiment of this application; Figure 3 This diagram illustrates the workflow of the system in the program loading and boot mode according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0019] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0021] In view of the technical problems mentioned in the background art, this application provides a dual-mode configuration system for chip bootloader, which can achieve secure, flexible and reliable chip booting and configuration through dynamic switching between dual modes and encryption based on the chip's unique information.

[0022] This application provides a dual-mode configuration system for a chip bootloader, integrated into the chip's internal ROM. It includes an OTP storage module, a dual-mode control module, a UART communication module, a key generation module, a CRC32 verification module, a QSPI interface module, and a command processing module. The OTP storage module stores the chip's unique information and SPI_FLASH parameters. The unique chip information includes a 32-bit CHIP_ID (device unique identifier), a 16-bit CHIP_VERSION (chip version number), and a 192-bit SID (chip management unique identifier). The SPI_FLASH parameters include read ID command, read data command, read start address, page size, clock phase / polarity, and communication rate. After the chip powers on, the OTP controller automatically loads the above parameters into the system register, providing data support for subsequent modules.

[0023] See the instruction manual appendix Figure 1 The dual-mode control module determines and triggers the operating mode based on the Boot pin level: when the Boot pin is low, the system enters configuration mode; when the Boot pin is high, the system enters program loading and booting mode, enabling power-on switching between the two modes without the need for external tools or additional communication steps. The two modes are fundamentally isolated through hardware pin levels, ensuring safe debugging and stable operation.

[0024] In this application, the dual-mode design of the chip BootLoader, consisting of a configuration mode and a program loading and guiding mode, addresses the differentiated needs of the chip throughout its entire lifecycle, from production debugging to stable operation, through functional decomposition and precise scenario adaptation. Compared to a single-mode design, it offers multiple significant advantages, including secure isolation, adaptation to diverse scenarios, and improved operating efficiency.

[0025] Specifically, the configuration mode focuses on chip debugging and parameter configuration (such as reading and writing registers, RAM, and software reset), while the program loading and booting mode focuses on secure program loading and execution (such as reading Flash programs and verifying code integrity). This avoids interference between debugging and program loading operations, prevents misoperations during the debugging phase from disrupting the program loading process, and also eliminates the possibility of external commands affecting the security of configuration parameters during program loading. The configuration mode supports interactive debugging between the host computer and the chip, allowing flexible modification of chip registers and RAM parameters to meet the needs of parameter calibration, functional testing, and troubleshooting during chip production, eliminating the need for a separate debugging system and simplifying the production process. The program loading and booting mode automatically completes Flash program reading, decryption, verification, and execution without manual intervention, adapting to the requirement of automatic startup after chip delivery and meeting the practical application scenario of embedded devices running immediately upon power-on. Thus, both modes are integrated into the same BootLoader system, eliminating the need to develop two separate firmware sets for debugging and program loading, reducing code redundancy and development workload.

[0026] The UART communication module is used to communicate with the host computer in configuration mode at a baud rate of 115200bps, with a frame format of 1 start bit + 1 stop bit + no parity, to transmit command frames and response frames; and in program loading and booting mode, it is used to report error logs (such as parameter verification failure, program verification failure).

[0027] The key generation module provides two key generation logics: a communication key is generated using a first key generation logic in configuration mode, and a program encryption key is generated using a second key generation logic in program loading and booting mode. That is, this application designs independent key generation rules for the different security requirements of configuration mode and program loading and booting mode.

[0028] In one embodiment, in configuration mode, the 16-bit CHIP_VERSION (high byte) and the 16-bit BootLoader version number (low byte) are combined to form 32-bit version information. This information is first XORed with the 32-bit CHIP_ID, and then XORed with the constant 0xA55A5AA5 to generate a 32-bit communication key for encryption of the communication data field. In program loading and booting mode, the 192-bit SID is divided into 6 groups of data in 4-byte blocks. These groups are XORed sequentially, and the result is then XORed with the constant 0xA55A5AA5 to generate a 32-bit program encryption key for encryption protection of off-chip Flash code.

[0029] This ensures that the communication key is bound to the CHIP_ID and version information, and the program encryption key is bound to a unique SID, guaranteeing that the key for each chip is independent and eliminating the risk of key reuse. Furthermore, the use of XOR operation makes hardware implementation simple and time-saving, eliminating the need for complex hash algorithms and adapting to the low-power and fast startup requirements of the BootLoader. In addition, a fixed constant 0xA55A5AA5 is introduced for final obfuscation to prevent the key strength from being reduced due to the original data (such as version number, SID part fields being 0), thereby improving the anti-cracking capability.

[0030] The CRC32 verification module is used in configuration mode to verify the plaintext of the command frame data field after decryption from the UART, ensuring the integrity of debugging commands issued by the host computer and preventing register and RAM read / write errors due to transmission errors. In program loading and booting mode, it performs CRC32 verification on the Code_Info area (configuration parameter area) and Code area (program code area) in the QSPI-Flash, first ensuring the validity of program parameters and then ensuring the integrity of program code, avoiding chip crashes caused by erroneous program execution. This achieves precise verification in different scenarios, preventing the flow of erroneous data. Furthermore, this logic of decryption before verification takes into account both encryption protection and the accuracy of verification results, forming a complete secure link of encrypted transmission / storage, decryption, verification, and execution.

[0031] The QSPI interface module operates only in program loading and boot mode. Based on the SPI_FLASH parameters loaded by the OTP storage module, the QSPI interface is configured as a single-wire communication mode. A command is sent to make the QSPI-Flash exit the low-power state. Then, the data in the Code_Info area and Code area of ​​the Flash is read and transferred to the chip's internal SRAM.

[0032] The command processing module operates only in configuration mode, receiving and parsing commands issued by the host computer, including read register, write register, read RAM, write RAM, software reset, and program boot. For read / write register commands, the command frame data field must include a signature (05H 50H A0H 0AH) and the target register address. After execution, it returns a response frame containing the register value (read command) or confirmation information (write command). For read / write RAM commands, the command frame data field must include a signature (05H 50H A0H), the target RAM address, and the data length (a multiple of 4 bytes). After execution, it returns a response frame. For software reset / program boot commands, the command frame data field must include a signature and a delay duration (in milliseconds). It first returns a confirmation frame, and after the delay, performs a reset or program boot operation (automatically initializing the program target address during boot).

[0033] The workflow for the two modes is explained below.

[0034] Participation instructions attached Figure 2 In configuration mode: Initialize data flow: After the chip is powered on, the OTP storage module transmits the stored chip unique information and various configuration parameters synchronously to the UART communication module, CRC32 verification module and command processing module through the chip's internal bus. After receiving the parameters, these modules complete their own initialization and prepare for subsequent work.

[0035] Version information interaction data flow: The host computer first sends the command to read the version information to the UART communication module, which then forwards the command to the command processing module. The command processing module retrieves relevant data such as CHIP_ID, CHIP_VERSION, and BootLoader version from the OTP storage module, and then integrates these data into a response frame via the UART communication module and sends it back to the host computer.

[0036] Encrypted communication data stream: The OTP storage module provides the key generation module with data such as CHIP_ID, CHIP_VERSION, and BootLoader version. The key generation module generates a communication key based on this and passes it to the UART communication module. The host computer encrypts the data field of the command frame it sends and sends it to the UART communication module. The UART communication module uses the communication key to decrypt the data. The decrypted data is transmitted to the CRC32 verification module for plaintext verification of the data field. Data that passes the verification is then sent to the command processing module to execute the corresponding command. After the command processing module completes the operation, it generates result data, which is encrypted by the UART communication module and fed back to the host computer in the form of a response frame.

[0037] Control operation data flow: The command processing module receives and executes read and write commands from the host computer, directly performing read and write operations on the chip's internal registers and RAM; when a software reset or program boot command is received, the command processing module first returns an acknowledgment response through the UART communication module, and then sends an execution signal to the system through the chip's internal bus. The system performs the reset or program boot operation, and exits the configuration mode after completion.

[0038] See the instruction manual appendix Figure 3 In program loading boot mode: Initialization of data flow: After the chip is powered on, the OTP storage module distributes the stored SPI_FLASH parameters, chip unique information and other data to the dual-mode control module, QSPI interface module, CRC32 verification module and UART communication module through the chip's internal bus. After receiving the data, each module completes its own initialization configuration and waits for subsequent instructions.

[0039] Flash data read data stream: The QSPI interface module first completes its own communication mode configuration based on the SPI_FLASH parameters obtained from the OTP storage module, then sends a command to the QSPI-Flash to make it exit the low power mode, and then reads the data of the Code_Info area and Code area from the QSPI-Flash. After reading, the data is transmitted to the CRC32 verification module for verification through the chip's internal bus.

[0040] Verification and execution data flow: The CRC32 verification module verifies the received Code_Info area data. If the verification fails, an error signal is sent to the UART communication module, which then reports the parameter verification failure log, and the entire program loading process terminates. If the verification passes, the CRC32 verification module then verifies the Code area data. If the verification fails, the UART communication module reports the program verification failure log and terminates the process. After all verifications pass, the Code area data is written to the SRAM via the internal bus. The chip core then retrieves the program data from the SRAM and jumps to the program's destination address to execute the program.

[0041] Encrypted data stream protection: The OTP storage module transmits the 192-bit SID and other unique chip information to the key generation module. The key generation module generates a program encryption key according to preset logic and then passes the key to the QSPI interface module. The QSPI interface module uses this key to encrypt and decrypt the program code read from the QSPI-Flash.

[0042] This application provides a dual-mode configuration system for a chip bootloader. Through communication encryption based on the chip's unique CHIP_ID and program encryption based on the unique SID, it achieves end-to-end security protection for communication and program, preventing data interception and tampering, and illegal code reuse. Simultaneously, CRC32 verification ensures data and program integrity, reducing security risks. The dual-mode design supports rapid switching via boot pin levels; the configuration process requires no external debugging tools, and the host computer can directly perform register / RAM read / write and system control. Flash parameters are dynamically read from the OTP, eliminating the need to modify the bootloader code when changing the Flash model, adapting to different Flash specifications, and reducing development and maintenance costs.

[0043] Furthermore, a multi-level verification system is constructed, comprising communication frame verification, Code_Info parameter verification, and Code program dual verification, comprehensively covering communication, parameter, and program stages. This avoids boot failures caused by data transmission errors, parameter configuration errors, or program corruption, thereby improving system stability. The configuration mode supports remote read / write and control, while the program loading mode is fully automated, requiring no manual intervention. Mode switching requires no hardware plugging or unplugging, achieving immediate response upon power-on, significantly simplifying the operation process and improving chip deployment and maintenance efficiency.

[0044] In other embodiments, the same inventive objective can also be achieved through the following alternatives.

[0045] Alternative key generation scheme: The CHIP_ID and SID are hashed using the SHA-256 hash algorithm, and the lower 32 bits of the result are used as the key. This scheme is more secure, but it requires the additional integration of the SHA-256 algorithm module, which increases the chip's computing power consumption and ROM usage. Preferably, this application chooses the XOR algorithm to balance security and resource cost.

[0046] Communication interface alternative: Use SPI interface instead of UART interface to realize host computer communication; SPI interface speed can reach 100MHz, which is higher than UART, but requires an additional 2-3 GPIO pins. Preferably, this application chooses UART interface to reduce hardware resource requirements and adapt to most host computer general interfaces.

[0047] Alternative verification algorithm: The MD5 algorithm is used instead of the CRC32 algorithm for verification. MD5 has stronger collision resistance, but its computational complexity is high, and the time taken for a single verification is about 5 times that of CRC32. Preferably, this application chooses the CRC32 algorithm to meet the time requirements of the BootLoader for fast booting.

[0048] Alternative mode switching solution: Mode switching is achieved by sending a mode switching command from the host computer instead of using the Boot pin level. This solution does not require hardware pins, but a communication connection must be established first, and it cannot achieve switching immediately upon power-on. Preferably, this application chooses pin level switching to improve response speed.

[0049] Based on the same inventive concept, this application also provides a chip integrating the dual-mode configuration system for chip bootloader described in any one of the above embodiments. Since the principle by which the chip in this application solves the problem is similar to the dual-mode configuration system for chip bootloader described in this application, the implementation of the chip can refer to the implementation of the method, and repeated details will not be elaborated further.

[0050] Finally, it should be noted that the above embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A chip BootLoader dual-mode configuration system, characterized in that, The internal ROM of the chip is integrated, including an OTP storage module, a dual-mode control module, a UART communication module, a key generation module, a CRC32 check module, a QSPI interface module and a command processing module; The OTP storage module is configured to store chip unique information and SPI_FLASH parameters. The dual-mode control module is configured to trigger a corresponding working mode through a Boot pin level state; when the Boot pin is at a low level, a configuration mode is triggered, and when the Boot pin is at a high level, a program loading boot mode is triggered. The UART communication module is configured to transmit a command frame and a response frame with a host computer in the configuration mode, and report an error log in the program loading boot mode. The key generation module is configured to generate a communication key through a first key generation logic in the configuration mode, and generate a program encryption key through a second key generation logic in the program loading boot mode. The CRC32 check module is configured to check a data field of a UART communication frame in the configuration mode, and check data in a QSPI-Flash in the program loading boot mode. The QSPI interface module is configured to configure a single-wire mode according to the SPI_FLASH parameters loaded by the OTP storage module in the program loading boot mode, and read data in the QSPI-Flash. The command processing module is configured to analyze a host computer command in the configuration mode, execute a corresponding operation, and return a corresponding response frame.

2. The chip BootLoader dual-mode configuration system of claim 1, wherein, In the configuration mode: The OTP storage module synchronously transmits the stored chip unique information and SPI_FLASH parameters to the UART communication module, the CRC32 check module and the command processing module through an internal bus for initialization. The host computer issues a version reading command through the UART communication module, the command processing module calls version data from the OTP storage module, and then feeds back the version data to the host computer through the UART communication module. The key generation module generates a communication key according to the version data provided by the OTP storage module and transmits the communication key to the UART communication module; the host computer transmits the encrypted command frame to the UART communication module, the UART communication module decrypts the data using the communication key, and transmits the decrypted data to the CRC32 check module for checking; the data that passes the checking is sent to the command processing module to execute a corresponding command, and the execution result is fed back to the host computer in the form of a response frame after being encrypted by the UART communication module.

3. The chip BootLoader dual-mode configuration system of claim 2, wherein, The command frame issued by the host computer includes reading / writing a register, reading / writing SRAM, software reset and program boot.

4. The dual-mode configuration system for chip BootLoader according to claim 1, wherein, In the program loading boot mode: The OTP storage module synchronously transmits the stored chip unique information and SPI_FLASH parameters to the QSPI interface module, the CRC32 check module and the UART communication module through an internal bus for initialization. After the QSPI interface module completes the communication mode configuration according to the SPI_FLASH parameters, the QSPI interface module sends a command to the QSPI-Flash to make it exit the low-power mode, reads data from the QSPI-Flash and transmits the data to the CRC32 check module through the internal bus of the chip. CRC32 check module passes the received data check, write to SRAM, chip kernel call data and execute the program.

5. The chip BootLoader dual-mode configuration system of claim 4, wherein, Wherein, QSPI interface module reads Code_Info area and Code area data from QSPI-Flash, and transmits to CRC32 check module through the internal bus; CRC32 check module first checks Code_Info area data, if failed, report log by UART communication module and terminate the process; check through the Code area, if failed, report log by UART communication module and terminate the process, if successful, Code area data is written into SRAM, chip kernel call data and execute the program.

6. The chip BootLoader dual-mode configuration system of claim 4, wherein, Wherein, Key generation module generates program encryption key according to the chip unique information provided by OTP storage module and transmits to QSPI interface module, QSPI interface module uses program encryption key to decrypt the program code read from QSPI-Flash; the program code in SPI-Flash is encrypted based on the chip unique information.

7. The dual-mode configuration system for chip BootLoader according to claim 1, wherein, The chip unique information includes 32bit CHIP_ID, 16bit CHIP_VERSION, 192bit SID; the SPI_FLASH parameters include reading ID command, reading data command, reading start address, page size, clock phase / polarity, communication rate.

8. The chip BootLoader dual-mode configuration system of claim 7, wherein, Wherein, Key generation module combines 16bit CHIP_VERSION high byte and 16bit BootLoader version as 32bit version information, XOR with 32bit CHIP_ID, and then XOR with constant 0xA55A5AA5 to generate 32bit communication key.

9. The chip BootLoader dual-mode configuration system of claim 7, wherein, Wherein, Key generation module divides 192bit SID into six groups of 4B data, XOR in turn, and then XOR with constant 0xA55A5AA5 to generate 32bit program encryption key.

10. A chip, characterized by Integrated with the chip BootLoader dual mode configuration system of any one of claims 1-9. Integrated with the chip BootLoader dual mode configuration system of any one of claims 1-9.

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