Gate driving circuit, display device and electronic device

Abstract

The invention relates to a gate driving circuit, a display device and an electronic device. The gate driving circuit comprises a first control circuit used for controlling the voltage of a first control node. A second control circuit for controlling a voltage of a second control node; and an output circuit for outputting a first clock signal or a first voltage as a gate signal based on the voltage of the first control node and the voltage of the second control node. The second control circuit includes: a switching circuit connected to the first node and the second node and configured to receive a second clock signal; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and a fourth capacitor including a first electrode for receiving a second voltage and a second electrode connected to the second node.

Description

Technical Field

[0001] Embodiments of the present invention relate to gate driving circuits, display devices, and electronic devices. More specifically, they relate to gate driving circuits, display devices including gate driving circuits, and electronic devices including gate driving circuits. Background Technology

[0002] Typically, a display device may include a display panel and a display panel driver. The display panel may include multiple gate lines, multiple emitter lines, multiple data lines, and multiple pixels. The display panel driver may include a gate driving circuit that provides gate signals to the gate lines, an emitter driving circuit that provides emitter signals to the emitter lines, and a data driving circuit that provides data voltages to the data lines. Additionally, the display panel driver may also include a drive controller that controls the gate driving circuit, the emitter driving circuit, and the data driving circuit.

[0003] The gate drive circuit may include multiple stages. Each stage may include multiple transistors and multiple capacitors. Additionally, each stage may receive multiple clock signals. These clock signals may be output as the stage's output signal.

[0004] When the voltage at the first electrode of the capacitor changes, the voltage at the second electrode may change due to the capacitor's coupling. That is, the voltage of the clock signal applied to the second electrode of the capacitor may change. When the clock signal voltage changes, the output signal of the stage that includes the capacitor and outputs the clock signal as its output signal may become unstable. Therefore, the stability and reliability of the gate drive circuit including this stage may decrease. Furthermore, the pixel receiving the output signal from the gate drive circuit may not be able to adequately operate the threshold voltage compensation operation. Therefore, the pixel may not be able to emit light at a brightness corresponding to the data voltage. Summary of the Invention

[0005] Embodiments of the present invention provide a gate drive circuit with improved stability and improved reliability.

[0006] An embodiment of the present invention provides a display device including the gate driving circuit.

[0007] An embodiment of the present invention provides an electronic device including the gate driving circuit.

[0008] In an embodiment of the gate driving circuit according to the present invention, the gate driving circuit includes: a first control circuit configured to control the voltage of a first control node based on an input signal, a first clock signal, and a second clock signal; a second control circuit configured to control the voltage of a second control node based on the first clock signal and the second clock signal; and an output circuit configured to output the first clock signal or a first voltage as a gate signal based on the voltage of the first control node and the voltage of the second control node. The second control circuit includes: a switching circuit connected to the first node and the second node, and the switching circuit is configured to receive the second clock signal; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and a fourth capacitor including a first electrode configured to receive a second voltage and a second electrode connected to the second node.

[0009] In an embodiment, the switching circuit may include: a sixth transistor, including a control electrode connected to the first node, a first electrode connected to the third node, and a second electrode configured to receive the second clock signal; and a seventh transistor, including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node.

[0010] In one embodiment, the switching circuit may include a seventh transistor, the seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode configured to receive the second clock signal.

[0011] In an embodiment, the second voltage may be substantially the same as the first voltage.

[0012] In an embodiment, the second control circuit may further include: a third transistor, including a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage, and a second electrode connected to a fifth node; a fourth transistor, including a control electrode configured to receive the first voltage, a first electrode connected to the fifth node, and a second electrode connected to the first node; a fifth transistor, including a control electrode connected to the first control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the fifth node; an eighth transistor, including a control electrode configured to receive the second clock signal, a first electrode connected to the second node, and a second electrode connected to the second control node; and a first capacitor, including a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

[0013] In an embodiment, the first control circuit may include: a first transistor, including a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a fourth node; a second transistor, including a control electrode connected to the first control node, a first electrode connected to a sixth node, and a second electrode configured to receive the second clock signal; an eleventh transistor, including a control electrode configured to receive the first voltage, a first electrode connected to the fourth node, and a second electrode connected to the first control node; and a third capacitor, including a first electrode connected to the first control node and a second electrode connected to the sixth node.

[0014] In one embodiment, the output circuit may include: a ninth transistor, including a control electrode connected to the second control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the output node; and a tenth transistor, including a control electrode connected to the first control node, a first electrode connected to the output node, and a second electrode configured to receive the first voltage.

[0015] In an embodiment, the gate drive circuit may further include a reset circuit configured to initialize the voltage of the first control node and the voltage of the second control node based on a reset signal. The reset circuit may include: a twelfth transistor comprising a control electrode configured to receive the reset signal, a first electrode configured to receive the first clock signal, and a second electrode connected to the fourth node; and a thirteenth transistor comprising a control electrode configured to receive the reset signal, a first electrode connected to the second control node, and a second electrode configured to receive the first voltage.

[0016] In an embodiment of the display device according to the present invention, the display device includes: a display panel including a plurality of pixels; a data driving circuit configured to provide data voltages to the plurality of pixels; a gate driving circuit configured to provide gate signals to the plurality of pixels; and a driving controller configured to control the data driving circuit and the gate driving circuit. The gate driving circuit includes: a first control circuit configured to control a voltage of a first control node based on an input signal, a first clock signal, and a second clock signal; a second control circuit configured to control a voltage of a second control node based on the first clock signal and the second clock signal; and an output circuit configured to output the first clock signal or a first voltage as the gate signal based on the voltage of the first control node and the voltage of the second control node. The second control circuit includes: a switching circuit connected to the first node and the second node, and the switching circuit configured to receive the second clock signal; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and a fourth capacitor including a first electrode configured to receive a second voltage and a second electrode connected to the second node.

[0017] In an embodiment, the switching circuit may include: a sixth transistor, including a control electrode connected to the first node, a first electrode connected to the third node, and a second electrode configured to receive the second clock signal; and a seventh transistor, including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node.

[0018] In one embodiment, the switching circuit may include a seventh transistor, the seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode configured to receive the second clock signal.

[0019] In an embodiment, the second voltage may be substantially the same as the first voltage.

[0020] In an embodiment, the second control circuit may further include: a third transistor, including a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage, and a second electrode connected to a fifth node; a fourth transistor, including a control electrode configured to receive the first voltage, a first electrode connected to the fifth node, and a second electrode connected to the first node; a fifth transistor, including a control electrode connected to the first control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the fifth node; an eighth transistor, including a control electrode configured to receive the second clock signal, a first electrode connected to the second node, and a second electrode connected to the second control node; and a first capacitor, including a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

[0021] In an embodiment, the first control circuit may include: a first transistor, including a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a fourth node; a second transistor, including a control electrode connected to the first control node, a first electrode connected to a sixth node, and a second electrode configured to receive the second clock signal; an eleventh transistor, including a control electrode configured to receive the first voltage, a first electrode connected to the fourth node, and a second electrode connected to the first control node; and a third capacitor, including a first electrode connected to the first control node and a second electrode connected to the sixth node.

[0022] In one embodiment, the output circuit may include: a ninth transistor, including a control electrode connected to the second control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the output node; and a tenth transistor, including a control electrode connected to the first control node, a first electrode connected to the output node, and a second electrode configured to receive the first voltage.

[0023] In an embodiment, the display device may further include a component configured to initialize the voltage of the first control node and the voltage of the second control node based on a reset signal. The reset circuit may include: a twelfth transistor comprising a control electrode configured to receive the reset signal, a first electrode configured to receive the first clock signal, and a second electrode connected to a fourth node; and a thirteenth transistor comprising a control electrode configured to receive the reset signal, a first electrode connected to the second control node, and a second electrode configured to receive the first voltage.

[0024] In an embodiment of the electronic device according to the present invention, the electronic device includes: a display panel including a plurality of pixels; a data driving circuit configured to provide data voltages to the plurality of pixels; a gate driving circuit configured to provide gate signals to the plurality of pixels; a driving controller configured to control the data driving circuit and the gate driving circuit; and a processor configured to output a power-on signal, input image data, and input a control signal to the driving controller. When the electronic device is powered on, the processor is configured to output the power-on signal to the driving controller. The driving controller is configured to output a reset signal to the gate driving circuit for initializing the gate driving circuit in response to the power-on signal, and to output a start signal, a first clock signal, and a second clock signal for operating the gate driving circuit in response to the input control signal. The gate drive circuit includes: a first control circuit configured to control the voltage of a first control node based on an input signal, a first clock signal, and a second clock signal; a second control circuit configured to control the voltage of a second control node based on the first clock signal and the second clock signal; a reset circuit configured to initialize the voltage of the first control node and the voltage of the second control node based on the reset signal; and an output circuit configured to output the first clock signal or a first voltage as the gate signal based on the voltage of the first control node and the voltage of the second control node. The second control circuit includes: a switching circuit connected to the first node and the second node, and the switching circuit is configured to receive the second clock signal; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and a fourth capacitor including a first electrode configured to receive a second voltage and a second electrode connected to the second node.

[0025] In an embodiment, the switching circuit may include: a sixth transistor, including a control electrode connected to the first node, a first electrode connected to the third node, and a second electrode configured to receive the second clock signal; and a seventh transistor, including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node.

[0026] In an embodiment, the second control circuit may further include: a third transistor, including a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage, and a second electrode connected to a fifth node; a fourth transistor, including a control electrode configured to receive the first voltage, a first electrode connected to the fifth node, and a second electrode connected to the first node; a fifth transistor, including a control electrode connected to the first control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the fifth node; an eighth transistor, including a control electrode configured to receive the second clock signal, a first electrode connected to the second node, and a second electrode connected to the second control node; and a first capacitor, including a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

[0027] In an embodiment, the first control circuit may include: a first transistor, including a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a fourth node; a second transistor, including a control electrode connected to the first control node, a first electrode connected to a sixth node, and a second electrode configured to receive the second clock signal; an eleventh transistor, including a control electrode configured to receive the first voltage, a first electrode connected to the fourth node, and a second electrode connected to the first control node; and a third capacitor, including a first electrode connected to the first control node and a second electrode connected to the sixth node.

[0028] According to embodiments of the present invention, a gate driving circuit, a display device including the gate driving circuit, and an electronic device including the gate driving circuit can improve the stability and reliability of the gate signal output from the gate driving circuit. More specifically, the gate driving circuit may include a second capacitor and a fourth capacitor. The second capacitor includes a first electrode for receiving a first clock signal and a second electrode connected to a second node. The fourth capacitor includes a first electrode for receiving a second voltage and a second electrode connected to the second node. The voltage difference between the second voltage and the voltage of the second node can be stored in the fourth capacitor. Therefore, when the voltage of the first node changes, the stability of the voltage of the second node can be improved by the voltage stored in the fourth capacitor. That is, when the voltage of the first node changes, the amount of change in the voltage of the second node can be reduced. Attached Figure Description

[0029] The above and other features and advantages of the present invention will become more apparent from a detailed description of embodiments of the invention with reference to the accompanying drawings, in which:

[0030] Figure 1This is a block diagram illustrating a display device according to an embodiment of the present invention;

[0031] Figure 2 It is shown Figure 1 A block diagram of the gate drive circuit of the display device;

[0032] Figure 3 It is shown Figure 2 A circuit diagram of an embodiment of the gate drive circuit stage;

[0033] Figure 4 It is shown Figure 3 Timing diagram of the operations at the [level] level;

[0034] Figure 5 It shows from Figure 3 A diagram of the gate signal output of the stage;

[0035] Figure 6 This shows the capacitor having a high level. Figure 5 A graph showing the maximum voltage of the gate signal;

[0036] Figure 7 This shows the capacitor having a high level. Figure 5 A graph showing the minimum voltage of the gate signal;

[0037] Figure 8 It is shown Figure 1 A circuit diagram of an embodiment of the pixels of a display device;

[0038] Figure 9 It is shown Figure 2 A circuit diagram of another embodiment of the gate drive circuit stage;

[0039] Figure 10 It is shown Figure 2 A circuit diagram of another embodiment of the gate drive circuit stage;

[0040] Figure 11 It is shown Figure 2 A circuit diagram of another embodiment of the gate drive circuit stage;

[0041] Figure 12 It is shown Figure 2 A circuit diagram of another embodiment of the gate drive circuit stage;

[0042] Figure 13 It is shown Figure 2 A circuit diagram of another embodiment of the gate drive circuit stage;

[0043] Figure 14 It is shown Figure 2 A circuit diagram of another embodiment of the gate drive circuit stage;

[0044] Figure 15 It is shown Figure 2 A circuit diagram of another embodiment of the gate drive circuit stage;

[0045] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment of the present invention;

[0046] Figure 17 It is shown Figure 16 The diagram shows an embodiment of an electronic device implemented as a smartphone; and

[0047] Figure 18 This is a block diagram illustrating an electronic device according to an embodiment of the present invention. Detailed Implementation

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” or “including” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0049] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as “second element,” “second component,” “second region,” “second layer,” or “second part.”

[0050] It will be understood that when an element is referred to as "connected to" another element, the element can be directly connected to the other element, or there can be an intermediary element between the element and the other element. In contrast, when an element is referred to as "directly connected to" another element, there is no intermediary element.

[0051] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “substantially the same” as used herein include the stated values ​​and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “substantially the same” could mean within one or more standard deviations, or within ±10%, ±5%, or ±2% of the stated value.

[0052] In the following description, the display device according to an embodiment will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0053] Figure 1 This is a block diagram illustrating a display device 1 according to an embodiment of the present invention.

[0054] refer to Figure 1 The display device 1 may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate drive circuit 300, a gamma reference voltage generator 400, a data drive circuit 500, and a transmit drive circuit 600.

[0055] The display panel 100 may have a display area in which an image is displayed and a peripheral area adjacent to the display area.

[0056] The display panel 100 may include multiple gate lines GWL, GCL, GIL, and GBL, multiple data lines DL, multiple emitter lines EML, and multiple pixels electrically connected to the gate lines GWL, GCL, GIL, and GBL, the data lines DL, and the emitter lines EML. The gate lines GWL, GCL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 intersecting the first direction D1, and the emitter lines EML may extend in the first direction D1.

[0057] The drive controller 200 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. For example, the input image data IMG may also include white image data. For example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0058] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0059] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate drive circuit 300 based on the input control signal CONT, and can output the first control signal CONT1 to the gate drive circuit 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0060] The drive controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data drive circuit 500, and can output the second control signal CONT2 to the data drive circuit 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0061] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data drive circuit 500.

[0062] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and can output the third control signal CONT3 to the gamma reference voltage generator 400.

[0063] The drive controller 200 can generate a fourth control signal CONT4 based on the input control signal CONT for controlling the operation of the transmit drive circuit 600, and can output the fourth control signal CONT4 to the transmit drive circuit 600.

[0064] The gate drive circuit 300 generates gate signals for driving gate lines GWL, GCL, GIL, and GBL in response to the first control signal CONT1 received from the drive controller 200. The gate drive circuit 300 can output the gate signals to the gate lines GWL, GCL, GIL, and GBL.

[0065] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can output the gamma reference voltage VGREF to the data drive circuit 500. The gamma reference voltage VGREF can have a value corresponding to the data signal DATA.

[0066] In this embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data drive circuit 500.

[0067] The data drive circuit 500 can receive the second control signal CONT2 and the data signal DATA from the drive controller 200, and can receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data drive circuit 500 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage with analog type. The data drive circuit 500 can output the data voltage to the data line DL.

[0068] For example, the data driver circuit 500 and the drive controller 200 can be implemented as a single integrated circuit, which may be referred to as a timing controller embedded data driver circuit (TED).

[0069] The transmit drive circuit 600 can generate a transmit signal to drive the transmit line EML in response to the fourth control signal CONT4 received from the drive controller 200. The transmit drive circuit 600 can output the transmit signal to the transmit line EML.

[0070] Although for the sake of explanation Figure 1 The gate driving circuit 300 is disposed on the first side of the display panel 100, and the emission driving circuit 600 is disposed on the second side of the display panel 100 opposite to the first side; however, the present invention is not limited to this. For example, both the gate driving circuit 300 and the emission driving circuit 600 may be disposed on the first side of the display panel 100. For example, both the gate driving circuit 300 and the emission driving circuit 600 may be disposed on both sides of the display panel 100. For example, the gate driving circuit 300 and the emission driving circuit 600 may be integrally formed.

[0071] Figure 2 It is shown Figure 1 A block diagram of the gate drive circuit 300 of the display device 1.

[0072] refer to Figure 1 and Figure 2 The gate drive circuit 300 may include multiple stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... may receive two clock signals from multiple clock signals CLK1, CLK2, CLK3, and CLK4. In addition, each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... may receive a start signal FLM as an input signal or a gate signal GC[N-1] output from the previous stage (i.e., the corresponding gate signal among gate signals GC[1], GC[2], GC[3], GC[4], ...), where N is an integer greater than or equal to 2. Each of STAGE1, STAGE2, STAGE3, STAGE4, ​​... can output a gate signal GC[N] based on two corresponding clock signals among clock signals CLK1, CLK2, CLK3 and CLK4 and a start signal FLM as an input signal or the gate signal GC[N-1] output from the previous stage (i.e., the corresponding gate signal among gate signals GC[1], GC[2], GC[3], GC[4], ...).

[0073] For example, STAGE1 can receive the first clock signal CLK1 and the second clock signal CLK2. STAGE1 can receive the start signal FLM. STAGE1 can output the first gate signal GC based on the first clock signal CLK1, the second clock signal CLK2 and the start signal FLM[1].

[0074] For example, the second stage STAGE2 can receive the second clock signal CLK2 and the third clock signal CLK3. The second stage STAGE2 can receive the first gate signal GC[1]. The second stage STAGE2 can output the second gate signal GC[2] based on the second clock signal CLK2, the third clock signal CLK3 and the first gate signal GC[1].

[0075] For example, STAGE3 can receive the third clock signal CLK3 and the fourth clock signal CLK4. STAGE3 can receive the second gate signal GC[2]. STAGE3 can output the third gate signal GC[3] based on the third clock signal CLK3, the fourth clock signal CLK4 and the second gate signal GC[2].

[0076] For example, the fourth stage STAGE4 can receive the fourth clock signal CLK4 and the first clock signal CLK1. The fourth stage STAGE4 can receive the third gate signal GC[3]. The fourth stage STAGE4 can output the fourth gate signal GC[4] based on the fourth clock signal CLK4, the first clock signal CLK1 and the third gate signal GC[3].

[0077] Figure 3 It is shown Figure 2 A circuit diagram of an embodiment of stage 310 of gate drive circuit 300.

[0078] refer to Figures 1 to 3 Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... can include multiple transistors and multiple capacitors. For ease of illustration, in Figure 3 Assuming that stage 310 is the first stage STAGE1 among stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... used to receive the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0079] The first stage 310 may include a first control circuit 311 for controlling the voltage of the first control node Q. The first stage 310 may also include a second control circuit 312 for controlling the voltage of the second control node QB. The first stage 310 may also include an output circuit 314 for outputting a first clock signal CLK1 or a first voltage VGL as a first gate signal GC[1]. For example, the first voltage VGL may have a first low level. For example, the first voltage VGL may be a constant voltage.

[0080] The first control circuit 311 can control the voltage of the first control node Q based on the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0081] The first control circuit 311 may include a first transistor T1, a second transistor T2, an eleventh transistor T11, and a third capacitor C3.

[0082] The first transistor T1 may include a control electrode for receiving a first clock signal CLK1, a first electrode for receiving a start signal FLM, and a second electrode connected to the fourth node N4.

[0083] The second transistor T2 may include a control electrode connected to the first control node Q, a first electrode connected to the sixth node N6, and a second electrode for receiving the second clock signal CLK2.

[0084] The eleventh transistor T11 may include a control electrode for receiving a first voltage VGL, a first electrode connected to a fourth node N4, and a second electrode connected to a first control node Q.

[0085] The third capacitor C3 may include a first electrode connected to the first control node Q and a second electrode connected to the sixth node N6.

[0086] The second control circuit 312 can control the voltage of the second control node QB based on the first clock signal CLK1 and the second clock signal CLK2.

[0087] The second control circuit 312 may include a third transistor T3, a fourth transistor T4 and a fifth transistor T5, a switching circuit 313a, a fourteenth transistor T14, an eighth transistor T8, a first capacitor C1, a second capacitor C2 and a fourth capacitor C4.

[0088] The switching circuit 313a may include a sixth transistor T6 and a seventh transistor T7.

[0089] The third transistor T3 may include a control electrode for receiving a first clock signal CLK1, a first electrode for receiving a first voltage VGL, and a second electrode connected to the fifth node N5.

[0090] The fourth transistor T4 may include a control electrode for receiving a first voltage VGL, a first electrode connected to a fifth node N5, and a second electrode connected to a first node N1.

[0091] The fifth transistor T5 may include a control electrode connected to the first control node Q, a first electrode for receiving the first clock signal CLK1, and a second electrode connected to the fifth node N5.

[0092] The sixth transistor T6 may include a control electrode connected to the first node N1, a first electrode connected to the third node N3, and a second electrode for receiving the second clock signal CLK2.

[0093] The seventh transistor T7 may include a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3.

[0094] The eighth transistor T8 may include a control electrode for receiving the second clock signal CLK2, a first electrode connected to the second node N2, and a second electrode connected to the second control node QB.

[0095] The fourteenth transistor T14 may include a control electrode connected to the first control node Q, a first electrode for receiving the first clock signal CLK1, and a second electrode connected to the second control node QB.

[0096] The first capacitor C1 may include a first electrode for receiving the first clock signal CLK1 and a second electrode connected to the second control node QB.

[0097] The second capacitor C2 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0098] The fourth capacitor C4 may include a first electrode for receiving the second voltage DC and a second electrode connected to the second node N2.

[0099] For example, the second voltage DC can be a constant voltage. For example, the second voltage DC can be less than the first voltage VGL.

[0100] The structure in which the control electrode of the sixth transistor T6 and the control electrode of the seventh transistor T7 are connected to each other, and the first electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are connected to each other, can be called a dual-transistor structure.

[0101] The dual-transistor structure prevents current leakage, thereby improving the reliability and stability of the gate drive circuit 300.

[0102] The output circuit 314 can output a first clock signal CLK1 or a first voltage VGL as a first gate signal GC[1] based on the voltage of the first control node Q and the voltage of the second control node QB.

[0103] The output circuit 314 may include a ninth transistor T9 and a tenth transistor T10.

[0104] The ninth transistor T9 may include a control electrode connected to the second control node QB, a first electrode for receiving the first clock signal CLK1, and a second electrode connected to the output node NO.

[0105] The tenth transistor T10 may include a control electrode connected to the first control node Q, a first electrode connected to the output node NO, and a second electrode for receiving a first voltage VGL.

[0106] In an embodiment, the first stage 310 may include a first type of transistor and / or a second type of transistor different from the first type of transistor. For example, the first type of transistor may be a P-type metal-oxide-semiconductor (PMOS) transistor, and the second type of transistor may be an N-type metal-oxide-semiconductor (NMOS) transistor. In an embodiment, the first stage 310 may include only PMOS transistors.

[0107] Although the first level 310 is in Figure 3The diagram is shown to include only PMOS transistors, but the invention is not limited thereto. For example, some transistors in the first stage 310 may be NMOS transistors, and other transistors in the first stage 310 may be PMOS transistors.

[0108] The fourth capacitor C4 can store the voltage difference between the second voltage DC and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the second voltage DC applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept at a high level. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0109] Figure 4 It is shown Figure 3 The timing diagram of the operation of level 310.

[0110] refer to Figure 3 and Figure 4 The operation period of Level 310 can include the first period P1 to the ninth period P9.

[0111] In the first time period P1, the level of the start signal FLM can be a first low level (e.g., the level of the first voltage VGL). The level of the first clock signal CLK1 can be a first low level. The level of the second clock signal CLK2 can be a high level (e.g., the level of the third voltage VGH (also referred to herein as the reference high voltage VGH)).

[0112] The first transistor T1 can be turned on in response to the first clock signal CLK1. The first transistor T1 can transmit the start signal FLM to the fourth node N4. The eleventh transistor T11 can be turned on by the first voltage VGL. The eleventh transistor T11 can transmit the voltage of the fourth node N4 to the first control node Q. That is, the start signal FLM with the first low level can be transmitted to the first control node Q.

[0113] The voltage of the first control node Q and the first clock signal CLK1 can have a first low level, such that the difference between the voltage of the control electrode of the fourteenth transistor T14 and the voltage of the first electrode of the fourteenth transistor T14 can be less than the magnitude (e.g., absolute value) of the threshold voltage of the fourteenth transistor T14. Therefore, the fourteenth transistor T14 can be turned off.

[0114] When the level of the first clock signal CLK1 decreases from a high level to a first low level, the voltage level of the second control node QB can be reduced to a first low level through the coupling of the first capacitor C1. That is, the voltage of the second control node QB can have a first low level. Therefore, the voltage of the first electrode of the first capacitor C1 and the voltage of the second control node QB can both have a first low level (e.g., the level of the first voltage VGL).

[0115] Furthermore, the voltage of the second control node QB and the first clock signal CLK1 have a first low level, such that the difference between the voltage of the control electrode of the ninth transistor T9 and the voltage of the first electrode of the ninth transistor T9 can be less than the threshold voltage of the ninth transistor T9. Therefore, the ninth transistor T9 can be turned off.

[0116] The fifth transistor T5 can be turned on by the voltage of the first control node Q. The fifth transistor T5 can transmit the first clock signal CLK1 to the fifth node N5. The fourth transistor T4 can be turned on by the first voltage VGL. The fourth transistor T4 can transmit the voltage of the fifth node N5 to the first node N1. Therefore, the voltage of the first node N1 can have a first low level.

[0117] The sixth transistor T6 and the seventh transistor T7 can be turned on by the voltage of the first node N1. The sixth transistor T6 and the seventh transistor T7 can transmit the second clock signal CLK2 to the second node N2. Therefore, the voltage of the second node N2 can have a high level. The second capacitor C2 can store a voltage that is the difference between the voltage of the first node N1 and the voltage of the second node N2. That is, the second capacitor C2 can store a voltage having a level that is the difference between a high level and a first low level. For example, the second capacitor C2 can store a voltage having a value of VGH-VGL (i.e., obtained by subtracting the magnitude of the first voltage VGL from the magnitude of the third voltage VGH).

[0118] The tenth transistor T10 can be turned on by the voltage of the first control node Q. The tenth transistor T10 can transmit the first voltage VGL to the output node NO. Therefore, the first stage 310 can output a voltage with a first low level as the first gate signal GC[1].

[0119] During the second time period P2, the start signal FLM can be high. The first clock signal CLK1 can be low. The second clock signal CLK2 can be high.

[0120] The first transistor T1 can be turned on by the first clock signal CLK1. The eleventh transistor T11 can be turned on by the first voltage VGL. The first transistor T1 and the eleventh transistor T11 can transmit the start signal FLM to the first control node Q. The voltage of the first control node Q can be high.

[0121] The fourteenth transistor T14 can be turned off by the voltage of the first control node Q. The eighth transistor T8 can be turned off by the second clock signal CLK2. Therefore, the voltage of the second control node QB can be maintained at a first low level by the first capacitor C1.

[0122] The third transistor T3 can be turned on by the first clock signal CLK1. The fourth transistor T4 can be turned on by the first voltage VGL. The third transistor T3 and the fourth transistor T4 can transmit the first voltage VGL to the first node N1. Therefore, the voltage of the first node N1 can have a first low level.

[0123] The sixth transistor T6 and the seventh transistor T7 can be turned on by the voltage of the first node N1. The sixth transistor T6 and the seventh transistor T7 can transmit the second clock signal CLK2 to the second node N2. Therefore, the voltage of the second node N2 can be high.

[0124] The second capacitor C2 can store a voltage that is the difference between the voltage at the first node N1 and the voltage at the second node N2. That is, the second capacitor C2 can store a voltage that is the difference between a high level and a first low level. For example, the second capacitor C2 can store a voltage of magnitude VGH-VGL.

[0125] The ninth transistor T9 can be turned on by the voltage of the second control node QB. The ninth transistor T9 can transmit the first clock signal CLK1 to the output node NO. Therefore, the first stage 310 can output a voltage with a first low level as the first gate signal GC[1].

[0126] In the third time period P3, the start signal FLM can be high. The first clock signal CLK1 can be low. The second clock signal CLK2 can be low.

[0127] The first transistor T1 can be turned on by the first clock signal CLK1. The eleventh transistor T11 can be turned on by the first voltage VGL. The first transistor T1 and the eleventh transistor T11 can transmit the start signal FLM to the first control node Q. The voltage of the first control node Q can be high.

[0128] The third transistor T3 can be turned on by the first clock signal CLK1. The fourth transistor T4 can be turned on by the first voltage VGL. The third transistor T3 and the fourth transistor T4 can transmit the first voltage VGL to the first node N1. Therefore, the voltage of the first node N1 can have a first low level.

[0129] The sixth transistor T6 and the seventh transistor T7 can be turned on by the voltage of the first node N1. The sixth transistor T6 and the seventh transistor T7 can transmit the second clock signal CLK2 to the second node N2. Therefore, the voltage of the second node N2 can have a first low level.

[0130] When the voltage level of the second node N2 decreases from a high level to a first low level, the voltage of the first node N1 can bootstrap to a voltage with a second low level (e.g., 2VGL (i.e., twice the level of the first voltage VGL)) through the coupling of the second capacitor C2.

[0131] The eighth transistor T8 can be turned on by the second clock signal CLK2. The eighth transistor T8 can transmit the voltage of the second node N2 to the second control node QB. Therefore, the voltage of the second control node QB can have a first low level. The voltage of the first electrode of the first capacitor C1 and the voltage of the second electrode of the first capacitor C1 can have a first low level.

[0132] The ninth transistor T9 can be turned on by the voltage of the second control node QB. The ninth transistor T9 can transmit the first clock signal CLK1 to the output node NO. Therefore, the first stage 310 can output a voltage with a first low level as the first gate signal GC[1].

[0133] In the fourth time period P4, the start signal FLM can be high. The first clock signal CLK1 can be high. The second clock signal CLK2 can be low.

[0134] The first transistor T1 can be turned off by the first clock signal CLK1. The voltage of the first control node Q can be kept high.

[0135] The third transistor T3 and the fifth transistor T5 can be turned off by the voltage of the first control node Q and the first clock signal CLK1. The voltage of the first node N1 can be kept at a second low level by the second capacitor C2.

[0136] The sixth transistor T6 and the seventh transistor T7 can be turned on by the voltage of the first node N1. The sixth transistor T6 and the seventh transistor T7 can transmit the second clock signal CLK2 to the second node N2. Therefore, the voltage of the second node N2 can have a first low level.

[0137] The eighth transistor T8 can be turned on by the second clock signal CLK2. The eighth transistor T8 can transmit the voltage of the second node N2 to the second control node QB. Therefore, the voltage of the second control node QB can have a first low level.

[0138] The ninth transistor T9 can be turned on by the voltage of the second control node QB. The ninth transistor T9 can transmit the first clock signal CLK1 to the output node NO. Therefore, the first stage 310 can output a voltage with a high level as the first gate signal GC[1].

[0139] In the fifth time period P5, the start signal FLM can be high. The first clock signal CLK1 can be high. The second clock signal CLK2 can be high.

[0140] The first transistor T1 can be turned off by the first clock signal CLK1. The voltage of the first control node Q can be kept high.

[0141] The sixth transistor T6 and the seventh transistor T7 can be turned on by the voltage of the first node N1, which is held at a second low level by the second capacitor C2. The sixth transistor T6 and the seventh transistor T7 can transmit the second clock signal CLK2 to the second node N2. Therefore, the voltage of the second node N2 can be high.

[0142] The third transistor T3 and the fifth transistor T5 can be turned off by the voltage of the first control node Q and the first clock signal CLK1. When the voltage level of the second node N2 increases from a first low level to a high level, the voltage level of the first node N1 can be increased from a second low level (e.g., 2VGL (i.e., twice the level of the first voltage VGL)) to a first low level (e.g., the level of the first voltage VGL) through the coupling of the second capacitor C2.

[0143] The fourteenth transistor T14 can be turned off by the voltage of the first control node Q. The eighth transistor T8 can be turned off by the second clock signal CLK2. Therefore, the voltage of the second control node QB can be maintained at a first low level by the first capacitor C1.

[0144] The ninth transistor T9 can be turned on by the voltage of the second control node QB. The ninth transistor T9 can transmit the first clock signal CLK1 to the output node NO. Therefore, the first stage 310 can output a voltage with a high level as the first gate signal GC[1].

[0145] In the sixth time period P6, the start signal FLM can have a first low level. The first clock signal CLK1 can have a high level. The second clock signal CLK2 can have a high level.

[0146] The first transistor T1 can be turned off by the first clock signal CLK1. The voltage of the first control node Q can be kept high.

[0147] The sixth transistor T6 and the seventh transistor T7 can be turned on by the voltage of the first node N1. The sixth transistor T6 and the seventh transistor T7 can transmit the second clock signal CLK2 to the second node N2. Therefore, the voltage of the second node N2 can be high.

[0148] The third transistor T3 and the fifth transistor T5 can be turned off by the voltage of the first control node Q and the first clock signal CLK1. The voltage of the first node N1 can be maintained at a first low level (e.g., the level of the first voltage VGL).

[0149] The fourteenth transistor T14 can be turned off by the voltage of the first control node Q. The eighth transistor T8 can be turned off by the second clock signal CLK2. Therefore, the voltage of the second control node QB can be maintained at a first low level by the first capacitor C1.

[0150] The ninth transistor T9 can be turned on by the voltage of the second control node QB. The ninth transistor T9 can transmit the first clock signal CLK1 to the output node NO. Therefore, the first stage 310 can output a voltage with a high level as the first gate signal GC[1].

[0151] In the seventh time period P7, the start signal FLM can have a first low level. The first clock signal CLK1 can have a first low level. The second clock signal CLK2 can have a high level.

[0152] The first transistor T1 can be turned on by the first clock signal CLK1. The eleventh transistor T11 can be turned on by the first voltage VGL. The first transistor T1 and the eleventh transistor T11 can transmit the start signal FLM to the first control node Q. Therefore, the voltage of the first control node Q can have a first low level.

[0153] When the level of the first clock signal CLK1 decreases from a high level to a first low level, the voltage of the second control node QB can bootstrap to a voltage with a second low level through the coupling of the first capacitor C1. Therefore, the voltage of the first electrode of the first capacitor C1 can have a first low level, and the voltage of the second control node QB can have a second low level.

[0154] The voltage of the first control node Q and the first clock signal CLK1 are both at a first low level, such that the difference between the voltage of the control electrode of the fourteenth transistor T14 and the voltage of the first electrode of the fourteenth transistor T14 can be less than the threshold voltage of the fourteenth transistor T14. Therefore, the fourteenth transistor T14 can be turned off. Additionally, the first clock signal CLK1 is at a first low level and the voltage of the second control node QB is at a second low level, such that the difference between the voltage of the control electrode of the ninth transistor T9 and the voltage of the first electrode of the ninth transistor T9 can be greater than the threshold voltage of the ninth transistor T9. Therefore, the ninth transistor T9 can be turned on. Thus, the ninth transistor T9 can transmit the first clock signal CLK1 with the first low level to the output node NO.

[0155] The fifth transistor T5 can be turned on by the voltage of the first control node Q. The fifth transistor T5 can transmit the first clock signal CLK1 to the fifth node N5. The fourth transistor T4 can be turned on by the first voltage VGL. The fourth transistor T4 can transmit the voltage of the fifth node N5 to the first node N1. Therefore, the voltage of the first node N1 can have a first low level.

[0156] The sixth transistor T6 and the seventh transistor T7 can be turned on by the voltage of the first node N1. The sixth transistor T6 and the seventh transistor T7 can transmit the second clock signal CLK2 to the second node N2. Therefore, the voltage of the second node N2 can have a high level. The second capacitor C2 can store the voltage difference between the voltage of the first node N1 and the voltage of the second node N2. That is, the second capacitor C2 can store a voltage having a level that is the difference between a high level and a first low level. For example, the second capacitor C2 can store a voltage of magnitude VGH-VGL.

[0157] The second transistor T2 can be turned on by the voltage of the first control node Q. The second transistor T2 can transmit the second clock signal CLK2 to the sixth node N6. Therefore, the voltage of the sixth node N6 can be high. Therefore, the third capacitor C3 can store the voltage difference between the voltage of the first control node Q and the voltage of the sixth node N6. That is, the third capacitor C3 can store a voltage having a level that is the difference between a high level and a first low level. For example, the third capacitor C3 can store a voltage of magnitude VGH-VGL. The tenth transistor T10 can be turned on by the voltage of the first control node Q. The tenth transistor T10 can transmit the first voltage VGL to the output node NO.

[0158] Therefore, the first clock signal CLK1 with the first low level and the first voltage VGL are transmitted to the output node NO, so that the first stage 310 can output a voltage with the first low level as the first gate signal GC[1].

[0159] In the eighth time period P8, the start signal FLM can have a first low level. The first clock signal CLK1 can have a first low level. The second clock signal CLK2 can have a first low level.

[0160] The second transistor T2 can be turned on by the voltage of the first control node Q. The second transistor T2 can transmit the second clock signal CLK2 to the sixth node N6. The voltage of the sixth node N6 can have a first low level. When the voltage level of the sixth node N6 drops from a high level to the first low level, the voltage of the first control node Q can bootstrap to a voltage with a second low level through the coupling of the third capacitor C3.

[0161] The sixth transistor T6 and the seventh transistor T7 can be turned on by the voltage of the first node N1. The sixth transistor T6 and the seventh transistor T7 can transmit the second clock signal CLK2 to the second node N2. Therefore, the voltage of the second node N2 can have a first low level.

[0162] When the voltage level of the second node N2 decreases from high to low, the voltage of the first node N1 can bootstrap to a voltage with a second low level through the coupling of the second capacitor C2.

[0163] The fourteenth transistor T14 can be turned on by the voltage of the first control node Q. Additionally, the voltage of the second control node QB can be maintained at a second low level by the first capacitor C1.

[0164] The voltage of the second control node QB has a second low level and the first clock signal CLK1 has a first low level, such that the difference between the voltage of the control electrode of the ninth transistor T9 and the voltage of the first electrode of the ninth transistor T9 can be greater than the threshold voltage of the ninth transistor T9. Therefore, the ninth transistor T9 can be turned on. Thus, the ninth transistor T9 can transmit the first clock signal CLK1 with the first low level to the output node NO.

[0165] The tenth transistor T10 can be turned on by the voltage of the first control node Q. The tenth transistor T10 can transmit the first voltage VGL to the output node NO.

[0166] Therefore, the first clock signal CLK1 with the first low level and the first voltage VGL are transmitted to the output node NO, so that the first stage 310 can output a voltage with the first low level as the first gate signal GC[1].

[0167] In the ninth time period P9, the start signal FLM can have a first low level. The first clock signal CLK1 can have a high level. The second clock signal CLK2 can have a first low level.

[0168] The first transistor T1 can be turned off by the first clock signal CLK1. The first control node Q can be kept at a second low level.

[0169] The fourteenth transistor T14 can be turned on by the voltage of the first control node Q. The fourteenth transistor T14 can transmit the first clock signal CLK1 to the second control node QB. Therefore, the voltage of the second control node QB can be high.

[0170] The fifth transistor T5 can be turned on by the voltage of the first control node Q. The fourth transistor T4 can be turned on by the first voltage VGL. The fourth transistor T4 and the fifth transistor T5 can transmit the first clock signal CLK1 to the first node N1. Therefore, the voltage of the first node N1 can be high.

[0171] The sixth transistor T6 and the seventh transistor T7 can be turned off by the voltage of the first node. The eighth transistor T8 can be turned on by the second clock signal CLK2. The eighth transistor T8 can transmit the voltage of the second control node QB to the second node N2. Therefore, the voltage of the second node N2 can be high. The voltage of the first electrode of the second capacitor C2 and the voltage of the second electrode of the second capacitor C2 can be high (e.g., the level of the third voltage VGH).

[0172] The tenth transistor T10 can be turned on by the voltage of the first control node Q. The tenth transistor T10 can transmit the first voltage VGL to the output node NO. Therefore, the first stage 310 can output a voltage with a first low level as the first gate signal GC[1].

[0173] The fourth capacitor C4 can store the voltage difference between the second voltage DC and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the second voltage DC applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can be kept constant due to the coupling of the second capacitor C2. For example, when the voltage level of the first node N1 in the first time period P1 decreases from a high level to a first low level by the first clock signal CLK1, the voltage of the second node N2 can be prevented from temporarily decreasing due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be kept high stably. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0174] Figure 5 It shows from Figure 3 The diagram shows the gate signal GC[1] output by stage 310. Figure 6 This shows the capacitor having a high level. Figure 5 The graph shows the maximum voltage of the gate signal GC[1]. Figure 7 This shows the capacitor having a high level. Figure 5 The graph shows the minimum voltage of the gate signal GC[1].

[0175] refer to Figures 3 to 5 The first gate signal GC[1] of the first stage 310 can be high during the fourth period P4 to the sixth period P6. The voltage of the first gate signal GC[1] with a high level can swing between the maximum voltage V1 and the minimum voltage V2 during the fourth period P4 to the sixth period P6.

[0176] As the maximum voltage V1 and the minimum voltage V2 approach the reference high voltage VGH, the first stage 310 can stably output the first gate signal GC[1]. Therefore, the gate drive circuit 300 (see [reference]) can be improved. Figure 2 The stability and reliability of ).

[0177] refer to Figures 3 to 6 The first gate signal GC[1] can have a maximum voltage V1 during the first maximum time period 700.

[0178] The maximum voltage V1 can be varied according to the capacitance of each of the first capacitor C1 through the fourth capacitor C4. The reference high voltage VGH can be 6.0 volts (V).

[0179] A conventional gate drive circuit may consist of only a first capacitor C1, a second capacitor C2, and a third capacitor C3. The capacitance of the second capacitor C2 may be 70 femtofarads (fF). The maximum voltage V1 may be a first maximum voltage V1a, which may be 6.5V.

[0180] In this embodiment, the capacitance of the second capacitor C2 can be 35fF, and the capacitance of the fourth capacitor C4 can be 140fF. The maximum voltage V1 can be the second maximum voltage V1b. The second maximum voltage V1b can be 6.38V. Compared with a conventional gate drive circuit, the magnitude of the maximum voltage V1 can be reduced. That is, the second maximum voltage V1b can be closer to the reference high voltage VGH than the first maximum voltage V1a. This can improve the stability of the first gate signal GC[1]. Therefore, the gate drive circuit 300 (see Figure 2 The stability and reliability of ).

[0181] In this embodiment, the capacitance of the second capacitor C2 can be 17.5 fF, and the capacitance of the fourth capacitor C4 can be 70 fF. The maximum voltage V1 can be the third maximum voltage V1c. The third maximum voltage V1c can be 6.43 V. Compared with a conventional gate drive circuit, the magnitude of the maximum voltage V1 can be reduced. That is, the third maximum voltage V1c can be closer to the reference high voltage VGH than the first maximum voltage V1a. This can improve the stability of the first gate signal GC[1]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0182] In this embodiment, the capacitance of the second capacitor C2 can be 10fF, and the capacitance of the fourth capacitor C4 can be 70fF. The maximum voltage V1 can be the fourth maximum voltage V1d. The fourth maximum voltage V1d can be 6.41V. Compared with a conventional gate drive circuit, the magnitude of the maximum voltage V1 can be reduced. That is, the fourth maximum voltage V1d can be closer to the reference high voltage VGH than the first maximum voltage V1a. In addition, as the capacitance of the third capacitor C3 decreases, the time for charging or discharging the third capacitor C3 can be reduced. Therefore, the load applied to the second clock signal CLK2 can be reduced. The stability of the first gate signal GC[1] can be improved. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0183] In this embodiment, the capacitance of the second capacitor C2 can be 70fF, and the capacitance of the fourth capacitor C4 can be 70fF. The maximum voltage V1 can be 6.44V. Compared with a conventional gate drive circuit, the magnitude of the maximum voltage V1 can be reduced. That is, the maximum voltage V1 can be closer to the reference high voltage VGH than the first maximum voltage V1a. This can improve the stability of the first gate signal GC[1]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0184] In this embodiment, the capacitance of the second capacitor C2 can be 70fF, and the capacitance of the fourth capacitor C4 can be 140fF. The maximum voltage V1 can be 6.39V. Compared with a conventional gate drive circuit, the magnitude of the maximum voltage V1 can be reduced. That is, the maximum voltage V1 can be closer to the reference high voltage VGH than the first maximum voltage V1a. This can improve the stability of the first gate signal GC[1]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0185] refer to Figures 3 to 5 as well as Figure 7 The first gate signal GC[1] can have a minimum voltage V2 during the second maximum time period 800.

[0186] The minimum voltage V2 can be varied based on the capacitance of each of the first capacitor C1 through the fourth capacitor C4. The reference high voltage VGH can be 6.0V.

[0187] In this embodiment, as the ratio of the capacitance of the second capacitor C2 to the capacitance of the fourth capacitor C4 decreases, the minimum voltage V2 can approach the reference high voltage VGH.

[0188] The voltage stored in the fourth capacitor C4 can be calculated using VC4 = (DC - Va) × (CF2 / (CF2 + CF4)). Here, VC4 represents the voltage stored in the fourth capacitor C4. DC represents the second voltage DC. Va represents the voltage at the first node N1. CF2 represents the capacitance of the second capacitor C2, and CF4 represents the capacitance of the fourth capacitor C4.

[0189] When the voltage of the first node N1 changes, the change in voltage stored in the fourth capacitor C4 can be calculated as ΔVC4 = ΔVA × (CF2 / (CF2+CF4)). Here, ΔVA represents the change in voltage of the first node N1, and ΔVC4 represents the change in voltage stored in the fourth capacitor C4. As the change in voltage stored in the fourth capacitor C4 decreases, the change in voltage of the second node N2 can decrease. When the change in voltage of the second node N2 decreases, the stability of the second clock signal CLK2 and the stability of the first gate signal GC[1] can be improved. For example, as the change in voltage of the second node N2 decreases, the minimum voltage V2 of the first gate signal GC[1] can approach the reference high voltage VGH. Therefore, as the capacitance of the second capacitor C2 decreases and the capacitance of the fourth capacitor C4 increases, the change in voltage of the second node N2 can decrease. Therefore, the stability of the second clock signal CLK2 and the stability of the first gate signal GC[1] can be improved.

[0190] A conventional gate drive circuit may consist only of a first capacitor C1, a second capacitor C2, and a third capacitor C3. The capacitance of the second capacitor C2 may be 70 fF. The minimum voltage V2 may be a first minimum voltage V2a, which may be 5.44 V.

[0191] In this embodiment, the capacitance of the second capacitor C2 can be 35fF, and the capacitance of the fourth capacitor C4 can be 140fF. The minimum voltage V2 can be the second minimum voltage V2b. The second minimum voltage V2b can be 5.53V. Compared with conventional gate drive circuits, the magnitude of the minimum voltage V2 can be increased. That is, the second minimum voltage V2b can be closer to the reference high voltage VGH than the first minimum voltage V2a. This can improve the stability of the first gate signal GC[1]. Therefore, the gate drive circuit 300 (see Figure 2The stability and reliability of ).

[0192] In this embodiment, the capacitance of the second capacitor C2 can be 17.5 fF, and the capacitance of the fourth capacitor C4 can be 70 fF. The minimum voltage V2 can be the third minimum voltage V2c. The third minimum voltage V2c can be 5.55 V. Compared with conventional gate drive circuits, the magnitude of the minimum voltage V2 can be increased. That is, the third minimum voltage V2c can be closer to the reference high voltage VGH than the first minimum voltage V2a. This can improve the stability of the first gate signal GC[1]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0193] In this embodiment, the capacitance of the second capacitor C2 can be 10fF, and the capacitance of the fourth capacitor C4 can be 70fF. The minimum voltage V2 can be the fourth minimum voltage V2d. The fourth minimum voltage V2d can be 5.62V. Compared with a conventional gate drive circuit, the magnitude of the minimum voltage V2 can be increased. That is, the fourth minimum voltage V2d can be closer to the reference high voltage VGH than the first minimum voltage V2a. In addition, as the capacitance of the third capacitor C3 decreases, the time for charging or discharging the third capacitor C3 can be reduced. Therefore, the load applied to the second clock signal CLK2 can be reduced. That is, the stability of the first gate signal GC[1] can be improved. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0194] In this embodiment, when the ratio of the capacitance of the second capacitor C2 to the capacitance of the fourth capacitor C4 is less than or equal to 0.25, the maximum voltage V1 and the minimum voltage V2 can approach the reference high voltage VGH. That is, the stability of the first gate signal GC[1] can be improved. In addition, when the ratio of the capacitance of the second capacitor C2 to the capacitance of the fourth capacitor C4 is less than or equal to 0.25, the power consumption of the gate drive circuit 300 can be reduced as the capacitance of each of the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 decreases.

[0195] Figure 8 It is shown Figure 1 A circuit diagram of an embodiment of the pixel PX of the display device 1.

[0196] refer to Figures 1 to 3 as well as Figure 8 The display panel 100 may include pixels PX, and each pixel PX may include a light-emitting element EE.

[0197] In this embodiment, the pixel PX can receive the data write gate signal GW[N], the compensation gate signal GC[N], the data initialization gate signal GI[N], the light-emitting element initialization gate signal GB[N], the data voltage VDATA, and the transmission signal EM[N], and can display an image based on the level of the data voltage VDATA.

[0198] In an embodiment, a pixel PX may include a first type of transistor and a second type of transistor, which is different from the first type of transistor. For example, the first type of transistor may be a PMOS transistor, and the second type of transistor may be an NMOS transistor.

[0199] Despite the pixel PX in Figure 8 The image is shown to include both NMOS and PMOS transistors, but the invention is not limited thereto. For example, a pixel PX may include only NMOS transistors.

[0200] At least one of the pixels PX may include a first pixel transistor PT1 to a seventh pixel transistor PT7, a storage capacitor CST, a boost capacitor CBOOST, and a light-emitting element EE.

[0201] The first pixel transistor PT1 may include a control electrode connected to the first pixel node NP1, a first electrode connected to the second pixel node NP2, and a second electrode connected to the third pixel node NP3.

[0202] The second pixel transistor PT2 may include a control electrode for receiving a data write gate signal GW[N], a first electrode for receiving a data voltage VDATA, and a second electrode connected to the second pixel node NP2.

[0203] The third pixel transistor PT3 may include a control electrode for receiving a compensation gate signal GC[N], a first electrode connected to the first pixel node NP1, and a second electrode connected to the third pixel node NP3.

[0204] The gate signal output from each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... of the gate drive circuit 300 can be a compensated gate signal GC[N].

[0205] The third pixel transistor PT3 can be turned on by a compensation gate signal GC[N] with a high level. The third pixel transistor PT3 can diode-connect the first pixel node NP1 and the third pixel node NP3 (e.g., diode-connect the first pixel transistor PT1). Pixel PX can operate a threshold voltage compensation operation to compensate for the threshold voltage.

[0206] The fourth pixel transistor PT4 may include a control electrode for receiving a data initialization gate signal GI[N], a first electrode connected to the first pixel node NP1, and a second electrode for receiving an initialization voltage VINIT.

[0207] The fifth pixel transistor PT5 may include a control electrode for receiving the transmit signal EM[N], a first electrode for receiving the high power supply voltage ELVDD, and a second electrode connected to the second pixel node NP2.

[0208] The sixth pixel transistor PT6 may include a control electrode for receiving the transmitted signal EM[N], a first electrode connected to the third pixel node NP3, and a second electrode connected to the anode of the light-emitting element EE.

[0209] The seventh pixel transistor PT7 may include a control electrode for receiving the light-emitting element initialization gate signal GB[N], a first electrode connected to the anode electrode Anode of the light-emitting element EE, and a second electrode for receiving the anode initialization voltage VAINIT.

[0210] The storage capacitor CST may include a first electrode for receiving a high power supply voltage ELVDD and a second electrode connected to the first pixel node NP1.

[0211] The boost capacitor CBOOST may include a first electrode for receiving the data write gate signal GW[N] and a second electrode connected to the first pixel node NP1.

[0212] The light-emitting element EE may include an anode connected to the second electrode of the sixth pixel transistor PT6 and a cathode for receiving a low power supply voltage ELVSS.

[0213] The driving current for pixel PX flows through the fifth pixel transistor PT5, the first pixel transistor PT1, and the sixth pixel transistor PT6 to drive the light-emitting element EE. The magnitude of the driving current is determined by the level of the data voltage VDATA. The brightness of the light-emitting element EE is determined by the magnitude of the driving current.

[0214] The fourth capacitor C4 can store the voltage difference between the second voltage DC and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the second voltage DC applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept high. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0215] When the second gate signal GC[2] is stably output, the pixel PX, which receives the second gate signal GC[2], can stably perform threshold voltage compensation operation. The data voltage VDATA can be sufficiently transmitted to the control electrode of the first pixel transistor PT1. Therefore, the pixel PX can emit light sufficiently with a brightness corresponding to the data voltage VDATA. This can improve the display quality of the display device 1.

[0216] Figure 9 It is shown Figure 2 A circuit diagram of an embodiment of stage 320 of gate drive circuit 300.

[0217] refer to Figures 1 to 3 as well as Figure 9 Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... can include multiple transistors and multiple capacitors. For ease of illustration, in Figure 9 Assuming that stage 320 is the first stage STAGE1 among stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... used to receive the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0218] Except for the voltage applied to the first electrode of the fourth capacitor C4 of the second control circuit 322 being the first voltage VGL, the first stage 320 and Figure 3 The first level 310 is essentially the same. Therefore, the same reference numerals will be used to refer to the same level as in [the previous level]. Figure 3 The components described in the previous embodiments are the same as or similar to those described above, and any repeated descriptions of the above components will be omitted.

[0219] The fourth capacitor C4 may include a first electrode for receiving a first voltage VGL and a second electrode connected to the second node N2.

[0220] The fourth capacitor C4 can store the voltage difference between the first voltage VGL and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the first voltage VGL applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept high. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0221] Figure 10 It is shown Figure 2 A circuit diagram of an embodiment of stage 330 of gate drive circuit 300.

[0222] refer to Figures 1 to 3 as well as Figure 10 Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... can include multiple transistors and multiple capacitors. For ease of illustration, in Figure 10 Assuming that stage 330 is the first stage STAGE1 among stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... used to receive the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0223] Except that the voltage applied to the first electrode of the fourth capacitor C4 in the second control circuit 322 is the third voltage VGH, the first stage 330 and Figure 3 The first level 310 is essentially the same. Therefore, the same reference numerals will be used to refer to the same level as in [the previous level]. Figure 3 The components described in the previous embodiments are the same as or similar to those described above, and any repeated descriptions of the above components will be omitted.

[0224] The fourth capacitor C4 may include a first electrode for receiving a third voltage VGH and a second electrode connected to the second node N2. The level of the third voltage VGH may be higher than the level of the first voltage VGL.

[0225] The fourth capacitor C4 can store the voltage difference between the third voltage VGH and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the third voltage VGH applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept high. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0226] Figure 11 It is shown Figure 2 A circuit diagram of an embodiment of stage 340 of gate drive circuit 300.

[0227] refer to Figures 1 to 3 as well as Figure 11 Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... can include multiple transistors and multiple capacitors. For ease of illustration, in Figure 11 Assuming that stage 340 is the first stage STAGE1 among stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... used to receive the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0228] In addition to the first stage 340, it also includes a reset circuit 315. The first stage 340 and Figure 3 The first level 310 is essentially the same. Therefore, the same reference numerals will be used to refer to the same level as in [the previous level]. Figure 3 The components described in the previous embodiments are the same as or similar to those described above, and any repeated descriptions of the above components will be omitted.

[0229] The first stage 340 may also include a reset circuit 315 for initializing the voltage of the first control node Q and the voltage of the second control node QB.

[0230] The reset circuit 315 may include a twelfth transistor T12 and a thirteenth transistor T13.

[0231] The twelfth transistor T12 may include a control electrode for receiving a reset signal SESR, a first electrode for receiving a first clock signal CLK1, and a second electrode connected to the fourth node N4.

[0232] The thirteenth transistor T13 may include a control electrode for receiving a reset signal SESR, a first electrode connected to a second control node QB, and a second electrode for receiving a first voltage VGL.

[0233] When the reset signal SESR is low, the twelfth transistor T12 and the thirteenth transistor T13 can be turned on. The voltage of the first control node Q can be initialized to a high level by the twelfth transistor T12. The voltage of the second control node QB can be initialized to a low level by the thirteenth transistor T13. The ninth transistor T9 can be turned on by the voltage of the second control node QB. The ninth transistor T9 can transmit the first clock signal CLK1 with a high level to the output node NO. Therefore, the first stage 340 can output the first gate signal GC with a high level[1].

[0234] When the gate drive circuit 300 operates for the first time, it can operate stably through the initialization operation of the reset circuit 315. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0235] In addition, the fourth capacitor C4 can store the voltage difference between the second voltage DC and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the second voltage DC applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept at a high level. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0236] Figure 12 It is shown Figure 2 A circuit diagram of an embodiment of stage 350 of gate drive circuit 300.

[0237] refer to Figures 1 to 3 as well as Figure 12 Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... can include multiple transistors and multiple capacitors. For ease of illustration, in Figure 12 Assuming that stage 350 is the first stage STAGE1 among stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... used to receive the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0238] Except for the voltage applied to the first electrode of the fourth capacitor C4 in the second control circuit 352 being the first voltage VGL, the first stage 350 and Figure 11 The first level 340 is essentially the same. Therefore, the same reference numerals will be used to refer to the same level as in [the previous level]. Figure 11 The components described in the previous embodiments are the same as or similar to those described above, and any repeated descriptions of the above components will be omitted.

[0239] The fourth capacitor C4 may include a first electrode for receiving a first voltage VGL and a second electrode connected to the second node N2.

[0240] The fourth capacitor C4 can store the voltage difference between the first voltage VGL and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the first voltage VGL applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept high. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0241] Figure 13 It is shown Figure 2 A circuit diagram of an embodiment of stage 360 ​​of the gate drive circuit 300.

[0242] refer to Figures 1 to 3 , Figure 10 as well as Figure 13 Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... can include multiple transistors and multiple capacitors. For ease of illustration, in Figure 13 Assuming that stage 360 ​​is the first stage STAGE1 among stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... used to receive the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0243] Except that the voltage applied to the first electrode of the fourth capacitor C4 in the second control circuit 362 is the third voltage VGH, the first stage 360 ​​and Figure 11 The first level 340 is essentially the same. Therefore, the same reference numerals will be used to refer to the same level as in [the previous level]. Figure 11 The components described in the previous embodiments are the same as or similar to those described above, and any repeated descriptions of the above components will be omitted.

[0244] The fourth capacitor C4 may include a first electrode for receiving a third voltage VGH and a second electrode connected to the second node N2. The level of the third voltage VGH may be higher than the level of the first voltage VGL.

[0245] The fourth capacitor C4 can store the voltage difference between the third voltage VGH and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the third voltage VGH applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept high. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0246] Figure 14 It is shown Figure 2 A circuit diagram of an embodiment of stage 370 of gate drive circuit 300.

[0247] refer to Figures 1 to 3 as well as Figure 14 Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... can include multiple transistors and multiple capacitors. For ease of illustration, in Figure 14 Assuming that stage 370 is the first stage STAGE1 among stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... used to receive the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0248] In addition to the switching circuit 313b of the second control circuit 372, the first stage 370 and Figure 3 The first level 310 is essentially the same. Therefore, the same reference numerals will be used to refer to the same level as in [the previous level]. Figure 3 The components described in the previous embodiments are the same as or similar to those described above, and any repeated descriptions of the above components will be omitted.

[0249] The switching circuit 313b may include a seventh transistor T7a.

[0250] The seventh transistor T7a may include a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode for receiving the second clock signal CLK2.

[0251] The second voltage DC can be a constant voltage. For example, the second voltage DC can be substantially the same as the first voltage VGL. For example, the level of the second voltage DC can be lower than the level of the first voltage VGL. For example, the level of the second voltage DC can be higher than the level of the first voltage VGL, and the second voltage DC can be a third voltage VGH.

[0252] The fourth capacitor C4 can store the voltage difference between the second voltage DC and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the second voltage DC applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept high. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0253] Figure 15 It is shown Figure 2 A circuit diagram of an embodiment of stage 380 of gate drive circuit 300.

[0254] refer to Figures 1 to 3 , Figure 14 as well as Figure 15 Each of the stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... can include multiple transistors and multiple capacitors. For ease of illustration, in Figure 15 Assuming that stage 380 is the first stage STAGE1 among stages STAGE1, STAGE2, STAGE3, STAGE4, ​​... used to receive the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2.

[0255] In addition to the first stage 380, it also includes a reset circuit 315. The first stage 380 and Figure 14 The first level 370 is essentially the same. Therefore, the same reference numerals will be used to refer to the same level as in [the previous level]. Figure 14 The components described in the previous embodiments are the same as or similar to those described above, and any repeated descriptions of the above components will be omitted.

[0256] The first stage 380 may also include a reset circuit 315 for initializing the voltage of the first control node Q and the voltage of the second control node QB.

[0257] The reset circuit 315 may include a twelfth transistor T12 and a thirteenth transistor T13.

[0258] The twelfth transistor T12 may include a control electrode for receiving a reset signal SESR, a first electrode for receiving a first clock signal CLK1, and a second electrode connected to the fourth node N4.

[0259] The thirteenth transistor T13 may include a control electrode for receiving a reset signal SESR, a first electrode connected to a second control node QB, and a second electrode for receiving a first voltage VGL.

[0260] When the reset signal SESR is low, the twelfth transistor T12 and the thirteenth transistor T13 can be turned on. The voltage of the first control node Q can be initialized to a high level by the twelfth transistor T12. The voltage of the second control node QB can be initialized to a low level by the thirteenth transistor T13. The ninth transistor T9 can be turned on by the voltage of the second control node QB. The ninth transistor T9 can transmit the first clock signal CLK1 with a high level to the output node NO. Therefore, the first stage 380 can output the first gate signal GC with a high level[1].

[0261] When the gate drive circuit 300 operates for the first time, it can operate stably through the initialization operation of the reset circuit 315. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0262] In addition, the fourth capacitor C4 can store the voltage difference between the second voltage DC and the voltage of the second node N2. The voltage of the second node N2 can be kept constant by the second voltage DC applied to the first electrode of the fourth capacitor C4 and the voltage stored in the fourth capacitor C4. Therefore, the voltage of the second node N2 can remain unchanged due to the coupling of the second capacitor C2. When the voltage of the second node N2 is kept constant, the second clock signal CLK2 transmitted to the second node N2 can be stably kept at a high level. Therefore, the second stage STAGE2 used to output the second clock signal CLK2 as the second gate signal GC[2] can stably output the second gate signal GC[2]. Therefore, the stability and reliability of the gate drive circuit 300 can be improved.

[0263] Figure 16 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Figure 17 It is shown Figure 16 The diagram shows an embodiment of the electronic device 1000 implemented as a smartphone.

[0264] refer to Figure 16 and Figure 17The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 1. In addition, the electronic device 1000 may also include a port for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices and other electronic devices.

[0265] In an embodiment, such as Figure 17 As shown, electronic device 1000 can be implemented as a smartphone. However, electronic device 1000 is not limited to this. For example, electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, and head-mounted display (HMD), etc.

[0266] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be coupled to other components via address bus, control bus, and data bus, etc. In addition, processor 1010 can be coupled to an expansion bus such as the peripheral component interconnect (PCI) bus.

[0267] Processor 1010 can output input image data IMG and input control signal CONT to Figure 1 The drive controller 200.

[0268] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0269] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, and read-only optical disc (CD-ROM) devices, etc.

[0270] I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, and touchscreen, as well as output devices such as a printer and speaker. According to an embodiment, I / O device 1040 may include display device 1060.

[0271] Power supply 1050 can provide power for the operation of electronic device 1000.

[0272] The display device 1060 can be connected to other components via a bus or other communication link.

[0273] Figure 18 This is a block diagram illustrating an electronic device 101 according to an embodiment of the present invention.

[0274] refer to Figures 1 to 18 The electronic device 101 outputs various information through the display module 140 in the operating system. When the processor 110 executes the application stored in the memory 120, the display module 140 provides application information to the user through the display panel 141.

[0275] Processor 110 receives external input via input module 130 or sensor module 161 and executes the application corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 141, processor 110 receives user input via input sensor 161-2 and activates camera module 171. Processor 110 transmits image data corresponding to the captured image obtained by camera module 171 to display module 140. Display module 140 can display the image corresponding to the captured image via display panel 141.

[0276] In this embodiment, when personal information authentication is performed in the display module 140, the fingerprint sensor 161-1 obtains the input fingerprint information as input data. The processor 110 compares the input data obtained by the fingerprint sensor 161-1 with the authentication data stored in the memory 120, and executes the application based on the comparison result. The display module 140 can display the information executed according to the application logic through the display panel 141.

[0277] In this embodiment, when a music stream icon displayed in the display module 140 is selected, the processor 110 obtains user input through the input sensor 161-2 and activates the music stream application stored in the memory 120. When a music execution command is entered in the music stream application, the processor 110 activates the sound output module 163 to provide the user with sound information corresponding to the music execution command.

[0278] The operation of electronic device 101 has been briefly described above. The configuration of electronic device 101 is described in detail below. Some components of electronic device 101, described later, may be integrated and provided as a single component, or a single component may be separated into two or more components.

[0279] Electronic device 101 can communicate with external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to an embodiment, electronic device 101 may include a processor 110, a memory 120, an input module 130, a display module 140, a power module 150, an embedded module 160, and an external module 170. According to an embodiment, at least one of the above-mentioned components may be omitted from electronic device 101, or one or more other devices may be added. According to an embodiment, some of the above-mentioned components (e.g., sensor module 161, antenna module 162, or voice output module 163) may be integrated into another component (e.g., display module 140).

[0280] Processor 110 can execute software to control at least one other element (e.g., hardware or software element) connected to electronic device 101 and perform various data processing or operations. According to an embodiment, as at least part of the data processing or operation, processor 110 can store instructions or data received from other elements (e.g., input module 130, sensor module 161, or communication module 173) in volatile memory 121, can process the instructions or data stored in volatile memory 121, and can store the result data of the processing in non-volatile memory 122.

[0281] Processor 110 may include a main processor 111 and an auxiliary processor 112. Main processor 111 may include at least one of a central processing unit (CPU) 111-1 and an application processor (AP). Main processor 111 may also include any one or more of a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 111 may also include a neural processing unit (NPU) 111-3. Neural processing unit 111-3 is a processor specifically designed to process artificial intelligence models. Artificial intelligence models can be generated through machine learning. Artificial intelligence models may include multiple layers of artificial neural networks (artificial neural networks). Artificial neural networks may be one or more of deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), and deep Q-networks, or a combination of two or more of these. However, artificial neural networks are not limited to the examples above. In addition to or instead of hardware structures, artificial intelligence models may include software structures. At least two of the aforementioned processing units and processors can be implemented as integrated elements (e.g., a single chip), or each can be implemented as a separate element (e.g., in multiple chips).

[0282] The main processor 111 can output image signals to the auxiliary processor 112. For example, the main processor 111 can output input image data IMG and input control signal CONT to the auxiliary processor 112.

[0283] The auxiliary processor 112 may include a controller. The controller may include interface conversion circuitry and timing control circuitry. The controller receives image signals from the main processor 111, converts the data format of the image signals to meet the interface specifications with the display module 140, and outputs the image data. The controller may output various control signals for driving the display module 140.

[0284] The auxiliary processor 112 may further include a data conversion circuit 112-2, a gamma correction circuit 112-3, and a rendering circuit 112-4. The data conversion circuit 112-2 can receive image data from the controller and can compensate the image data according to the characteristics of the electronic device 101 or user settings to display the image at a desired brightness, or can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit 112-3 can convert the image data or gamma reference voltage so that the image displayed in the electronic device 101 has desired gamma characteristics. The rendering circuit 112-4 can receive image data from the controller and can render the image data based on the pixel arrangement of the display panel 141 included in the electronic device 101. At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 may be integrated into another component (e.g., the main processor 111 or the controller). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into the data driver 143, which will be described later.

[0285] The memory 120 may store various data used by at least one element of the electronic device 101 (e.g., processor 110 or sensor module 161), as well as input or output data for commands in connection therewith. The memory 120 may include at least one of volatile memory 121 and non-volatile memory 122.

[0286] The input module 130 can receive commands or data from outside the electronic device 101 (e.g., from a user or external electronic device 102) for components of the electronic device 101 (e.g., processor 110, sensor module 161, or sound output module 163).

[0287] Input module 130 may include a first input module 131 for receiving commands or data from a user and a second input module 132 for receiving commands or data from an external electronic device 102. The first input module 131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 132 may support a specified protocol enabling wired or wireless connection to the external electronic device 102. According to embodiments, the second input module 132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 132 may include a connector (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)) physically connected to the external electronic device 102.

[0288] Display module 140 visually provides information to the user. Display module 140 may include display panel 141, scan driver 142, and data driver 143. Display module 140 may also include a window, a base, and a bracket to protect display panel 141.

[0289] Display panel 141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel. The type of display panel 141 is not particularly limited. Display panel 141 may be rigid or flexible, capable of being rolled or folded. Display module 140 may also include a support member or heat dissipation member supporting display panel 141.

[0290] The scan driver 142 can be mounted as a driver chip on the display panel 141. Alternatively, the scan driver 142 can be integrated into the display panel 141. For example, the scan driver 142 may include an amorphous silicon thin-film transistor (TFT) gate driver circuit (ASG), a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) integrated into the display panel 141. The scan driver 142 receives control signals from the controller and outputs scan signals to the display panel 141 in response to the control signals.

[0291] The display module 140 may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel 141 in response to a control signal received from the controller. The light-emitting driver may be formed independently of the scan driver 142. Alternatively, the light-emitting driver and the scan driver 142 may be formed integrally.

[0292] The data driver 143 receives a control signal from the controller and converts the image data into an analog voltage (e.g., a data voltage), and outputs the data voltage to the display panel 141 in response to the control signal.

[0293] The data driver 143 can be integrated into another component (e.g., a controller). The functions of the interface conversion circuitry and timing control circuitry of the controller described above can be integrated into the data driver 143.

[0294] The display module 140 may also include a voltage generation circuit. The voltage generation circuit can output various voltages for driving the display panel 141.

[0295] Power module 150 provides power to components of electronic device 101. Power module 150 may include a battery that supplies power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 150 may include a power management integrated circuit (PMIC). The PMIC provides optimized power to each of the modules described above and those described later. Power module 150 may include wireless power transmitting / receiving components electrically connected to the battery. The wireless power transmitting / receiving components may include multiple antenna radiators in the form of coils.

[0296] The electronic device 101 may also include an embedded module 160 and an external module 170. The embedded module 160 may include a sensor module 161, an antenna module 162, and a sound output module 163. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0297] The sensor module 161 can detect input via the user's body or via a pen in the first input module 131 and generate an electrical signal or data value corresponding to the input. The sensor module 161 may include at least one of a fingerprint sensor 161-1, an input sensor 161-2, and a digitizer 161-3.

[0298] The fingerprint sensor 161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 161-1 may include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0299] Input sensor 161-2 can generate data values ​​corresponding to coordinate information of input via the user's body or via a pen. Input sensor 161-2 generates capacitance changes caused by the input as data values. Input sensor 161-2 can detect input via a passive pen or send / receive data to / from an active pen.

[0300] Input sensor 161-2 can measure biosignals such as blood pressure, water content, or body fat. For example, when a user touches a part of their body to the sensor layer or sensing panel and does not move it within a specific time period, input sensor 161-2 can detect biosignals based on changes in the electric field caused by the part of the body, allowing display module 140 to output the information desired by the user.

[0301] The digitizer 161-3 can generate data values ​​corresponding to coordinate information input via a pen. The digitizer 161-3 generates data values ​​from the electromagnetic changes caused by the input. The digitizer 161-3 can detect input via a passive pen or send / receive data to / from an active pen.

[0302] At least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be formed as a sensor layer on the display panel 141 via a continuous process. The fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be disposed on the display panel 141. At least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 (e.g., digitizer 161-3) can be disposed beneath the display panel 141.

[0303] At least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be integrated into the sensing panel using the same process. When at least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 are integrated into the sensing panel, the sensing panel can be positioned between the display panel 141 and a window positioned above the upper surface of the display panel 141. According to an embodiment, the sensing panel can be positioned on the window. The invention is not limited to the position of the sensing panel.

[0304] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be embedded in the display panel 141. For example, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 may be formed simultaneously with the display panel 141 by a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 141.

[0305] Additionally, sensor module 161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 101. For example, sensor module 161 may also include a gesture sensor, gyroscope sensor, barometric pressure sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, IR (infrared) sensor, biosensor, temperature sensor, humidity sensor, or illuminance sensor.

[0306] Antenna module 162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. According to an embodiment, communication module 173 may transmit or receive signals to or from external electronic device 102 via an antenna suitable for a communication method. The antenna pattern of antenna module 162 may be integrated with elements of display module 140 (e.g., display panel 141) or input sensors 161-2.

[0307] The sound output module 163 is a device for outputting sound signals to the outside of the electronic device 101. For example, the sound output module 163 may include a speaker for general purposes such as playing multimedia or recording, and a receiver specifically for receiving calls. According to embodiments, the receiver may be integrally formed with the speaker or formed separately from the speaker. The sound output pattern of the sound output module 163 may be integrated with the display module 140.

[0308] Camera module 171 can capture still images and moving images. According to embodiments, camera module 171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 171 may also include an infrared camera capable of determining the presence or absence of a user, the user's location, and the user's gaze.

[0309] The optical module 172 can provide light. The optical module 172 may include a light-emitting diode or a xenon lamp. The optical module 172 can operate in conjunction with the camera module 171 or independently.

[0310] Communication module 173 can support the establishment of wired or wireless communication channels between electronic device 101 and external electronic device 102, as well as communication through the established communication channels. Communication module 173 may include one or both of the following: wireless communication modules such as cellular communication modules, short-range wireless communication modules, or Global Navigation Satellite System (GNSS) communication modules; and wired communication modules such as local area network (LAN) communication modules or power line communication modules. Communication module 173 can communicate with external electronic device 102 via short-range communication networks such as Bluetooth, WiFi Direct, or Infrared Data Association (IrDA), or long-range communication networks such as cellular networks, the Internet, or computer networks (e.g., LAN or WAN). The various types of communication modules 173 described above can be implemented as a single chip, or can be implemented as separate chips.

[0311] The input module 130, sensor module 161, and camera module 171 can be used in conjunction with the processor 110 to control the operation of the display module 140.

[0312] The processor 110 outputs commands or data to the display module 140, the sound output module 163, the camera module 171, or the optical module 172 based on the input data received from the input module 130. For example, the processor 110 can generate image data corresponding to the input data applied by a mouse or active pen and output the generated image data to the display module 140, or the processor 110 can generate command data corresponding to the input data and output the generated command data to the camera module 171 or the optical module 172. When no input data is received from the input module 130 during a specific time interval, the processor 110 switches the operating mode of the electronic device 101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 101.

[0313] Processor 110 outputs commands or data to display module 140, sound output module 163, camera module 171, or optical module 172 based on sensing data received from sensor module 161. For example, processor 110 can compare authentication data applied by fingerprint sensor 161-1 with authentication data stored in memory 120, and then execute an application based on the comparison result. Processor 110 can execute commands or output corresponding image data to display module 140 based on sensing data sensed by input sensor 161-2 or digitizer 161-3. When sensor module 161 includes a temperature sensor, processor 110 can receive temperature data for the temperature measured from sensor module 161, and can also perform brightness correction on image data based on the temperature data.

[0314] Processor 110 can receive data from camera module 171 that relates to the presence or absence of a user, the user's position, and the user's gaze. Processor 110 can also perform brightness correction on image data based on the determined data. For example, processor 110, which determines the presence or absence of a user based on input from camera module 171, can display image data with brightness corrected by data conversion circuit 112-2 or gamma correction circuit 112-3 on display module 140.

[0315] Some of the above components can be connected to each other via communication methods such as buses, general purpose input / output (GPIO), serial peripheral interfaces (SPI), mobile industrial processor interfaces (MIPI), or ultrapath interconnect (UPI) links to exchange signals (e.g., commands or data). Processor 110 can communicate with display module 140 through a pre-defined interface. For example, processor 110 can communicate with display module 140 through any of the above communication methods. The invention is not limited to these communication methods.

[0316] The electronic device 101 according to the various embodiments disclosed in this disclosure can be of various types. For example, the electronic device 101 may include at least one of portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. The electronic device 101 according to the embodiments of this disclosure is not limited to the foregoing devices.

[0317] For example, Figure 1 The display panel 100 can correspond to Figure 18 Display panel 141. For example, Figure 1 The drive controller 200 can correspond to Figure 18 The controller of the auxiliary processor 112. For example. Figure 1 The gate drive circuit 300 can correspond to Figure 18 The scan driver 142. For example. Figure 1 The data drive circuit 500 can correspond to Figure 18 Data drive 143.

[0318] Alternatively, the main processor 111 can be an application processor (AP). When the electronic device 101 is powered on, the application processor (AP) can output a power-on signal to the drive controller 200. When the drive controller 200 receives the power-on signal, it can output a low-level reset signal SESR to the gate drive circuit 300. The twelfth transistor T12 and the thirteenth transistor T13 included in the gate drive circuit 300 can be turned on in response to the low-level reset signal SESR. The voltage of the first control node Q can be initialized to a high-level voltage through the twelfth transistor T12. The voltage of the second control node QB can be initialized to a low-level voltage through the thirteenth transistor T13.

[0319] Additionally, the application processor (AP) can send the input image data IMG and the input control signal CONT to the drive controller 200. The drive controller 200 can output a first control signal CONT1 to the gate drive circuit 300 in response to the input control signal CONT. The first control signal CONT1 may include a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2.

[0320] This invention can be applied to any display device and any electronic device that includes such a display device. For example, this invention can be applied to televisions (TV), digital TVs, 3D TVs, mobile phones, smartphones, PCs (e.g., tablet computers, laptop computers), home electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0321] The foregoing is illustrative of the invention and should not be construed as limiting it. Although several embodiments of the invention have been described, those skilled in the art will readily understand that many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. In the claims, the device plus function clause is intended to cover structures described herein as performing the described functions, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the invention and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the appended claims, which will be included by the equivalents of the claims.

Claims

1. A gate drive circuit, wherein, The gate drive circuit includes: a first control circuit configured to control a voltage of a first control node based on an input signal, a first clock signal, and a second clock signal; a second control circuit configured to control a voltage of a second control node based on the first clock signal and the second clock signal; and an output circuit configured to output the first clock signal or a first voltage as a gate signal based on the voltage of the first control node and the voltage of the second control node, wherein the second control circuit includes: a switching circuit connected to a first node and a second node, and the switching circuit is configured to receive the second clock signal; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and a fourth capacitor including a first electrode configured to receive a second voltage and a second electrode connected to the second node.

2. The gate drive circuit according to claim 1, wherein The switching circuit includes: a sixth transistor including a control electrode connected to the first node, a first electrode connected to a third node, and a second electrode configured to receive the second clock signal; and a seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node.

3. The gate drive circuit according to claim 1, wherein The switching circuit includes a seventh transistor including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode configured to receive the second clock signal.

4. The gate drive circuit of claim 1, wherein, The second voltage is the same as the first voltage.

5. The gate drive circuit of claim 1, wherein, The second control circuit further includes: a third transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage, and a second electrode connected to a fifth node; a fourth transistor including a control electrode configured to receive the first voltage, a first electrode connected to the fifth node, and a second electrode connected to the first node; a fifth transistor including a control electrode connected to the first control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the fifth node; an eighth transistor including a control electrode configured to receive the second clock signal, a first electrode connected to the second node, and a second electrode connected to the second control node; and a first capacitor including a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

6. The gate drive circuit of claim 1, wherein, The first control circuit includes: a first transistor including a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a fourth node; a second transistor including a control electrode connected to the first control node, a first electrode connected to a sixth node, and a second electrode configured to receive the second clock signal; an eleventh transistor including a control electrode configured to receive the first voltage, a first electrode connected to the fourth node, and a second electrode connected to the first control node; and a tenth transistor including a control electrode connected to the second control node, a first electrode connected to the sixth node, and a second electrode configured to receive the second clock signal. a third capacitor comprising a first electrode connected to the first control node and a second electrode connected to the sixth node.

7. The gate drive circuit of claim 1, wherein, the output circuit comprises: a ninth transistor comprising a control electrode connected to the second control node, a first electrode configured to receive the first clock signal, and a second electrode connected to an output node; and a tenth transistor comprising a control electrode connected to the first control node, a first electrode connected to the output node, and a second electrode configured to receive the first voltage.

8. The gate drive circuit of claim 1, wherein, the gate driving circuit further comprises a reset circuit configured to initialize the voltage of the first control node and the voltage of the second control node based on a reset signal, wherein the reset circuit comprises: a twelfth transistor comprising a control electrode configured to receive the reset signal, a first electrode configured to receive the first clock signal, and a second electrode connected to a fourth node; and a thirteenth transistor comprising a control electrode configured to receive the reset signal, a first electrode connected to the second control node, and a second electrode configured to receive the first voltage.

9. A display device, wherein, the display device comprises: a display panel comprising a plurality of pixels; a data driving circuit configured to provide data voltages to the plurality of pixels; a gate driving circuit configured to provide gate signals to the plurality of pixels; and a driving controller configured to control the data driving circuit and the gate driving circuit, wherein the gate driving circuit comprises: a first control circuit configured to control a voltage of a first control node based on an input signal, a first clock signal, and a second clock signal; a second control circuit configured to control a voltage of a second control node based on the first clock signal and the second clock signal; and an output circuit configured to output, as the gate signals, the first clock signal or a first voltage based on the voltage of the first control node and the voltage of the second control node, wherein the second control circuit comprises: a switching circuit connected to a first node and a second node, and the switching circuit is configured to receive the second clock signal; a second capacitor comprising a first electrode connected to the first node and a second electrode connected to the second node; and a fourth capacitor comprising a first electrode configured to receive a second voltage and a second electrode connected to the second node.

10. The display device of claim 9, wherein, the switching circuit comprises: a sixth transistor comprising a control electrode connected to the first node, a first electrode connected to a third node, and a second electrode configured to receive the second clock signal; and a seventh transistor comprising a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node.

11. The display device of claim 9, wherein, the switching circuit comprises a seventh transistor comprising a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode configured to receive the second clock signal.

12. The display device of claim 9, wherein, the second voltage is the same as the first voltage.

13. The display device of claim 9, wherein, the second control circuit further comprises: a third transistor comprising a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage, and a second electrode connected to a fifth node; a fourth transistor comprising a control electrode configured to receive the first voltage, a first electrode connected to the fifth node, and a second electrode connected to the first node; a fifth transistor comprising a control electrode connected to the first control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the fifth node; an eighth transistor comprising a control electrode configured to receive the second clock signal, a first electrode connected to the second node, and a second electrode connected to the second control node; and a first capacitor comprising a first electrode configured to receive the first clock signal and a second electrode connected to the second control node.

14. The display device of claim 9, wherein, The first control circuit comprises: a first transistor comprising a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a fourth node; a second transistor comprising a control electrode connected to the first control node, a first electrode connected to a sixth node, and a second electrode configured to receive the second clock signal; an eleventh transistor comprising a control electrode configured to receive the first voltage, a first electrode connected to the fourth node, and a second electrode connected to the first control node; and a third capacitor comprising a first electrode connected to the first control node and a second electrode connected to the sixth node.

15. The display device of claim 9, wherein, The output circuit comprises: a ninth transistor comprising a control electrode connected to the second control node, a first electrode configured to receive the first clock signal, and a second electrode connected to an output node; and a tenth transistor comprising a control electrode connected to the first control node, a first electrode connected to the output node, and a second electrode configured to receive the first voltage.

16. The display device of claim 9, wherein, The gate drive circuit further comprises a reset circuit configured to initialize the voltage of the first control node and the voltage of the second control node based on a reset signal, wherein the reset circuit comprises: a twelfth transistor comprising a control electrode configured to receive the reset signal, a first electrode configured to receive the first clock signal, and a second electrode connected to a fourth node; and a thirteenth transistor comprising a control electrode configured to receive the reset signal, a first electrode connected to the second control node, and a second electrode configured to receive the first voltage.

17. An electronic device, wherein, The electronic device comprises: a display panel comprising a plurality of pixels; a data driving circuit configured to provide a data voltage to the plurality of pixels; a gate drive circuit configured to provide a gate signal to the plurality of pixels; a driving controller configured to control the data driving circuit and the gate drive circuit; and a processor configured to output a power-on signal, input image data, and an input control signal to the driving controller, wherein, when the electronic device is powered on, the processor is configured to output the power-on signal to the driving controller, wherein, in response to the power-on signal, the driving controller is configured to output a reset signal for initializing the gate driving circuit to the gate driving circuit, in response to the input control signal, output a start signal, a first clock signal and a second clock signal for operating the gate driving circuit, wherein the gate driving circuit comprises: a first control circuit configured to control a voltage of a first control node based on an input signal, the first clock signal and the second clock signal; a second control circuit configured to control a voltage of a second control node based on the first clock signal and the second clock signal; a reset circuit configured to initialize the voltage of the first control node and the voltage of the second control node based on the reset signal; and an output circuit configured to output the first clock signal or a first voltage as the gate signal based on the voltage of the first control node and the voltage of the second control node, wherein the second control circuit comprises: a switching circuit connected to a first node and a second node, and the switching circuit is configured to receive the second clock signal; a second capacitor comprising a first electrode connected to the first node and a second electrode connected to the second node; and a fourth capacitor comprising a first electrode configured to receive a second voltage and a second electrode connected to the second node. 18.The electronic device of claim 17, wherein, the switching circuit comprises: a sixth transistor comprising a control electrode connected to the first node, a first electrode connected to a third node and a second electrode configured to receive the second clock signal; and a seventh transistor comprising a control electrode connected to the first node, a first electrode connected to the second node and a second electrode connected to the third node. 19.The electronic device of claim 17, wherein, the second control circuit further comprises: a third transistor comprising a control electrode configured to receive the first clock signal, a first electrode configured to receive the first voltage and a second electrode connected to a fifth node; a fourth transistor comprising a control electrode configured to receive the first voltage, a first electrode connected to the fifth node and a second electrode connected to the first node; a fifth transistor comprising a control electrode connected to the first control node, a first electrode configured to receive the first clock signal and a second electrode connected to the fifth node; an eighth transistor comprising a control electrode configured to receive the second clock signal, a first electrode connected to the second node and a second electrode connected to the second control node; and a first capacitor comprising a first electrode configured to receive the first clock signal and a second electrode connected to the second control node. 20.The electronic device of claim 17, wherein, the first control circuit comprises: a first transistor comprising a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal and a second electrode connected to a fourth node; a second transistor comprising a control electrode connected to the fourth node, a first electrode connected to the first control node and a second electrode connected to a third node; and a third transistor comprising a control electrode connected to the third node, a first electrode connected to the first control node and a second electrode configured to receive the input signal. a second transistor comprising a control electrode connected to the first control node, a first electrode connected to a sixth node, and a second electrode configured to receive the second clock signal; an eleventh transistor comprising a control electrode configured to receive the first voltage, a first electrode connected to the fourth node, and a second electrode connected to the first control node; and a third capacitor comprising a first electrode connected to the first control node and a second electrode connected to the sixth node.

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