Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a plurality of sub-pixels which are distributed in rows and columns; the driving system comprises a controller, a data driver and a gate driver, the controller is electrically connected with the data driver and the gate driver, the data driver is electrically connected with the sub-pixels through data lines, and the gate driver is electrically connected with the sub-pixels through gate lines; the controller controls the work of the data driver and the gate driver, the data driver receives image data and converts the image data into data voltage, the data voltage of each row of sub-pixels is written into the sub-pixels line by line, and the gate driver scans the sub-pixels line by line; wherein the controller and / or the data driver comprises a thin film transistor. According to the embodiment of the invention, the display panel can be applied to a flexible display product.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and flat display devices based on Light Emitting Diode (LED) technology have been widely applied to mobile phones, televisions, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0003] However, the performance of the current OLED display products needs to be improved. SUMMARY

[0004] The display panel and the display device provided by the embodiments of the present application can be applied to flexible display products.

[0005] In a first aspect, the embodiments of the present application provide a display panel, comprising: a plurality of sub-pixels, arranged in a row-column distribution; a driving system, the driving system comprising a controller, a data driver and a gate driver, the controller being electrically connected with the data driver and the gate driver, the data driver being electrically connected with the sub-pixels through data lines, and the gate driver being electrically connected with the sub-pixels through gate lines; the controller controls the operation of the data driver and the gate driver, the data driver receives image data and converts the image data into data voltages, and writes the data voltages of each row of sub-pixels into the sub-pixels row by row, and the gate driver scans the sub-pixels row by row; wherein the controller and / or the data driver comprises a thin film transistor.

[0006] In a possible implementation manner of the first aspect, the controller, the data driver and the gate driver all comprise thin film transistors; Preferably, the sub-pixels comprise thin film transistors, and the active layers of at least part of the thin film transistors in the controller, the data driver and the gate driver are arranged in the same layer as the active layers of the thin film transistors in the sub-pixels.

[0007] In a possible implementation manner of the first aspect, the data driver comprises a shift register, a row latch and a data voltage converter, the controller is electrically connected with the shift register, the row latch is electrically connected between the shift register and the data voltage converter, and the data voltage converter is electrically connected with the sub-pixels through the data lines; the shift register receives image data and writes the image data of each row of sub-pixels into the row latch row by row, the row latch temporarily stores the image data of one row of sub-pixels, and the data voltage converter converts the image data temporarily stored in the row latch into data voltages and writes the data voltages into the sub-pixels row by row.

[0008] In a possible implementation of the first aspect, the driving system further comprises a level conversion circuit configured to lift the accessed signals from the first voltage domain to the second voltage domain. Preferably, the accessed signals of the controller, the shift register and the gate driver are signals converted by the level conversion circuit; or the level conversion circuit comprises a first level conversion circuit and / or a second level conversion circuit, the first level conversion circuit is electrically connected to a data transmission path from the row latch to the sub-pixel, the gate driver comprises a gate drive circuit, an output terminal of the gate drive circuit is electrically connected to the sub-pixel through a gate line, and the second level conversion circuit is electrically connected to an input terminal of the gate drive circuit.

[0009] In a possible implementation of the first aspect, the gate driver comprises a first counter, a gate drive signal generation circuit and a gate drive circuit, the first counter is electrically connected to an input terminal of the gate drive signal generation circuit, an output terminal of the gate drive signal generation circuit is electrically connected to an input terminal of the gate drive circuit, and an output terminal of the gate drive circuit is electrically connected to the sub-pixel through a gate line. The first counter comprises a row counter, a column counter and a logic circuit, the logic circuit generates a write enable signal of the row latch when the column counter counts to the number of the sub-pixels in a row. The row counter counts to the total number of rows of the sub-pixels, indicating that the scanning of a frame is completed. The gate drive signal generation circuit generates trigger signals and clock signals required by the gate drive circuit based on the row counter and the column counter, to control the gate drive circuit to scan the sub-pixels row by row.

[0010] In a possible implementation of the first aspect, the controller comprises a state machine, and a control state of the state machine comprises a write image data state, the column counter counts when the state machine is in the write image data state and the chip select signal is at a valid level. Preferably, the column counter is cleared when the chip select signal is at an invalid level. Preferably, the row counter counts up by one when the state machine is in the write image data state and at each falling edge of the chip select signal. Preferably, the row counter is set when the row counter counts to a preset value, and the row counter counts in a next counting period after being set.

[0011] In a possible implementation of the first aspect, the driving system further comprises an interface logic circuit, the interface logic circuit analyzes the input signals and generates control signals of the driving system. Preferably, the controller comprises a state machine, a register, a read address decoder, a write address decoder, the register stores control parameters, the read address decoder controls enabling of reading of the register, the write address decoder controls enabling of writing of the register, the state machine is configured to realize jump control between a reset state, a register reading state, a register writing state and an image data writing state, wherein, in the reset state, the register is cleared; in the register reading state, the register is read; in the register writing state, the register is written; in the image data writing state, image data is written into the shift register; Preferably, the signal accessed by the driving system comprises a system instruction, a parameter instruction and an image instruction, and the state machine performs state jump based on the system instruction; Preferably, the system instruction is 8-bit data, and the most significant bit of the system instruction is in front; Preferably, the parameter instruction is 24-bit data, wherein the address is 8-bit and the parameter value is 16-bit, and the most significant bit of the parameter instruction is in front; Preferably, the image instruction comprises image data, and the image data is transmitted in cycles of data corresponding to an entire row of sub-pixels; Preferably, the valid level width of the chip select signal is 24 cycles of the clock signal, and the signal corresponding to the chip select signal is the parameter instruction; Preferably, when the state machine is in the image data writing state, if the valid level width of the chip select signal is greater than 8 cycles of the clock signal, the signal corresponding to the chip select signal is the image instruction; if the valid level width of the chip select signal is equal to 8 cycles of the clock signal, the signal corresponding to the chip select signal is the system instruction; Preferably, the interface logic circuit generates an instruction identification signal, and the instruction identification signal is used to identify the system instruction.

[0012] In a possible implementation manner of the first aspect, the read address decoder is short-circuited with a read enable pin of the register, and the driving system further comprises a parallel-serial conversion circuit, the parallel-serial conversion circuit is electrically connected with the read address decoder and the register, and the parallel-serial conversion circuit converts data read from the register in time division into serial data and outputs the serial data; Preferably, the register comprises a first static random access memory, the first static random access memory comprises an inner node and an outer node, the inner node and the outer node are connected through a read control transistor, a gate of the read control transistor is electrically connected with an output terminal of the read address decoder as a read enable pin, the outer nodes of a plurality of first static random access memories are short-circuited and then electrically connected with the parallel-serial conversion circuit through a first inverter, and the outer nodes of the plurality of first static random access memories output signals to the first inverter in time division; Preferably, the inner node is electrically connected with a gate driver through a second inverter; Preferably, the driving system comprises a plurality of registers arranged in an array, the write enable pins of the registers in the same row are short-circuited, the read enable pins of the registers in the same row are short-circuited, the input pins of the registers in the same column are short-circuited, and the output nodes of the registers in the same column are short-circuited.

[0013] In a possible implementation of the first aspect, the image data is m-bit, and the data voltage converter comprises a first transistor, a second transistor, and m third transistors, the first transistor is electrically connected between a first reference gamma voltage terminal and a data line, the first electrode of the second transistor is electrically connected to the data line, and the m third transistors are connected in parallel between the second electrode of the second transistor and a second reference gamma voltage terminal; the gates of the m third transistors are electrically connected to a row latch, and the width-length ratios of the m third transistors are different. Preferably, the width-length ratios of the m third transistors increase in turn. Preferably, the width-length ratio of the i+1th third transistor is twice the width-length ratio of the ith third transistor, and i is any value in 1 to m-1. Preferably, in the first stage, the first transistor is turned on, and the second transistor is turned off; in the second stage, the first transistor is turned off, the second transistor is turned on, and at least one of the m third transistors is turned on.

[0014] In a possible implementation of the first aspect, the data voltage converter comprises a digital-to-analog converter and an operational amplifier, the digital-to-analog converter is electrically connected between the row latch and the input terminal of the operational amplifier, and the output terminal of the operational amplifier is electrically connected to the data line.

[0015] In a possible implementation of the first aspect, the data voltage converter comprises an inverter, and the inverter is electrically connected between the row latch and the data line. Preferably, the inverter comprises a fourth transistor and a fifth transistor, the first electrode of the fourth transistor is electrically connected to a high-level signal terminal, the first electrode of the fifth transistor is electrically connected to a low-level signal terminal, the gate of the fourth transistor and the gate of the fifth transistor are short-circuited as an input terminal, and the second electrode of the fourth transistor and the second electrode of the fifth transistor are short-circuited as an output terminal; the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0016] In a possible implementation of the first aspect, the shift register comprises a plurality of D flip-flops connected in series, and the clock terminals of the plurality of D flip-flops are connected to the same clock signal. Preferably, the driving system comprises a plurality of shift registers, the first preset number of D flip-flops of the first shift register are used to receive a system instruction, a parameter instruction, and an image instruction, and the other D flip-flops of the first shift register and the shift registers of the other strings after the first string are used to receive the image instruction.

[0017] In one possible implementation of the first aspect, the row latch includes a plurality of second static random access memories; the controller includes a register, the register including a first static random access memory, the first static random access memory and / or the second static random access memory including: The sixth transistor has its first terminal connected to the write signal line, its second terminal connected to the first node, and its gate connected to the write control signal. The seventh transistor has its first terminal connected to a high-level signal terminal, its second terminal connected to the first node, and its gate connected to the second node. The eighth transistor has its first terminal connected to the first node, its second terminal connected to the low-level signal terminal, and its gate connected to the second node. The ninth transistor has its first terminal connected to a high-level signal terminal, its second terminal connected to the second node, and its gate connected to the first node. The tenth transistor has its first terminal connected to the second node, its second terminal connected to a low-level signal terminal, and its gate connected to the first node. The eleventh transistor has its first terminal connected to the second node, its second terminal connected to the read signal line, and its gate connected to the read control signal. The sixth, seventh, ninth, and eleventh transistors are P-type transistors, while the eighth and tenth transistors are N-type transistors.

[0018] In one possible implementation of the first aspect, the level conversion circuit includes: The twelfth transistor has its first terminal connected to the first high-level signal terminal, its second terminal connected to the third node, and its gate connected to the input signal terminal. The thirteenth transistor has its first terminal connected to the third node, its second terminal connected to the first low-level signal terminal, and its gate connected to the input signal terminal. The fourteenth transistor has its first terminal connected to the first high-level signal terminal, its second terminal connected to the fourth node, and its gate connected to the input signal terminal. The fifteenth transistor has its first terminal connected to the fourth node, its second terminal connected to the second low-level signal terminal, and its gate connected to the fifth node. The sixteenth transistor has its first terminal connected to the first high-level signal terminal, its second terminal connected to the fifth node, and its gate connected to the third node. The seventeenth transistor has its first terminal connected to the fifth node, its second terminal connected to the second low-level signal terminal, and its gate connected to the fourth node. The eighteenth transistor has its first terminal connected to the second high-level signal terminal, its second terminal connected to the sixth node, and its gate connected to the seventh node. The nineteenth transistor has its first terminal connected to the sixth node, its second terminal connected to the second low-level signal terminal, and its gate connected to the fifth node. The twentieth transistor has its first terminal connected to the second high-level signal terminal, its second terminal connected to the seventh node, and its gate connected to the sixth node. The twenty-first transistor has its first terminal connected to the seventh node, its second terminal connected to the second low-level signal terminal, and its gate connected to the fourth node; the seventh node is connected to the output signal terminal. The twelfth, fourteenth, sixteenth, eighteenth, and twentieth transistors are P-type transistors, while the thirteenth, fifteenth, seventeenth, nineteenth, and twenty-first transistors are N-type transistors.

[0019] In one possible implementation of the first aspect, the controller includes a second counter electrically connected to a shift register, wherein the second counter controls the shift register to receive image data when the count of the second counter reaches a preset value.

[0020] In one possible implementation of the first aspect, the driving system further includes a charge pump configured to generate a driving voltage for the display panel, the driving voltage including a first reference gamma voltage, a second reference gamma voltage, a high-level voltage, and a low-level voltage.

[0021] Secondly, embodiments of this application provide a display device, including a display panel as described in any embodiment of the first aspect. According to the display panel provided in the embodiments of this application, the driving system can drive sub-pixels to display, and the controller and / or data driver includes thin-film transistors. Thin-film transistors are flexible devices that can avoid the use of rigid silicon-based ICs for driving, enabling the display panel to be applied to flexible display products. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0023] Figure 1 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application; Figure 2 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 3 This illustration shows another structural diagram of the display panel provided in an embodiment of this application; Figure 4 This illustration shows a schematic diagram of a shift register provided in an embodiment of this application; Figure 5 This illustration shows a schematic diagram of a D flip-flop provided in an embodiment of this application; Figure 6 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 7 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 8 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 9 This illustration shows a schematic diagram of a level conversion circuit provided in an embodiment of this application; Figure 10 This illustration shows a structural diagram of a counter provided in an embodiment of this application; Figure 11 This diagram illustrates a timing structure of a gate drive circuit provided in an embodiment of this application. Figure 12 This illustration shows a state transition diagram of a state machine provided in an embodiment of this application; Figure 13 This illustration shows a timing diagram of system instructions provided in an embodiment of this application; Figure 14 This diagram illustrates a timing diagram of parameter instructions provided in an embodiment of this application. Figure 15 This illustration shows a timing diagram of image instructions provided in an embodiment of this application; Figure 16 This illustration shows a schematic diagram of a register structure provided in an embodiment of this application; Figure 17 This diagram illustrates a connection of multiple registers provided in an embodiment of this application. Figure 18 This illustration shows an address diagram of a decoder provided in an embodiment of this application; Figure 19 This diagram illustrates a readout structure for serial data provided in an embodiment of this application. Figure 20 This diagram illustrates a timing sequence for reading serial data according to an embodiment of this application. Figure 21 This illustration shows a structural schematic of a row latch provided in an embodiment of this application; Figure 22 This illustration shows a schematic diagram of a data voltage converter provided in an embodiment of this application; Figure 23 Show Figure 22 A timing diagram; Figure 24 This diagram illustrates a correspondence between different data provided in an embodiment of this application. Figure 25This diagram illustrates a timing schematic of a display panel provided in an embodiment of this application. Figure 26 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 27 This illustration shows a schematic diagram of an inverter provided in an embodiment of this application; Figure 28 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0024] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0025] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0026] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0027] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0028] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0029] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0030] Current OLED display panels are typically driven using silicon-based driver chips (ICs). However, when these panels are used in augmented reality (AR) glasses, space constraints prevent the use of silicon-based ICs, and silicon-based ICs are not flexible. Therefore, how to drive a display panel and achieve a flexible display without an IC is a technical problem faced by those skilled in the art.

[0031] To address the aforementioned technical problems, this application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0032] This application provides a display panel, which may be an organic light-emitting diode (OLED) display panel.

[0033] like Figure 1 As shown, the display panel 100 provided in this application embodiment includes sub-pixels 10, data lines DL, gate lines GL, and a driving system 20.

[0034] The display panel 100 includes a display area AA and a non-display area that at least partially surrounds the display area. Sub-pixels 10 are located in the display area, and the driving system 20 is located in the non-display area. Data lines DL and gate lines GL extend from the non-display area to the display area to realize the connection between the sub-pixels 10 and the driving system 20.

[0035] Multiple sub-pixels 10 are arranged in rows and columns along intersecting first and second directions X and Y, respectively. For example, the first direction X is the row direction and the second direction Y is the column direction. A data line DL extends along the second direction Y, and one data line DL is electrically connected to multiple sub-pixels 10 in the same column. A gate line GL extends along the first direction X, and one gate line GL is electrically connected to multiple sub-pixels 10 in the same row.

[0036] The driving system 20 includes a controller 21, a data driver 22, and a gate driver 23. The controller 21 is electrically connected to the data driver 22 and the gate driver 23. The data driver 22 is electrically connected to the sub-pixel 10 via a data line DL, and the gate driver 23 is electrically connected to the sub-pixel 10 via a gate line GL.

[0037] The controller 21 is used to control the operation of the data driver 22 and the gate driver 23. The data driver 22 receives image data and converts it into data voltage, and writes the data voltage of each sub-pixel 10 to the sub-pixel 10 line by line. The gate driver 23 scans the sub-pixels line by line.

[0038] The data driver 22 can receive image data from the host system. The image data includes at least grayscale data of the image to be displayed. The data driver 22 converts the image data into a data voltage that can directly drive the sub-pixel 10.

[0039] like Figure 2 As shown, sub-pixel 10 includes pixel circuit 11 and light-emitting element 12. Pixel circuit 11 includes driving transistor M1 and switching transistor M2. The gate of switching transistor M2 is connected to gate line GL, the first electrode of switching transistor M2 is connected to data line DL, the second electrode of switching transistor M2 is connected to the gate of driving transistor M1, the first electrode of driving transistor M1 is connected to the first power line ELVDD, the second electrode of driving transistor M1 is connected to the anode of light-emitting element 12, and the cathode of light-emitting element 12 is connected to the second power line ELVSS. A capacitor may also be connected between the gate of driving transistor M1 and the first power line ELVDD.

[0040] When the gate driver 23 scans a sub-pixel, the switching transistor M2 is turned on, and the data voltage on the data line DL is written into the gate of the driving transistor M1. The driving transistor M1 generates a driving current, thereby driving the light-emitting element 12 to emit light. Different data voltage values ​​result in different driving currents generated by the driving transistor M1, and thus different brightness of the light-emitting element 12.

[0041] It should be noted that, Figure 2 The structure of the pixel circuit shown is merely an example and is not intended to limit this application.

[0042] The controller 21 and / or data driver 22 include a thin film transistor (TFT). That is, the circuit architecture of the controller 21 and / or data driver 22 can be constructed based on the thin film transistor. This application does not limit the specific circuit architecture of the controller 21 and / or data driver 22, as long as the circuit architecture of the controller 21 and / or data driver 22 can realize the driving of the sub-pixel.

[0043] According to the display panel provided in the embodiments of this application, the driving system 20 can drive the sub-pixels 10 for display, and the controller 21 and / or data driver 22 include thin-film transistors. Thin-film transistors are flexible devices, which can avoid the use of rigid silicon-based ICs for driving, enabling the display panel to be applied to flexible display products. Furthermore, because the driving system built with thin-film transistors can be fabricated on the display panel, it can be uniformly packaged with other structures of the display panel. Compared to the packaging structure of silicon-based ICs, this reduces space requirements and thus reduces volume.

[0044] In some embodiments, the controller 21, data driver 22, and gate driver 23 all include thin-film transistors. In this way, a driving system 20 composed entirely of thin-film transistors can be used to replace rigid silicon-based ICs, thereby better ensuring that the display panel can be applied to flexible display products.

[0045] For example, sub-pixel 10 includes a thin-film transistor, and the active layers of at least some of the thin-film transistors in controller 21, data driver 22, and gate driver 23 are disposed on the same layer as the active layers of the thin-film transistors in sub-pixel 10. This embodiment can simultaneously fabricate at least some of the thin-film transistors in controller 21, data driver 22, and gate driver 23 and the thin-film transistors in sub-pixel 10 through the same process steps, thereby simplifying the process steps.

[0046] For example, sub-pixel 10 includes a P-type thin film transistor, and the active layer of the P-type thin film transistor in controller 21, data driver 22 and gate driver 23 is disposed on the same layer as the active layer of the P-type thin film transistor in sub-pixel 10.

[0047] In the case where sub-pixel 10 includes only P-type thin-film transistors and not N-type thin-film transistors, and at least one of controller 21, data driver 22 and gate driver 23 includes N-type thin-film transistors, the active layer of the N-type thin-film transistor and the active layer of the P-type thin-film transistor are located in different film layers.

[0048] The display panel includes a substrate and a driving device layer located on one side of the substrate. The driving device layer includes thin-film transistors in the sub-pixel 10, as well as thin-film transistors in the controller 21, data driver 22, and gate driver 23. That is, the pixel circuit of the sub-pixel 10 and the controller 21, data driver 22, and gate driver 23 are all formed in the driving device layer. The controller 21, data driver 22, and gate driver 23 are not external structures of the display panel.

[0049] In some embodiments, such as Figure 3 As shown, the data driver 22 includes a shift register 221, a row latch 222, and a data voltage converter 223. The controller 21 is electrically connected to the shift register 221, and the row latch 222 is electrically connected between the shift register 221 and the data voltage converter 223. The data voltage converter 223 is electrically connected to the sub-pixel 10 through the data line DL. The shift register 221 receives image data and writes the image data of each row of sub-pixel 10 to the row latch 222 line by line. The row latch 222 temporarily stores the image data of one row of sub-pixel 10. The data voltage converter 223 converts the image data temporarily stored in the row latch 222 into data voltage and writes it to the sub-pixel 10 line by line.

[0050] The shift register 221, also known as the shift register, receives serial image data from the host system (such as a graphics card) and then writes the image data of each row of sub-pixels to the row latch 222 line by line. Once all the image data of a row of sub-pixels has been written to the row latch 222, the row latch 222 latches the entire row of image data in parallel. Before the next row of sub-pixels is written, the data in the row latch 222 remains unchanged. Then, the ready data voltage converter 223 converts the image data of the current row stored in the row latch 222 into a data voltage, which is applied simultaneously to all sub-pixels of the current row via the data line DL. It can be understood that at this time, the gate driver 23 scans the current row of sub-pixels; that is, the gate driver 23 controls the thin-film transistors in the current row of sub-pixels to be in the on state for data writing.

[0051] After writing the data voltage for one row of sub-pixels, shift register 221 receives the image data for the next row of sub-pixels, and the above process is repeated. When all rows of sub-pixels have been written with sequential data voltages, the display of one frame of image is complete.

[0052] The shift register 221, the row latch 222, and the data voltage converter 223 all include thin-film transistors. Some exemplary structures of the shift register 221, the row latch 222, and the data voltage converter 223 will be described later.

[0053] In this embodiment, the shift register 221, the row latch 222, and the data voltage converter 223 work together to form a simple function similar to a silicon-based IC, realizing the row-by-row scanning and refreshing of sub-pixels.

[0054] In some specific embodiments, such as Figure 4 As shown, the shift register includes multiple D flip-flops connected in series, and the clock terminals CLK of the multiple D flip-flops are connected to the same clock signal DCLK.

[0055] The input terminal of the first-stage D flip-flop is electrically connected to the host system. This input terminal receives signals from the host system, which include at least image data. The output segment Q of the previous-stage D flip-flop is electrically connected to the input terminal of the next-stage D flip-flop. The clock signal DCLK of the D flip-flop is electrically connected to the host system and is used to receive the clock signal from the host system.

[0056] In this embodiment, D flip-flops are connected in series and share the same clock signal to build a shift register. Under the trigger of the clock signal, the input signal will shift to the right step by step, moving one bit each clock cycle, thereby realizing the shift storage of the signal.

[0057] Thin-film transistors (TFTs) come in N-type and P-type types. N-type and P-type TFTs can be fabricated using low-temperature polysilicon (LTPS), or N-type TFTs can be fabricated using amorphous silicon (a-Si) or indium gallium zinc oxide (IGZO). N-type and P-type TFTs can be used to build digital logic gates such as NAND gates, NOR gates, and NOT gates. NAND gates and NOT gates can be used to construct... Figure 5 The D flip-flop shown is an example. As an example, the shift register in this application can be... Figure 5 The structure shown is a D flip-flop. This type of D flip-flop only transmits the signal on the transition edge of the clock signal, assigning the signal at the output terminal Q to the signal at the input terminal D, and the output terminal... Assigned value .

[0058] In some embodiments, such as Figure 3 As shown, the driving system includes multiple shift registers S / R, with the first shift register 1... st The S / R has a preset number of D flip-flops 2210 for receiving system commands, parameter commands, and image commands. The first string shift register 1 st Other D flip-flops in the S / R and other shift registers after the first string are used to receive image commands.

[0059] For example, each shift register is 1 bit, and 2n shift registers are connected in series to form a shift register string. The number of shift register strings included in the driving system is A, where n and A are both integers.

[0060] n is related to the resolution of the display panel, the color depth of the image (i.e., the grayscale range of the image), and the number of data communication lines between the driving system and the host system. For example, if the resolution is 640*480 and the color depth of the image is 2 bits, then the image data of one row of subpixels has 640*2=1280 bits. Assuming that Slin[x:0] is 8 bits wide, that is, the number of data communication lines between the driving system and the host system is 8, n=(1280 / 8) / 2=80, that is, 160 shift registers are connected in series to form a shift register.

[0061] A corresponds to x in Slin[x:0], A=x+1; the length of the shift register is B, B=Hactive *2bit / A; Hactive is the horizontal resolution of the display panel, and 2bit is the color depth of the image.

[0062] For example, the first string shift register 1 st The first 24 shift registers of the S / R serve as the target unit to receive system instructions, parameter instructions, and image instructions; that is, the first string of shift registers 1 st The first 24 shift registers of the S / R have three multiplexing modes to receive three types of instructions, and multiplexing can save the number of circuit units.

[0063] Of the three types of instructions, system instructions have the highest priority. Once a system instruction is received, the driver system will enter the corresponding state according to the instruction. The switching between states is controlled by system instructions, and system instructions can be received in any state. The various states will be described below.

[0064] Parameter commands are used to configure the operating parameters of the drive system. They are sent at the beginning or when a mode change is needed, and remain basically unchanged within a frame.

[0065] Image instructions are the raw pixel data itself to be displayed, and constitute the largest portion of the data stream. Image instructions include image data, which is used to generate data voltages to drive sub-pixels to emit light.

[0066] For example, the interface signals received by the shift register include the clock signal DLCK, the chip select signal CSB, and the data signal SIin[x:0]. Taking SIin[x:0] as an 8-bit width as an example, the interface signals consist of DCLK / CSB / SI0~SI7. When CSB is low, it indicates that SI0~SI7 are valid. When the effective width of the chip select signal CSB is 8 cycles of the clock signal DCLK, it is determined to be a system instruction. When the effective width of the chip select signal CSB is 24 cycles of the clock signal DCLK, it is determined to be a parameter instruction. When in the image data writing state, if the effective width of the chip select signal CSB is greater than 8 cycles of the clock signal DCLK, it is determined to be an image instruction, and the image instruction (i.e., image data) is written to each shift register.

[0067] System commands and parameter commands appear only on the SI0 data communication line, while image data uses all data communication lines, that is, image data uses the eight data communication lines SI0 to SI7.

[0068] In some embodiments, such as Figure 6 to Figure 8 As shown, the drive system also includes a level shifting circuit LS, which is configured to boost the input signal from the first voltage domain to the second voltage domain.

[0069] For example, the high voltage of the second voltage domain is greater than the high voltage of the first voltage domain, and the low voltage of the second voltage domain is lower than the low voltage of the first voltage domain. For instance, the high voltage of the second voltage domain is VGH, the low voltage of the second voltage domain is VGL, the high voltage of the first voltage domain is VDD, the low voltage of the first voltage domain is VSS, and VGH > VDD, VGL < VSS.

[0070] The signal level received by the drive system from the host system is in a first voltage domain, which has a low voltage, such as 1.8V or 3.3V. In this embodiment, by setting a level conversion circuit LS, at least some circuits in the drive system can operate in a high voltage domain, which can improve signal integrity and increase the reliability of the drive system.

[0071] As an example, such as Figure 6 As shown, the signals connected to the controller 21, shift register 221, and gate driver 23 are all signals converted by the level conversion circuit LS. In other words, placing the level conversion circuit LS at the very beginning of the drive system can significantly reduce the number of level conversion circuits LS. For example, the number of level conversion circuits LS can be reduced from hundreds to a dozen, reducing the area of ​​the drive system. At the same time, it allows most of the circuits in the drive system to operate in the high voltage domain, significantly improving the reliability of the drive system.

[0072] As another example, such asFigure 7 or Figure 8 As shown, the level conversion circuit includes a first level conversion circuit LS1 and / or a second level conversion circuit LS2. The first level conversion circuit LS1 is electrically connected to the data transmission path from the row latch 222 to the sub-pixel. The gate driver includes a gate driving circuit GIP. The output terminal of the gate driving circuit GIP is electrically connected to the sub-pixel 10 through the gate line GL. The second level conversion circuit LS2 is electrically connected to the input terminal of the gate driving circuit GIP.

[0073] The row latch 222 includes multiple output channels, each of which can correspond to a first level shifting circuit LS1. The voltage domain boosted by the first level shifting circuit LS1 is a high voltage VGH and a low voltage VGL. This example can reduce the operating frequency of a single first level shifting circuit LS1, thereby reducing power consumption and the risk of the first level shifting circuit LS1 overheating and burning out.

[0074] The gate drive circuit GIP receives multiple signals, such as the trigger signal STV and two clock signals GCK1 and GCK2. Figure 7 and Figure 8 In the diagram, 3CH indicates that each of the three signal channels has a corresponding second-level conversion circuit LS2. Specifically, one second-level conversion circuit LS2 is installed on the transmission channel of the trigger signal STV, one on the transmission channel of the clock signal GCK1, and one on the transmission channel of the clock signal GCK2. The voltage domain boosted by the second-level conversion circuit LS2 is high voltage VGH and low voltage VGL. This example reduces the operating frequency of a single second-level conversion circuit LS2, thereby reducing power consumption and the risk of the second-level conversion circuit LS2 overheating and burning out.

[0075] In some embodiments, the level shifting circuit includes a thin-film transistor; for example, an N-type thin-film transistor and a P-type thin-film transistor can be used to construct the level shifter.

[0076] As a concrete example, such as Figure 9 As shown, the level conversion circuit includes transistors twelfth to twenty-first. Each transistor in the level conversion circuit is a thin-film transistor, and the connection relationship of each transistor is as follows; The twelfth transistor T12 has its first terminal connected to the first high-level signal terminal VDD, its second terminal connected to the third node N3, and its gate connected to the input signal terminal Vin. The thirteenth transistor T13 has its first terminal connected to the third node N3, its second terminal connected to the first low-level signal terminal VSS, and its gate connected to the input signal terminal Vin. The fourteenth transistor T14 has its first terminal connected to the first high-level signal terminal VDD, its second terminal connected to the fourth node N4, and its gate connected to the input signal terminal Vin. The fifteenth transistor T15 has its first terminal connected to the fourth node N4, its second terminal connected to the second low-level signal terminal VGL, and its gate connected to the fifth node N5. The sixteenth transistor T16 has its first terminal connected to the first high-level signal terminal VDD, its second terminal connected to the fifth node N5, and its gate connected to the third node N3. The seventeenth transistor T17 has its first terminal connected to the fifth node N5, its second terminal connected to the second low-level signal terminal VGL, and its gate connected to the fourth node N4. The eighteenth transistor T18 has its first terminal connected to the second high-level signal terminal VGH, its second terminal connected to the sixth node N6, and its gate connected to the seventh node N7. The nineteenth transistor T19 has its first terminal connected to the sixth node N6, its second terminal connected to the second low-level signal terminal VGL, and its gate connected to the fifth node N5. The twentieth transistor T20 has its first terminal connected to the second high-level signal terminal VGH, its second terminal connected to the seventh node N7, and its gate connected to the sixth node N6. The twenty-first transistor T21 has its first terminal connected to the seventh node N7, its second terminal connected to the second low-level signal terminal VGL, and its gate connected to the fourth node N4; the seventh node N7 is connected to the output signal terminal Vout.

[0077] The twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, the eighteenth transistor T18, and the twentieth transistor T20 are P-type transistors, while the thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are N-type transistors.

[0078] When the input signal terminal Vin is low, the twelfth transistor T12 is turned on, the thirteenth transistor T13 is turned off, and the third node N3 is high level VDD; the fourteenth transistor T14 is turned on, the sixteenth transistor T16 is turned off, and the fourth node N4 is high level VDD; the seventeenth transistor T17 is turned on, the fifth node N5 is low level VGL, the fifteenth transistor is turned off, the nineteenth transistor T19 is turned off, the twenty-first transistor T21 is turned on, and the seventh node N7 is low level VGL; the eighteenth transistor T18 is turned on, the sixth node N6 is high level VGH, the twentieth transistor T20 is turned off, and the output signal terminal Vout outputs low level VGL, VGL < VSS.

[0079] When the input signal Vin is high, the thirteenth transistor T13 is turned on, the twelfth transistor T12 is turned off, and the third node N3 is low (VSS); the fourteenth transistor T14 is turned off, the sixteenth transistor T16 is turned on, and the fifth node N5 is high (VDD); the fifteenth transistor T15 is turned on, and the fourth node N4 is low (VGL). The nineteenth transistor T19 is turned on, and the sixth node N6 is at a low level VGL; the twentieth transistor T20 is turned on, and the seventh node N7 is at a high level VGH; the eighteenth transistor T18 is turned off, the twenty-first transistor T21 is turned off, and the output signal terminal Vout outputs a high level VGH, VGH>VDD.

[0080] Figure 9 The level conversion circuit shown functions to change the voltage values ​​of the high and low levels of the input signal, but does not change the phase of the signal.

[0081] In some embodiments, such as Figure 6 As shown, the gate driver 23 includes a first counter 231, a gate drive signal generation circuit GEN, and a gate drive circuit GIP. The first counter 231 is electrically connected to the input terminal of the gate drive signal generation circuit GEN, and the output terminal of the gate drive signal generation circuit GEN is electrically connected to the input terminal of the gate drive circuit GIP. The output terminal of the gate drive circuit GIP is electrically connected to the sub-pixel 10 through the gate line GL. The first counter 231 includes a row counter 2311, a column counter 2312, and a logic circuit 2313. When the count of the column counter 2312 reaches the number of sub-pixels 10 in a row, the logic circuit 2313 generates a write enable signal WR_EN for the row latch 222. When the count of the row counter 2311 reaches the total number of rows of sub-pixels 10, it indicates that a frame scan is completed. The gate drive signal generation circuit GEN generates the trigger signal STV and clock signals GCK1\GCK2 required by the gate drive circuit GIP based on the row counter 2311 and the column counter 2312 to control the gate drive circuit GIP to scan the sub-pixels row by row.

[0082] Column counter 2312 is used to indicate the position of a sub-pixel within a row. Clocked by the clock signal DCLK, column counter 2312 generates a write enable signal WR_EN when the count reaches the Hactive value (i.e., the number of sub-pixels in a row). The write enable signal WR_EN controls the write enable of row latch 222, meaning that row latch 222 writes the image data corresponding to a row of sub-pixels 10. For example, when the write enable signal WR_EN is low, the image data in shift register 221 is written to row latch 222. Before the next row of image data is written, the data in row latch 222 remains unchanged, representing the image data of the current row.

[0083] The row counter 2311 is used to indicate the row number of a sub-pixel. The row counter 2311 operates on a scan row cycle; when it reaches the Vactive value (i.e., the number of sub-pixels in a column), it indicates that one frame of image data has been received and one frame scan is complete. The row counter 2311 can receive a reset signal RST from the controller 21. After completing one frame scan, the row counter 2311 is reset to zero and starts counting again from 0.

[0084] The row counter 2311 and column counter 2312 control the gate drive signal generation circuit GEN to generate the trigger signal STV and clock signals GCK1 / GCK2 required by the gate drive circuit GIP, thereby driving the gate drive circuit GIP to work and achieving synchronization between row scanning and data voltage writing.

[0085] Each counter in this application includes a thin-film transistor, and the structure of each counter can be designed using a conventional counter structure, as long as its function meets the function of each counter in this application.

[0086] As an example, see the reference. Figure 10 The structure of the 4-bit synchronous decimal counter shown is designed with row counter 2311 and column counter 2312. Of course, Figure 10 This is merely an example and is not intended to limit this application.

[0087] In some embodiments, such as Figure 6 As shown, the controller 21 includes a state machine 211. The control states of the state machine 211 include a write image data state (WR state for short). When the state machine 211 is in the write image data state and the chip select signal CSB is at an active level (e.g., low level), the column counter 2312 counts.

[0088] When state machine 211 is in the write image data state (WR state) and chip select signal CSB is active, the image data in shift register 221 is written to row latch 222, and column counter 2312 will count to ensure that the data voltage can be accurately written to each sub-pixel in a row.

[0089] For example, column counter 2312 may not have a set mechanism, but it does require a clear mechanism. For instance, column counter 2312 is cleared when the chip select signal CSB is at an invalid level (e.g., high).

[0090] When state machine 211 is in the write image data state (WR state), the row counter 2311 increments by one on each falling edge of the chip select signal CSB.

[0091] The row counter 2311 needs to have a setting mechanism. When the count of the row counter 2311 reaches the preset value (usually the Vtotal value), the row counter 2311 is set, and the set row counter 2311 starts the next counting cycle.

[0092] For example, when the row counter 2311 reaches a preset value (usually the Vtotal value), it generates an EndOfFrame (EOF) signal. The EOF signal is used to generate a set signal of one clock cycle length. After the column counter 2312 finishes counting the last row of sub-pixels, the row counter 2311 is set. After being set, the row counter 2311 enters the next counting cycle, that is, it starts scanning the next frame, and so on.

[0093] Based on the row counter 2311 and the column counter 2312, the gate drive signal generation circuit GEN generates the trigger signal STV and clock signals GCK1 and GCK2 required by the gate drive circuit GIP. The generation mechanism of the signals required by the gate drive circuit GIP is described below as an example.

[0094] For the trigger signal STV: Set the default level, and set the row number of the first transition edge in STV. H1 Set the column number of the first transition edge STV D1 Set the second transition edge to the row number STV H2 Set the second transition edge to the column number STV. D2 Based on the above parameters, the width and effective pulse level of the trigger signal STV can be determined, and the cycle period of the trigger signal STV is one frame time.

[0095] For the first clock signal GCK1: Set the default level, set the row number (odd or even) of the short pulse width signal, set the short pulse polarity, and set the column number of the short pulse start edge GCK1. start Set the short pulse end (End) along the column number GCK1. end Based on the above parameters, the width and effective pulse level of the first clock signal GCK1 can be determined. The cycle period of the first clock signal GCK1 can be the scan time of 2 rows of sub-pixels or the scan time of 4 rows of sub-pixels.

[0096] For the second clock signal GCK2: the setting method is the same as that for the first clock signal GCK1, so it will not be repeated here.

[0097] The period of clock signals GCK1 / GCK2 can be set through registers in the state machine, supporting 2 or 4 lines of time.

[0098] As an example, the timing of the trigger signal STV and clock signals GCK1\GCK2 is as follows:Figure 11 As shown, Figure 11 In this process, the period of clock signals GCK1 and GCK2 is the scanning time of two rows of sub-pixels. When the trigger signal STV is low, a line-by-line scan is performed within one frame. During the first low-level period of clock signal GCK1, the data voltage (Source Data) on the data line is written to the first row of sub-pixels; during the first low-level period of clock signal GCK2, the data voltage (Source Data) on the data line is written to the second row of sub-pixels; during the second low-level period of clock signal GCK1, the data voltage (Source Data) on the data line is written to the third row of sub-pixels; and so on, to achieve line-by-line scanning of sub-pixels and line-by-line writing of data voltage.

[0099] In some embodiments, such as Figure 6 or Figure 7 or Figure 8 As shown, the drive system also includes an interface logic circuit 24, which parses the input signals and generates control signals for the drive system.

[0100] For example, such as Figure 6 As shown, the input signal of the interface logic circuit 24 comes from the output signal of the level conversion circuit LS, and the input signal of the level conversion circuit LS comes from the output signal of the host system. Alternatively, as... Figure 7 or Figure 8 As shown, the input signals of the interface logic circuit 24 come directly from the host system. The output signals of the host system include DCLKin, SIin[x:0], CSBin, etc.

[0101] For example, the control signals generated by the interface logic circuit 24 include CS_D9, CS_RISE, etc. CS_D9 is an instruction recognition signal, which is used to identify system instructions.

[0102] For example, the system instruction for switching states in the control state machine 211 is 8-bit. The interface logic circuit 24 generates the CS_D9 signal, which can be used to identify whether it is a system instruction. If the CS_D9 signal is high and the chip select signal CS is high, it is a system instruction; if the CS_D9 signal is high and the chip select signal CS is low, it is not a system instruction. The CS_RISE signal represents the rising edge of the chip select signal CS, and its width is one cycle of the clock signal DLCK. The CS_RISE signal is used to control the shift register 221 to write image data to the row latch 222. A high level for the CS_RISE signal indicates an active level. Here, the chip select signal CS is equivalent to the chip select signal CSB.

[0103] For example, such as Figure 6As shown, the controller 21 includes a state machine 211, a register 212, a read address decoder 213, and a write address decoder 214.

[0104] Register 212 is used to store control parameters. Read address decoder 213 enables reading from register 212, and write address decoder 214 enables writing to register 212.

[0105] State machine 211 is configured to implement jump control between four states: reset state (RST state), read register state (RD state), write register state (REG state), and write image data state (WR state).

[0106] In the reset state (RST state), register 212 is cleared. For example, in the RST state, the state machine generates a soft reset signal, and the soft reset and hardware reset together control the clearing and resetting of register 212 and components such as counters in the drive system.

[0107] In the read register state (RD state), register 212 can be read.

[0108] In the write register state (REG state), register 212 can be written to. For example, in REG state, the value of register 212 can be modified to change the parameters of the signal waveform connected to the gate drive circuit GIP, control the power supply, and perform other operations.

[0109] In the write image data state (WR state), image data is written to shift register 221. For example, in the WR state, image data is written to shift register 221 for all strings, and then to row latch 222, realizing the transmission of image data and the display of sub-pixels. The WR state is also called the display state, in which the display panel is displaying an image.

[0110] State machine 211 controls the operation of the entire drive system, and the state machine performs different tasks in each state.

[0111] like Figure 12 As shown, the switching between each state is controlled by system commands. Once a system command is received, the four states can be switched freely. Figure 12 The numbers ① to ⑨ represent the switching codes for each state corresponding to the system instruction. For example, when system instruction 0xA3 is detected, the state machine enters the REG state; when system instruction 0xAC is detected, the state machine enters the RD state; and when system instruction 0xA1 is received in the RD state, the state machine enters the WR state.

[0112] by Figure 6For example, the signals of the host system are DCLKin, CSBin, SIin[x:0], and SOout. After being converted by the level conversion circuit LS, the signals obtained are DCLK, CSB, SI[x:0], and SO. The level levels of the level conversion circuit LS are VGH and VGL. The level-converted signals enter the interface logic circuit 24 and the shift register 221. The interface logic circuit 24 can generate the signals required for internal control.

[0113] like Figure 13 to Figure 15 As shown, taking SIin[x:0] as an 8-bit width as an example, the input signal consists of DCLK / CSB / SI0~SI7. When CSB is low, it indicates that SI0~SI7 are valid. The received data is divided into three types: system commands, parameter commands, and image commands.

[0114] System instructions are 8-bit data, with the most significant bit (MSB) first and the least significant bit (LSB) last. The MSB represents the leftmost bit of a binary number, and the LSB represents the rightmost bit.

[0115] If the effective width of the chip select signal CSB is equal to 8 cycles of the clock signal DCLK, the signal corresponding to the chip select signal is a system instruction. System instructions have the highest priority and control the state machine 211 transitions; they can receive system instructions in any state.

[0116] The parameter instruction is 24 bits of data, with the most significant bit (MSB) first and the least significant bit (LSB) last. The address is 8 bits (i.e., ADDR has 8 bits) and the data is 16 bits (i.e., the parameter value DATA has 16 bits).

[0117] When the effective level width of the chip select signal CSB is 24 cycles of the clock signal DCLK, the signal parameter instruction corresponding to the chip select signal is executed. The parameter instruction can only be received when state machine 211 is in REG or RD state; otherwise, it is ignored. The parameter value in the parameter instruction will be written to register 212 at the corresponding address.

[0118] Image commands include image data, which is transmitted in whole rows of subpixels. Assuming the image resolution is 640*480, then the image data for one row of subpixels is 640*2=1280 bits. It takes 480 times, or 480 chip select cycles (CS cycles), to send one frame of image data.

[0119] When state machine 211 is in the write image data state (WR state), if the effective level width of the chip select signal CSB is greater than 8 cycles of the clock signal DCLK, the signal corresponding to the chip select signal is the image instruction.

[0120] In some embodiments, the read address decoder 213 is shorted to the read enable pin of register 212, such as... Figure 6 As shown, the drive system also includes a parallel-to-serial converter 215, which is electrically connected to the address decoder 213 and the register 212. The parallel-to-serial converter 215 converts the data read from the register 212 in a time-division manner into serial data and outputs it.

[0121] Register 212 is used to store parameters that can be used to control the reset of other modules, enable the power supply module, and generate signal waveforms for the gate driver 23. The parallel-to-serial converter 215 can convert the data read from register 212 into serial data and output it from the SO pin.

[0122] Register 21 can be implemented using Static Random-Access Memory (SRAM). Write operations to register 212 can only be performed when state machine 211 is in the REG state; otherwise, the instruction is ignored, thus preventing accidental writing to register 212. Furthermore, the clearing and resetting of register 212 can be controlled by both hardware and software resets. Hardware reset refers to a reset triggered by external physical circuits or signals, while software reset is a reset triggered by the state machine executing specific program instructions; it is a software-controlled reset.

[0123] As an example, such as Figure 16 As shown, the register includes a first static random access memory (SRAM) 1. The SRAM 1 includes an internal node N21 and an external node N31, which are connected via a read control transistor T111. The gate of the read control transistor T111 serves as a read enable pin RD, electrically connected to the output of the read address decoder 213, thus enabling read control. The SRAM 1 also includes a write control transistor T61, whose gate serves as a write enable pin, electrically connected to the output of the write address decoder 214, thus enabling write control.

[0124] To facilitate differentiation Figure 16 The first static random access memory (SRAM1) and shown are Figure 21 The second static random access memory (SRAM2) shown is... Figure 16 The transistors in the diagram are labeled T61, T71, T81, T91, T101, and T111, respectively.

[0125] For example, the first static random access memory (SRAM) 1 is 1 bit, and a register 212 is 16 bits. Sixteen SRAMs 1 constitute one register 212. Multiple registers 212 are set up within the driver system to store parameters for different applications.

[0126] Multiple external nodes N31 of the first static random access memory (SRAM1) within the same register 212 are shorted and electrically connected to the parallel-to-serial converter 215 via the first inverter 261. The external nodes N31 of the multiple SRAM1 output signals to the first inverter 215 in a time-division manner. The shorting of the external nodes N31 of the multiple SRAM1 forms a read bus DO, which is output to the parallel-to-serial converter 215 after passing through the first inverter 261. Only one register 212 is selected for reading at a time; the read bus DO is output in a time-division manner under the control of the RD pin.

[0127] The internal node N21 of the first static random access memory (SRAM1) is electrically connected to the gate driver 23 through the second inverter 261. Multiple internal nodes N21 of the first SRAM1 within the same register are output simultaneously, enabling multiple subsequent circuits connected to the second inverter 261 to operate normally at the same time.

[0128] For example, such as Figure 17 As shown, the drive system includes multiple registers 212 arranged in an array. Figure 17 A gray filled box represents a register 212.

[0129] The write enable pins WR of multiple registers 212 in the same row are shorted, the read enable pins RD of multiple registers 212 in the same row are shorted, the input pins DI of multiple registers 212 in the same column are shorted, and the external nodes DO of multiple registers 212 in the same column are shorted.

[0130] It should be noted that, Figure 17 The number of registers 212 shown is merely an example and is not intended to limit this application.

[0131] For example, in write register state (REG state), register 212 receives a total of 24 bits of data, of which the high-order 8 bits are the register address (if the number of first static random access memories (SRAM1) in the register is small, only 4 bits of the register address may be used). The register address is passed to write address decoder 214, which generates a write enable signal (e.g., denoted as REGxx_flag signal). The write enable signal is transmitted to the write enable pin WR of the first static random access memory (SRAM1) in the register, and the low-order 16 bits of the 24 bits are parameter values, which are written to the register corresponding to the address.

[0132] Taking the high-order 8 bits as the register address as an example, such as Figure 18 As shown, both the write address decoder 214 and the read address decoder 213 support 8-bit address values ​​ADDR[7:0], with a total of 2 =256 encodings, with 256 output lines. Each line corresponds to a unique input address encoding. At any given time, only one of the 256 output lines is at a valid level (let's say high level 1), while the other 255 lines are at an invalid level (0). The valid line selects the register at the corresponding address, making it readable and writable.

[0133] Please refer to Figure 19 and Figure 20 In the read register state (RD state), the read address is written to the read address decoder 213, which outputs read enable signals, which are transmitted to the RD pins of each register. The function of the read address decoder 213 is to enable only one register's RD pin at a time, meaning that only one register outputs a signal to the read bus DO[15:0] at any given time. The read bus DO[15:0] outputs signals to the parallel-to-serial converter 215, which converts the data into serial data and outputs it from the SO pin.

[0134] The row latch 222 can also be implemented using static random-access memory (SRAM). For ease of distinction, the static random-access memory of the row latch 222 is referred to as the second static random-access memory.

[0135] In some embodiments, the row latch 222 includes a plurality of second static random access memories (SRAMs) 2, for example, each second static random access memory (SRAM) 2 is 1 bit, and 2n second static random access memories (SRAMs) 2 are combined into a group, and each group of second static random access memories (SRAMs) 2 is interconnected with each string of shift registers. Here, 2n shift registers are connected in series to form a string of shift registers, where n has the same value.

[0136] likeFigure 21 As shown, the second static random access memory (SRAM2) includes transistors T6 through T11, and the connection relationship of each transistor is as follows: The sixth transistor T6 has its first terminal connected to the write signal line DI, its second terminal connected to the first node N1, and its gate used as the write enable pin WR. The seventh transistor T7 has its first terminal connected to the high-level signal terminal VDD or VGH, its second terminal connected to the first node N1, and its gate connected to the second node N2. The eighth transistor T8 has its first terminal connected to the first node N1, its second terminal connected to the low-level signal terminal VSS or VGL, and its gate connected to the second node N2. The ninth transistor T9 has its first terminal connected to the high-level signal terminal VDD or VGH, its second terminal connected to the second node N2, and its gate connected to the first node N1. The tenth transistor T10 has its first terminal connected to the second node N2, its second terminal connected to the low-level signal terminal VSS or VGL, and its gate connected to the first node N1. The eleventh transistor T11 has its first terminal connected to the second node N2, its second terminal connected to the read signal line DO, and its gate used as the read enable pin RD.

[0137] The sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the eleventh transistor T11 are P-type transistors, while the eighth transistor T8 and the tenth transistor T10 are N-type transistors.

[0138] The row latch 222 is used to temporarily store image data for one row of sub-pixels. In one row latch 222, the WR pins of all second static random access memory (SRAM2) are shorted together and controlled by the WR_EN signal; the RD pins of all second static random access memory (SRAM2) are shorted together and controlled by the / WR_EN signal. / WR_EN is the inverted signal of WR_EN. The input signal on the write signal line DI comes from the shift register. The input data and output data of the SRAM are inverted. When / WR_EN is low, the row latch outputs the inverted data of D[1:0] to the data voltage converter 223.

[0139] Please refer to the reference. Figure 16 and Figure 21 The circuit structures of the first static random access memory (SRAM1) and the second static random access memory (SRAM2) are the same, but the differences include: the enable signal, the input signal, and the output signal are different.

[0140] In addition, if the front-end circuit of the static random access memory (SRAM) does not include the level shifting circuit LS, then the high voltage connected to the SRAM is VDD and the low voltage is VSS; if the front-end circuit of the SRAM includes the level shifting circuit LS, then the high voltage connected to the SRAM is VGH and the low voltage is VGL.

[0141] The following provides an example of some structures of the data-to-voltage converter 223.

[0142] In some embodiments, the image data is m bits, such as Figure 22 As shown, the data voltage converter 223 includes a first transistor T1, a second transistor T2, and m third transistors T3. The first transistor T1 is electrically connected between the first reference gamma voltage terminal VGMP and the data line DL. The first terminal of the second transistor T2 is electrically connected to the data line DL. The m third transistors T3 are connected in parallel between the second terminal of the second transistor T2 and the second reference gamma voltage terminal VGSP. The gates of the m third transistors T3 are electrically connected to a row latch. The width-to-length ratios of the m third transistors T3 are different.

[0143] Multiple data voltage converters 223 and multiple data lines DL can be electrically connected one-to-one.

[0144] The voltage range on the data line DL is VGMP~VGSP, where VGSP is generated during the discharge process and does not require external supply.

[0145] Y1 to Ym are the gate signals for the 1st to mth third transistors T3, controlling whether the 1st to mth third transistors T3 are turned on or off. The gate signals Y1 to Ym are generated based on the image data.

[0146] When the first transistor T1 is turned on, the first reference gamma voltage terminal VGMP charges the data line DL. When the second transistor T2 and at least one third transistor T3 are turned on, the data line DL discharges to the second reference gamma voltage terminal VGSP. Gate signals Y1 to Ym determine which third transistors T3 are turned on. Furthermore, the width-to-length ratios of the m third transistors T3 are different. When different third transistors T3 are turned on, the discharge current of the data line DL to the second reference gamma voltage terminal VGSP is different, resulting in different voltages after the data line DL is discharged. Therefore, gate signals Y1 to Ym determine the voltage value on the data line DL, thereby driving the sub-pixels to display grayscale levels of different brightness.

[0147] For example, the aspect ratios of the m third transistors T3 increase sequentially. For instance, the aspect ratio of the second third transistor T3 is greater than that of the first third transistor T3, the aspect ratio of the third third transistor T3 is greater than that of the second third transistor T3, and so on. In this text, the aspect ratio of a transistor is the ratio of its channel width to its channel length.

[0148] As an example, the width-to-length ratio of the (i+1)th third transistor T3 is twice that of the ith third transistor T3, where i is any value from 1 to m-1. The width-to-length ratio of the second third transistor T3 is twice that of the first third transistor T3, the width-to-length ratio of the third third transistor T3 is twice that of the second third transistor T3, and so on.

[0149] Please refer to the reference. Figure 22 and Figure 13 The operation of the data voltage converter includes a first stage P1 and a second stage P2.

[0150] In the first stage P1, control signal SW1 is low and control signal SW2 is high, the first transistor T1 is turned on and the second transistor T2 is turned off. At this time, the first reference gamma voltage terminal VGMP charges the data lines DL, and the voltage of all data lines DL is charged to the voltage of the first reference gamma voltage terminal VGMP. The aspect ratio of the first transistor T1 can be smaller than that of the second transistor T2, and the aspect ratio of the first transistor T1 can be smaller than that of the third transistor T3, to ensure that the first transistor T1 has a strong driving capability.

[0151] In the second stage P2, control signal SW1 is high, control signal SW2 is low, and at least one of the gate signals Y1 to Ym is low. The first transistor T1 is off, the second transistor T2 is on, and at least one of the m third transistors T3 is on. At this time, the data line DL discharges to the second reference gamma voltage terminal VGSP.

[0152] Multiple third transistors T3 connected in parallel are equivalent to multiple resistors, and the width-to-length ratio of the (i+1)th third transistor T3 is twice that of the ith third transistor T3. The discharge current of each path is close to constant current; for example, the discharge current values ​​of the first to third third transistors T3 are I, 2I, and 4I, respectively. When the input image data is different, the gate signals Y1~Ym are different, causing different third transistors T3 to conduct, thereby discharging the data line DL to different voltages.

[0153] Taking 2-bit image data as an example, the correspondence between image data D[1:0], gate signal Y[1:0], grayscale, voltage on data line DL, and brightness is as follows:Figure 24 As shown.

[0154] Then, refer to the references. Figure 2 and Figure 23 For each row of sub-pixels, the working process also includes a third stage P3. In the third stage P3, the signal on the gate line GL of the sub-pixel is at a low level, the switching transistor M2 is turned on, the data voltage on the data line DL is written to the sub-pixel, and the sub-pixel is driven to emit light. Figure 23 In the diagram, ROW1, ROW2, and ROW3 represent the scanning and data refresh processes of the three rows of sub-pixels, respectively. Row1-S1 represents the signal on the gate line GL of the first row of sub-pixels, Row2-S1 represents the signal on the gate line GL of the second row of sub-pixels, and Row3-S1 represents the signal on the gate line GL of the third row of sub-pixels. The sub-pixels are scanned and refreshed row by row.

[0155] For example, please refer to the reference. Figure 22 and Figure 25 1H represents the scan and data refresh time of a row of sub-pixels. The column counter counts based on the clock signal DLCK, thereby distinguishing the scan and data refresh time of different rows of sub-pixels.

[0156] During the first 1H time period, the second static random access memory (SRAM2) in the row latch stores the image data of the first row of sub-pixels. During the first 1H time period, control signals SW1 and SW2 are sequentially low, and the data voltage converter 223 converts the image data into data voltage. The voltage on the data line DL is the converted data voltage. When Row1-S1 is low, this data voltage is written to the first row of sub-pixels.

[0157] During the second 1H time interval, the image data H2 corresponding to the second row of sub-pixels is written to the second static random access memory (SRAM2) in the row latch. Control signals SW1 and SW2 are sequentially low, and the data voltage converter 223 converts the image data H1 into a data voltage. The voltage on the data line DL is the converted data voltage. When Row1-S1 is low, this data voltage is written to the second row of sub-pixels. This process is repeated line by line to achieve sub-pixel scanning and data voltage writing.

[0158] In other embodiments, such as Figure 8 As shown, the data voltage converter 22 includes a digital-to-analog converter DAC and an operational amplifier OP. The digital-to-analog converter DAC is electrically connected between the input terminals of the row latch 222 and the operational amplifier OP, and the output terminal of the operational amplifier OP is electrically connected to the data line DL.

[0159] A digital-to-analog converter (DAC) can convert digital image data signals into analog data voltage signals, and an operational amplifier (OP) can amplify the data voltage to drive sub-pixels. Through the cooperation of the DAC and the OP, a more accurate analog data voltage can be output.

[0160] The number of operational amplifiers (OPs) can be multiple, and multiple operational amplifiers (OPs) and multiple data lines (DLs) are electrically connected in a one-to-one correspondence.

[0161] The digital-to-analog converter (DAC) and operational amplifier (OP) only need to be able to perform the corresponding functions, and this application does not limit their specific structure.

[0162] In some other embodiments, such as Figure 27 As shown, the data voltage converter includes an inverter 224, which is electrically connected between the row latch 222 and the data line DL.

[0163] As mentioned earlier, the row latch can use an SRAM structure. The SRAM outputs an inverted signal. Therefore, the inverter 224 inverts the image signal again, so that the phase of the signal finally input to the data line DL is consistent with the phase of the image data provided by the host system.

[0164] Since the data voltage converter only includes an inverter 224, the final displayed image color depth is 1 bit, that is, the sub-pixel can only display 0 gray level and 1 gray level. Although the displayed gray level range is relatively small, the structure of the driving system is relatively simple, which can reduce the area occupied by the driving system.

[0165] For example, such as Figure 27 As shown, the inverter includes a fourth transistor T4 and a fifth transistor T5. The first terminal of the fourth transistor T4 is electrically connected to the high-level signal terminal VDD, and the first terminal of the fifth transistor T5 is electrically connected to the low-level signal terminal VSS. The gates of the fourth transistor T4 and the fifth transistor T5 are shorted to form the input terminal Vin, and the second terminals of the fourth transistor T4 and the fifth transistor T5 are shorted to form the output terminal Vout. The fourth transistor T4 is a P-type transistor, and the fifth transistor T5 is an N-type transistor. The input terminal Vin of the inverter 224 is electrically connected to the output terminal of the horizontal latch 222, and the output terminal Vout of the inverter 224 can be electrically connected to the data line DL through the first level conversion circuit LS1.

[0166] In some embodiments, such as Figure 26 As shown, the controller includes a second counter 216, which is electrically connected to a shift register 221. When the count of the second counter 216 reaches a preset value, it controls the shift register 221 to receive image data.

[0167] For example, the second counter 216 is also used to control the power-on and power-off of the power supply.

[0168] Compared to Figure 6 , Figure 26 The structure shown is equivalent to removing the interface logic circuit, state machine, register, read address decoder, write address decoder and other circuit structures, and realizing the image data reception control through a second counter; it simplifies the design, reduces the image color depth, and makes the system less complex and more stable.

[0169] In addition, the first level conversion circuit LS1 is connected to the output of the inverter 224, which enables most of the circuit to operate in a low-voltage mode, resulting in relatively low power consumption and reducing the risk of device burnout.

[0170] In some embodiments, with Figure 6 For example, the driving system also includes a charge pump 25, which is configured to generate the driving voltage for the display panel. The driving voltage includes a first reference gamma voltage VGMP, a second reference gamma voltage VGSP, a high-level voltage VGH, and a low-level voltage VGL. Additionally, the first power supply voltage ELVDD and the second power supply voltage ELVSS can be provided by the host system.

[0171] The charge pump 25 can also be made of transistors.

[0172] It should be noted that for N-type transistors, the on-level is high and the off-level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa; no distinction is made here. Additionally, the on-level and off-level in this embodiment are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0173] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 28 , Figure 28 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 28 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application.Figure 28 This embodiment uses AR glasses as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other types of wearable products, mobile phones, computers, televisions, vehicle-mounted display devices, or other display devices with display functions. This application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0174] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of sub-pixels arranged in a matrix; a driving system comprising a controller, a data driver and a gate driver, the controller being electrically connected to the data driver and the gate driver, the data driver being electrically connected to the sub-pixels through data lines, and the gate driver being electrically connected to the sub-pixels through gate lines; the controller controls the operation of the data driver and the gate driver, the data driver receives image data and converts it into data voltages, and writes the data voltages of each row of the sub-pixels into the sub-pixels row by row, and the gate driver scans the sub-pixels row by row; wherein the controller and / or the data driver comprises a thin film transistor.

2. The display panel of claim 1, wherein, The controller, the data driver and the gate driver all comprise thin film transistors; Preferably, the sub-pixels comprise thin film transistors, and the active layers of at least part of the thin film transistors in the controller, the data driver and the gate driver are arranged in the same layer as the active layers of the thin film transistors in the sub-pixels.

3. The display panel of claim 1 or 2, wherein, The data driver comprises a shift register, a row latch and a data voltage converter, the controller is electrically connected to the shift register, the row latch is electrically connected between the shift register and the data voltage converter, and the data voltage converter is electrically connected to the sub-pixels through data lines; the shift register receives the image data and writes the image data of each row of the sub-pixels into the row latch row by row, the row latch temporarily stores the image data of one row of the sub-pixels, and the data voltage converter converts the image data temporarily stored in the row latch into data voltages and writes the data voltages into the sub-pixels row by row.

4. The display panel of claim 3, wherein, The driving system further comprises a level conversion circuit configured to lift the accessed signals from a first voltage domain to a second voltage domain; Preferably, the signals accessed by the controller, the shift register and the gate driver are the signals converted by the level conversion circuit; or the level conversion circuit comprises a first level conversion circuit and / or a second level conversion circuit, the first level conversion circuit is electrically connected to the data transmission path from the row latch to the sub-pixels, the gate driver comprises a gate driving circuit, the output end of the gate driving circuit is electrically connected to the sub-pixels through gate lines, and the second level conversion circuit is electrically connected to the input end of the gate driving circuit.

5. The display panel of claim 1 or 2, wherein, The gate driver comprises a first counter, a gate driving signal generation circuit and a gate driving circuit, the first counter is electrically connected to the input end of the gate driving signal generation circuit, the output end of the gate driving signal generation circuit is electrically connected to the input end of the gate driving circuit, and the output end of the gate driving circuit is electrically connected to the sub-pixels through the gate lines; The first counter comprises a row counter, a column counter and a logic circuit, when the count of the column counter reaches the number of the sub-pixels in one row, the logic circuit generates a write enable signal of the row latch; When the count of the row counter reaches the total number of rows of the sub-pixels, it indicates that the scanning of one frame is completed. The gate driving signal generation circuit generates trigger signals and clock signals required by the gate driving circuit based on the row counter and the column counter, so as to control the gate driving circuit to scan the sub-pixels row by row.

6. The display panel of claim 5, wherein, The controller comprises a state machine, and a control state of the state machine comprises a write image data state; when the state machine is in the write image data state and a chip select signal is at a valid level, the column counter counts; Preferably, when the chip select signal is at an invalid level, the column counter is cleared; Preferably, when the state machine is in the write image data state and at each falling edge of the chip select signal, the count of the row counter is incremented by one; Preferably, when the count of the row counter reaches a preset value, the row counter is set.

7. The display panel of claim 1 or 2, wherein, The driving system further comprises an interface logic circuit, which analyzes input signals and generates control signals of the driving system; Preferably, the controller comprises a state machine, a register, a read address decoder and a write address decoder; the register stores control parameters; the read address decoder controls enabling of reading of the register; the write address decoder controls enabling of writing of the register; the state machine is configured to realize jump control between a reset state, a read register state, a write register state and a write image data state; in the reset state, the register is cleared; in the read register state, the register is read; in the write register state, the register is written; in the write image data state, the image data is written into the shift register; Preferably, the signals input into the driving system comprise system instructions, parameter instructions and image instructions; the state machine performs state jump based on the system instructions; Preferably, the system instructions are 8-bit data, and the most significant bit of the system instructions is in the front; Preferably, the parameter instructions are 24-bit data, wherein 8 bits are addresses and 16 bits are parameter values; the most significant bit of the parameter instructions is in the front; Preferably, the image instructions comprise the image data, and the image data is transmitted in cycles of data corresponding to an entire row of sub-pixels; Preferably, the width of the valid level of the chip select signal is 24 cycles of a clock signal, and the signal corresponding to the chip select signal is the parameter instructions; Preferably, when the state machine is in the write image data state, if the width of the valid level of the chip select signal is greater than 8 cycles of the clock signal, the signal corresponding to the chip select signal is the image instructions; if the width of the valid level of the chip select signal is equal to 8 cycles of the clock signal, the signal corresponding to the chip select signal is the system instructions; Preferably, the interface logic circuit generates instruction identification signals, which are used to identify the system instructions.

8. The display panel of claim 7, wherein, The read address decoder is short-circuited with a read enable pin of the register, and the driving system further comprises a parallel-serial conversion circuit electrically connected with the read address decoder and the register, and the parallel-serial conversion circuit converts data read from the register in time into serial data and outputs the serial data. Preferably, the register comprises a first static random access memory, the first static random access memory comprises an inner node and an outer node, the inner node and the outer node are connected through a read control transistor, a gate of the read control transistor is electrically connected with an output terminal of the read address decoder as a read enable pin, and the outer nodes of the plurality of first static random access memories are electrically connected with the parallel-serial conversion circuit through a first inverter after being short-circuited, and the outer nodes of the plurality of first static random access memories output signals to the first inverter in time. Preferably, the inner node is electrically connected with the gate driver through a second inverter. Preferably, the driving system comprises a plurality of registers arranged in an array, the write enable pins of the plurality of registers in the same row are short-circuited, the read enable pins of the plurality of registers in the same row are short-circuited, the input pins of the plurality of registers in the same column are short-circuited, and the outer nodes of the plurality of registers in the same column are short-circuited.

9. The display panel of claim 3, wherein, The image data is m-bit, and the data voltage converter comprises a first transistor, a second transistor and m third transistors, the first transistor is electrically connected between a first reference gamma voltage terminal and the data line, the first electrode of the second transistor is electrically connected with the data line, and the m third transistors are connected in parallel between the second electrode of the second transistor and a second reference gamma voltage terminal; the gates of the m third transistors are electrically connected with the row latch, and the width-length ratios of the m third transistors are different. Preferably, the width-length ratios of the m third transistors increase in turn. Preferably, the width-length ratio of the i+1 third transistor is twice the width-length ratio of the i third transistor, and i is any value in 1 to m-1. Preferably, in the first stage, the first transistor is turned on, and the second transistor is turned off. In the second stage, the first transistor is turned off, the second transistor is turned on, and at least one of the m third transistors is turned on.

10. The display panel of claim 3, wherein, The data voltage converter comprises a digital-to-analog converter and an operational amplifier, the digital-to-analog converter is electrically connected between the row latch and the input terminal of the operational amplifier, and the output terminal of the operational amplifier is electrically connected with the data line.

11. The display panel of claim 3, wherein, The data voltage converter comprises an inverter electrically connected between the row latch and the data line. Preferably, the inverter comprises a fourth transistor and a fifth transistor, the first electrode of the fourth transistor is electrically connected with a high-level signal terminal, the first electrode of the fifth transistor is electrically connected with a low-level signal terminal, the gate of the fourth transistor and the gate of the fifth transistor are short-circuited as an input terminal, the second electrode of the fourth transistor and the second electrode of the fifth transistor are short-circuited as an output terminal; the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

12. The display panel of claim 3, wherein, The shift register comprises a plurality of D flip-flops connected in series, clock terminals of the plurality of D flip-flops being connected to the same clock signal; Preferably, the driving system comprises a plurality of the shift registers, a preset number of D flip-flops in a first shift register are used to receive system instructions, parameter instructions and image instructions, other D flip-flops in the first shift register and other shift registers after the first shift register are used to receive image instructions.

13. The display panel of claim 3, wherein, The row latch comprises a plurality of second static random access memories; the controller comprises a register comprising a first static random access memory, the first static random access memory and / or the second static random access memory comprises: A sixth transistor, a first electrode of which is connected to a write signal line, a second electrode of which is connected to a first node, and a gate of which is connected to a write control signal; A seventh transistor, a first electrode of which is connected to a high-level signal end, a second electrode of which is connected to the first node, and a gate of which is connected to a second node; An eighth transistor, a first electrode of which is connected to the first node, a second electrode of which is connected to a low-level signal end, and a gate of which is connected to the second node; A ninth transistor, a first electrode of which is connected to the high-level signal end, a second electrode of which is connected to the second node, and a gate of which is connected to the first node; A tenth transistor, a first electrode of which is connected to the second node, a second electrode of which is connected to the low-level signal end, and a gate of which is connected to the first node; An eleventh transistor, a first electrode of which is connected to the second node, a second electrode of which is connected to a read signal line, and a gate of which is connected to a read control signal; The sixth transistor, the seventh transistor, the ninth transistor and the eleventh transistor are P-type transistors, and the eighth transistor and the tenth transistor are N-type transistors.

14. The display panel of claim 4, wherein, The level conversion circuit comprises: A twelfth transistor, a first electrode of which is connected to a first high-level signal end, a second electrode of which is connected to a third node, and a gate of which is connected to an input signal end; A thirteenth transistor, a first electrode of which is connected to the third node, a second electrode of which is connected to a first low-level signal end, and a gate of which is connected to the input signal end; A fourteenth transistor, a first electrode of which is connected to the first high-level signal end, a second electrode of which is connected to a fourth node, and a gate of which is connected to the input signal end; A fifteenth transistor, a first electrode of which is connected to the fourth node, a second electrode of which is connected to a second low-level signal end, and a gate of which is connected to a fifth node; A sixteenth transistor, a first electrode of which is connected to the first high-level signal end, a second electrode of which is connected to the fifth node, and a gate of which is connected to the third node; A seventeenth transistor, a first electrode of which is connected to the fifth node, a second electrode of which is connected to the second low-level signal end, and a gate of which is connected to the fourth node; An eighteenth transistor, a first electrode of which is connected to a second high-level signal end, a second electrode of which is connected to a sixth node, and a gate of which is connected to a seventh node; A nineteenth transistor, a first electrode of which is connected to the sixth node, a second electrode of which is connected to the second low-level signal end, and a gate of which is connected to the fifth node; A twentieth transistor, a first electrode of which is connected to the second high-level signal end, a second electrode of which is connected to the seventh node, and a gate of which is connected to the sixth node; A twenty-first transistor, a first electrode of which is connected to the seventh node, a second electrode of which is connected to the second low level signal terminal, and a gate of which is connected to a fourth node; and the seventh node is connected to an output signal terminal; The twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor and the twentieth transistor are P-type transistors, and the thirteenth transistor, the fifteenth transistor, the seventeenth transistor, the nineteenth transistor and the twenty-first transistor are N-type transistors.

15. The display panel of claim 3, wherein, The controller comprises a second counter, which is electrically connected with the shift register; when the count of the second counter reaches a preset value, the shift register is controlled to receive image data.

16. The display panel of claim 1 or 2, wherein, The driving system further comprises a charge pump configured to generate a driving voltage of the display panel, and the driving voltage comprises a first reference gamma voltage, a second reference gamma voltage, a high level voltage and a low level voltage.

17. A display device comprising: A display panel comprising any one of claims 1-16.

Images