Pixel circuit and display device including same

Abstract

A pixel circuit is disclosed in the present disclosure. A pixel circuit according to an embodiment of the present disclosure includes: a first node connected to a driving voltage line configured to receive a first constant voltage; a third node connected to a fourth node, the fourth node being connected to a light emitting element; a first driver including a first driving element; and a second driver including a second driving element. The first driver and the second driver may be alternately driven for each frame. In the pixel circuit according to the present disclosure, a threshold voltage offset phenomenon and a degradation phenomenon of the driving element can be prevented or suppressed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0121496, filed on September 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a pixel circuit and a display device including the pixel circuit. Background Technology

[0004] Based on the material of the emitting layer, electroluminescent display devices can be divided into inorganic light-emitting display devices and organic light-emitting display devices. Active-matrix organic light-emitting display devices include organic light-emitting diodes (OLEDs) that emit light themselves, and they have advantages such as fast response speed, high luminous efficiency, high brightness, and wide viewing angle. In organic light-emitting display devices, an organic light-emitting diode (OLED) is formed in each pixel. Organic light-emitting display devices not only have fast response speed, excellent luminous efficiency, brightness, and viewing angle, but also provide excellent contrast and color reproduction because they can represent black grayscale as true black.

[0005] The pixel circuit of an organic light-emitting display device includes an OLED and driving elements for driving the OLED. Data voltage and reference voltage can be alternately applied to the data lines connected to the pixel circuit. In this case, because the data lines are charged and discharged with data voltage and reference voltage in a horizontal cycle, the power consumption of the display device increases.

[0006] In pixel circuits where the driving element is connected to the OLED, the brightness of the pixel changes due to the capacitance and resistance of the OLED when the pixel circuit is driven during the sampling and addressing phases. If there are deviations in the capacitance and resistance of the OLED between pixels due to process variations, the brightness unevenness between pixels may be even more severe.

[0007] Furthermore, each of the multiple pixels includes a driving element that controls the driving current flowing through the OLED based on the voltage Vgs across the gate and source electrodes. The electrical characteristics of the driving element may degrade over time and may vary from pixel to pixel. Summary of the Invention

[0008] This disclosure aims to address the aforementioned needs and / or resolve problems encountered in related technologies.

[0009] The purposes of embodiments according to this disclosure are not limited to those described above, and other purposes not described herein will be apparent to those skilled in the art from the following description.

[0010] A pixel circuit according to an exemplary embodiment of the present disclosure includes: a first node connected to a drive voltage line configured to receive a first constant voltage; a third node connected to a fourth node, the fourth node being connected to a light-emitting element; a first driver including a first driving element; and a second driver including a second driving element. The first driver and the second driver can be driven alternately for each frame.

[0011] According to various exemplary embodiments of this disclosure, the second driver is turned off in the Nth frame, and the first driver is turned off in the N+1th frame, where N is a natural number greater than or equal to 1. The Nth frame may include the time interval in which the first driving element is turned on, and the N+1th frame may include the time interval in which the second driving element is turned on.

[0012] According to various exemplary embodiments of the present disclosure, the first driving element may include a gate electrode connected to a second-first node, a first electrode connected to the first node, and a second electrode connected to the third node, and the second driving element may include a gate electrode connected to a second-second node, a first electrode connected to the first node, and a second electrode connected to the third node.

[0013] According to various exemplary embodiments of the present disclosure, the first driver may further include a first-first switching element configured to include a gate electrode connected to a first-first gate line to which a first-first scan pulse is applied, a first electrode connected to a data line to which a data voltage is applied, and a second electrode connected to the second-first node. The second driver may further include a first-second switching element configured to include a gate electrode connected to a first-second gate line to which a first-second scan pulse is applied, a first electrode connected to the data line, and a second electrode connected to the second-second node.

[0014] According to various exemplary embodiments of this disclosure, the second driver is turned off in the Nth frame, and the first driver is turned off in the N+1th frame, where N is a natural number greater than or equal to 1. The Nth frame may include a time interval in which the first-to-first switching element is turned on, and the N+1th frame may include a time interval in which the first-to-second switching element is turned on.

[0015] According to various exemplary embodiments of the present disclosure, the first driver may further include a second-first switching element configured to include a gate electrode connected to a second-first gate line to which a second-first scan pulse is applied, a first electrode connected to a reference voltage line to which a second constant voltage is applied, and a second electrode connected to the second-first node. The second driver may also include a second-second switching element configured to include a gate electrode connected to a second-second gate line to which a second-second scan pulse is applied, a first electrode connected to a reference voltage line to which a second constant voltage is applied, and a second electrode connected to the second-second node.

[0016] According to various exemplary embodiments of this disclosure, the second driver is turned off in the Nth frame, and the first driver is turned off in the N+1th frame, where N is a natural number greater than or equal to 1. The Nth frame may include a time interval in which the second-first switching element is turned on, and the N+1th frame may include a time interval in which the second-second switching element is turned on.

[0017] According to various exemplary embodiments of the present disclosure, the first driver may further include a first-first capacitor configured to include a first electrode connected to the second-first node and a second electrode connected to the third node, and the second driver may further include a first-second capacitor configured to include a first electrode connected to the second-second node and a second electrode connected to the third node.

[0018] According to various exemplary embodiments of the present disclosure, the first driver may further include: a first-first switching element configured to include a gate electrode connected to a first-first gate line to which a first-first scan pulse is applied, a first electrode connected to a data line to which a data voltage is applied, and a second electrode connected to the second-first node; and a second-first switching element configured to include a gate electrode connected to a second-first gate line to which a second-first scan pulse is applied, a first electrode connected to a reference voltage line to which a second constant voltage is applied, and a second electrode connected to the second-first node.

[0019] According to various exemplary embodiments of the present disclosure, the second driver may further include: a first-second switching element configured to include a gate electrode connected to a first-second gate line to which a first-second scan pulse is applied, a first electrode connected to a data line to which a data voltage is applied, and a second electrode connected to the second-second node; and a second-second switching element configured to include a gate electrode connected to a second-second gate line to which a second-second scan pulse is applied, a first electrode connected to a reference voltage line to which a second constant voltage is applied, and a second electrode connected to the second-second node.

[0020] According to various exemplary embodiments of the present disclosure, the pixel circuit may further include: a third switching element configured to include a gate electrode connected to a third gate line to which a third scan pulse is applied, a first electrode connected to the fourth node, and a second electrode to which a third constant voltage is applied; and a fourth switching element disposed between the drive voltage line and the first node.

[0021] According to various exemplary embodiments of the present disclosure, the fourth switching element may include a gate electrode connected to a fourth gate line to which a first EM pulse is applied, a first electrode connected to the drive voltage line, and a second electrode connected to the first node.

[0022] According to various exemplary embodiments of the present disclosure, the pixel circuit may further include a fifth switching element disposed between the third node and the fourth node.

[0023] According to various exemplary embodiments of the present disclosure, the fifth switching element may include a gate electrode connected to a fifth gate line to which a second EM pulse is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node.

[0024] In another aspect, a display device according to an exemplary embodiment of the present disclosure includes: a display panel including a plurality of data lines, a plurality of gate lines intersecting the data lines, a plurality of power lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power lines; a data driver configured to provide a data voltage for pixel data to the data lines; and a gate driver configured to provide a gate signal to the gate lines. Each of the plurality of pixel circuits includes: a first node connected to a drive voltage line configured to receive a first constant voltage; a third node connected to a fourth node connected to a light-emitting element; a first driver including a first driving element; and a second driver including a second driving element. The first driver and the second driver can be driven alternately for each frame.

[0025] According to various exemplary embodiments of this disclosure, the second driver is turned off in the Nth frame, and the first driver is turned off in the N+1th frame, where N is a natural number greater than or equal to 1. The Nth frame may include a time interval in which the first driving element is turned on, and the N+1th frame may include a time interval in which the second driving element is turned on.

[0026] According to various exemplary embodiments of the present disclosure, the first driving element may include a gate electrode connected to a second-first node, a first electrode connected to the first node, and a second electrode connected to the third node, and the second driving element may include a gate electrode connected to a second-second node, a first electrode connected to the first node, and a second electrode connected to the third node.

[0027] According to various exemplary embodiments of the present disclosure, the first driver may further include a first-first switching element configured to include a gate electrode connected to a first-first gate line to which a first-first scan pulse is applied, a first electrode connected to a data line to which a data voltage is applied, and a second electrode connected to the second-first node. The second driver may further include a first-second switching element configured to include a gate electrode connected to a first-second gate line to which a first-second scan pulse is applied, a first electrode connected to the data line, and a second electrode connected to the second-second node.

[0028] According to various exemplary embodiments of the present disclosure, the first driver may further include a second-first switching element, the second-first switching element being configured to include a gate electrode connected to a second-first gate line to which a second-first scan pulse is applied, a first electrode connected to a reference voltage line to which a second constant voltage is applied, and a second electrode connected to the second-first node. The second driver may further include a second-second switching element, the second-second switching element being configured to include a gate electrode connected to a second-second gate line to which a second-second scan pulse is applied, a first electrode connected to a reference voltage line to which the second constant voltage is applied, and a second electrode connected to the second-second node.

[0029] According to various exemplary embodiments of the present disclosure, the first driver may further include a first-first capacitor configured to include a first electrode connected to the second-first node and a second electrode connected to the third node, and the second driver may further include a first-second capacitor configured to include a first electrode connected to the second-second node and a second electrode connected to the third node.

[0030] According to various exemplary embodiments of this disclosure, the load applied to the driving element can be reduced. Furthermore, threshold voltage shift in the pixel circuitry can be reduced, and the operating cycle can be extended.

[0031] According to various exemplary embodiments of this disclosure, threshold voltage shift and degradation of the driving element can be prevented or suppressed.

[0032] According to various exemplary embodiments of this disclosure, the lifespan of the display device can be improved, while low-power operation can be achieved over a long period of time.

[0033] It should be understood that the above general description and the following detailed description are given by way of example and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0034] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate exemplary embodiments of this disclosure and, together with the specification, serve to explain the various principles of this disclosure.

[0035] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0036] Figure 2 This is a plan view of a display device according to an exemplary embodiment of the present disclosure.

[0037] Figure 3 This is a plan view showing pixels according to an exemplary embodiment of the present disclosure.

[0038] Figure 4 This is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure.

[0039] Figure 5 This is a view illustrating a gate driver according to an exemplary embodiment of the present disclosure.

[0040] Figure 6 This is a schematic diagram illustrating an exemplary pixel circuit.

[0041] Figure 7 It shows the basis Figure 6 Waveform diagram of the driving method of the pixel circuit.

[0042] Figure 8 This is a view showing the duration of an example display.

[0043] Figure 9 It is a waveform diagram showing the timing signal synchronized with the image signal.

[0044] Figure 10 This is a view illustrating a pixel circuit according to a first exemplary embodiment of the present disclosure.

[0045] Figure 11 This is a waveform diagram illustrating a method for driving a pixel circuit according to a first exemplary embodiment of the present disclosure.

[0046] Figure 12 This is a view showing the current flowing in the pixel circuit according to the first exemplary embodiment during the initialization phase of the Nth frame.

[0047] Figure 13 This is a view showing the current flowing in the pixel circuit according to the first exemplary embodiment during the sampling phase of the Nth frame.

[0048] Figure 14 This is a view showing the current flowing in the pixel circuit according to the first exemplary embodiment during the addressing phase of the Nth frame.

[0049] Figure 15 This is a view showing the current flowing in the pixel circuit according to the first exemplary embodiment during the transmission phase of the Nth frame.

[0050] Figure 16 This is a view showing the current flowing in the pixel circuit according to the first exemplary embodiment during the initialization phase of the N+1th frame.

[0051] Figure 17 This is a view showing the current flowing in the pixel circuit according to the first exemplary embodiment during the sampling phase of the N+1th frame.

[0052] Figure 18 This is a view showing the current flowing in the pixel circuit according to the first exemplary embodiment during the addressing phase of the N+1th frame.

[0053] Figure 19 This is a view showing the current flowing in the pixel circuit according to the first exemplary embodiment during the transmission phase of the N+1th frame.

[0054] Figure 20 This is a view illustrating a pixel circuit according to a second exemplary embodiment of the present disclosure.

[0055] Figure 21 This is a waveform diagram illustrating a method for driving a pixel circuit according to a second exemplary embodiment of the present disclosure.

[0056] Figure 22 This is a view illustrating a pixel circuit according to a third exemplary embodiment of the present disclosure.

[0057] Figure 23 This is a waveform diagram illustrating a method for driving a pixel circuit according to a third exemplary embodiment of the present disclosure.

[0058] Figure 24 This is a view illustrating a pixel circuit according to a fourth exemplary embodiment of the present disclosure.

[0059] Figure 25 This is a waveform diagram illustrating a method for driving a pixel circuit according to a fourth exemplary embodiment of the present disclosure.

[0060] Figure 26 This is a view illustrating a pixel circuit according to a fifth exemplary embodiment of the present disclosure.

[0061] Figure 27 This is a waveform diagram illustrating a method for driving a pixel circuit according to a fifth exemplary embodiment of the present disclosure. Detailed Implementation

[0062] The advantages and features of this disclosure, as well as the methods for implementing this disclosure, will become clearer from the exemplary embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. More precisely, the description of these exemplary embodiments will make the disclosure more complete and allow those skilled in the art to more fully understand the scope of this disclosure. The scope of protection of this disclosure can be limited to the appended claims and their equivalents.

[0063] In describing this disclosure, a detailed description of relevant known technologies may be omitted if it may unnecessarily obscure the subject matter of this disclosure.

[0064] Where terms such as “comprising,” “having,” or “compose” are used in this disclosure, other parts may be added unless more restrictive terms such as “only” are also used. Where a component is represented in the singular, the singular includes the plural unless otherwise specified.

[0065] When describing the location or interconnection between two components, terms such as “on top of”, “above”, “below”, “next to”, “connected to or coupled with”, “cross”, “intersect”, etc., unless more restrictive terms such as “immediately” or “directly” are used, one or more other components may be inserted between them.

[0066] When describing temporal context, phrases such as “after,” “following,” “next,” or “before” may not be continuous on the time scale unless more restrictive terms such as “immediately” or “directly” are used.

[0067] The terms “first”, “second”, etc., can be used to refer to components that are separate from each other, but the function or structure of a component is not limited by the serial number or component name preceding it.

[0068] The following embodiments can be combined or associated with each other, in whole or in part, and various types of linkages and drives are technically possible. The embodiments can be implemented independently of each other or together in an interrelated relationship.

[0069] The terminology used in the embodiments of this disclosure (including technical and scientific terms) may be interpreted in the sense commonly understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise explicitly and specifically defined. Furthermore, commonly used terms, such as predefined terms, may be interpreted in light of their contextual meaning in the relevant art.

[0070] In the display device according to various embodiments of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may include oxide TFTs comprising oxide semiconductors or low-temperature polycrystalline silicon TFTs comprising low-temperature polycrystalline silicon (LTPS).

[0071] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. Charge carriers can flow from the source in a transistor. The drain is the electrode through which charge carriers flow from the transistor to the outside. In a transistor, charge carriers flow from the source to the drain.

[0072] In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the voltage applied to them. Therefore, this disclosure is not limited to the disclosed content due to the source and drain of the transistor. In the following description, the source and drain of the transistor can be used interchangeably and are referred to as the first electrode and the second electrode.

[0073] The gate signal can oscillate between the gate turn-on voltage and the gate turn-off voltage. The transistor can turn on in response to the gate turn-on voltage and turn off in response to the gate turn-off voltage. In the case of an n-channel transistor, the gate turn-on voltage can be gate high (GHV), and the gate turn-off voltage can be gate low (VGL). For a p-channel transistor, the gate turn-on voltage can be gate low (VGL), and the gate turn-off voltage can be gate high (VGH).

[0074] Various exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0075] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0076] Please refer to Figure 1 According to one embodiment of the present disclosure, the display device may be an organic light-emitting display device. The display device includes a display panel 100, display panel driving circuits 110 and 120 for writing image data to pixels of the display panel 100, and a power supply circuit 140 for generating power to drive the pixels. The driving circuits 110 and 120 and the power supply circuit 140 may be display panel drivers that drive the display panel.

[0077] The display panel 100 can be a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction.

[0078] The display area AA of the display panel 100 may include a pixel array for displaying images thereon. The pixel array may include multiple data lines 102, multiple gate lines 103 intersecting the multiple data lines 102, multiple sensing lines 104, and pixels P arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels P. The power lines may be connected to the pixels P and provide a constant voltage to drive the pixels P.

[0079] A pixel P can be divided into two or more subpixels to represent color. For example, three pixels arranged sequentially along the X-axis can be divided into red, green, and blue subpixels. Furthermore, four pixels arranged sequentially along the X-axis can be divided into red, green, blue, and white subpixels.

[0080] Each pixel P can be connected to a data line, a gate line, and a power line.

[0081] The pixel array may include multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln may include a line of pixels P arranged along the line direction (X-axis direction) of the pixel array in the display panel 100. Pixels arranged as a pixel line may share a gate line 103. Pixels P arranged along the data line direction in the column direction (Y-axis direction) may share the same data line 102 and the same sensing line 104. A horizontal period is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0082] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and the actual object in the background is visible. The display panel 100 can also be implemented as a flexible display panel.

[0083] Figure 2 This is a plan view of a display device according to an embodiment of the present disclosure.

[0084] refer to Figure 2 The substrate 211 may include a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA of the substrate 211 may be adjacent to the display area AA and may be located outside the display area AA.

[0085] The display area AA can be an area in which multiple pixels P are arranged to display an image. Pixel P can also include multiple sub-pixels SP_1, SP_2, and SP_3.

[0086] Multiple subpixels SP are individual units that emit light, and each of the subpixels SP can emit, for example, red light, green light, blue light, or white light, but is not limited to these.

[0087] Each of the sub-pixels SP_1, SP_2, and SP_3 can be equipped with a thin-film transistor and a light-emitting device layer. For example, light-emitting elements for displaying images and circuitry for driving these elements can be arranged in multiple sub-pixels SP.

[0088] Each subpixel SP may include multiple thin-film transistors and storage capacitors. For example, a subpixel SP may consist of two transistors and one capacitor (2T1C), but is not limited to this configuration, and may also be implemented as a subpixel using other configurations such as 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 5T2C, 6T2C, 7T2C, or 8T2C.

[0089] A pixel P can be composed of one or more sub-pixels SP that emit different colors. For example, a pixel P may include a first sub-pixel SP_1, a second sub-pixel SP_2, and a third sub-pixel SP_3.

[0090] The exemplary shapes of the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 can be, but are not limited to, rectangles, pentagons, hexagons, octagons, circles, ellipses, etc.

[0091] The first sub-pixel SP-1, the second sub-pixel SP-2, and the third sub-pixel SP-3 can emit light of different colors, and can emit at least one of red, green, or blue. The third sub-pixel SP-3 can have a larger area than the other sub-pixels. The third sub-pixel SP-3 can be arranged across the other sub-pixels.

[0092] The non-display area NA can be an area where no image is displayed, and it can be an area in which various traces and driving circuits for driving multiple sub-pixels SP located in the display area AA are arranged. For example, various driving circuits such as gate drivers and data drivers can be arranged in the non-display area NA. The non-display area NA can be a border area, but is not limited to this.

[0093] The non-display area NA can be located around the display area AA. For example, the non-display area NA can be located around the display area AA. The non-display area NA can be, but is not limited to, an area in which multiple sub-pixels SP are not arranged.

[0094] The display area AA and the non-display area NA can be any shape suitable for the design of an electronic device on which the display panel 100 is mounted. If the display device is located on a user wearable device such as a common wristwatch, it can have a circular shape, and the concepts of the embodiments of this disclosure can also be applied to free-form displays, such as those present in vehicle dashboards, etc. Exemplary shapes of the display area AA can be, but are not limited to, pentagons, hexagons, circles, ellipses, etc.

[0095] The display panel 100 disclosed herein may include various additional components for generating various signals or driving multiple sub-pixels SP_1, SP_2, and SP_3 within the display area AA. For example, one or more driving circuits for controlling the sub-pixels SP may be included in the display device. The driving circuits for controlling (or driving) the sub-pixels SP_1, SP_2, and SP_3 may include a gate driver 120, a data driver (not shown), a multiplexer (not shown), an electrostatic discharge (ESD) circuit (not shown), power lines, inverter circuits, signal lines, etc. The power lines may be high-potential voltage lines VDD and / or low-potential voltage lines VSS.

[0096] In addition to the functions used to drive subpixels SP_1, SP_2, and SP_3, the display panel 100 may also include additional components. For example, the display panel 100 may include additional components that provide touch sensing functions, user authentication functions (e.g., fingerprint recognition), multi-level pressure sensing functions, haptic feedback functions, etc. These additional components may be located in the non-display area NA or in external circuitry connected via a connection interface.

[0097] The pad portion PAD can be located on one side of the non-display area NA. The pad portion PAD can be a metal pattern to which external modules, such as flexible printed circuit boards (FPCBs) and chip-on-film (COF), are bonded. Although the pad portion PAD is shown as being located on one side of substrate 211, the shape and position of the pad portion are not limited thereto.

[0098] The gate driver 120, used to provide gate signals to the thin-film transistor, can be arranged on the other side of the non-display area NA. The gate driver 120 may include various gate driving circuits, and the gate driving circuits may be formed directly on the substrate 211. In this case, the gate driver 120 may be of the gate in-panel (GIP) type.

[0099] The gate driver 120 may be located between the display area AA and the dam section DAM arranged in the non-display area NA of the substrate 211.

[0100] The gate driver 120 may include a scan driving circuit, a light-emitting driving circuit, and signal lines.

[0101] Signal lines can transmit and control signals supplied from the pad portion to the scan drive circuit or the light-emitting drive circuit. For example, a signal line can be a clock line.

[0102] The data driver that provides data signals to the thin-film transistor can be located on the other side of the non-display area NA. The data driver can include various data drive circuits.

[0103] A high-potential voltage line VDD, a low-potential voltage line VSS, a multiplexer, an anti-static circuit, and multiple connecting lines can be arranged between the display area AA and the data driver. These components can be arranged between the display area AA and the curved area BA.

[0104] The interconnect portion can be located in the non-display area NA. For example, the interconnect portion can be located in the bending area BA in the non-display area NA, where the substrate is bent. The interconnect portion can be configured to transmit signals (voltages) from an external module bonded to the pad portion to the display area AA or to circuitry such as gate driver 120 and data driver. For example, various signals such as data signals, high-potential voltages, and low-potential voltages used to drive gate driver 120 can be transmitted through the interconnect portion.

[0105] The dam section DAM can be located in the non-display area NA, surrounding all or part of the display area AA. The dam section DAM can be adjacent to the display area AA, or it can be located outside the display area AA.

[0106] A dammed array (DAM) can be positioned around the perimeter of the display area AA to control the flow of the organic material layer within the encapsulation layer arranged on the light-emitting element layer. Multiple dammed arrays (DAMs) can be present. The DAMs can be positioned between the display area AA and the high-potential voltage line VDD, the low-potential voltage line VSS, a multiplexer, or an anti-static circuit.

[0107] The panel crack detector PCD can also be arranged in a portion of the non-display area NA of the substrate 211. The panel crack detector PCD can be arranged between an end point (or end) of the substrate 211 and the dam section DAM. Alternatively, the panel crack detector PCD is located downstream of the dam section DAM, and the panel crack detector PCD can at least partially overlap with the dam section DAM.

[0108] Figure 3 This is a plan view illustrating pixels according to an embodiment of the present disclosure.

[0109] refer to Figure 3The display panel 100 disclosed herein may include three sub-pixels SP1, SP2, and SP3, which are consecutive in one direction (from left to right) to form a single pixel P. Within each pixel P, a plurality of sub-pixels SP may be arranged to be spaced apart from each other by a predetermined interval.

[0110] Within a pixel P, the first to third data lines DL1, DL2, and DL3 extending along the Y-axis can correspond to the boundary arrangement of sub-pixels SP1, SP2, and SP3.

[0111] At the boundaries between sub-pixels SP1, SP2, and SP3, power lines PL extending along a first direction for applying a high-potential power supply voltage can be arranged. At the boundaries of sub-pixels SP1, SP2, and SP3 adjacent to the power lines PL, reference lines RL for applying a reference voltage Vref can be arranged. Furthermore, at the boundaries of sub-pixels SP1, SP2, and SP3 adjacent to the power lines PL, initialization lines for applying an initialization voltage Vinit can also be arranged.

[0112] At each vertically adjacent boundary of sub-pixels SP1, SP2, and SP3, gate lines GL1, GL2, GL3, and GL4 extending along the X-axis can be arranged. These gate lines intersect with the first to third data lines DL1, DL2, DL3, the power line PL, and the reference line RL. Transmit control signal lines EML1, EML2, and EML3 can be arranged parallel to and spaced apart from the gate lines GL1, GL2, GL3, and GL4.

[0113] With the development of display devices with higher resolution and greater pixel density, the spatial constraints on pixel arrangement have increased. Therefore, power lines PL and reference lines RL can be configured to be shared by multiple sub-pixels SP. This configuration can be called a flip structure, in which power lines PL and reference lines RL are shared between two adjacent sub-pixels SP, thereby reducing the number of signal lines providing a common signal to each sub-pixel SP and saving the area occupied by signal lines.

[0114] Therefore, some of the sub-pixels SP can be directly connected to the power line PL and the reference line RL, while other sub-pixels SP can be connected to each of the power line PL and the reference line RL via a separate connection pattern CP, instead of being directly connected to the power line PL and the reference line RL.

[0115] Figure 4 This is a cross-sectional view illustrating a display device according to an embodiment of the present disclosure.

[0116] refer to Figure 4The display device may include two thin-film transistors (TFTs) 1 and TFT2 and a capacitor CST. The two TFTs 1 and TFT2 may include a first TFT 1 comprising a polycrystalline semiconductor material and a second TFT 2 comprising an oxide semiconductor material.

[0117] Pixel P may include a light-emitting element EL and a pixel driving circuit that applies a driving current to the light-emitting element EL. The pixel driving circuit may be disposed on substrate 211, and the light-emitting element EL may be disposed on the pixel driving circuit. Furthermore, an encapsulation layer 220 may be disposed on the light-emitting element EL. The encapsulation layer 220 protects the light-emitting element EL.

[0118] A pixel driving circuit refers to the pixel P array portion, which includes driving thin-film transistors, switching thin-film transistors, and capacitors. A light-emitting element (EL) refers to the array portion used for light emission, which includes an anode electrode, a cathode electrode, and a light-emitting layer disposed between the anode and cathode electrodes.

[0119] In one embodiment, the driving thin-film transistor and at least one switching thin-film transistor may use oxide semiconductor as the active layer. Compared with thin-film transistors using polycrystalline semiconductor materials as the active layer, thin-film transistors using oxide semiconductor materials as the active layer have excellent leakage current blocking effect and relatively low manufacturing cost. Therefore, in order to reduce power consumption and manufacturing cost, the pixel driving circuit according to the embodiment may include a driving thin-film transistor and at least one switching thin-film transistor using oxide semiconductor materials.

[0120] All thin-film transistors forming the pixel driving circuit can be implemented using oxide semiconductor materials, or only some of the switching thin-film transistors can be implemented using oxide semiconductor materials.

[0121] However, since thin-film transistors using oxide semiconductor materials are difficult to ensure reliability, while thin-film transistors using polycrystalline semiconductor materials have high operating speed and excellent reliability, embodiments may include switching thin-film transistors using oxide semiconductor materials and switching thin-film transistors using polycrystalline semiconductor materials.

[0122] The substrate 211 can be implemented using a multilayer in which organic films and inorganic films are stacked alternately. For example, the substrate 211 can be stacked with alternating organic films (e.g., polyimide) and inorganic films (e.g., silicon oxide (SiO2)).

[0123] A lower buffer layer 212a can be formed on the substrate 211. The lower buffer layer 212a can be formed by stacking silicon oxide (SiO2) layers or the like in multiple layers to block moisture or the like that may penetrate from the outside. An auxiliary buffer layer 212b can be further located on the lower buffer layer 212a to protect the device from moisture penetration.

[0124] The first thin-film transistor TFT1 can be formed on the substrate 211. The first thin-film transistor TFT1 can utilize a polycrystalline semiconductor as the active layer. The first transistor TFT1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2. The first active layer ACT1 includes a channel through which electrons or holes move.

[0125] The first active layer ACT1 may include a first channel region, a first source region located on one side of the first channel region, and a first drain region located on the other side of the first channel region.

[0126] The first source region and the first drain region are regions obtained by doping an intrinsic polycrystalline semiconductor material with a predetermined concentration of Group 5 or Group 3 impurity ions (e.g., phosphorus (P) or boron (B)) to make it conductive. The first channel region in which the polycrystalline semiconductor material retains its intrinsic state can provide a path for the movement of electrons or holes.

[0127] On the other hand, the first thin-film transistor TFT1 may include a first gate electrode GE1 that overlaps with the first channel region of the first active layer ACT1. A first gate insulating layer 213 may be disposed between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 213 may be formed by stacking inorganic layers such as silicon oxide (SiO2) and silicon nitride (SiNx) in a single layer or multiple layers.

[0128] In one embodiment, the first thin-film transistor TFT1 has a top gate structure in which the first gate electrode GE1 is located on top of the first active layer ACT1. Therefore, the first electrode CST1 included in the capacitor CST and the light-shielding layer LS included in the first thin-film transistor TFT1 can be formed of the same material as the first gate electrode GE1. Forming the first gate electrode GE1, the first electrode CST1, and the light-shielding layer LS in a single mask process reduces the number of mask processes. However, without limitation, the light-shielding layer LS can be formed on the lower buffer layer 212a and the auxiliary buffer layer 212b by separate mask processes. In this case, the light-shielding layer LS can be formed under any transistor, not limited to the first thin-film transistor TFT1. Furthermore, the light-shielding layer LS can be arranged to overlap with the lower portion of the capacitor CST to form a dual capacitor.

[0129] When the substrate 211 is formed of a transparent material, a light-shielding layer LS can be formed below the active layers ACT1 and ACT2. The light-shielding layer LS can block light passing through the transparent substrate 211 and reaching the active layers ACT1 and ACT2, thereby maintaining the function of the active layers ACT1 and ACT2. The light-shielding layer LS can be formed on the lower buffer layer 212a or on the auxiliary buffer layer 212b.

[0130] The first gate electrode GE1 can be formed of a metallic material. For example, the first gate electrode GE1 can be a single layer or multiple layers made of any one of, but not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0131] The first interlayer insulating layer 214 can be disposed on the first gate electrode GE1. The first interlayer insulating layer 214 can be implemented using silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0132] The display panel 100 may further include an upper buffer layer 215, a second gate insulating layer 216, and a second interlayer insulating layer 217 sequentially disposed on top of the first interlayer insulating layer 214, and the second thin film transistor TFT2 may include a second source electrode SD3 and a second drain electrode SD4 formed on the first interlayer insulating layer 214 and respectively connected to the second source region and the second drain region.

[0133] The first source electrode SD1 and the first drain electrode SD2 can be made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, in single or multiple layers.

[0134] The upper buffer layer 215 can separate the second active layer ACT2 of the second thin film transistor TFT2, which is made of oxide semiconductor material, from the first active layer ACT1, which is made of polycrystalline semiconductor material, and provides a base for forming the second active layer ACT2.

[0135] The second gate insulating layer 216 covers the second active layer ACT2 of the second thin-film transistor TFT2. The second gate insulating layer 216 can be formed above the second active layer ACT2, which can be implemented using an oxide semiconductor material, and therefore the second gate insulating layer 216 can be implemented using an inorganic film. For example, the second gate insulating layer 216 can be silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0136] The second gate electrode GE2 can be formed of a metallic material. For example, the second gate electrode GE2 can be a single layer or multiple layers made of any one of, but not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0137] On the other hand, the second thin-film transistor TFT2 may include a second active layer ACT2 formed on the upper buffer layer 215 and implemented with an oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 216, a second source electrode SD3 disposed on the second interlayer insulating layer, and a second drain electrode SD4 disposed on the second interlayer insulating layer.

[0138] The second active layer ACT2 can be implemented using an oxide semiconductor material and can include an intrinsic second channel region that is undoped and a second source region and a second drain region that are doped to conduct electricity.

[0139] The second thin-film transistor TFT2 may further include a light-shielding layer LS located above the upper buffer layer 215 and overlapping the second active layer ACT2. The light-shielding layer LS can block light incident on the second active layer ACT2 to ensure the reliability of the second thin-film transistor TFT2. The light-shielding layer LS can be formed of the same material as the second gate electrode GE2 and can be formed on the upper surface of the first gate insulating layer 213. The light-shielding layer LS can be electrically connected to the second gate electrode GE2 to form a dual gate.

[0140] The second source electrode SD3 and the second drain electrode SD4 can be formed simultaneously on the second interlayer insulating layer 217 from the same material as the first source electrode SD1 and the first drain electrode SD2, in order to reduce the number of mask processes.

[0141] On the other hand, the capacitor CST can be implemented by arranging the second electrode CST2 on the first interlayer insulating layer 214 to overlap with the first electrode CST1. For example, the second electrode CST2 can be a single layer or multiple layers made of any one of, but not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0142] The capacitor CST can store the data voltage applied through the data line DL for a certain period of time and supply it to the light-emitting element EL. The capacitor CST may include two corresponding electrodes and a dielectric disposed therebetween. A first interlayer insulating layer 214 may be located between the first electrode CST1 and the second electrode CST2.

[0143] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the second thin-film transistor TFT2. However, the connection relationship of the capacitor CST can vary depending on the pixel driving circuit, but is not limited to this.

[0144] On the other hand, a first planarization layer 218 and a second planarization layer 219 can be sequentially arranged on top of the pixel driving circuit to planarize the top of the pixel driving circuit. The first planarization layer 218 and the second planarization layer 219 can be organic films such as polyimide or acrylic resin. A light-emitting element (EL) can be formed on top of the second planarization layer 219.

[0145] The light-emitting element (EL) may include an anode electrode (ANO), a cathode electrode (CAT), and an OLED light-emitting layer disposed between the anode electrode (ANO) and the cathode electrode (CAT). When a pixel driving circuit connected to the cathode electrode (CAT) is implemented using a common low potential voltage, the anode electrode (ANO) can be arranged as a separate electrode for each sub-pixel. Conversely, when a pixel driving circuit is implemented using a common high potential voltage, the cathode electrode (CAT) can also be arranged as a separate electrode for each sub-pixel.

[0146] The light-emitting element EL can be electrically connected to the driving element via an intermediate electrode CNE disposed on the first planarization layer 218. Specifically, the anode electrode ANO of the light-emitting element EL forming the pixel driving circuit and the second source electrode SD3 of the second thin-film transistor TFT2 can be connected to each other via the intermediate electrode CNE.

[0147] The anode electrode ANO can be connected to the intermediate electrode CNE exposed through a contact hole passing through the second planarization layer 219. The intermediate electrode CNE can be connected to the second source electrode SD3 exposed through a contact hole passing through the first planarization layer 218.

[0148] The intermediate electrode CNE can be used as a medium between the second source electrode SD3 and the anode electrode ANO. The intermediate electrode CNE can be made of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0149] The anode electrode (ANO) can be formed as a multilayer structure comprising a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film can be made of a material with a relatively large work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film can be formed as a single-layer or multilayer structure containing aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode electrode (ANO) can be formed as a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are stacked sequentially, or it can be formed as a structure in which a transparent conductive film and an opaque conductive film are stacked sequentially.

[0150] An OLED with a light-emitting layer can be formed by stacking a hole-correlated layer, an organic light-emitting layer, and an electron-correlated layer on an anode electrode (ANO) in either order or in reverse order.

[0151] The dam layer BNK can be a pixel-defined film that exposes the anode electrode ANO of each pixel P. The dam layer BNK can be formed of an opaque material (e.g., black) to prevent or mitigate light interference between adjacent pixels P. In this case, the dam layer BNK can include a light-blocking material made of at least one of colored pigments, organic black, and carbon. Additional spacers can be arranged on the dam layer BNK.

[0152] The cathode electrode CAT can face the anode electrode ANO, wherein the emitting layer OLED is interposed between the cathode electrode CAT and the anode electrode ANO, and the cathode electrode CAT can be formed on the upper and side surfaces of the emitting layer OLED. The cathode electrode CAT can be integrally formed across the display area AA. When applied to a front-emitting organic light-emitting display device, the cathode electrode CAT can be formed from a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0153] An encapsulation layer 220 may be further arranged on top of the cathode electrode CAT to prevent or mitigate moisture penetration.

[0154] The encapsulation layer 220 can prevent or suppress the penetration of external moisture or oxygen into the light-emitting element (EL), which is susceptible to external moisture or oxygen. Therefore, the encapsulation layer 220 may include, but is not limited to, at least one inorganic encapsulation layer and at least one organic encapsulation layer. This disclosure will be described using an example of a structure in which the first encapsulation layer 221, the second encapsulation layer 222, and the third encapsulation layer 223 are stacked sequentially.

[0155] A first encapsulation layer 221 can be formed on a substrate 211 on which a cathode electrode CAT is formed. A third encapsulation layer 223 can be formed on a substrate 211 on which a second encapsulation layer 222 is formed, and can be formed together with the first encapsulation layer 221 to surround the top, bottom, and side surfaces of the second encapsulation layer 222. This first encapsulation layer 221 and third encapsulation layer 223 can suppress or prevent external moisture or oxygen from penetrating into the light-emitting element EL. The first encapsulation layer 221 and third encapsulation layer 223 can be formed from inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3) that can be deposited at low temperatures. Because the first encapsulation layer 221 and third encapsulation layer 223 are deposited in a low-temperature atmosphere, the deposition process of the first encapsulation layer 221 and third encapsulation layer 223 can prevent or mitigate damage to the light-emitting element EL, which is susceptible to damage from high-temperature atmospheres.

[0156] The second encapsulation layer 222 can serve as a buffer to alleviate interlayer stress caused by bending of the display device and can flatten the step differences between layers. This second encapsulation layer 222 can be formed on a substrate 211 on which the first encapsulation layer 221 is formed, using, but not limited to, non-sensitive organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon carbide (SiOC), or photosensitive organic insulating materials such as photoacrylic acid. When the second encapsulation layer 222 is formed using an inkjet printing method, a dammed area (DAM) can be arranged to prevent or inhibit the diffusion of the liquid form of the second encapsulation layer 222 into the edges of the substrate 211. The dammed area (DAM) can be arranged closer to the edges of the substrate 211 than the second encapsulation layer 222. The dammed area (DAM) can prevent or inhibit the diffusion of the second encapsulation layer 222 into the pad area, where the conductive pads are located at the outermost part of the substrate 211.

[0157] Even if the dammed DAM is designed to prevent or suppress the diffusion of the second encapsulation layer 222, if the second encapsulation layer 222 is formed during the process to exceed the height of the dammed DAM, the second encapsulation layer 222, as an organic layer, can be exposed to the outside, thereby facilitating the penetration of moisture and other substances into the light-emitting element. Therefore, to prevent or suppress this situation, the dammed DAM can be formed in at least 10 or more overlapping layers. For example, the dammed DAM may include a first dammed DAM1 and a second dammed DAM2.

[0158] The dam section DAM can be arranged on the second interlayer insulation layer 217 of the non-display area NA.

[0159] Furthermore, the dam section DAM can be formed simultaneously with the first planarization layer 218 and the second planarization layer 219. The dam section DAM can be stacked in a dual structure such that when the first planarization layer 218 is formed, the lower layer of the dam section DAM is formed together, and when the second planarization layer 219 is formed, the upper layer of the dam section DAM is formed together.

[0160] Therefore, the dam section DAM can be formed of, but is not limited to, the same material as the first planarization layer 218 and the second planarization layer 219.

[0161] The dam section DAM can be formed to overlap with low-potential voltage lines. For example, in the non-display area NA, a low-potential voltage line can be formed in the lower layer of the area where the dam section DAM is located.

[0162] A low-potential voltage line and a gate driver in the form of a gate in-panel (GIP) are formed around the periphery of the display panel, and the low-potential voltage line may be located outside the gate driver. Furthermore, the low-potential voltage line may be connected to the cathode electrode CAT to apply a common voltage. The gate driver is simplified in the plan and cross-sectional views, but it can be formed using a thin-film transistor with the same structure as the thin-film transistor in the display area AA.

[0163] The low-potential voltage line can be arranged outside the gate driver. The low-potential voltage line can be arranged outside the gate driver and can surround the display area AA. For example, the low-potential voltage line can be made of the same material as the first gate electrode GE1, but is not limited thereto, and the low-potential voltage line can be made of the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2, but is not limited thereto.

[0164] Furthermore, the low-potential voltage line can be electrically connected to the cathode electrode CAT. The low-potential voltage line can provide a low-potential drive voltage ELVSS to multiple pixels P in the display area AA.

[0165] A touch layer may be disposed on top of the encapsulation layer 220. In the touch layer, a touch buffer film 251 may be located between the touch sensor metal including touch electrode connection lines 252 and 254 and touch electrodes 255 and 256 and the cathode electrode CAT of the light-emitting element EL.

[0166] The touch buffer film 251 can prevent or suppress the penetration of external chemical liquids (such as developer or etchant liquids) or moisture into the OLED emission layer containing organic materials during the manufacturing process of the touch sensor metal disposed on the touch buffer film 251. Therefore, the touch buffer film 251 can prevent or suppress damage to the OLED emission layer that is susceptible to chemical solutions or moisture.

[0167] The touch buffer film 251 can be formed of an organic insulating material that can be formed at a specific temperature (e.g., 100 degrees Celsius or lower) and has a low dielectric constant of 1 to 3 to prevent or suppress damage to the OLED emitter layer, which contains organic materials susceptible to high temperatures. For example, the touch buffer film 251 can be formed of acrylic, epoxy, or siloxane materials. The touch buffer film 251, with its planarization properties, acts as an organic insulating material to prevent damage to the encapsulation layer 220 due to bending of the organic light-emitting display device and to prevent breakage of the touch sensor metal formed on the touch buffer film 251.

[0168] According to the mutual capacitance-based touch sensor structure, touch electrodes 255 and 256 are arranged on the touch buffer film 251, and touch electrodes 255 and 256 can be arranged to cross each other.

[0169] Touch electrode connecting wires 252 and 254 can be electrically connected between touch electrodes 255 and 256. Touch electrode connecting wires 252 and 254 and touch electrodes 255 and 256 can be located on different layers, so that touch insulating film 253 is inserted therebetween.

[0170] Touch electrode connection lines 252 and 254 can be arranged to overlap with the embankment layer BNK, thereby preventing or suppressing a decrease in the opening ratio.

[0171] On the other hand, touch electrodes 255 and 256 can be electrically connected to touch driving circuitry (not shown) via touch pads PAD, and a portion of touch electrode connection line 252 extends through the upper and side surfaces of package layer 220 and the upper and side portions of dam DAM to touch pads PAD.

[0172] A portion of the touch electrode connection line 252 can receive touch drive signals from the touch drive circuit and transmit them to the touch electrodes 255 and 256, and can also transmit touch sensing signals from the touch electrodes 255 and 256 to the touch drive circuit.

[0173] The touch protective film 257 can be disposed above the touch electrodes 255 and 256. Although the touch protective film 257 is shown as being disposed only above the touch electrodes 255 and 256, it is not limited thereto. The touch protective film 257 can extend before or after the dam section DAM, and can also be disposed above the touch electrode connection line 252, but is not limited thereto.

[0174] Furthermore, a filter (not shown in the figure) may be further arranged on the encapsulation layer 220, and the filter may be located on the touch layer or between the encapsulation layer 220 and the touch layer.

[0175] Figure 5 This is a view illustrating a gate driver according to an embodiment of the present disclosure.

[0176] refer to Figure 5 Such a gate driver may include multiple gate drivers that output gate signal pulses. According to one embodiment, the gate driver may include a first gate driver 310 that outputs a first gate signal SC1, a second gate driver 320 that outputs a second gate signal SC2, a third gate driver 330 that outputs a third gate signal SC3, a fourth gate driver 340 that outputs a fourth gate signal EM1, and a fifth gate driver 350 that outputs a fifth gate signal EM2.

[0177] Some of the multiple gate drivers can be implemented using shift register circuitry, while others can be implemented using edge-triggered circuitry. For example, the first gate driver 310 can be implemented using shift register circuitry, and the second to fifth gate drivers 320 can be implemented using edge-triggered circuitry. Shift register circuitry can output a gate signal to only one pixel line, while edge-triggered circuitry can output a gate signal to two or more pixel lines simultaneously. Therefore, each of the first gate drivers 310 implemented using shift register circuitry can be connected to each of the odd-numbered and even-numbered pixel lines.

[0178] Furthermore, the second gate driver 320 to the fifth gate driver 350, implemented using an edge-triggered circuit, can be connected together to two pixel lines.

[0179] In this embodiment, the fourth gate signal EM1 and the fifth gate signal EM2 may be transmit control signals, and the first gate signal SC1, the second gate signal SC2 and the third gate signal SC3 may be scan signals.

[0180] The fifth gate driver 350, which outputs the fifth gate signal EM2 as a transmit control signal, can be arranged at the outermost position of the gate drivers. Furthermore, the second gate driver 320, which outputs the second gate signal SC2 as a scan signal, and the third gate driver 330, which outputs the third gate signal SC3, can be arranged between the fourth gate driver 340 and the fifth gate driver 350, which output the fourth gate signal EM1.

[0181] The fourth gate driver 340, which outputs the fourth gate signal EM1, can be arranged between the first gate driver 310 and the second gate driver 320, which output the first gate signal SC1 as a scan signal. However, this is not a limitation.

[0182] In the illustrated embodiment, gate drivers 340 and 350 for outputting transmit control signals and gate drivers 310, 320, and 330 for outputting scan signals are shown arranged symmetrically with respect to the display area AA. However, the embodiments of this disclosure are not limited to this. For example, gate drivers 340 and 350 for outputting transmit control signals and gate drivers 310, 320, and 330 for outputting scan signals may be arranged asymmetrically with respect to the display area AA.

[0183] Figure 6 This is a schematic diagram showing the pixel circuit. Figure 7 It shows the basis Figure 6 Waveform diagram of the driving method of the pixel circuit.

[0184] refer to Figure 6 and Figure 7 The pixel circuit may include a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, multiple switching elements M1 to M5, a first capacitor C1, and a second capacitor C2. The driving element DT and the switching elements M1, M2, M3, M4, and M5 can be implemented using n-channel transistors.

[0185] The gate signal may include a first scan pulse (or a first gate pulse SC1), a second scan pulse (or a second gate pulse SC2), a third scan pulse (or a third gate pulse SC3), a first EM pulse (or a fourth gate pulse EM1), and a second EM pulse (or a fifth gate pulse EM2).

[0186] The gate driver may include a first shift register that sequentially outputs a first scan pulse SC1, a second shift register that sequentially outputs a second scan pulse SC2, a third shift register that sequentially outputs a third scan pulse SC3, a fourth shift register that sequentially outputs a first EM pulse EM1, and a fifth shift register that sequentially outputs a second EM pulse EM2.

[0187] Constant voltages such as pixel drive voltage ELVDD, low-potential supply voltage ELVSS, reference voltage Vref, and initialization voltage Vinit can be applied to the pixel circuit. The pixel drive voltage ELVDD can be higher than the low-potential supply voltage ELVSS.

[0188] The gate turn-on voltages VGH and VEH can be set to voltages higher than the pixel drive voltage ELVDD. The gate turn-off voltages VGL and VEL can be set to voltages lower than the low-potential supply voltage ELVSS. However, this is not a limitation.

[0189] The initialization voltage Vinit can be set to a low potential voltage higher than the low-potential supply voltage ELVSS. The reference voltage Vref can be set to the voltage that turns on the drive element DT. The reference voltage Vref can be set to a voltage within the range of the data voltage Vdata output from the data driver. The maximum voltage of the data voltage Vdata can be lower than the pixel drive voltage ELVDD, and the minimum voltage of the data voltage Vdata can be higher than the low-potential supply voltage ELVSS.

[0190] To ensure that the threshold voltage Vth of the driving element DT is sampled during the sampling phase, the reference voltage Vref is preferably set to a voltage higher than the initialization voltage Vinit. The voltage difference between the reference voltage Vref and the initialization voltage Vinit can be set to a voltage greater than the threshold voltage Vth of the driving element DT. The initialization voltage Vinit can be set to a voltage lower than the threshold voltage of the light-emitting element EL in order to achieve the minimum brightness of the pixel, i.e., the brightness of the black grayscale.

[0191] The driving method for pixel circuits may include an initialization phase INIT, followed by a sampling phase SMPL, then an addressing phase WR, and finally an emission phase EMIS.

[0192] The first scan pulse SC1 can be synchronized with the pixel data data voltage Vdata and generated as the gate turn-on voltage VGH during the addressing phase WR. The first scan pulse SC1 can be the gate turn-off voltage VGL during the initialization phase INIT, the sampling phase SMPL, and the emission phase EMIS.

[0193] The second scan pulse SC2 can be generated as the gate turn-on voltage VGH during the initialization phase (INIT) and the sampling phase (SMPL). The second scan pulse SC2 can also be the gate turn-off voltage VGL during the addressing phase (WR) and the emitter phase (EMIS).

[0194] The third scan pulse SC3 can be generated as the gate turn-on voltage VGH during the initialization phase (INIT). The third scan pulse SC3 can also be the gate turn-off voltage VGL during the sampling phase (SMPL), the addressing phase (WR), and the emitter phase (EMIS).

[0195] During the initialization phase (INIT) and the addressing phase (WR), the first EM pulse EM1 can be the gate turn-off voltage (VEL). However, without limitation, the first EM pulse EM1 can be generated as the gate turn-on voltage (VEH) during the initialization phase (INIT). The first EM pulse EM1 can also be the gate turn-on voltage (VEH) during the sampling phase (SMPL) and the emit phase (EMIS).

[0196] The second scan pulse EM2 can be generated as the gate turn-on voltage VEH during the initialization phase (INIT) and the emission phase (EMIS). The second EM pulse EM2 can also be the gate turn-off voltage VEL during the sampling phase (SMPL) and the addressing phase (WR).

[0197] Each of the switching elements M1 to M5 can be turned on when gate turn-on voltages VGH and VEH are applied to its gate electrode, but can be turned off when gate turn-off voltages VGL and VEL are applied to its gate electrode. The driving element DT can be turned on when the gate-source voltage Vgs is higher than the threshold voltage Vth, so as to generate a current according to the gate-source voltage Vgs to drive the light-emitting element EL.

[0198] The light-emitting element (EL) can be implemented using an OLED. An OLED may include an organic compound layer formed between its anode and cathode electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0199] The anode of the light-emitting element EL can be connected to the fourth node n4, and the cathode can be connected to the ELVSS line to which a low potential power supply voltage ELVSS is applied.

[0200] When a voltage is applied to the anode and cathode electrodes of the light-emitting element (EL), holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) are transported to the emitter layer (EML), where excitons can be formed. In this case, light can be emitted from the EML. The light can be in the visible light spectrum.

[0201] The driving element DT may include a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD, and a third electrode connected to the third node DRS. Therefore, the voltage applied to each of the electrodes of the driving element DT may be the same as the voltage of each of the first to third nodes DRD, DRG, and DRS.

[0202] The first capacitor C1 can be connected between the second node DRG and the third node DRS. The first capacitor C1 can store the gate-source voltage Vgs of the driving element DT.

[0203] The second capacitor C2 can be connected between the third node DRS and the ELVDD line. The pixel drive voltage ELVDD can be applied to the ELVDD line.

[0204] The transmission rate of the data voltage Vdata from the gate-source voltage Vgs of the driving element DT can be determined by the capacitance ratio of the first capacitor C1 and the second capacitor C2. The capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be appropriately selected based on the voltage range of the data voltage Vdata and the driving characteristics of the display panel.

[0205] In the pixel circuit, during the emission phase of the EMIS, the gate-source voltage Vgs of the driving element DT can be Vgs = (1-C') × (Vdata - Vref) + Vth. C' can be C1 / (C1 + C2). If C2 = 0, then C' = 1, and (1-C') is 0 (zero) in the above equation, making Vgs = Vth. Therefore, a second capacitor C2 can be used to change the gate-source voltage Vgs of the driving element DT according to the pixel data voltage Vdata.

[0206] During the addressing phase WR, the first switching element M1 can be turned on according to the gate turn-on voltage VGH of the first scan pulse SC1 to provide the data voltage Vdata to the second node DRG. The first switching element M1 may include a gate electrode connected to a first gate line to which the first scan pulse SC1 is applied, a first electrode connected to a data line DL to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0207] During the initialization phase (INIT) and the sampling phase (SMPL), the second switching element M2 can be turned on according to the gate turn-on voltage VGH of the second scan pulse SC2 to provide the reference voltage Vref to the second node DRG. The second switching element M2 may include a gate electrode connected to the second gate line to which the second scan pulse SC2 is applied, a first electrode connected to the reference voltage line to which the reference voltage Vref is applied, and a second electrode connected to the second node DRG.

[0208] When the data voltage Vdata and reference voltage Vref are applied to the pixel circuit through the data line DL, the number of transitions applied to the data line DL may increase. This could lead to higher frequencies and increased power consumption in the display device.

[0209] In contrast, since this embodiment separates the data line DL to which the data voltage Vdata is applied and the reference voltage line Vref is applied, the frequency of the voltage applied to the data line DL can be reduced, thereby reducing power consumption.

[0210] During the initialization phase (INIT), the third switching element M3 can be turned on according to the gate turn-on voltage VGH of the third scan pulse SC3 to apply the initialization voltage Vinit to the third node DRS. The third switching element M3 may include a gate electrode connected to the third gate line to which the third scan pulse SC3 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the Vinit line to which the initialization voltage Vinit is applied.

[0211] During the initialization phase (INIT) and the addressing phase (WR), the fourth switching element M4 can be turned off according to the gate turn-off voltage (VEL) of the first EM pulse EM1 to block the current path between the ELVDD line, to which the pixel drive voltage ELVDD is applied, and the first node DRD. During the sampling phase (SMPL) and the emission phase (EMIS), the fourth switching element M4 can be turned on according to the gate turn-on voltage (VEH) of the first EM pulse EM1 to connect the ELVDD line to the first node DRD. The fourth switching element M4 may include a gate electrode connected to the fourth gate line to which the first EM pulse EM1 is applied, a first electrode connected to the ELVDD line, and a second electrode connected to the first node DRD.

[0212] During the sampling phase SMPL and the addressing phase WR, the fifth switching element M5 can be turned off according to the gate turn-off voltage VEL of the second EM pulse EM2 to block the current path between the third node DRS and the fourth node n4. During the initialization phase INIT and the emission phase EMIS, the fifth switching element M5 can be turned on according to the gate turn-on voltage VEH of the second EM pulse EM2 to form a current path between the driving element DT and the light-emitting element EL. The fifth switching element M5 may include a gate electrode connected to the fifth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the fourth node n4.

[0213] Figure 8 This is a view that shows the duration of the displayed duration.

[0214] refer to Figure 8 The duration of the display can include a first non-display period X1, a second non-display period X2, and an image display period X0. The first non-display period X1 can be defined as the interval from power-on to the start of the first frame (time interval). The second non-display period X2 can be defined as the interval from power-off to power-on (time interval).

[0215] The image display period X0 may include an effective interval (effective time interval) AT during which data voltage is written to sub-pixels and a vertical blanking interval (vertical blanking interval time interval) VB during which no image data is written. The compensation period may be located outside the effective interval AT. The compensation period may be part of a first non-display period X1, a second non-display period X2, or the vertical blanking interval VB. During the compensation period, the data driver may extract the threshold voltage of the driving transistor and calculate the change in the threshold voltage based on this to generate the compensation data voltage. The compensation cycle may include a programming cycle, a sensing cycle, a sampling cycle, etc.

[0216] The effective interval AT can include the Nth frame FR(N) and the (N+1)th frame FR(N+1), where N is a natural number greater than or equal to 1. The vertical blanking interval VB can be between the Nth frame FR(N) and the (N+1)th frame FR(N+1).

[0217] The display device according to the embodiment can be adjusted based on the result of the time interval between the power activation signals generated by the power control circuit sensed in the Nth frame FR(N).

[0218] Figure 9 It is a waveform diagram showing the timing signal synchronized with the image signal.

[0219] refer to Figure 9 The vertical synchronization signal Vsync defines a frame interval (1 frame). A frame (1 frame) can be the sum of the effective interval AT and the vertical blanking interval VB. The vertical blanking interval VB can be specified as a predetermined time between the effective interval AT of the Nth frame interval and the effective interval AT of the (N+1)th frame interval. The timing controller can receive the data enable signal DE and data from the input image during the effective interval AT. The data enable signal DE and the data from the input image may not be present during the vertical blanking interval VB. During the effective interval AT, the control circuitry can receive data for one frame to be written to a pixel.

[0220] The horizontal synchronization signal Hsync defines a horizontal period 1H. The data enable signal DE can be synchronized with the pixel data to be displayed on the display panel to define the effective pixel data interval. One pulse period of the data enable signal DE is a horizontal period 1H, and the high logic interval (high logic time interval) of the data enable signal DE represents the pixel data input interval (time interval) of one pixel line. A horizontal period 1H is set as the time period for writing data to the pixels in one pixel line on the display panel. Pixel lines are arranged along the gate line direction and may include pixels connected to the same gate line. Pixels in one pixel line can share a gate line to which a gate signal (or scan signal) is applied, and can be addressed simultaneously according to the scan signal to receive the data voltage of the pixel data.

[0221] As indicated by the data enable signal DE, the display device may not receive any input data during the vertical blanking interval VB. The vertical blanking interval VB may include the vertical synchronization time VS, the vertical front porch FP, and the vertical back porch BP.

[0222] Figure 10 This is a schematic diagram illustrating a pixel circuit according to a first embodiment of the present disclosure. Figure 11 This is a waveform diagram illustrating a method of driving a pixel circuit according to a first embodiment of the present disclosure. The same reference numerals are assigned to configurations performing substantially the same functions as the aforementioned pixel circuit, and repeated detailed descriptions are omitted.

[0223] refer to Figure 10 and Figure 11 The pixel circuit according to embodiments of the present disclosure may include a plurality of driving elements DT1 and DT2 to prevent or suppress threshold voltage shift and degradation of the driving elements DT during the driving time. Furthermore, the pixel circuit may include a plurality of second nodes DRG1 and DRG2 connected to the gate electrodes of each of the driving elements DT1 and DT2, a first capacitor C11 and a second capacitor C12 connected to the second nodes DRG1 and DRG2, first switching elements M11 and M12, second switching elements M21 and M22, etc.

[0224] By alternately driving each of the multiple drivers DP1 and DP2 for each frame, threshold voltage shift and degradation phenomena that occur when using a single driving element can be prevented or suppressed. For example, in the Nth frame, a pixel circuit including the first driver DP1 can be driven, and in the N+1th frame, a pixel circuit including the second driver DP2 can be driven. As a result, the load applied to the driving element can be reduced. Furthermore, threshold voltage shift phenomena in the pixel circuit can be reduced, and the operating cycle can be extended. The lifespan of the display device can be improved, while low-power operation can be achieved over a long period.

[0225] The pixel circuit according to embodiments of the present disclosure may include a plurality of driving elements DT1 and DT2, a first switching element M11 and M12, a second switching element M21 and M22, and a first capacitor C11 and a second capacitor C12.

[0226] The pixel circuit may include a first driver DP1 and a second driver DP2. The first driver DP1 may include a first driving element DT1, a first-first switching element M11, a second-first switching element M21, and a first-first capacitor C11. The second driver DP2 may include a second driving element DT2, a first-second switching element M12, a second-second switching element M22, and a first-second capacitor C12. Note that the second capacitor C2 has a first electrode connected to the ELVDD line supplied with the pixel driving voltage ELVDD and a second electrode connected to the third node DRS, and may not be included in the second driver DP2.

[0227] The Nth frame of the pixel circuit may include the Nth initialization phase INIT(N), the Nth sampling phase SMPL(N), the Nth addressing phase WR(N), and the Nth transmission phase EMIS(N). The N+1th frame of the pixel circuit may include the N+1th initialization phase INIT(N+1), the N+1th sampling phase SMPL(N+1), the N+1th addressing phase WR(N+1), and the N+1th transmission phase EMIS(N+1).

[0228] During the Nth addressing phase WR(N), the first-first switching element M11 can be turned on according to the gate turn-on voltage VGH of the first-first scan pulse SC11 to supply the data voltage Vdata to the second-first node DRG1. The first-first switching element M11 may include a gate electrode connected to the first-first gate line to which the first-first scan pulse SC11 is applied, a first electrode connected to the data line DL to which the data voltage Vdata is applied, and a second electrode connected to the second-first node DRG1.

[0229] During the Nth initialization phase INIT(N) and the Nth sampling phase SMPL(N), the second-first switching element M21 can be turned on according to the gate turn-on voltage VGH of the second-first scan pulse SC21 to provide the reference voltage Vref to the second-first node DRG1. The second-first switching element M21 may include a gate electrode connected to the second-first gate line to which the second-first scan pulse SC21 is applied, a first electrode connected to the reference voltage line to which the reference voltage Vref is applied, and a second electrode connected to the second-first node DRG1.

[0230] The first-first capacitor C11 may include a first electrode connected to the second-first node DRG1 and a second electrode connected to the third node DRS. The first-first capacitor C11 may store the gate-source voltage Vgs of the first driving element DT1.

[0231] During the N+1 addressing phase WR(N+1), the first-second switching element M12 can be turned on according to the gate turn-on voltage VGH of the first-second scan pulse SC12 to provide the data voltage Vdata to the second-second node DRG2. The first-second switching element M12 may include a gate electrode connected to the first-second gate line to which the first-second scan pulse SC12 is applied, a first electrode connected to the data line DL to which the data voltage Vdata is applied, and a second electrode connected to the second-second node DRG2.

[0232] During the N+1 initialization phase INIT(N+1) and the N+1 sampling phase SMPL(N+1), the second-second switching element M22 can be turned on according to the gate turn-on voltage VGH of the second-second scan pulse SC22 to provide the reference voltage Vref to the second-second node DRG2. The second-second switching element M22 may include a gate electrode connected to the second-second gate line to which the second-second scan pulse SC22 is applied, a first electrode connected to the reference voltage line to which the reference voltage Vref is applied, and a second electrode connected to the second-second node DRG2.

[0233] The first-second capacitor C12 may include a first electrode connected to the second-second node DRG2 and a second electrode connected to the third node DRS. The first-second capacitor C12 may store the gate-source voltage Vgs of the second driving element DT2.

[0234] Figure 12 This is a view showing the current flowing in the pixel circuit according to the first embodiment during the initialization phase of the Nth frame. Figure 13This is a view showing the current flowing in the pixel circuit according to the first embodiment during the sampling phase of the Nth frame. Figure 14 This is a view showing the current flowing in the pixel circuit according to the first embodiment during the addressing phase of the Nth frame. Figure 15 This is a view showing the current flowing in the pixel circuit according to the first embodiment during the transmission phase of the Nth frame.

[0235] refer to Figures 12 to 15 During frame N, the second driver DP2 can be turned off. For example, during frame N, the switching elements and / or driving elements included in the second driver DP2 can be turned off. For example, during frame N, the first-second switching element M12 and the second-second switching element M22, as well as the second driving element DT2, can be turned off.

[0236] refer to Figure 12 During the Nth initialization phase INIT(N), the second-first switching element M21, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 can be turned on. During the Nth initialization phase INIT(N), the first-first switching element M11 can be turned off.

[0237] During the Nth initialization phase INIT(N), the voltages of the master node are DRD = Vref + Vth1, DRG1 = Vref, and DRS = Vinit. Here, "Vth1" is the threshold voltage of the first driving element DT1. Therefore, the first driving element DT1 can be turned on because its gate-source voltage Vgs is Vref - Vinit, which is greater than the threshold voltage Vth1 during the Nth initialization phase INIT(N).

[0238] refer to Figure 13 During the Nth sampling phase SMPL(N), the second-first switching element M21 and the fourth switching element M4 can be turned on, while the other switching elements M11 and M5 can be turned off.

[0239] During the Nth sampling phase SMPL(N), when the voltage of the third node DRS rises and the gate-source voltage Vgs of the first driving element DT1 reaches the threshold voltage Vth1, the first driving element DT1 can be turned off. At the end of the Nth sampling phase SMPL(N), the voltages of the master node are DRD = ELVDD, DRG1 = Vref, and DRS = Vref - Vth1. Therefore, at the end of the Nth sampling phase SMPL(N), the gate-source voltage Vgs of the first driving element DT1 is Vgs = Vth1. The threshold voltage Vth1 of the first driving element DT1 sampled in this way can be charged to the first capacitor C11.

[0240] refer to Figure 14 During the Nth addressing phase WR(N), the first-first switching element M11 can be turned on, so the pixel data voltage Vdata can be applied to the second-first node DRG1. At this time, the other switching elements M21, M4 and M5 can be turned off.

[0241] At the end of the Nth addressing phase WR(N), the voltage of the master node can be DRD = ELVDD, DRG1 = Vdata, and DRS = Vref - Vth2 + C' × (Vdata - Vref). Where C' = C1 / (C1 + C2). During the Nth addressing phase WR(N), the gate-source voltage Vgs of the first driving element DT1 can change to Vgs = (1 - C') × (Vdata - Vref) + Vth1.

[0242] During the Nth sampling phase SMPL(N) and the Nth addressing phase WR(N), the third node DRS can be electrically isolated from the fourth node n4. As a result, the threshold voltage sampling and data addressing of the first driving element DT1 can be unaffected by the resistance of the light-emitting element EL and the process variations of the light-emitting element EL. Therefore, the brightness of the pixel is not affected by the light-emitting element EL.

[0243] refer to Figure 15 During the Nth emission phase EMIS(N), the fourth switching element M4 and the fifth switching element M5 can be turned on, while the other switching elements M11, M21 and M3 can be turned off.

[0244] During the Nth emission phase EMIS(N), the voltage of the master node can vary as DRD = ELVDD, DRG1 = Vdata, and DRS = Vref - Vth1 + C' × (Vdata - Vref). During the Nth emission phase EMIS(N), the voltage of the third node DRS can be equal to the anode voltage of the light-emitting element EL. During the Nth emission phase EMIS(N), the gate-source voltage Vgs of the first driving element DT1 is Vgs = (1 - C') × (Vdata - Vref) + Vth1.

[0245] Figure 16 This is a view showing the current flowing in the pixel circuit according to the first embodiment during the initialization phase of the N+1th frame. Figure 17 This is a view showing the current flowing in the pixel circuit according to the first embodiment during the sampling phase of the N+1th frame. Figure 18 This is a view showing the current flowing in the pixel circuit according to the first embodiment during the addressing phase of the N+1th frame. Figure 19This is a view showing the current flowing in the pixel circuit according to the first embodiment during the transmission phase of the N+1th frame.

[0246] refer to Figures 16 to 19 During frame N+1, the first driver DP1 can be turned off. For example, during frame N+1, the switching elements and / or driving elements included in the first driver DP1 can be turned off. For example, during frame N+1, the first switching element M11 and the second switching element M21, as well as the first driving element DT1, can be turned off.

[0247] refer to Figure 16 During the N+1 initialization phase INIT(N+1), the second-second switching element M22, the third switching element M3, and the fifth switching element M5 can be turned on. During the N+1 initialization phase INIT(N+1), the first switching element M12 and the fourth switching element M4 can be turned off.

[0248] During the (N+1)th initialization phase INIT(N+1), the voltages of the master node are DRD = Vref + Vth2, DRG2 = Vref, and DRS = Vinit. Here, "Vth2" is the threshold voltage of the second driving element DT2. Therefore, during the (N+1)th initialization phase INIT(N+1), since the gate-source voltage Vgs of the second driving element DT2 is greater than the threshold voltage Vth2 (Vref - Vinit), the second driving element DT2 can be turned on.

[0249] refer to Figure 17 During the N+1 sampling phase SMPL(N+1), the second-second switching element M22 and the fourth switching element M4 can be turned on, while the other switching elements M12 and M5 can be turned off.

[0250] During the N+1 sampling phase SMPL(N+1), when the voltage of the third node DRS rises and the gate-source voltage Vgs of the second driving element DT2 reaches the threshold voltage Vth2, the second driving element DT2 can be turned off. At the end of the N+1 sampling phase SMPL(N+1), the voltages of the master node are DRD = ELVDD, DRG2 = Vref, and DRS = Vref - Vth2. Therefore, at the end of the N+1 sampling phase SMPL(N+1), the gate-source voltage Vgs of the second driving element DT2 is Vgs = Vth2. The threshold voltage Vth2 of the second driving element DT2 sampled in this way can be charged to the first-second capacitor C12.

[0251] refer to Figure 18During the N+1 addressing phase WR(N+1), the first-second switching element M12 can be turned on, and thus the pixel data voltage Vdata can be applied to the second node DRG2. At this time, the other switching elements M22, M4, and M5 can be turned off.

[0252] At the end of the N+1 addressing phase WR(N+1), the voltage of the master node can be DRD = ELVDD, DRG2 = Vdata, and DRS = Vref - Vth2 + C' × (Vdata - Vref). Where C' = C1 / (C1 + C2). During the N+1 addressing phase WR(N+1), the gate-source voltage Vgs of the second driving element DT2 can change to Vgs = (1 - C') × (Vdata - Vref) + Vth2.

[0253] During the N+1 sampling phase SMPL(N+1) and the N+1 addressing phase WR(N+1), the third node DRS can be electrically isolated from the fourth node n4. As a result, the threshold voltage sampling and data addressing of the second driving element DT2 are unaffected by the resistance of the light-emitting element EL and its process variations. Therefore, the pixel brightness is not affected by the light-emitting element EL.

[0254] refer to Figure 19 In the N+1 transmission phase of EMIS (N+1), the fourth switching element M4 and the fifth switching element M5 can be turned on, while the other switching elements M12, M22 and M3 can be turned off.

[0255] During the N+1 emission phase EMIS(N+1), the voltage of the master node can vary as DRD = ELVDD, DRG2 = Vdata, and DRS = Vref - Vth2 + C' × (Vdata - Vref). During the N+1 emission phase (EMIS(N+1)), the voltage of the third node DRS can be equal to the anode voltage of the light-emitting element EL. In the N+1 emission phase EMIS(N+1), the gate-source voltage Vgs of the second driving element DT2 is Vgs = (1 - C') × (Vdata - Vref) + Vth2.

[0256] Figure 20 This is a view showing a pixel circuit according to a second embodiment of the present disclosure. Figure 21 This is a waveform diagram illustrating a method for driving a pixel circuit according to a second embodiment of the present disclosure. The same reference numerals are assigned to configurations performing substantially the same functions as the foregoing first embodiment, and repeated detailed descriptions are omitted.

[0257] refer to Figure 20 and Figure 21The pixel circuit may include a first driver DP1 and a second driver DP2. This embodiment may be a pixel circuit implemented with diode connections.

[0258] During the Nth sampling / addressing phase SMPL(N) / WR(N), the first-first switching element M11 can be turned on according to the gate turn-on voltage VGH of the first-first scan pulse SC11 to provide a data voltage Vdata to the third node DRS. The first-first switching element M11 may include a gate electrode connected to the first-first gate line to which the first-first scan pulse SC11 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the data line DL to which the data voltage Vdata is applied.

[0259] During the Nth initialization phase INIT(N) and the Nth sampling / addressing phase SMPL(N) / WR(N), the second-first switching element M21 can be turned on according to the gate turn-on voltage VGH of the second-first scan pulse SC21 to connect the gate electrode and the first electrode of the first driving element DT1. The second-first switching element M21 may include a gate electrode connected to the second-first gate line to which the second-first scan pulse SC21 is applied, a first electrode connected to the second-first node DRG1, and a second electrode connected to the first node DRD.

[0260] The first capacitor C11 can be connected between the second node DRG1 and the fourth node n4.

[0261] During the N+1 sampling / addressing phase SMPL(N+1) / WR(N+1), the first-second switching element M12 can be turned on according to the gate turn-on voltage VGH of the first-second scan pulse SC12 to provide the data voltage Vdata to the third node DRS. The first-second switching element M12 may include a gate electrode connected to the first-second gate line to which the first-second scan pulse SC12 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the data line DL to which the data voltage Vdata is applied.

[0262] During the N+1 initialization phase INIT(N+1) and the N+1 sampling / addressing phase SMPL(N+1) / WR(N+1), the second-second switching element M22 can be turned on according to the gate turn-on voltage VGH of the second-second scan pulse SC22 to connect the gate electrode of the second driving element DT2 and the first electrode. The second-second switching element M22 may include a gate electrode connected to the second-second gate line to which the second-second scan pulse SC22 is applied, a first electrode connected to the first node DRD, and a second electrode connected to the second-second node DRG2.

[0263] The first and second capacitors C12 can be connected between the second node DRG2 and the fourth node n4.

[0264] The second EM pulse EM2 can be generated as a high gate voltage VEH during the Nth initialization phase INIT(N), the Nth sampling / addressing phase SMPL(N) / WR(N), the N+1th initialization phase INIT(N+1), and the N+1th sampling / addressing phase SMPL(N+1) / WR(N+1). The second EM pulse EM2 can be generated as a low gate voltage VEL at the Nth emitter phase EMIS(N) and the N+1th emitter phase EMIS(N+1).

[0265] In this embodiment, the fifth switching element M5 can be implemented using a p-channel transistor, and the third switching element M3 can be implemented using an n-channel transistor.

[0266] When the second EM pulse EM2 is generated as a gate high voltage VEH, the fifth element M5 can be turned off and the third switching element M3 can be turned on. When the second EM pulse EM2 is generated as a gate low voltage VEL, the fifth switching element M5 can be turned on and the third switching element M3 can be turned off.

[0267] During the Nth initialization phase INIT(N), the Nth sampling / addressing phase SMPL(N) / WR(N), the N+1th initialization phase INIT(N+1), and the N+1th sampling / addressing phase SMPL(N+1) / WR(N+1), the third switching element M3 can be turned on according to the gate high voltage VEH of the second EM pulse EM2 to apply the initialization voltage Vinit to the fourth node n4. The third switching element M3 may include a gate electrode connected to the fifth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the Vinit line to which the initialization voltage Vinit is applied.

[0268] During the Nth initialization phase INIT(N), the Nth sampling / addressing phase SMPL(N) / WR(N), the N+1th initialization phase INIT(N+1), and the N+1th sampling / addressing phase SMPL(N+1) / WR(N+1), the fifth switching element M5 can be turned off according to the high gate voltage VEH of the second EM pulse EM2 to block the current path between the third node DRS and the fourth node n4. During the Nth emission phase EMIS(N) and the N+1th emission phase EMIS(N+1), the fifth switching element M5 can be turned on according to the low gate voltage VEL of the second EM pulse EM2 to form a current path between the driving elements DT1 and DT2 and the light-emitting element EL. The fifth switching element M5 may include a gate electrode connected to the fifth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the fourth node n4.

[0269] Figure 22 This is a schematic diagram of a pixel circuit according to a third embodiment of the present disclosure. Figure 23 This is a waveform diagram of a method for driving a pixel circuit according to a third embodiment of the present disclosure. The same reference numerals are assigned to configurations that perform substantially the same functions as the foregoing first embodiment, and repeated detailed descriptions are omitted.

[0270] refer to Figure 22 and Figure 23 Compared with the first embodiment described above, a fifth switching element may not be arranged between the third node DRS and the fourth node n4.

[0271] Referring to the driving method of the first embodiment described above, the third scan pulse SC3 is generated as the gate turn-on voltage VGH in the sampling phase SMPL(N), SMPL(N+1) and the addressing phase WR(N), WR(N+1), but it does not significantly affect the drivers DP1 and DP2 due to the presence of the fifth switching element.

[0272] The difference in this embodiment is that instead of arranging a fifth switching element, the third scan pulse SC3 can be generated as the gate turn-off voltage VGL during the sampling phases SMPL(N), SMPL(N+1) and the addressing phases WR(N), WR(N+1).

[0273] Figure 24 This is a schematic diagram illustrating a pixel circuit according to a fourth embodiment of the present disclosure. Figure 25 This is a waveform diagram of a method for driving a pixel circuit according to a fourth embodiment of the present disclosure. The same reference numerals are assigned to configurations that perform substantially the same functions as the foregoing first embodiment, and repeated detailed descriptions are omitted.

[0274] refer to Figure 24 and Figure 25 The fourth switching element M4 can be implemented using a p-channel transistor. The difference between the behavior of a p-channel transistor and that of an n-channel transistor is that a low gate voltage is the gate turn-on voltage, and a high gate voltage is the gate turn-off voltage.

[0275] In one embodiment, the first EM pulse EM1 can be the gate turn-on voltage VEL during the initialization phases INIT(N), INIT(N+1), the sampling phases SMPL(N), SMPL(N+1), and the emit phases EMIS(N), EMIS(N+1). The first EM pulse EM1 can also be the gate turn-off voltage VEH at the addressing phases WR(N), WR(N+1).

[0276] Figure 26 This is a schematic diagram of a pixel circuit according to a fifth embodiment of the present disclosure. Figure 27 This is a waveform diagram of a method for driving a pixel circuit according to a fifth embodiment of the present disclosure. The same reference numerals are assigned to configurations that perform substantially the same functions as the foregoing first embodiment, and repeated detailed descriptions are omitted.

[0277] refer to Figure 26 and Figure 27 The fourth switching element M4 can be implemented using a p-channel transistor. The difference between the behavior of a p-channel transistor and that of an n-channel transistor is that a low gate voltage is the gate turn-on voltage, and a high gate voltage is the gate turn-off voltage.

[0278] In one embodiment, during the initialization phases INIT(N), INIT(N+1) and the addressing phases WR(N), WR(N+1), the first EM pulse EM1 may be a gate high voltage VEH. During the sampling phases SMPL(N), SMPL(N+1) and the emission phases EMIS(N), EMIS(N+1), the first EM pulse EM1 may be a gate low voltage VEL.

[0279] In this embodiment, the third switching elements M31 and M32 may include a third-first switching element M31 that provides a reference voltage Vref to the second capacitor C2 and a third-second switching element M32 that provides an anode reset voltage VAR to the fourth node n4.

[0280] The third-first switching element M31 may include a gate electrode to which a third scan pulse SC3 is applied, a first electrode connected to a second capacitor C2, and a second electrode connected to a reference voltage line to which a reference voltage Vref is applied.

[0281] The third-second switching element M32 may include a gate electrode to which a first EM pulse EM1 is applied, a first electrode connected to a fourth node n4, and a second electrode connected to a VAR line to which an anode reset voltage VAR is applied.

[0282] During the initialization phases INIT(N), INIT(N+1) and the addressing phases WR(N), WR(N+1), the gate high voltage VEH can turn off the fourth switching element M4 and turn on the third-second switching element M32. When the third-second switching element M32 is turned on, the anode reset voltage VAR can be applied to the third node DRS.

[0283] During the sampling phase SMPL(N), SMPL(N+1) and the emission phase EMIS(N), EMIS(N+1), the fourth switching element M4 can be turned on and the third-second switching element M32 can be turned off by the low gate voltage VEL.

[0284] During the sampling phases SMPL(N) and SMPL(N+1), the third scan pulse SC3 can be the gate turn-on voltage VGH, thus turning on the third-first switching element M31. The reference voltage Vref can be provided to the third node DRS. When the voltage of the third node DRS rises and the gate-source voltage Vgs of the driving elements DT1 and DT2 reach the threshold voltages Vth1 and Vth2, the driving elements DT1 and DT2 can be turned off. The sampled threshold voltages Vth1 and Vth2 of the driving elements DT1 and DT2 can charge the first capacitor C11 and the second capacitor C12.

[0285] During the emission phases EMIS(N) and EMIS(N+1), the second EM pulse EM2 can be the gate turn-on voltage VEH, so the fifth switching element M5 can be turned on.

[0286] Although various exemplary embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and various modifications can be made without departing from the technical concept of the present disclosure.

[0287] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but are merely illustrative by way of example, and the scope of the technical concept of this disclosure is not limited to these embodiments.

[0288] Therefore, it should be understood that the above embodiments are illustrative and not limiting in all respects.

[0289] The scope of protection of this disclosure shall be interpreted according to the claims and their equivalents, and all technical ideas within the scope of their equivalents shall be understood to be included within the scope of this disclosure.

Claims

1. A pixel circuit comprising: a first node connected to a drive voltage line configured to receive a first constant voltage; a third node connected to a fourth node connected to a light emitting element; a first driver comprising a first drive element; and a second driver comprising a second drive element, wherein the first driver and the second driver are alternately driven for each frame.

2. The pixel circuit according to claim 1, wherein: the second driver is configured to be turned off in an Nth frame, the first driver is configured to be turned off in an N+1th frame, N is a natural number greater than or equal to 1, the Nth frame includes a time interval in which the first drive element is turned on, and the N+1th frame includes a time interval in which the second drive element is turned on. the first drive element comprises a gate electrode connected to a second-first node, a first electrode connected to the first node, and a second electrode connected to the third node; and 3. The pixel circuit of claim 1, wherein, the second drive element comprises a gate electrode connected to a second-second node, a first electrode connected to the first node, and a second electrode connected to the third node.

4. The pixel circuit according to claim 3, wherein: the first driver further comprises a first-first switching element configured to comprise a gate electrode connected to a first-first gate line configured to receive a first-first scan pulse, a first electrode connected to a data line configured to receive a data voltage, and a second electrode connected to the second-first node, and the second driver further comprises a first-second switching element configured to comprise a gate electrode connected to a first-second gate line configured to receive a first-second scan pulse, a first electrode connected to the data line, and a second electrode connected to the second-second node.

5. The pixel circuit according to claim 4, wherein: the second driver is turned off in an Nth frame, the first driver is turned off in an N+1th frame, N is a natural number greater than or equal to 1, the Nth frame includes a time interval in which the first-first switching element is turned on, and the N+1th frame includes a time interval in which the first-second switching element is turned on.

6. The pixel circuit according to claim 3, wherein: the first driver further comprises a second-first switching element configured to comprise a gate electrode connected to a second-first gate line configured to receive a second-first scan pulse, a first electrode connected to a reference voltage line configured to receive a second constant voltage, and a second electrode connected to the second-first node; and the second driver further comprises a second-second switching element configured to comprise a gate electrode connected to a second-second gate line configured to receive a second-second scan pulse, a first electrode connected to the reference voltage line, and a second electrode connected to the second-second node. ​ ​ The second driver further includes a second-second switching element configured to include a gate electrode connected to a second-second gate line configured to receive a second-second scan pulse, a first electrode connected to the reference voltage line, and a second electrode connected to the second-second node.

7. The pixel circuit according to claim 6, wherein: the second driver is turned off in an Nth frame, the first driver is turned off in an N+lth frame, N is a natural number greater than or equal to 1, the Nth frame includes a time interval in which the second-first switching element is turned on, and the N+lth frame includes a time interval in which the second-second switching element is turned on.

8. The pixel circuit of claim 3, wherein, the first driver further includes a first-first capacitor configured to include a first electrode connected to the second-first node and a second electrode connected to the third node; and the second driver further includes a first-second capacitor configured to include a first electrode connected to the second-second node and a second electrode connected to the third node. the first driver further includes:

9. The pixel circuit of claim 3, wherein, a first-first switching element configured to include a gate electrode connected to a first-first gate line configured to receive a first-first scan pulse, a first electrode connected to a data line configured to receive a data voltage, and a second electrode connected to the second-first node; and a second-first switching element configured to include a gate electrode connected to a second-first gate line configured to receive a second-first scan pulse, a first electrode connected to a reference voltage line configured to receive a second constant voltage, and a second electrode connected to the second-first node. the second driver further includes:

10. The pixel circuit of claim 3, wherein, a first-second switching element configured to include a gate electrode connected to a first-second gate line configured to receive a first-second scan pulse, a first electrode connected to a data line configured to receive a data voltage, and a second electrode connected to the second-second node; and a second-second switching element configured to include a gate electrode connected to a second-second gate line configured to receive a second-second scan pulse, a first electrode connected to a reference voltage line configured to receive a second constant voltage, and a second electrode connected to the second-second node. the pixel circuit further includes:

11. The pixel circuit of claim 1, wherein, a third switching element configured to include a gate electrode connected to a third gate line configured to receive a third scan pulse, a first electrode connected to the fourth node, and a second electrode configured to receive a third constant voltage; and a fourth switching element arranged between the drive voltage line and the first node. ​ 12. The pixel circuit of claim 11, wherein, The fourth switching element includes: a gate electrode connected to a fourth gate line configured to receive a first EM pulse, 13. The pixel circuit of claim 11, wherein, a first electrode connected to the drive voltage line, and a second electrode connected to the first node.

14. The pixel circuit of claim 13, wherein, The pixel circuit further includes: a fifth switching element arranged between the third node and the fourth node. The fifth switching element includes: a gate electrode connected to a fifth gate line configured to receive a second EM pulse, a first electrode connected to the third node, and a second electrode connected to the fourth node.

15. A display device comprising: a display panel including a plurality of data lines, a plurality of gate lines intersecting the data lines, a plurality of power supply lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power supply lines; a data driver configured to supply a data voltage of pixel data to the data lines; and a gate driver configured to supply a gate signal to the gate lines, wherein each of the plurality of pixel circuits includes: a first node connected to a drive voltage line configured to receive a first constant voltage; a third node connected to a fourth node connected to a light emitting element; a first driver including a first drive element; and a second driver including a second drive element, and wherein the first driver and the second driver are alternately driven for each frame.

16. The display device according to claim 15, wherein:

17. The display device of claim 15, wherein, the second driver is turned off in an Nth frame, the first driver is turned off in an N+1th frame, N is a natural number greater than or equal to 1, 18. The display device of claim 17, wherein, the Nth frame includes a time interval in which the first drive element is turned on, and the N+1th frame includes a time interval in which the second drive element is turned on. The first drive element includes: a gate electrode connected to a second-first node, a first electrode connected to the first node, and a second electrode connected to the third node; and The second drive element includes: a gate electrode connected to a second-second node, a first electrode connected to the first node, and a second electrode connected to the third node. The first driver further includes a first-first switching element configured to include: a gate electrode connected to a first-first gate line configured to receive a first-first scan pulse, a first electrode connected to a data line configured to receive a data voltage, and a second electrode connected to the second-first node, and The second driver further includes a first-second switching element configured to include: a gate electrode connected to a first-second gate line configured to receive a first-second scan pulse, a first electrode connected to the data line, and a second electrode connected to the second-second node.

19. The display device according to claim 17, wherein: The first driver further includes a second-first switching element configured to include a gate electrode connected to a second-first gate line configured to receive a second-first scan pulse, a first electrode connected to a reference voltage line configured to receive a second constant voltage, and a second electrode connected to the second-first node, and The second driver further includes a second-second switching element configured to include a gate electrode connected to a second-second gate line configured to receive a second-second scan pulse, a first electrode connected to the reference voltage line to which the second constant voltage is applied, and a second electrode connected to the second-second node. 20.The display apparatus according to claim 17, wherein: The first driver further includes a first-first capacitor configured to include a first electrode connected to the second-first node and a second electrode connected to the third node; and The second driver further includes a first-second capacitor configured to include a first electrode connected to the second-second node and a second electrode connected to the third node. ​

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