Pixel circuit, display device including same, and electronic device

Abstract

The invention discloses a pixel circuit, a display device comprising the pixel circuit and an electronic device. The pixel circuit includes: a light emitting element; a first transistor connected between the first node and the light emitting element, and including a control terminal connected to a second node; a second transistor connected between a corresponding data line among the data lines and the first node, and including a control terminal connected to a first scan signal line among the scan signal lines; a third transistor connected between the second node and a first initialization voltage line, and including a control terminal connected to a first initialization signal line among the initialization signal lines; and a fourth transistor connected between the first node and the bias voltage line, and including a control terminal connected to a second initialization signal line among the initialization signal lines. The second initialization signal line is connected to a control terminal of a third transistor of another pixel circuit connected to the first initialization voltage line.

Description

Technical Field

[0001] Embodiments of this disclosure relate to pixel circuits, display devices including the pixel circuits, and electronic devices. Background Technology

[0002] The display device displays images based on input image data received from the main processor (e.g., a graphics processing unit or graphics card). The rendering frequency of the main processor providing the input image data may not match the operating frequency of the display device. This frequency mismatch can cause tearing as visible boundaries in the image displayed on the display device. To prevent tearing, the display device can operate in a variable frequency mode to synchronize the rendering frequency of the main processor with the operating frequency of the display device. Summary of the Invention

[0003] In a display device operating in a variable frequency mode, the brightness of its display panel may vary due to changes in the frame rate, and these changes in brightness may cause flickering.

[0004] The embodiments aim to provide a pixel circuit that can prevent flickering in a display device operating in a variable frequency mode while improving the integration of the display panel, and a display device including the pixel circuit.

[0005] According to an embodiment, the pixel circuit of a display panel including multiple pixel circuits includes: a light-emitting element; a first transistor connected between a first node and the light-emitting element, and including a control terminal connected to a second node; a second transistor connected between a corresponding data line among multiple data lines and the first node, and including a control terminal connected to a first scan signal line among multiple scan signal lines connected to the multiple pixel circuits; a third transistor connected between the second node and a first initialization voltage line transmitting a first initialization voltage, and including a control terminal connected to the first initialization signal line among multiple initialization signal lines connected to the multiple pixel circuits; and a fourth transistor connected between the first node and a bias voltage line transmitting a bias voltage, and including a control terminal connected to a second initialization signal line among the multiple initialization signal lines, different from the first initialization signal line. In such an embodiment, the second initialization signal line is connected to the control terminal of the third transistor of another pixel circuit that is connected to the first initialization voltage line.

[0006] In one embodiment, the other pixel circuit may be connected to a second scan signal line, which is different from the first scan signal line, among a plurality of scan signal lines.

[0007] In an embodiment, the pixel circuit may further include: a fifth transistor connected between the second node and the third transistor, and including a control terminal connected to a corresponding compensation signal line among a plurality of compensation signal lines connected to the plurality of pixel circuits; and a sixth transistor connected between the first transistor and the third transistor, and including a control terminal connected to a corresponding compensation signal line.

[0008] In one embodiment, the pixel circuit may further include a seventh transistor connected between the fifth and third transistors, and includes a control terminal connected to a corresponding compensation signal line. In such an embodiment, a sixth transistor may be connected to the node between the fifth and seventh transistors.

[0009] In one embodiment, the pixel circuit may further include a seventh transistor connected between the fifth and third transistors, and includes a control terminal connected to a corresponding compensation signal line. In such an embodiment, a sixth transistor may be connected to the node between the third and seventh transistors.

[0010] In an embodiment, the fifth and sixth transistors can be turned on during one of the multiple frame periods in which an image is displayed, and can be turned off during the remaining frame periods in the multiple frame periods.

[0011] In one embodiment, the pixel circuit may further include: a fifth transistor connected between the second node and the third transistor, and including a control terminal connected to a corresponding first compensation signal line among a plurality of first compensation signal lines connected to the plurality of pixel circuits; and a sixth transistor connected between the first transistor and the third transistor, and including a control terminal connected to a corresponding second compensation signal line among a plurality of second compensation signal lines connected to the plurality of pixel circuits. In such an embodiment, the fifth transistor may be an N-type transistor, and the sixth transistor may be a P-type transistor. In such an embodiment, the level of the signal applied to the corresponding first compensation signal line and the level of the signal applied to the corresponding second compensation signal line are opposite to each other.

[0012] In this embodiment, the first to fourth transistors may be P-type transistors.

[0013] In an embodiment, the pixel circuit may further include: a fifth transistor connected between a first terminal of the light-emitting element and a second initialization voltage line that transmits a second initialization voltage, and including a control terminal connected to the second initialization signal line.

[0014] In an embodiment, the pixel circuit may further include: a holding capacitor connected between a first power line transmitting a first power supply voltage and a first node.

[0015] In an embodiment, the pixel circuit may further include: a fifth transistor connected between the second node and the third transistor, and a control terminal connected to the first initialization signal line.

[0016] In an embodiment, the pixel circuit may further include: a fifth transistor connected between a first power line transmitting a first power supply voltage and a first node, and including a control terminal connected to a corresponding light-emitting control line among a plurality of light-emitting control lines connected to a plurality of pixel circuits; and a sixth transistor connected between the first transistor and the light-emitting element, and including a control terminal connected to a corresponding light-emitting control line.

[0017] A display device according to an embodiment includes: a display panel including a plurality of pixels connected to a plurality of scan signal lines, a plurality of initialization signal lines, and a plurality of data lines; a scan driver connected to the plurality of scan signal lines, wherein the scan driver provides a plurality of scan signals to the plurality of pixels; an initialization driver connected to the plurality of initialization signal lines, wherein the initialization driver provides a plurality of initialization signals to the plurality of pixels; and a data driver connected to the plurality of data lines, wherein the data driver provides a plurality of data signals to the plurality of pixels. In such an embodiment, a first pixel among the plurality of pixels includes: a light-emitting element; a first transistor connected between a first node and the light-emitting element, and including a control terminal connected to a second node; a second transistor connected between a corresponding data line among the plurality of data lines and the first node, and including a control terminal connected to a first scan signal line among the plurality of scan signal lines; a third transistor connected between the second node and a first initialization voltage line transmitting a first initialization voltage, and including a control terminal connected to the first initialization signal line among the plurality of initialization signal lines; and a fourth transistor connected between the first node and a bias voltage line transmitting a bias voltage, and including a control terminal connected to a second initialization signal line among the plurality of initialization signal lines that is different from the first initialization signal line. In such an embodiment, the second initialization signal line is connected to the control terminal of the third transistor of the second pixel, which is connected to the first initialization voltage line. In such an embodiment, the second pixel is connected to a second scan signal line, which is different from the first scan signal line, among a plurality of scan signal lines.

[0018] In an embodiment, the first pixel may further include: a fifth transistor connected between the second node and the third transistor, and including a control terminal connected to a corresponding compensation signal line among a plurality of compensation signal lines; and a sixth transistor connected between the first transistor and the third transistor, and including a control terminal connected to a corresponding compensation signal line.

[0019] In one embodiment, the fifth and sixth transistors can be turned on during one of the multiple frame periods in which an image is displayed, and are turned off during the remaining frame periods in the multiple frame periods.

[0020] In an embodiment, the first pixel may further include: a fifth transistor connected between a first terminal of the light-emitting element and a second initialization voltage line that transmits a second initialization voltage, and includes a control terminal connected to the second initialization signal line.

[0021] In an embodiment, the first pixel may further include: a fifth transistor connected between a first power line transmitting a first power supply voltage and a first node, and including a control terminal connected to a corresponding light-emitting control line among a plurality of light-emitting control lines connected to a plurality of pixels; and a sixth transistor connected between the first transistor and a light-emitting element, and including a control terminal connected to a corresponding light-emitting control line.

[0022] According to embodiments of this disclosure, flickering in a display device operating in a variable frequency mode can be effectively prevented while improving the integration of the display panel. Attached Figure Description

[0023] Figure 1 This is a block diagram schematically illustrating a display device according to an embodiment.

[0024] Figure 2 This is a pixel circuit diagram of the pixel according to an embodiment.

[0025] Figure 3 It is a diagram. Figure 2 A pixel circuit diagram of an embodiment where the pixel circuits share an initialization signal line.

[0026] Figure 4 yes Figure 3 A planar image of pixels.

[0027] Figure 5 It is a signal timing diagram used to describe the operation of pixels according to an embodiment.

[0028] Figure 6 It is a signal timing diagram used to describe the operation of pixels according to an embodiment.

[0029] Figure 7 This is a pixel circuit diagram used to describe the operation of a pixel circuit in a variable frequency mode according to an embodiment.

[0030] Figure 8 This is a pixel circuit diagram of a pixel according to another embodiment.

[0031] Figure 9This is a pixel circuit diagram of a pixel according to another embodiment.

[0032] Figure 10 This is a pixel circuit diagram of a pixel according to another embodiment.

[0033] Figure 11 This is a pixel circuit diagram of a pixel according to another embodiment.

[0034] Figure 12 This is a pixel circuit diagram of a pixel according to another embodiment.

[0035] Figure 13 It is used to describe Figure 12 The signal timing diagram for the operation of the pixel circuit.

[0036] Figure 14 This is a block diagram of an electronic device according to some embodiments.

[0037] Figure 15 Schematic diagrams of electronic devices according to various embodiments are shown. Detailed Implementation

[0038] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0039] For clarity of this disclosure, parts irrelevant to the description have been omitted, and throughout the specification, the same reference numerals are used for the same or similar parts.

[0040] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings herein.

[0041] Furthermore, for better understanding and ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated, and this disclosure is not necessarily limited to those illustrated. Thicknesses may be enlarged in the drawings to clearly show multiple layers and regions. Additionally, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0042] It will be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, reference to “a” element followed by reference to “the” element in the claims includes one element and multiple elements. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” is not to be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or variations thereof, or “including” and / or variations thereof, when used in this specification, indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0044] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to also cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” of the other elements will be oriented to be “up” of the other elements. Thus, depending on the specific orientation of the drawing, the term “down” can cover both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will be oriented to be “above” the other elements. Thus, the terms “below” or “under” can cover both “up” and “down” orientations.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0046] Embodiments are described herein with reference to schematic diagrams of preferred embodiments. Therefore, variations in the illustrated shapes will be expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape, for example, resulting from manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of this disclosure.

[0047] Figure 1 This is a block diagram schematically illustrating a display device according to an embodiment.

[0048] refer to Figure 1 The display device 1 according to the embodiment may include a display panel 10, a gate driver 20, a data driver 30, a light-emitting driver 40, a power supply 50, and a signal controller 60.

[0049] The display panel 10 may include multiple pixels PX and multiple signal lines for applying electrical signals to the multiple pixels PX.

[0050] Signal lines for applying electrical signals to multiple pixels PX may include a first direction ( Figure 1 Multiple gate signal lines GWL1, GWL2 to GWL (extending in the horizontal / row direction) n GCL1, GCL2 to GCL n and GIL0, GIL1, GIL2 to GIL n-1 and GIL n and multiple light-emitting control signal lines EML1, EML2 to EML n And in the second direction ( Figure 1 Multiple data signal lines DL1, DL2 to DL3 extending in the vertical / column direction (in the middle) m (Also known as data lines). Here, n and m are natural numbers greater than 1. Multiple gate signal lines GWL1 to GWL n GCL1 to GCL n and GIL0 to GIL n They can be arranged separately along the second direction, and the gate signal can be transmitted to the pixel PX. Multiple data signal lines DL1 to DL m They can be arranged separately from each other along the first direction, and data signals can be transmitted to the pixel PX.

[0051] Multiple pixels (PX) can be arranged repeatedly in both the first and second directions. The multiple pixels (PX) can be arranged in various forms, such as stripe arrangement, pentile arrangement, and mosaic arrangement. The multiple pixels (PX) can be individually connected to multiple gate signal lines GWL1 to GWL. n GCL1 to GCL n and GIL0 to GIL n The corresponding gate signal line and multiple light emission control signal lines EML1 to EML n The corresponding light emission control signal line and multiple data signal lines DL1 to DL m The corresponding data signal lines. In the embodiment, although not in Figure 1 The display panel 10 is illustrated, but each of the multiple pixels PX can be connected to a power supply line and supplied with a first power supply voltage ELVDD, a second power supply voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, or a bias voltage Vbias, etc.

[0052] In an embodiment, each of the plurality of pixels PX may include an organic light-emitting diode (OLED) as a light-emitting element (or display element). Each OLED may be supplied with a drive current corresponding to a data signal transmitted through a corresponding data signal line. Each OLED may emit light of a specific brightness corresponding to the drive current supplied to it to generate an image.

[0053] The gate driver 20 can be connected to multiple gate signal lines. The gate driver 20 can generate gate signals based on a first control signal CONT1 received from the signal controller 60. The gate driver 20 can sequentially supply the generated gate signals to each pixel PX via the gate signal lines. Each gate signal line can be connected to the gate of a transistor in the corresponding pixel PX. The gate signal can have an on-state voltage level that can turn on the transistor connected to the corresponding gate signal line and an off-state voltage level that can turn off the transistor. The on-state voltage can be a high-level voltage, and the off-state voltage can be a low-level voltage. Alternatively, the on-state voltage can be a low-level voltage, and the off-state voltage can be a high-level voltage. Depending on the operation performed by the transistor receiving the gate signal in each pixel PX of the display panel 10, the duration for which the on-state voltage and the duration for which the off-state voltage of each gate signal are maintained can be different.

[0054] Multiple gate signal lines can include multiple scan signal lines GWL1 to GWL n Multiple compensation signal lines GCL1 to GCL n and multiple initialization signal lines GIL0 to GIL nThe gate signal supplied to each pixel PX by the gate driver 20 may include a scan signal, a compensation signal, and an initialization signal. The gate driver 20 may include a scan driver 21 that supplies the scan signal to each pixel PX, a compensation driver 22 that supplies the compensation signal to each pixel PX, and an initialization driver 23 that supplies the initialization signal to each pixel PX. The scan driver 21 may be connected to multiple scan signal lines GWL1 to GWL2. n Furthermore, it can output multiple scan signals to multiple scan signal lines GWL1 to GWL n The compensation driver 22 can be connected to multiple compensation signal lines GCL1 to GCL2. n Furthermore, multiple compensation signals can be output to multiple compensation signal lines GCL1 to GCL2. n The initialization driver 23 can be connected to multiple initialization signal lines GIL0 to GIL1. n Furthermore, multiple initialization signals can be output to multiple initialization signal lines GIL0 to GIL0. n .

[0055] The scan driver 21, compensation driver 22, and initialization driver 23 may each include multiple stages that sequentially generate and output corresponding gate signals. In an embodiment, for example, the scan driver 21 may include multiple stages that sequentially generate and output corresponding scan signals, the compensation driver 22 may include multiple stages that sequentially generate and output corresponding compensation signals, and the initialization driver 23 may include multiple stages that sequentially generate and output corresponding initialization signals.

[0056] Multiple stages included in each of the scan driver 21, compensation driver 22, and initialization driver 23 can be connected to each other in a subordinate manner (e.g., cascaded). In an embodiment, for example, a stage in the multiple stages included in scan driver 21 connected to scan signal line GWL1 can be connected to the next stage connected to scan signal line GWL2. In the multiple stages included in each of the scan driver 21, compensation driver 22, and initialization driver 23, the first stage begins operation via a vertical start signal transmitted from signal controller 60, and subsequent stages begin operation via the output of the preceding stage, such that these stages can operate sequentially. When each stage begins driving, a gate signal can be output to the corresponding gate signal line.

[0057] In some embodiments, the display device 1 can operate in a variable frequency mode. In the variable frequency mode, the display device 1 can display an image based on an image data display over multiple frame periods. During at least one frame period when the display device 1 operates in the variable frequency mode, the compensation driver 22 can stop generating multiple compensation signals.

[0058] The gate driver 20 can be implemented on the same substrate as the display panel 10 (or integrally formed).

[0059] Data driver 30 can be connected to multiple data signal lines DL1 to DL2. m The data driver 30 can receive an image data signal DATA with grayscale (including grayscale information) from the signal controller 60. The data driver 30 converts the received image data signal DATA into a voltage or current format to generate a data signal (or data voltage), and can generate a data signal corresponding to each pixel PX. The data driver 30 can generate the data signal based on a second control signal CONT2 received from the signal controller 60. The data driver 30 can connect to the data signal line DL1 via DL... m The generated data signal is supplied to each pixel PX. When supplying the data signal, the data driver 30 can synchronize with the gate signal output from the gate driver 20 to supply the data signal to each pixel PX.

[0060] The LED driver 40 can be connected to multiple LED control signal lines EML1 to EML2. n The LED driver 40 can generate an LED control signal based on the third control signal CONT3 received from the signal controller 60. The LED driver 40 can connect multiple LED control signal lines EML1 to EML2. n The generated light emission control signal is supplied to each pixel PX. The light emission control signal can be transmitted to the light emission control transistor of each pixel PX via the corresponding light emission control signal line. The light emission control transistor can control the light emission element of the corresponding pixel PX to emit light in response to the received light emission control signal. Based on the control of the light emission control transistor, the light emission element can emit or not emit light with a brightness corresponding to the data signal.

[0061] Power supply 50 can supply a first power supply voltage ELVDD, a second power supply voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, or a bias voltage Vbias to each pixel PX of display panel 10. The first power supply voltage ELVDD can have a higher voltage level than the second power supply voltage ELVSS. The voltage supplied from power supply 50 is not particularly limited, but the voltage value can be set or controlled according to the fourth control signal CONT4 transmitted from signal controller 60.

[0062] The signal controller 60 can convert externally received input image data into an image data signal DATA and transmit the image data signal DATA to the data driver 30. The signal controller 60 can generate control signals CONT1, CONT2, and CONT3 based on externally received synchronization signals or clock signals. That is, the signal controller 60 can generate a first control signal CONT1 for controlling the operation of the gate driver 20, a second control signal CONT2 for controlling the operation of the data driver 30, and a third control signal CONT3 for controlling the operation of the light-emitting driver 40. The signal controller 60 can transmit the generated control signals CONT1, CONT2, and CONT3 to the gate driver 20, the data driver 30, and the light-emitting driver 40, respectively. The signal controller 60 can generate a fourth control signal (or power control signal) CONT4 for controlling the drive of the power supply 50 and transmit the fourth control signal CONT4 to the power supply 50.

[0063] The display device 1 according to the embodiment can be implemented as an electronic device such as a mobile phone, smartphone, laptop computer, smartwatch, navigation device, game console, television (TV), vehicle head unit, tablet computer, personal media player (PMP), and personal digital assistant (PDA).

[0064] In the following text, reference will be made to Figures 2 to 7 Description includes Figure 1 An embodiment of the pixel circuit and driving method for each pixel PX in the display panel 10.

[0065] Figure 2 This is a pixel circuit diagram of the pixel according to an embodiment.

[0066] refer to Figure 2 Each pixel PX in the display panel 10 of the display device 1 according to the embodiment may include a plurality of transistors T1, T2, T3-1, T3-2, T4, T5, T6, T7 and T8, a storage capacitor Cst, and a light-emitting element EE. Hereinafter, the plurality of transistors T1, T2, T3-1, T3-2, T4, T5, T6, T7 and T8 may be referred to as driving transistor T1, switching transistor T2, compensation transistors T3-1 and T3-2, initialization transistor T4, operation control transistor T5, light-emitting control transistor T6, light-emitting element initialization transistor T7, and bias transistor T8, respectively.

[0067] In an embodiment, pixel PX can be connected to multiple signal lines. The signal lines connected to pixel PX may include a scan signal line 101 for transmitting a scan signal GW[i], a first initialization signal line 102 for transmitting a first initialization signal GI[i], a second initialization signal line 103 for transmitting a second initialization signal GI[i-1], and a compensation signal line 110 for transmitting a compensation signal GC[i]. The scan signal line 101, the first initialization signal line 102, the second initialization signal line 103, and the compensation signal line 110 can be connected to... Figure 1 The gate signal lines of the gate driver 20. That is, the scan signal GW[i], the first initialization signal GI[i], the second initialization signal GI[i-1], and the compensation signal GC[i] can be gate signals output from the gate driver 20.

[0068] The signal line connected to the pixel PX can further include transmission from Figure 1 The data signal line 105 for the data signal D[j] output by the data driver 30, the light emission control signal line 104 (also called the light emission control line) for transmitting the light emission control signal EM[i] output from the light emission driver 40, the first power supply line 106 and the second power supply line 107 for transmitting the first power supply voltage ELVDD and the second power supply voltage ELVSS respectively, the first initialization voltage line 108 and the second initialization voltage line 109 for transmitting the first initialization voltage Vint and the second initialization voltage Vaint respectively, and the bias voltage line 111 for transmitting the bias voltage Vbias.

[0069] The driving transistor T1 may include a first terminal connected to the first node N1, a second terminal connected to the third node N3, and a control terminal connected to the second node N2. The first node N1 may be connected to the first power supply line 106 supplying the first power supply voltage ELVDD via the operation control transistor T5. The first node N1 may be connected to the data signal line 105 transmitting the data signal D[j] via the switching transistor T2. The second node N2 may be connected to the second terminal of the storage capacitor Cst. The first node N1 may be connected to the bias voltage line 111 transmitting the bias voltage Vbias via the bias transistor T8. The second node N2 may also be connected to the first initialization voltage line 108 transmitting the first initialization voltage Vint via the first compensation transistor T3-1 and the initialization transistor T4. The second node N2 may also be connected to the third node N3 via the first compensation transistor T3-1 and the second compensation transistor T3-2. The third node N3 may be connected to the anode terminal (also referred to as the first terminal) of the light-emitting element EE via the light-emitting control transistor T6. The driving transistor T1 can provide a driving current corresponding to the data signal D[j] to the light-emitting element EE.

[0070] The switching transistor T2 may include a first terminal connected to the data signal line 105 for transmitting the data signal D[j], a second terminal connected to the first node N1, and a control terminal connected to the scan signal line 101 for transmitting the scan signal GW[i]. The switching transistor T2 can be turned on in response to the scan signal GW[i] received through the scan signal line 101. When the switching transistor T2 is turned on, it can transmit the data signal D[j] transmitted through the data signal line 105 to the first node N1 (i.e., the first terminal of the driving transistor T1).

[0071] The first compensation transistor T3-1 may include a first terminal connected to the second node N2, a second terminal connected to the fifth node N5, and a control terminal connected to the compensation signal line 110 for transmitting the compensation signal GC[i]. The second compensation transistor T3-2 may include a first terminal connected to the fifth node N5, a second terminal connected to the third node N3, and a control terminal connected to the compensation signal line 110 for transmitting the compensation signal GC[i]. The first compensation transistor T3-1 and the second compensation transistor T3-2 can be turned on in response to the compensation signal GC[i] received through the compensation signal line 110. When the first compensation transistor T3-1 and the second compensation transistor T3-2 are turned on, the driving transistor T1 can be diode-connected by connecting the second node N2 and the third node N3 (i.e., the control terminal and the second terminal of the driving transistor T1) to each other. Through the diode connection of the driving transistor T1, the data voltage after threshold voltage compensation of the driving transistor T1 can be written to the storage capacitor Cst for the data signal D[j].

[0072] The initialization transistor T4 may include a first terminal connected to the fifth node N5, a second terminal connected to the first initialization voltage line 108 for transmitting the first initialization voltage Vint, and a control terminal connected to the first initialization signal line 102 for transmitting the first initialization signal GI[i]. The fifth node N5 may be connected to the second node N2 via the first compensation transistor T3-1. The initialization transistor T4 may be turned on in response to the first initialization signal GI[i] received via the first initialization signal line 102. When the initialization transistor T4 is turned on, it can transmit the first initialization voltage Vint to the second node N2. That is, when the initialization transistor T4 is turned on at the same time as the first compensation transistor T3-1 is turned on, the first initialization voltage Vint can be transmitted to the second node N2 through the initialization transistor T4 and the first compensation transistor T3-1. When the first initialization voltage Vint is transmitted to the second node N2, the control terminal voltage of the driving transistor T1 and the voltage of the storage capacitor Cst can be initialized by the first initialization voltage Vint. The first initialization voltage Vint may have a voltage level lower than the voltage level of the data signal D[j]. When the display panel 10 operates at a low driving frequency, if the first initialization voltage Vint supplied to the second node N2 is too low, the hysteresis of the driving transistor T1 may become severe, causing flickering. Therefore, the first initialization voltage Vint can have a voltage level higher than the voltage level of the second power supply voltage ELVSS.

[0073] The operational control transistor T5 may include a first terminal connected to a first power supply line 106 supplying the first power supply voltage ELVDD, a second terminal connected to a first node N1, and a control terminal connected to a light-emitting control signal line 104 transmitting the light-emitting control signal EM[i]. The light-emitting control transistor T6 may include a first terminal connected to a third node N3, a second terminal connected to a fourth node N4, and a control terminal connected to the light-emitting control signal line 104 transmitting the light-emitting control signal EM[i]. The fourth node N4 may be connected to the anode terminal of the light-emitting element EE. Both the operational control transistor T5 and the light-emitting control transistor T6 may be turned on simultaneously in response to the light-emitting control signal EM[i] received through the light-emitting control signal line 104. When both the operational control transistor T5 and the light-emitting control transistor T6 are turned on, the drive current generated by the driving transistor T1 may flow to the light-emitting element EE.

[0074] The light-emitting element initialization transistor T7 may include a first terminal connected to the fourth node N4, a second terminal connected to the second initialization voltage line 109 for transmitting the second initialization voltage Vaint, and a control terminal connected to the second initialization signal line 103 for transmitting the second initialization signal GI[i-1]. The light-emitting element initialization transistor T7 can be turned on according to the second initialization signal GI[i-1] received via the second initialization signal line 103. When the light-emitting element initialization transistor T7 is turned on, it can initialize the voltage at the anode terminal of the light-emitting element EE to the second initialization voltage Vaint by transmitting the second initialization voltage Vaint to the anode terminal of the light-emitting element EE. When the second initialization voltage Vaint is transmitted to the anode terminal of the light-emitting element EE, the parasitic capacitor of the light-emitting element EE is discharged, thereby effectively preventing unwanted micro-emissions and thus improving the black performance of the pixel circuit. The second initialization voltage Vaint may have the same or different voltage level as the first initialization voltage Vint. The second initialization voltage Vaint may have a voltage level lower than the voltage level of the data signal D[j]. When the second initialization voltage Vaint supplied to the fourth node N4 exceeds a predetermined value, the parasitic capacitor of the light-emitting element EE can be charged instead of discharged. Therefore, the second initialization voltage Vaint can be set to a sufficiently low voltage (e.g., below the second supply voltage ELVSS) to discharge the parasitic capacitor of the light-emitting element EE.

[0075] The bias transistor T8 may include a first terminal connected to a bias voltage line 111 for transmitting a bias voltage Vbias, a second terminal connected to a first node N1, and a control terminal connected to a second initialization signal line 103 for transmitting a second initialization signal GI[i-1]. The bias transistor T8 may be turned on in response to the second initialization signal GI[i-1] received via the second initialization signal line 103. When the bias transistor T8 is turned on, it can initialize the hysteresis characteristics of the driving transistor T1 by transmitting the bias voltage Vbias to the first node N1. Accordingly, the brightness variation caused by the hysteresis of the driving transistor T1 can be improved. The bias voltage Vbias may have a voltage level that can mitigate the hysteresis characteristics of the driving transistor T1 by keeping the driving transistor T1 in a specific on-bias state in pixel PX. The bias voltage Vbias may have a predetermined voltage level within the voltage range of the data signal D[j], or have an on-voltage level of the scan signal GW[i].

[0076] The storage capacitor Cst may include a first terminal connected to a first power line 106 that transmits the first power supply voltage ELVDD and a second terminal connected to a second node N2. The storage capacitor Cst may store a data voltage corresponding to the data signal D[j].

[0077] The light-emitting element EE may include an anode terminal connected to the fourth node N4 and a cathode terminal connected to the second power line 107 that transmits the second power supply voltage ELVSS. The light-emitting element EE can emit light by receiving a drive current generated by the drive transistor T1.

[0078] At least one of the transistors T1, T2, T3-1, T3-2, T4, T5, T6, T7, and T8 constituting the pixel circuit can be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. Furthermore, one of the first and second terminals of each of transistors T1, T2, T3-1, T3-2, T4, T5, T6, T7, and T8 can be a drain terminal, and the other can be a source terminal. Additionally, the control terminal of each of transistors T1, T2, T3-1, T3-2, T4, T5, T6, T7, and T8 can be a gate terminal.

[0079] In an embodiment, such as Figure 2 As shown, the plurality of transistors T1, T2, T3-1, T3-2, T4, T5, T6, T7, and T8 constituting the pixel circuit can be P-type transistors, but the type of each transistor is not particularly limited. In another embodiment, for example, at least one of the plurality of transistors T1, T2, T3-1, T3-2, T4, T5, T6, T7, and T8 constituting the pixel circuit can be an N-type transistor. In some embodiments, among the plurality of transistors T1, T2, T3-1, T3-2, T4, T5, T6, T7, and T8, the first compensation transistor T3-1 can be an N-type transistor, and the other transistors can be P-type transistors. In such an embodiment, the compensation signal line 110 may include a first compensation signal line connected to the control terminal of the first compensation transistor T3-1 and a second compensation signal line connected to the control terminal of the second compensation transistor T3-2. The levels of the compensation signal transmitted to the first compensation signal line and the levels of the compensation signal transmitted to the second compensation signal line may be opposite to each other. (Refer to later...) Figure 12 This will be described.

[0080] In an embodiment, such as Figure 2 As shown, the control terminals of the light-emitting element initialization transistor T7 and the bias transistor T8 of each pixel PX can be connected to the same wiring (i.e., the second initialization signal line 103). The first initialization signal line 102 and the second initialization signal line 103 can be connected to... Figure 1The initialization signal line of the initialization driver 23 is the stage of the initialization driver 23. The stage in the initialization driver 23 connected to the second initialization signal line 103 can be the stage in the initialization driver 23 that is connected to the first initialization signal line 102. Therefore, the second initialization signal GI[i-1] is an initialization signal output from the stage that outputs the first initialization signal GI[i], and can be a preceding initialization signal output before the first initialization signal GI[i]. In addition, the first initialization signal GI[i] can have an activation level (i.e., a conduction voltage level) at different level periods than the second initialization signal GI[i-1].

[0081] In this embodiment, the first initialization signal GI[i] applied to the initialization transistor T4 can be applied as an initialization signal to the light-emitting element initialization transistor and bias transistor of another pixel PX. That is, the initialization transistor T4 can share the initialization signal line (i.e., the first initialization signal line 102) with the light-emitting element initialization transistor T7 and bias transistor T8 of another pixel PX. The other pixel PX sharing the first initialization signal line 102 with the initialization transistor T4 can be a pixel connected to the next level of the level connected to the current pixel PX among the multiple levels included in the scan driver 21. In other words, the other pixel PX sharing the first initialization signal line 102 with the initialization transistor T4 can be a pixel included in a pixel row (the next pixel row) different from the pixel row of the current pixel PX.

[0082] In this embodiment, the second initialization signal GI[i-1] applied to the light-emitting element initialization transistor T7 and the bias transistor T8 can also be applied as an initialization signal to the initialization transistors of other pixels PX. That is, the light-emitting element initialization transistor T7 and the bias transistor T8 can share an initialization signal line (i.e., the second initialization signal line 103) with the initialization transistor T4 of another pixel PX. The other pixel PX sharing the second initialization signal line 103 with the light-emitting element initialization transistor T7 and the bias transistor T8 can be a pixel connected to a stage preceding the stage connected to the current pixel PX among the multiple stages included in the scan driver 21. In other words, the other pixel PX sharing the second initialization signal line 103 with the light-emitting element initialization transistor T7 and the bias transistor T8 can be a pixel included in a pixel row different from the pixel row of the current pixel PX (in the preceding pixel row).

[0083] In the embodiment, as described above, the first initialization signal line 102 connected to the initialization transistor T4 is jointly connected to the light-emitting element initialization transistor and the bias transistor of another pixel PX, and the second initialization signal line 103 connected to the light-emitting element initialization transistor T7 and the bias transistor T8 is jointly connected to the initialization transistor of another pixel PX. Accordingly, the number of pixels in the display panel 10 in the first direction ( Figure 1 The number of horizontal wirings extending in the horizontal direction.

[0084] Figure 3 It is a diagram. Figure 2 A pixel circuit diagram of an embodiment where the pixel circuits share an initialization signal line. Figure 4 yes Figure 3 A planar image of pixels.

[0085] refer to Figure 3 and Figure 4 In an embodiment, the first pixel PXa connected to the i-th scan signal line and the j-th data signal line can share the second initialization signal line 103 with the second pixel PXb connected to the (i-1)-th scan signal line and the j-th data signal line. That is, the second initialization signal line 103 can be connected to the control terminals of the light-emitting element initialization transistor T7 and the bias transistor T8 of the first pixel PXa, and can also be connected to the initialization transistor T4 of the second pixel PXb. Therefore, the second initialization signal GI[i-1] supplied through the second initialization signal line 103 can simultaneously control the light-emitting element initialization transistor T7 and the bias transistor T8 of the first pixel PXa, as well as the initialization transistor T4 of the second pixel PXb. Accordingly, the number of signal lines used to supply the initialization signal to the pixels PX can be reduced, thereby achieving a high degree of integration in the display panel 10. In an embodiment, as... Figure 3 As shown, the second pixel PXb can be connected to the signal lines of the transmission scan signal GW[i-1], initialization signal GI[i-2], compensation signal GC[i-1], and light emission control signal EM[i-1].

[0086] Figure 5 This is a signal timing diagram used to describe the operation of pixels according to an embodiment, showing the signal applied during the data write period. Figure 2 The timing of the signals in the pixel circuit.

[0087] refer to Figure 5At the first time point t1, a high-level light emission control signal EM[i] of H can be supplied to pixel PX through the corresponding light emission control signal line 104. During the non-light emission period NEP between the first time point t1 and the fourteenth time point t14, the operation control transistor T5 and the light emission control transistor T6 can remain in the off state. Therefore, during the non-light emission period NEP, the electrical connection between the first power supply line 106 transmitting the first power supply voltage ELVDD and the driving transistor T1 is interrupted, and as a result, the electrical connection between the driving transistor T1 and the light-emitting element EE is interrupted, so that the light-emitting element EE can remain in the non-light emission state.

[0088] At the second time point t2, the low-level compensation signal GC[i] can be supplied to pixel PX through the corresponding compensation signal line 110. During the compensation period CP between the second time point t2 and the ninth time point t9, the first compensation transistor T3-1 and the second compensation transistor T3-2 can remain in the on state. Accordingly, during the compensation period CP, the driving transistor T1 can be diode-connected by the first compensation transistor T3-1 and the second compensation transistor T3-2.

[0089] At the third time point t3, a low-level second initialization signal GI[i-1] can be supplied to pixel PX through the corresponding second initialization signal line 103. During the first initialization period IP1 between the third time point t3 and the fourth time point t4, when the low-level second initialization signal GI[i-1] is supplied, the light-emitting element initialization transistor T7 and the bias transistor T8 can remain in the on state. Therefore, during the first initialization period IP1, the second initialization voltage Vaint is transmitted to the anode terminal of the light-emitting element EE through the light-emitting element initialization transistor T7, and the anode terminal voltage of the light-emitting element EE can be initialized. In addition, during the first initialization period IP1, the bias voltage Vbias is transmitted to the first terminal of the driving transistor T1, and the hysteresis characteristic of the driving transistor T1 can be initialized.

[0090] At the fifth time point t5, the low-level first initialization signal GI[i] can be supplied to pixel PX through the corresponding first initialization signal line 102. During the second initialization period IP2 between the fifth time point t5 and the sixth time point t6, when the low-level first initialization signal GI[i] is supplied, the initialization transistor T4 can remain on. During the second initialization period IP2, the first compensation transistor T3-1 can also remain on. Therefore, during the second initialization period IP2, the first initialization voltage Vint is transmitted to the second node N2 through the initialization transistor T4 and the first compensation transistor T3-1, and the voltage of the control terminal of the driving transistor T1 and the storage capacitor Cst can be initialized to the first initialization voltage Vint, which is lower than the voltage of the data signal D[j].

[0091] At time point t7, a low-level scan signal GW[i] can be supplied to pixel PX via the corresponding scan signal line 101. During the write period WP between time point t7 and time point t8, when the low-level scan signal GW[i] is supplied, switching transistor T2 can remain on. During the write period WP, ​​the data signal D[j] corresponding to pixel PX can be supplied via the corresponding data signal line 105. Therefore, during the write period WP, ​​the data signal D[j] can be transmitted to the first node N1. During the write period WP, ​​the first compensation transistor T3-1 and the second compensation transistor T3-2 can also remain on. Therefore, during the write period WP, ​​the voltage (Vdata+Vth) obtained by reflecting the threshold voltage (Vth) of driving transistor T1 in the data voltage (Vdata) of data signal D[j] is transmitted to the second node N2 via the diode-connected driving transistor T1, and this voltage can be stored in the storage capacitor Cst.

[0092] At the ninth time point t9, the high-level H compensation signal GC[i] can be supplied to pixel PX through the corresponding compensation signal line 110. The first compensation transistor T3-1 and the second compensation transistor T3-2 can be turned off by the high-level H compensation signal GC[i].

[0093] At the tenth time point t10, the low-level second initialization signal GI[i-1] of L can be resupplyed to pixel PX through the corresponding second initialization signal line 103. During the third initialization period IP3 between the tenth time point t10 and the eleventh time point t11, when the low-level second initialization signal GI[i-1] is supplied, the light-emitting element initialization transistor T7 and the bias transistor T8 can remain in the on state. Therefore, during the third initialization period IP3, the second initialization voltage Vaint can be transmitted to the anode terminal of the light-emitting element EE through the light-emitting element initialization transistor T7, and the anode terminal voltage of the light-emitting element EE can be reinitialized. In addition, during the third initialization period IP3, the bias voltage Vbias is transmitted to the first terminal of the driving transistor T1, and the hysteresis characteristic of the driving transistor T1 can be reinitialized.

[0094] At the twelfth time point t12, the low-level first initialization signal GI[i] can be supplied to pixel PX through the corresponding first initialization signal line 102. During the fourth initialization period IP4 between the twelfth time point t12 and the thirteenth time point t13, when the low-level first initialization signal GI[i] is supplied, the initialization transistor T4 can remain in the on state, but the first compensation transistor T3-1 can remain in the off state. Therefore, during the fourth initialization period IP4, the initialization operation of the control terminal voltage of the driving transistor T1 and the voltage of the storage capacitor Cst can be omitted.

[0095] At time point t14, a low-level L-level light emission control signal EM[i] can be supplied to pixel PX through the corresponding light emission control signal line 104. Operation control transistor T5 and light emission control transistor T6 can be turned on by the low-level L-level light emission control signal EM[i]. Therefore, the first power supply line 106 transmitting the first power supply voltage ELVDD and the driving transistor T1 can be electrically connected to each other, and the driving transistor T1 and the light-emitting element EE can be electrically connected to each other. As a result, driving current flows through the driving transistor T1 to the light-emitting element EE, and the light-emitting element EE can emit light.

[0096] In some embodiments, the display device 1 can operate in a variable frequency mode. The multiple frame periods during which the display device 1 operates in the variable frequency mode may include a first frame period and multiple second frame periods. In the first frame period, multiple data signals are applied to multiple pixels PX, and a data voltage is written to each of the multiple pixels PX via the multiple data signals. The multiple pixels PX emit light based on the data voltage. In the multiple second frame periods, the multiple pixels PX emit light based on the already stored data voltage without writing the data voltage. In the multiple second frame periods, the data voltage is not written to each pixel PX, but the initialization operation of the light-emitting element EE and the biasing operation of the driving transistor T1 can be performed. Therefore, the non-light-emitting period NEP of each of the multiple second frame periods may only include the initialization periods IP1 to IP4, excluding the compensation period CP and the write period WP. (Refer to...) Figure 6 This will be described.

[0097] Figure 6 This is a signal timing diagram used to describe the operation of pixels according to an embodiment, and illustrates the signal applied during the self-scan period. Figure 2 The timing of the signals in the pixel circuit. Additionally, Figure 7 This is a pixel circuit diagram used to describe the operation of a pixel circuit in a variable frequency mode according to an embodiment.

[0098] refer to Figure 6 During multiple second frame periods of the display device 1, in the non-light-emitting period NEP during which the light-emitting control signal EM[i] is held at a high level H, the compensation signal GC[i] and the scan signal GW[i] can be held at a cutoff voltage level (or a deactivated level). In an embodiment, for example, during the non-light-emitting period NEP of each of the multiple second frame periods, the compensation signal GC[i] at a high level H can be supplied to the pixel PX through the compensation signal line 110, and the scan signal GW[i] at a high level H can be supplied to the pixel PX through the scan signal line 101.

[0099] Therefore, during the second initialization period IP2 and the fourth initialization period IP4, when the low-level first initialization signal GI[i] is supplied, the initialization operations for the control terminal voltage of the driving transistor T1 and the voltage of the storage capacitor Cst can be omitted. (See reference...) Figure 7Since the compensation signal GC[i] remains at a high level (cutoff voltage level) during the self-scan period, the first compensation transistor T3-1 and the second compensation transistor T3-2 can remain in the off state. Therefore, even if a low-level first initialization signal GI[i] is supplied during the second initialization period IP2 and the fourth initialization period IP4 and the initialization transistor T4 is turned on, the transmission of the first initialization voltage Vint will be blocked by the first compensation transistor T3-1, which is in the off state. In such an embodiment, when a low-level second initialization signal GI[i-1] is supplied during the first initialization period IP1 and the third initialization period IP3 during the self-scan period, the light-emitting element initialization transistor T7 and the bias transistor T8 are normally turned on, and the initialization operation of the light-emitting element EE and the bias operation (hysteresis characteristic initialization) of the driving transistor T1 can also be performed normally. In the following, reference will be made to Figures 8 to 13 Various embodiments of the pixel circuit are described. In the following text, for ease of description, any repeated detailed descriptions of components that are identical or similar to those in the pixel circuit described above may be omitted.

[0100] Figure 8 This is a pixel circuit diagram of a pixel according to another embodiment.

[0101] In another embodiment, such as Figure 8 As shown, the pixel circuitry may further include a holding capacitor Chold. (Reference) Figure 8 The holding capacitor Chold may include a first terminal connected to a first power line 106 that provides the first power supply voltage ELVDD and a second terminal connected to a first node N1. The holding capacitor Chold can perform the function of keeping the voltage of the first node N1 (i.e., the first terminal of the driving transistor T1) constant.

[0102] Figure 9 This is a pixel circuit diagram of a pixel according to another embodiment.

[0103] In another embodiment, such as Figure 9 As shown, the pixel circuit can reduce leakage current by constructing the initialization transistor as a dual-transistor. (Reference) Figure 9 The pixel circuit may include execution Figure 2The initialization transistor T4 comprises a first initialization transistor T4-1 and a second initialization transistor T4-2. The first initialization transistor T4-1 and the second initialization transistor T4-2 can be connected in series between the fifth node N5 and the first initialization voltage line 108, and the control terminals of the first initialization transistor T4-1 and the second initialization transistor T4-2 can be connected to the first initialization signal line 102. That is, the first initialization transistor T4-1 may include a first terminal connected to the fifth node N5, a second terminal connected to the first terminal of the second initialization transistor T4-2, and a control terminal connected to the first initialization signal line 102. Similarly, the second initialization transistor T4-2 may include a first terminal connected to the second terminal of the first initialization transistor T4-1, a second terminal connected to the first initialization voltage line 108, and a control terminal connected to the first initialization signal line 102. Figure 2 Similar to the initialization transistor T4, the first initialization transistor T4-1 and the second initialization transistor T4-2 can be turned on by the first initialization signal GI[i].

[0104] Figure 10 This is a pixel circuit diagram of a pixel according to another embodiment.

[0105] In another embodiment, such as Figure 10 As shown, Figure 10 The pixel circuitry may further include a third compensation transistor T3-3 for reducing leakage current. (Reference) Figure 10 The pixel circuit may further include a third compensation transistor T3-3 connected between the fifth node N5 and the initialization transistor T4. The third compensation transistor T3-3 may include a first terminal connected to the fifth node N5, a second terminal connected to the first terminal of the initialization transistor T4, and a control terminal connected to the compensation signal line 110. The third compensation transistor T3-3 can be turned on by the compensation signal GC[i].

[0106] Figure 11 This is a pixel circuit diagram of a pixel according to another embodiment.

[0107] In another embodiment, such as Figure 11 As shown, the pixel circuit may further include a fourth compensation transistor T3-4 for reducing leakage current. (Reference) Figure 11 The pixel circuit may further include a fourth compensation transistor T3-4 connected between the first compensation transistor T3-1 and the fifth node N5. The fourth compensation transistor T3-4 may include a first terminal connected to the second terminal of the first compensation transistor T3-1, a second terminal connected to the fifth node N5, and a control terminal connected to the compensation signal line 110. The fourth compensation transistor T3-4 can be turned on by the compensation signal GC[i].

[0108] Figure 12 This is a pixel circuit diagram of a pixel according to another embodiment. Figure 13 It is used to describe Figure 12 The signal timing diagram for the operation of the pixel circuit.

[0109] In an embodiment, such as Figure 12 As shown, the first compensation transistor T3-1 and the second compensation transistor T3-2 of the pixel circuit are of different types, and may further include compensation signal lines to independently control the first compensation transistor T3-1 and the second compensation transistor T3-2. (Reference) Figure 12 The compensation signal lines connected to pixel PX may include a first compensation signal line 112 that transmits the first compensation signal GC1[i] to the N-type first compensation transistor T3-1 and a second compensation signal line 113 that transmits the second compensation signal GC2[i] to the P-type second compensation transistor T3-2. Therefore, as... Figure 13 As shown, during the compensation period CP, the first compensation signal GC1[i] and the second compensation signal GC2[i], whose signal levels are opposite to each other, can be input to the first compensation transistor T3-1 and the second compensation transistor T3-2, respectively. During the compensation period CP, the first compensation transistor T3-1 can be turned on by the first compensation signal GC1[i] at a high level H, and the second compensation transistor T3-2 can be turned on by the second compensation signal GC2[i] at a low level L. In the embodiment, as... Figure 12 As shown, although the driving timing of the first compensation signal GC1[i] and the second compensation signal GC2[i] can be the same, the driving timing of the first compensation signal GC1[i] and the second compensation signal GC2[i] can be set differently or independently.

[0110] The display device 1 according to the above embodiments can be applied to various electronic devices. The electronic device according to the embodiments may include the display device 1, and in addition to the display device 1, may further include modules or devices with additional functions.

[0111] Figure 14 This is a block diagram of an electronic device according to some embodiments. (Reference) Figure 14 The electronic device 1000 according to the embodiment may include a display module 1100, a processor 1200, a memory 1300, and a power module 1400.

[0112] The processor 1200 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0113] The memory 1300 can store data information required for the operation of the processor 1200 or the display module 1100. When the processor 1200 executes the application stored in the memory 1300, image data signals and / or input control signals are transmitted to the display module 1100, and the display module 1100 can process the received signals to display images on the screen.

[0114] The power module 1400 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1000.

[0115] At least one of the components of electronic device 1000 may be included within display device 1 according to the above embodiment. Furthermore, some of the individual modules functionally included in a single module may be included in display device 1, while other individual modules may be provided separately from display device 1. For example, display device 1 may include display module 1100, while processor 1200, memory 1300, and power module 1400 may be provided as other devices within electronic device 1000 that are not part of display device 1.

[0116] Figure 15 Schematic diagrams of electronic devices according to various embodiments are shown.

[0117] refer to Figure 15 Various electronic devices having a display device according to the embodiments may include not only image display electronic devices such as smartphones 1000_1a, tablet PCs 1000_1b, laptop computers 1000_1c, TVs 1000_1d, and desktop monitors 1000_1e, but also wearable electronic devices with display modules such as smart glasses 1000_2a, head-mounted displays 1000_2b, and smartwatches 1000_2c, as well as automotive electronic devices having display modules 1000_3 (such as display modules placed on car dashboards, central instrument panels, CID (Central Information Display), interior mirror displays, etc.).

[0118] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the concept of the invention to those skilled in the art.

[0119] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A pixel circuit of a display panel including a plurality of pixel circuits, the pixel circuit comprising: a light emitting element; a first transistor connected between a first node and the light emitting element, and including a control terminal connected to a second node; a second transistor connected between a corresponding data line among a plurality of data lines and the first node, and including a control terminal connected to a first scan signal line among a plurality of scan signal lines connected with the plurality of pixel circuits; a third transistor connected between the second node and a first initialization voltage line that transmits a first initialization voltage, and including a control terminal connected to a first initialization signal line among a plurality of initialization signal lines connected with the plurality of pixel circuits; and a fourth transistor connected between the first node and a bias voltage line that transmits a bias voltage, and including a control terminal connected to a second initialization signal line among the plurality of initialization signal lines different from the first initialization signal line, wherein the second initialization signal line is connected to a control terminal of a third transistor of another pixel circuit connected to the first initialization voltage line.

2. The pixel circuit according to claim 1, wherein the other pixel circuit is connected to a second scan signal line among the plurality of scan signal lines different from the first scan signal line.

3. The pixel circuit according to claim 1, further comprising: a fifth transistor connected between the second node and the third transistor, and including a control terminal connected to a corresponding compensation signal line among a plurality of compensation signal lines connected with the plurality of pixel circuits; and a sixth transistor connected between the first transistor and the third transistor, and including a control terminal connected to the corresponding compensation signal line.

4. The pixel circuit according to claim 3, further comprising: a seventh transistor connected between the fifth transistor and the third transistor, and including a control terminal connected to the corresponding compensation signal line, wherein the sixth transistor is connected to a node between the fifth transistor and the seventh transistor.

5. The pixel circuit according to claim 3, further comprising: a seventh transistor connected between the fifth transistor and the third transistor, and including a control terminal connected to the corresponding compensation signal line, wherein the sixth transistor is connected to a node between the third transistor and the seventh transistor.

6. The pixel circuit according to claim 3, wherein in one frame period among a plurality of frame periods of displaying one image, the fifth transistor and the sixth transistor are turned on, and in remaining frame periods among the plurality of frame periods, the fifth transistor and the sixth transistor are in an off state.

7. The pixel circuit according to claim 1, further comprising: a fifth transistor connected between the second node and the third transistor, and including a control terminal connected to a corresponding first compensation signal line among a plurality of first compensation signal lines connected with the plurality of pixel circuits; and a sixth transistor connected between the first transistor and the third transistor, and including a control terminal connected to the corresponding first compensation signal line. ​ ​ a sixth transistor connected between the first transistor and the third transistor, and including a control terminal connected to a corresponding second compensation signal line among a plurality of second compensation signal lines connected to the plurality of pixel circuits, wherein the fifth transistor is an N-type transistor and the sixth transistor is a P-type transistor, wherein a level of a signal applied to the corresponding first compensation signal line and a level of a signal applied to the corresponding second compensation signal line are opposite to each other, and wherein the first transistor to the fourth transistor are P-type transistors.

8. The pixel circuit according to claim 1, further comprising: a fifth transistor connected between a first terminal of the light emitting element and a second initialization voltage line that transmits a second initialization voltage, and including a control terminal connected to the second initialization signal line; a holding capacitor connected between a first power supply line that transmits a first power supply voltage and the first node; or a sixth transistor connected between the second node and the third transistor, and including a control terminal connected to the first initialization signal line.

9. The pixel circuit according to claim 1, further comprising: a fifth transistor connected between a first power supply line that transmits a first power supply voltage and the first node, and including a control terminal connected to a corresponding light emission control line among a plurality of light emission control lines connected to the plurality of pixel circuits; and a sixth transistor connected between the first transistor and the light emitting element, and including a control terminal connected to the corresponding light emission control line.

10. A display device comprising: a display panel including a plurality of pixels connected to a plurality of scan signal lines, a plurality of initialization signal lines, and a plurality of data lines; a scan driver connected to the plurality of scan signal lines, wherein the scan driver supplies a plurality of scan signals to the plurality of pixels; an initialization driver connected to the plurality of initialization signal lines, wherein the initialization driver supplies a plurality of initialization signals to the plurality of pixels; and a data driver connected to the plurality of data lines, wherein the data driver supplies a plurality of data signals to the plurality of pixels, wherein a first pixel among the plurality of pixels includes: a light emitting element; a first transistor connected between a first node and the light emitting element, and including a control terminal connected to a second node; a second transistor connected between a corresponding data line among the plurality of data lines and the first node, and including a control terminal connected to a first scan signal line among the plurality of scan signal lines; a third transistor connected between the second node and a first initialization voltage line that transmits a first initialization voltage, and including a control terminal connected to a first initialization signal line among the plurality of initialization signal lines; and a fourth transistor connected between the first node and a bias voltage line that transmits a bias voltage, and including a control terminal connected to a second initialization signal line among the plurality of initialization signal lines different from the first initialization signal line, and wherein the first initialization signal line and the second initialization signal line are different from each other. ​ wherein the second initialization signal line is connected to a control terminal of a third transistor of the second pixel of the plurality of pixels connected to the first initialization voltage line, and wherein the second pixel is connected to a second scan signal line of the plurality of scan signal lines different from the first scan signal line. 11.An electronic device comprising: a memory; a processor executing an application stored in the memory; and a display device including a display module displaying an image based on input image data from the application, wherein the display device includes: a display panel including a plurality of pixels connected to a plurality of scan signal lines, a plurality of initialization signal lines, and a plurality of data lines; a scan driver connected to the plurality of scan signal lines, wherein the scan driver provides a plurality of scan signals to the plurality of pixels; an initialization driver connected to the plurality of initialization signal lines, wherein the initialization driver provides a plurality of initialization signals to the plurality of pixels; and a data driver connected to the plurality of data lines, wherein the data driver provides a plurality of data signals to the plurality of pixels, wherein a first pixel of the plurality of pixels includes: a light emitting element; a first transistor connected between a first node and the light emitting element, and including a control terminal connected to a second node; a second transistor connected between a corresponding data line of the plurality of data lines and the first node, and including a control terminal connected to a first scan signal line of the plurality of scan signal lines; a third transistor connected between the second node and a first initialization voltage line transmitting a first initialization voltage, and including a control terminal connected to a first initialization signal line of the plurality of initialization signal lines; and a fourth transistor connected between the first node and a bias voltage line transmitting a bias voltage, and including a control terminal connected to a second initialization signal line of the plurality of initialization signal lines different from the first initialization signal line, and wherein the second initialization signal line is connected to a control terminal of a third transistor of the second pixel of the plurality of pixels connected to the first initialization voltage line, and wherein the second pixel is connected to a second scan signal line of the plurality of scan signal lines different from the first scan signal line.

Images