Pixel circuit and display device including same

Abstract

Disclosed are a pixel circuit and a display device including the same. A pixel circuit according to an embodiment of the present specification includes a first node connected to a VDD line to which a first constant voltage is applied, a third node connected to a fourth node connected to a light emitting element, a 4-1 switching element disposed between the VDD line and the first node, and a 4-2 switching element disposed between the VDD line and the first node. The initialization phase, the sampling phase, the addressing phase and the transmission phase during the driving step are repeatedly performed. The (4-1) th switching element and the (4-2) th switching element are PWM-driven in the transmission phase. With this configuration, a display device with improved moire (mura) can be provided.

Description

[0001] Intersection of related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0121279, filed on September 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This specification relates to a pixel circuit and a display device including the pixel circuit. Background Technology

[0004] Based on the material of the emitting layer, electroluminescent displays are broadly classified into inorganic light-emitting display devices and organic light-emitting display devices. Active-matrix organic light-emitting display devices include organic light-emitting diodes (OLEDs). OLEDs emit light themselves and have advantages such as fast response time, high luminous efficiency, high brightness, and wide viewing angle. In organic light-emitting display devices, OLEDs are formed on each pixel. This type of organic light-emitting display device features fast response time, excellent luminous efficiency, high brightness, and wide viewing angle, as well as excellent contrast and color reproduction, because it can represent true black.

[0005] In the case of organic light-emitting display devices, images are displayed based on light generated from light-emitting elements within pixels. This has various advantages, but during driving, mura, such as spots, occurs due to coupling between wires within pixels or the operating conditions of the driving signal, leading to uniformity defects. This can be a factor that reduces the image quality satisfaction of the display device. Summary of the Invention

[0006] This specification is intended to address the aforementioned needs and / or problems in the prior art.

[0007] The problems addressed in this specification are not limited to those described above, and additional problems not mentioned herein will be apparent to those skilled in the art from the following description.

[0008] The pixel circuit according to embodiments of this specification may include: a first node connected to a VDD line configured to be applied a first constant voltage; a third node connected to a fourth node connected to a light-emitting element; a fourth-first switching element disposed between the VDD line and the first node; and a fourth-second switching element disposed between the VDD line and the first node, wherein an initialization phase, a sampling phase, an addressing phase, and an emission phase are configured to be repeatedly executed during a driving step, and the fourth-first switching element and the fourth-second switching element may be configured to be PWM driven during the emission phase.

[0009] According to various embodiments of the present specification, the emission phase can include a first emission phase in which the 1-1 EM pulse including the gate-on voltage and the 1-2 EM pulse including only the gate-off voltage are applied and a second emission phase in which the 1-2 EM pulse including the gate-on voltage and the 1-1 EM pulse including only the gate-off voltage are applied.

[0010] According to various embodiments of the present specification, the 1-1 EM pulse can be configured to be applied to a gate electrode of the 4-1 switching element, and the 1-2 EM pulse can be configured to be applied to a gate electrode of the 4-2 switching element.

[0011] According to various embodiments of the present specification, the emission phase can be performed by alternately repeating the first emission phase and the second emission phase.

[0012] According to various embodiments of the present specification, the 4-1 switching element can include a gate electrode connected to receive the 1-1 EM pulse, a first electrode connected to the VDD line, and a second electrode connected to the first node, and the 4-2 switching element can include a gate electrode connected to receive the 1-2 EM pulse, a first electrode connected to the VDD line, and a second electrode connected to the first node.

[0013] According to various embodiments of the present specification, the emission phase can be performed by alternately repeating the first emission phase and the second emission phase, and the 1-1 EM pulse can include the gate-on voltage and the gate-off voltage in the first emission phase and can include the gate-off voltage in the second emission phase.

[0014] According to various embodiments of the present specification, the emission phase can be performed by alternately repeating the first emission phase and the second emission phase, and the 1-2 EM pulse can include the gate-off voltage in the first emission phase and the gate-on voltage and the gate-off voltage in the second emission phase.

[0015] According to various embodiments of the present specification, the 1-2 EM pulse can be in the gate-off voltage in the interval in which the 1-1 EM pulse is in the gate-on voltage, and the 1-1 EM pulse can be in the gate-off voltage in the interval in which the 1-2 EM pulse is in the gate-on voltage.

[0016] According to various embodiments of the present specification, the 1-2 EM pulse can include an interval in which the gate-on voltage is in an interval in which the gate-off voltage is in the interval in which the 1-1 EM pulse is in the gate-off voltage, and the 1-1 EM pulse can include an interval in which the gate-on voltage is in an interval in which the gate-off voltage is in the interval in which the 1-2 EM pulse is in the gate-off voltage.

[0017] According to various embodiments of this specification, the first constant voltage may be a pixel driving voltage.

[0018] A display device according to an embodiment of this specification may include: a display panel, wherein a plurality of data lines, a plurality of gate lines intersecting the data lines, a plurality of power lines, and a plurality of pixel circuits connected to the data lines, gate lines, and power lines are disposed; a data driver configured to supply a data voltage for pixel data to the data lines; and a gate driver configured to supply a gate signal to the gate lines, wherein each of the plurality of pixel circuits may include: a first node connected to a VDD line configured to be applied a first constant voltage; a third node connected to a fourth node connected to a light-emitting element; a fourth-first switching element disposed between the VDD line and the first node; and a fourth-second switching element disposed between the VDD line and the first node, and wherein the pixel circuits may be configured to repeatedly perform an initialization phase, a sampling phase, an addressing phase, and an emission phase in a driving phase, and in the emission phase, the fourth-first switching element and the fourth-second switching element may be configured to be driven by PWM.

[0019] According to various embodiments of this specification, the display panel may include: a plurality of pixel lines, each of the plurality of pixel lines may include a plurality of pixels, each of the plurality of pixel lines may include pixel circuitry, and each of the plurality of pixel lines may share one of the gate lines.

[0020] According to various embodiments of this specification, during the driving step, an emission phase can be performed on one of the multiple pixel lines, and a sampling phase can be performed on another of the multiple pixel lines.

[0021] According to various embodiments of this specification, each of the plurality of pixel circuits may further include: a driving element, including a gate electrode connected to a second node, a first electrode connected to a first node, and a second electrode connected to a third node.

[0022] According to various embodiments of this specification, each of the plurality of pixel circuits may further include: a third switching element including a gate electrode, a first electrode connected to a fourth node, and a second electrode configured to be applied a third constant voltage.

[0023] According to various embodiments of this specification, each of the plurality of pixel circuits may further include: a first switching element including a gate electrode connected to a first gate line configured to be applied a first scan pulse, a first electrode connected to a data line configured to be applied a data voltage; and a second electrode connected to a second node; and a second switching element including a gate electrode connected to a second gate line configured to be applied a second scan pulse, a first electrode connected to a reference line configured to be applied a second constant voltage, and a second electrode connected to the second node.

[0024] According to various embodiments of this specification, each of the plurality of pixel circuits may further include: a second capacitor connected between the third node and the VDD line.

[0025] According to various embodiments of this specification, each of the plurality of pixel circuits may further include: a fifth switching element including a gate electrode connected to a fifth gate line configured to be applied a second EM pulse, a first electrode connected to a third node, and a second electrode connected to a fourth node, wherein the gate electrode of the third switching element may be connected to a third gate line configured to be applied a third scan pulse.

[0026] According to various embodiments of this specification, each of the plurality of pixel circuits may further include: a first switching element including a gate electrode connected to a first gate line configured to be applied a first scan pulse, a first electrode connected to a third node, and a second electrode connected to a data line configured to be applied a data voltage; and a second switching element including a gate electrode connected to a second gate line configured to be applied a second scan pulse, a first electrode connected to a second node, and a second electrode connected to the first node.

[0027] According to various embodiments of this specification, each of the plurality of pixel circuits further includes: a fifth switching element including a gate electrode connected to a fifth gate line configured to be applied a second EM pulse, a first electrode connected to a third node, and a second electrode connected to a fourth node, wherein the gate electrode of the third switching element may be connected to the fifth gate line.

[0028] According to this specification, the deviation in the number of gate cutoff voltages can be reduced without changing the brightness of the pixels.

[0029] According to this specification, variations in the pixel drive voltage supplied during the sampling phase can be prevented.

[0030] According to this specification, a display device can be provided with an improved mura pattern. Attached Figure Description

[0031] The above and other objects, features and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings, wherein:

[0032] Figure 1 This is a block diagram illustrating a display device according to an embodiment of this specification;

[0033] Figure 2 This is a plan view of a display device according to an embodiment of this specification;

[0034] Figure 3 This is a plan view illustrating pixels according to an embodiment of this specification;

[0035] Figure 4 This is a cross-sectional view showing a display device according to an embodiment of this specification;

[0036] Figure 5 This is a diagram illustrating a gate driver according to an embodiment of this specification;

[0037] Figure 6 It is a circuit diagram illustrating the pixel circuit;

[0038] Figure 7 This describes the driver. Figure 6 Waveform diagram of the pixel circuit method;

[0039] Figure 8 This is shown in the initialization phase according to Figure 6 A diagram of the current flowing in the pixel circuit;

[0040] Figure 9 This shows that during the sampling phase, according to Figure 6 A diagram of the current flowing in the pixel circuit;

[0041] Figure 10 This indicates that during the addressing phase, according to Figure 6 A diagram of the current flowing in the pixel circuit;

[0042] Figure 11 This shows that during the launch phase, according to Figure 10 A diagram of the current flowing in the pixel circuit;

[0043] Figure 12 This is a diagram showing the drive cycle of the display device;

[0044] Figure 13 It is a waveform diagram showing the timing signal synchronized with the image signal;

[0045] Figure 14 This is a waveform diagram illustrating the method of driving the first EM pulse during the transmission phase;

[0046] Figure 15 and Figure 16 It is a diagram used to illustrate the cloud-like patterns that appear in a display device;

[0047] Figure 17 This is a graph showing the change of the driving current of a pixel line over time;

[0048] Figure 18 It is a graph showing the changes in pixel drive voltage and gate-source voltage over time;

[0049] Figure 19 This is a graph illustrating the sampling error;

[0050] Figure 20 It is a circuit diagram showing the pixels that perform the emission phase at a specific time;

[0051] Figure 21 It is a circuit diagram showing the pixels performing the sampling phase at a specific time;

[0052] Figure 22 This is a circuit diagram illustrating a pixel circuit according to a first embodiment of this specification;

[0053] Figure 23 This is a waveform diagram illustrating a driving method for a pixel circuit according to a first embodiment of this specification;

[0054] Figure 24 This is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the initialization phase;

[0055] Figure 25 This is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the sampling phase;

[0056] Figure 26 This is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the addressing phase;

[0057] Figure 27 It is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the first emission phase;

[0058] Figure 28 It is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the second emission phase;

[0059] Figure 29 This is a waveform diagram explaining the period of the 1-1 EM pulse;

[0060] Figure 30 This is a diagram illustrating a display device with improved cloud-like patterns;

[0061] Figure 31This is a schematic diagram showing how the driving current of a pixel line changes over time.

[0062] Figure 32 It is a graph showing the changes in pixel drive voltage and gate-source voltage over time;

[0063] Figure 33 This is a graph used to illustrate the relationship between the number of pixel rows and the number of cutoffs for the 1-1 EM pulse;

[0064] Figure 34 This is a graph showing the change of the driving current of a pixel line over time;

[0065] Figure 35 This is a circuit diagram illustrating a pixel circuit according to a second embodiment of this specification;

[0066] Figure 36 This is a waveform diagram illustrating a driving method for a pixel circuit according to a second embodiment of this specification;

[0067] Figure 37 This is a circuit diagram illustrating a pixel circuit according to a third embodiment of this specification; and

[0068] Figure 38 This is a view illustrating a driving method for a pixel circuit according to a third embodiment of this specification. Detailed Implementation

[0069] The advantages and features disclosed herein, as well as the methods for implementing them, will become clearer from the embodiments described below with reference to the accompanying drawings. The invention is not limited to the embodiments described below, which may be implemented in various different forms; rather, these embodiments are provided to make the disclosure of the invention complete and to allow those skilled in the art to fully understand the scope of the invention, which is limited only by the scope of the appended claims.

[0070] In describing this invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this invention.

[0071] Terms used herein such as “comprising,” “including,” “having,” and “consisting of” are generally intended to allow for the addition of additional components unless used in conjunction with the term “only.” Unless otherwise expressly stated, references to the singular should be interpreted to include the plural.

[0072] When describing the location or interconnection between two components, terms such as “on top of,” “above,” “below,” “next to,” “connected or coupled,” “cross,” “intersect,” etc., may indicate that one or more other components may be inserted between them, unless “immediately adjacent” or “directly” is used.

[0073] When describing temporal context, terms such as “after,” “after,” “after,” or “before” may not be continuous on the time scale unless “immediately” or “directly” is used.

[0074] The terms "first," "second," etc., can be used to distinguish components, but the function or structure of these components is not limited to the serial number or component name attached to the component.

[0075] The following embodiments can be combined or associated with each other, in whole or in part, and various types of interlocks and drives are technically possible. The embodiments can be implemented independently of each other, or they can be implemented together in an interrelated relationship.

[0076] The terms used in the embodiments of the specification (including technical and scientific terms) should be interpreted as those commonly understood by one of ordinary skill in the art to which this invention pertains, unless otherwise specifically defined and described, and commonly used terms such as dictionary-defined terms should be interpreted according to their meaning in the context of the relevant field.

[0077] In the display device described in this specification, the pixel circuit and gate drive circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs including low-temperature polycrystalline silicon, etc.

[0078] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain.

[0079] In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, the current flows from the drain to the source. In the case of a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, the current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the present invention is not limited to the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0080] The gate signal can oscillate between the gate on-state voltage and the gate off-state voltage. A transistor can turn on in response to the gate on-state voltage and turn off in response to the gate off-state voltage. In the case of an n-channel transistor, the gate on-state voltage can be the gate high voltage VGH, and the gate off-state voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate on-state voltage can be the gate low voltage VGL, and the gate off-state voltage can be the gate high voltage VGH.

[0081] In the following description, embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0082] Figure 1 This is a block diagram illustrating a display device according to an embodiment of this specification.

[0083] refer to Figure 1 In one embodiment of this specification, the display device may be an organic light-emitting display device. The display device includes a display panel 100, display panel driving circuits 110 and 120 for writing image data to pixels of the display panel 100, and a power supply circuit 140 for generating power required to drive the pixels and the display panel driving circuits 110 and 120. The display panel driving circuits 110 and 120 and the power supply circuit 140 may be a display panel driver for driving the display panel.

[0084] The display panel 100 can be a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction.

[0085] The display area AA of the display panel 100 may include a pixel array for displaying images thereon. The pixel array may include multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, multiple sensing lines 104, and pixels P arranged in a matrix. The display panel 100 may further include multiple power lines commonly connected to the pixels P. The power lines may be connected to the pixels P and provide a constant voltage required to drive the pixels P. The pixels P include multiple pixel circuits connected to the data lines 102, gate lines 103, and power lines.

[0086] A pixel P can be divided into two or more subpixels for color implementation. For example, three pixels arranged sequentially along the X-axis can be divided into red, green, and blue subpixels. Furthermore, four pixels arranged sequentially along the X-axis can be divided into red, green, blue, and white subpixels.

[0087] Each pixel P can be connected to a data line, a gate line, and a power line.

[0088] The pixel array may include multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln may include multiple pixels P arranged along the line direction (X-axis direction) of the pixel array in the display panel 100. Each pixel arranged in a pixel line may share a gate line 103. Pixels P arranged along the data line direction in the column direction (Y-axis direction) may share the same data line 102 and the same sensing line 104. A horizontal period is the time obtained by dividing one frame period by the total number of pixel lines L1 to Ln.

[0089] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and the actual object in the background is visible. The display panel 100 can also be implemented as a flexible display panel.

[0090] Figure 2 This is a plan view of a display device according to an embodiment of this specification.

[0091] refer to Figure 2 The substrate 211 in the display device may include a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA of the substrate 211 may be adjacent to the display area AA and may be located outside the display area AA.

[0092] The display area AA can be an area in which multiple pixels P are arranged to display an image. Pixel P can further include multiple sub-pixels SP_1, SP_2, and SP_3.

[0093] Multiple subpixels SP are individual units that emit light, and each subpixel SP may emit, for example, red, green, blue or white light, but is not limited to these.

[0094] Thin-film transistors and light-emitting device layers can be arranged in each of the sub-pixels SP_1, SP_2, and SP_3. For example, light-emitting elements for displaying images and circuitry for driving the light-emitting elements can be arranged in multiple sub-pixels SP.

[0095] Each subpixel SP may include multiple thin-film transistors and storage capacitors. For example, a subpixel SP may consist of two transistors and one capacitor (2T1C), but is not limited to this configuration, and may also be implemented as a subpixel using other configurations such as 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 5T2C, 6T2C, 7T2, or 8T2C.

[0096] A pixel P can be composed of one or more sub-pixels SP that emit different colors. For example, a pixel P may include a first sub-pixel SP_1, a second sub-pixel SP_2, and a third sub-pixel SP_3.

[0097] The example shapes of the first sub-pixel SP_1, the second sub-pixel SP_2, and the third sub-pixel SP_3 can be, but are not limited to, rectangles, pentagons, hexagons, octagons, circles, ellipses, etc.

[0098] The first sub-pixel SP-1, the second sub-pixel SP-2, and the third sub-pixel SP-3 can emit light of different colors, and can emit at least one of red, green, or blue. The third sub-pixel SP-3 can have a larger area than the other sub-pixels. The third sub-pixel SP-3 can be arranged across the other sub-pixels.

[0099] The non-display area NA can be an area where no image is displayed, or it can be an area where various lines and driving circuits for driving multiple sub-pixels SP located in the display area AA are arranged. For example, various driving circuits such as gate drivers and data drivers can be arranged in the non-display area NA. The non-display area NA can be a border area, but is not limited to this.

[0100] The non-display area NA can be located around the display area AA. For example, the non-display area NA can be located around the display area AA. The non-display area NA can be, but is not limited to, an area in which multiple sub-pixels SP are not arranged.

[0101] The display area AA and the non-display area NA can be any shape suitable for the design of an electronic device on which the display panel 100 is mounted. If the display device is on a user wearable device, it can have a circular shape, such as a common watch, and the concepts of the embodiments in this specification can also be applied to free-form displays, such as those in vehicle dashboards. Example shapes of the display area AA can be, but are not limited to, pentagons, hexagons, circles, ellipses, etc.

[0102] The display device described in this specification may include various additional components for generating various signals or driving multiple sub-pixels SP_1, SP_2, and SP_3 within the display area AA. For example, the display device may include one or more driving circuits for controlling the sub-pixels SP. The driving circuits for controlling (or driving) the sub-pixels SP_1, SP_2, and SP_3 may include a gate driver 120, a data driver (not shown), a multiplexer (not shown), an electrostatic discharge (ESD) circuit (not shown), power lines, inverter circuits, signal lines, etc. The power lines may be high-voltage lines VDD and / or low-voltage lines VSS.

[0103] In addition to the functions used to drive subpixels SP_1, SP_2, and SP_3, the display panel 100 may further include additional components. For example, the display panel 100 may include additional components that provide touch sensing functions, user authentication functions (e.g., fingerprint recognition), multi-level pressure sensing functions, haptic feedback functions, etc. These additional components may be located in the non-display area NA or in external circuitry connected via a connection interface.

[0104] The pad portion PAD can be located on one side of the non-display area NA. The pad portion PAD can be a metal pattern to which external modules, such as flexible printed circuit boards (FPCBs) and chip-on-film (COF), are bonded. Although the pad portion PAD is shown located on one side of substrate 211, the shape and position of the pad portion are not limited thereto.

[0105] The gate driver 120, used to provide gate signals to the thin-film transistor, can be arranged on the other side of the non-display area NA. The gate driver 120 can provide gate signals to the gate line 103. The gate driver 120 can include various gate driving circuits, and the gate driving circuits can be directly formed on the substrate 211. In this case, the gate driver 120 can be a gate in panel (GIP).

[0106] The gate driver 120 may be located between the display area AA and the dam section DAM in the non-display area NA of the substrate 211.

[0107] The gate driver 120 may include a scan driving circuit, a light-emitting driving circuit, and signal lines.

[0108] Signal lines can transmit and control signals supplied from the pad section to the scan driver circuit or the light-emitting driver circuit. For example, a signal line can be a clock line.

[0109] The data driver, which provides data signals to the thin-film transistor, can be located on the other side of the non-display area NA. The data driver can provide the data voltage Vdata of the pixel data to the data line 102. The data driver can include various data driving circuits.

[0110] A high-potential voltage line VDD, a low-potential voltage line VSS, a multiplexer, an anti-static circuit, and multiple connecting lines can be installed between the display area AA and the data driver. These components can be arranged between the display area AA and the curved area BA.

[0111] The connection line portion can be located in the non-display area NA. For example, it can be located in the bent area BA of the substrate bend in the non-display area NA. The connection line portion can be configured to deliver signals (voltages) from an external module bonded to the pad portion to the display area AA or to circuitry such as the gate driver 120 and the data driver. For example, various signals (such as data signals, high-potential voltages, and low-potential voltages) used to drive the gate driver 120 can be delivered through the connection line portion.

[0112] The dam section (DAM) can be located in the non-display area NA to surround the entire or part of the display area AA. The dam section (DAM) can be adjacent to the display area AA or located outside the display area AA.

[0113] A dammed array (DAM) can be positioned along the periphery of the display area AA to control the flow of the organic material layer within the encapsulation layer disposed on the light-emitting element layer. Multiple dammed arrays (DAMs) can be used. The dammed arrays (DAMs) can be positioned between the display area AA and the high-voltage line VDD, the low-voltage line VSS, a multiplexer, or an anti-static circuit.

[0114] The panel crack detector PCD can also be arranged in a portion of the non-display area NA of the substrate 211. The panel crack detector PCD can be arranged between an end point (or end) of the substrate 211 and the dam section DAM. Alternatively, the panel crack detector PCD can be located downstream of the dam section DAM, and it can at least partially overlap with the dam section DAM.

[0115] Figure 3 This is a plan view illustrating pixels according to an embodiment of this specification.

[0116] refer to Figure 3 In the display device described in this specification, three consecutive sub-pixels SP1, SP2, and SP3 in one direction (left-right direction) can constitute a pixel P. Within each pixel P, each sub-pixel SP can be arranged to be spaced apart from each other at a predetermined interval.

[0117] Within a pixel P, the first to third data lines DL1, DL2 and DL3 extending along the Y-axis can correspond to the boundary arrangement of each sub-pixel SP1, SP2 and SP3.

[0118] A power line PL, extending in the first direction and used to apply a high-potential power supply voltage, can be arranged at the boundary between sub-pixels SP1, SP2, and SP3. A reference line RL, used to apply a reference voltage Vref, can be arranged at the boundary of each of the sub-pixels SP1, SP2, and SP3 adjacent to the power line PL. Furthermore, an initialization line, used to apply an initialization voltage Vinit, can also be arranged at the boundary of each of the sub-pixels SP1, SP2, and SP3 adjacent to the power line PL.

[0119] Gate lines GL1, GL2, GL3, and GL4, which intersect the first to third data lines DL1, DL2, and DL3, the power line PL, and the reference line RL and extend in the X-axis direction, can be arranged at the upper and lower adjacent boundaries of each sub-pixel in sub-pixels SP1, SP2, and SP3. Transmit control signal lines EML1, EML2, and EML3 can be arranged spaced apart from and parallel to the gate lines GL1, GL2, GL3, and GL4.

[0120] With the recent development of display devices with higher resolution and higher pixel integration, constraints on pixel arrangement space are increasing, and power lines PL and reference lines RL can be formed to be shared by multiple sub-pixels SP. This is a method of saving space occupied by signal lines by reducing the number of signal lines supplying common signals to each sub-pixel SP, and can be called a flip structure, in which the power line PL and reference line RL are shared by two adjacent sub-pixels SP.

[0121] Therefore, some subpixels SP can be directly connected to the power line PL and the reference line RL, while some other subpixels SP can be connected to each of the power line PL and the reference line RL through a separate connection pattern CP, instead of being directly connected to the power line PL and the reference line RL.

[0122] Figure 4 This is a cross-sectional view illustrating a display device according to an embodiment of this specification.

[0123] refer to Figure 4 The display device may include two thin-film transistors (TFTs) 1 and TFT2 and a capacitor CST. The two TFTs 1 and TFT2 may include a first TFT 1 comprising a polycrystalline semiconductor material and a second TFT 2 comprising an oxide semiconductor material.

[0124] A pixel P may include a light-emitting element EL and a pixel driving circuit that applies a driving current to the light-emitting element EL. The pixel driving circuit may be located on the substrate 211, and the light-emitting element EL may be located on the pixel driving circuit. Furthermore, an encapsulation layer 220 may be located on the light-emitting element EL. The encapsulation layer 220 can protect the light-emitting element EL.

[0125] A pixel driving circuit refers to a pixel P array portion that includes driving thin-film transistors, switching thin-film transistors, and capacitors. Furthermore, a light-emitting element EL refers to a light-emitting array portion that includes an anode electrode, a cathode electrode, and an emitting layer located therebetween.

[0126] In one embodiment, the driving thin-film transistor and at least one switching thin-film transistor may use oxide semiconductor as the active layer. Compared with thin-film transistors using polycrystalline semiconductor materials as the active layer, thin-film transistors using oxide semiconductor materials as the active layer have excellent leakage current blocking effect and lower manufacturing cost. Therefore, in order to reduce power consumption and manufacturing cost, the pixel driving circuit according to one embodiment may include a driving thin-film transistor and at least one switching thin-film transistor using oxide semiconductor materials.

[0127] All thin-film transistors that make up a pixel driving circuit can be implemented using oxide semiconductor materials, or only some switching thin-film transistors can be implemented using oxide semiconductor materials.

[0128] However, since it is difficult to guarantee the reliability of thin-film transistors using oxide semiconductor materials, and thin-film transistors using polycrystalline semiconductor materials have fast operating speeds and excellent reliability, one embodiment may include switching thin-film transistors using oxide semiconductor materials and switching thin-film transistors using polycrystalline semiconductor materials.

[0129] The substrate 211 can be implemented as a multilayer in which organic films and inorganic films are stacked alternately. For example, the substrate 211 can be stacked with alternating organic films such as polyimide and inorganic films such as silicon oxide (SiO2).

[0130] A lower buffer layer 212a may be formed on the substrate 211. The lower buffer layer 212a is intended to block moisture and other substances that may penetrate from the outside, and can be used by stacking films of silicon oxide (SiO2) and the like into multiple layers. An auxiliary buffer layer 212b may be further located on the lower buffer layer 212a to protect the device from moisture penetration.

[0131] The first thin-film transistor (TFT) 1 may be formed on the substrate 211. The first thin-film transistor TFT 1 may use a polycrystalline semiconductor as the active layer. The first thin-film transistor TFT 1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2. The first active layer ACT1 includes a channel through which electrons or holes move.

[0132] The first active layer ACT1 may include a first channel region, a first source region located on one side interposed between the first channel region and a first drain region located on the other side.

[0133] The first source region and the first drain region are regions in which the intrinsic polycrystalline semiconductor material is doped with group 5 or group 3 impurity ions (such as phosphorus (P) or boron (B)) at a predetermined concentration to make it conductive. The first channel region can maintain the intrinsic state of the polycrystalline semiconductor material to provide a path for the movement of electrons or holes.

[0134] Simultaneously, the first thin-film transistor TFT1 may include a first gate electrode GE1 overlapping with the first channel region of the first active layer ACT1. A first gate insulating layer 213 may be located between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 213 may be used by stacking inorganic layers such as silicon oxide SiO2 film or silicon nitride SiNx into a single layer or multiple layers.

[0135] In one embodiment, the first thin-film transistor TFT1 has a top-gate structure, wherein the first gate electrode GE1 is located above the first active layer ACT1. Therefore, the first electrode CST1 included in the capacitor CST and the light-shielding layer LS included in the second thin-film transistor TFT2 can be formed of the same material as the first gate electrode GE1. The masking process can be reduced by forming the first gate electrode GE1, the first electrode CST1, and the light-shielding layer LS using a single masking process. However, this specification is not limited to this; the light-shielding layer LS can be formed on the lower buffer layer 212a and the auxiliary buffer layer 212b using separate masking processes. In this case, the light-shielding layer LS is not limited to the second thin-film transistor TFT2 but can be formed at the bottom of all transistors. Additionally, the light-shielding layer LS can be positioned to overlap with the bottom of the capacitor CST to form a dual capacitor.

[0136] When the substrate 211 is formed of a transparent material, a light-shielding layer LS can be formed below the active layers ACT1 and ACT2. The light-shielding layer LS can block light passing through the transparent substrate 211 and reaching the active layers ACT1 and ACT2, thereby maintaining the function of the active layers ACT1 and ACT2. The light-shielding layer LS can be formed in the lower buffer layer 212a or the auxiliary buffer layer 212b.

[0137] The first gate electrode GE1 can be formed of a metallic material. For example, the first gate electrode GE1 can be a single layer or multiple layers made of, but not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof.

[0138] The first interlayer insulating layer 214 can be located on the first gate electrode GE1. The first interlayer insulating layer 214 can be implemented using silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0139] The display 100 may further include an upper buffer layer 215, a second gate insulating layer 216, and a second interlayer insulating layer 217 sequentially disposed on the first interlayer insulating layer 214, and the first thin film transistor TFT1 may include a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 217 and connected to each of the first source region and the first drain region.

[0140] The first source electrode SD1 and the first drain electrode SD2 can be single-layered or multi-layered, but are not limited to any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0141] The upper buffer layer 215 can separate the second active layer ACT2 of the second thin film transistor TFT2, which is made of oxide semiconductor material, from the first active layer ACT1, which is made of polycrystalline semiconductor material, and can provide a basis for forming the second active layer ACT2.

[0142] The second gate insulating layer 216 covers the second active layer ACT2 of the second thin-film transistor TFT2. Since the second gate insulating layer 216 is formed on the second active layer ACT2, which is implemented by an oxide semiconductor material, it can be implemented by an inorganic film. For example, the second gate insulating layer 216 can be silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0143] The second gate electrode GE2 can be formed of a metallic material. For example, the second gate electrode GE2 can be a single layer or multiple layers made of, but not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof.

[0144] Meanwhile, the second thin-film transistor TFT2 may include a second active layer ACT2 formed on the upper buffer layer 215 and implemented with an oxide semiconductor material, a second gate electrode GE2 located on the second gate insulating layer 216, a second source electrode SD3 located on the second interlayer insulating layer 217, and a second drain electrode SD4.

[0145] The second active layer ACT2 may include an intrinsic second channel region made of an oxide semiconductor material and undoped, and a second source region and a second drain region doped with impurities to conduct electricity.

[0146] The second thin-film transistor TFT2 may further include a light-shielding layer LS, which is located below the upper buffer layer 215 and overlaps with the second active layer ACT2. The light-shielding layer LS blocks light incident on the active layer 401 to ensure the reliability of the second thin-film transistor TFT2. The light-shielding layer LS may be formed of the same material as the first gate electrode GE1 and may be formed on the upper surface of the first gate insulating layer 213. The light-shielding layer LS may be electrically connected to the second gate electrode GE2 to form a dual-gate.

[0147] The second source electrode SD3 and the second drain electrode SD4 can be formed on the second interlayer insulating layer 217 simultaneously with the first source electrode SD1 and the first drain electrode SD2 from the same material, thereby reducing the number of mask processes.

[0148] Meanwhile, the capacitor CST can be realized by arranging a second electrode CST2 overlapping the first electrode CST1 on the first interlayer insulating layer 214. The second electrode CST2 can be a single layer or multiple layers made of any of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof.

[0149] The capacitor CST can store the data voltage applied through the data line DL for a specific period of time and then provide it to the light-emitting element EL. The capacitor CST may include two corresponding electrodes and a dielectric material between them. A first interlayer insulating layer 214 may be located between the first electrode CST1 and the second electrode CST2.

[0150] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the second thin-film transistor TFT2. However, this specification is not limited to this, and the connection relationship of the capacitor CST can be changed according to the pixel driving circuit.

[0151] Simultaneously, the first planarization layer 218 and the second planarization layer 219 can be sequentially located above the pixel driving circuit to planarize the upper end of the pixel driving circuit. The first planarization layer 218 and the second planarization layer 219 can be organic films such as polyimide or acrylic resin. The light-emitting element EL can be formed on the second planarization layer 219.

[0152] The light-emitting element (EL) may include an anode electrode (ANO), a cathode electrode (CAT), and an emitting layer (OLED) located between the anode electrode (ANO) and the cathode electrode (CAT). When the pixel driving circuitry uses a common low-potential voltage connected to the cathode electrode (CAT), the anode electrode (ANO) may be arranged as a separate electrode for each sub-pixel. When the pixel driving circuitry uses a common high-potential voltage, the cathode electrode (CAT) may be arranged as a separate electrode for each sub-pixel.

[0153] The light-emitting element EL can be electrically connected to the driving element via an intermediate electrode CNE located on the first planarization layer 218. Specifically, the anode electrode ANO of the light-emitting element EL constituting the pixel driving circuit and the first source electrode SD1 of the first thin-film transistor TFT1 can be interconnected via the intermediate electrode CNE.

[0154] The anode electrode ANO can be connected to the intermediate electrode CNE exposed through a contact hole penetrating the second planarization layer 219. Furthermore, the intermediate electrode CNE can be connected to the first source electrode SD1 exposed through a contact hole penetrating the first planarization layer 218.

[0155] The intermediate electrode CNE can be used as a medium to connect the first source electrode SD1 and the anode electrode ANO. The intermediate electrode CNE can be made of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0156] The anode electrode (ANO) can be formed as a multilayer structure comprising a transparent conductive film with high reflectivity and an opaque conductive film. The transparent conductive film can be formed from a material with a relatively high work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film can be formed from a single layer or multiple layers comprising aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode electrode (ANO) can be formed as a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially stacked, or it can be formed as a structure in which a transparent conductive film and an opaque conductive film are sequentially stacked.

[0157] An OLED with an emission layer can be formed by stacking a hole-correlated layer, an organic emission layer, and an electron-correlated layer on an anode electrode (ANO) in either a sequential or reverse order.

[0158] The barrier layer BNK can be a pixel-defining film that exposes the anode electrode ANO of each pixel P. The barrier layer BNK can be formed of an opaque material (e.g., black) to prevent light interference between adjacent pixels P. In this case, the barrier layer BNK can include a light-shielding material composed of at least one of colored pigments, organic black, and carbon. Spacers can further be located on the barrier layer BNK.

[0159] The cathode electrode (CAT) faces the anode electrode (ANO), and the emitting layer (OLED) is located between the cathode electrode (CAT) and the anode electrode (ANO), and can be formed on the upper and side surfaces of the emitting layer (OLED). The cathode electrode (CAT) can be integrally formed on the entire display area (AA). When applied to front-emitting organic light-emitting display devices, the cathode electrode (CAT) can be made of a transparent conductive film, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0160] The encapsulation layer 220 used to suppress moisture penetration can be further arranged on the cathode electrode CAT.

[0161] The encapsulation layer 220 can prevent external moisture or oxygen from penetrating into the light-emitting element (EL), which is susceptible to external moisture or oxygen. Therefore, the encapsulation layer 220 may have, but is not limited to, at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this specification, the structure of the encapsulation layer 220, in which the first encapsulation layer 121, the second encapsulation layer 122, and the third encapsulation layer 123 are stacked sequentially, will be described as an example.

[0162] The first encapsulation layer 121 can be formed on a substrate 211 on which a cathode electrode CAT is formed. The third encapsulation layer 123 can be formed on the substrate 211 on which the second encapsulation layer 122 is formed, and can be formed together with the first encapsulation layer 121 to surround the upper surface, lower surface, and side surface of the second encapsulation layer 122. These first encapsulation layers 121 and third encapsulation layers 123 can minimize or prevent the penetration of external moisture or oxygen into the light-emitting element EL. The first encapsulation layer 121 and third encapsulation layer 123 can be formed of an inorganic insulating material that can be deposited at low temperatures, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer 121 and third encapsulation layer 123 are deposited in a low-temperature atmosphere, damage to the light-emitting element EL, which is susceptible to high-temperature atmospheres, can be prevented during the deposition of the first encapsulation layer 121 and third encapsulation layer 123.

[0163] The second encapsulation layer 122 can serve as a buffer layer to alleviate inter-layer stress caused by bending of the display device and can flatten the step differences between layers. The second encapsulation layer 122 can be formed from, but is not limited to, a non-photosensitive organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon oxycarbonate (SiOC)) or a photosensitive organic insulating material (such as photoacrylic acid) on the substrate 211 where the first encapsulation layer 121 is formed. When the second encapsulation layer 122 is formed using an inkjet printing method, a dammed area (DAM) can be positioned to prevent the liquid form of the second encapsulation layer 122 from diffusing to the edges of the substrate 211. The dammed area (DAM) can be positioned closer to the edges of the substrate 211 than the second encapsulation layer 122. The dammed area (DAM) can prevent the second encapsulation layer 122 from diffusing into the pad area where conductive pads located on the outermost portion of the substrate 211 are arranged.

[0164] The dam-type diaphragm (DAM) is designed to prevent the diffusion of the second encapsulation layer 122. However, if the second encapsulation layer 122 is formed to exceed the height of the dam-type DAM during the process, the second encapsulation layer 122, as an organic layer, may be exposed to the outside, allowing moisture and other substances to easily penetrate into the light-emitting element. Therefore, to prevent this, the dam-type DAM can be formed as at least 10 or more replicas.

[0165] The dam section DAM can be located on the second interlayer insulation layer 217 of the non-display area NDA.

[0166] Furthermore, the dam section DAM can be formed simultaneously with the first planarization layer 218 and the second planarization layer 219. When the first planarization layer 218 is formed, the lower layer of the dam section DAM can be formed together, and when the second planarization layer 219 is formed, the upper layer of the dam section DAM can be formed together, thus stacking in a double-layer structure.

[0167] Therefore, the dam section DAM can be made of, but is not limited to, the same material as the first planarization layer 218 and the second planarization layer 219.

[0168] Dam-shaped DAMs can be formed by overlapping low-potential voltage lines. For example, low-potential voltage lines can be formed in the lower layer of the area where the dam-shaped DAM is located in the non-display area NDA.

[0169] The gate driver, configured as a low-potential voltage line and a gate-in-panel (GIP), is formed around the outer periphery of the display panel, with the low-potential voltage line potentially located further out of the gate driver. Furthermore, the low-potential voltage line can be connected to the cathode electrode CAT to apply a common voltage. The gate driver is simplified in plan and cross-sectional views, but can be configured using a thin-film transistor with the same structure as the thin-film transistor in the display area AA.

[0170] The low-potential voltage line can be located outside the gate driver. The low-potential voltage line can be located outside the gate driver and surround the display area AA. For example, the low-potential voltage line can be made of, but is not limited to, the same material as the first gate electrode GE1, and can be made of, but is not limited to, the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2.

[0171] Furthermore, the low-potential voltage line can be electrically connected to the cathode electrode CAT. The low-potential voltage line can provide a low-potential drive voltage EVSS to multiple pixels P in the display area AA.

[0172] The touch layer may be located on the encapsulation layer 220. In the touch layer, the touch buffer film 251 may be located between the touch sensor metal including touch electrode connection lines 252 and 254 and touch electrodes 255 and 256 and the cathode electrode CAT of the light-emitting element EL.

[0173] The touch buffer film 251 can prevent chemical liquids (such as developers, etchants, etc.) used in the manufacturing process of the touch sensor metal located on the touch buffer film 251 or moisture from the outside from penetrating into the OLED emission layer containing organic materials. Therefore, the touch buffer film 251 can prevent damage to the OLED emission layer, which is susceptible to chemical liquids or moisture.

[0174] The touch buffer film 251 can be formed of an organic insulating material that can be formed at a low temperature below a certain temperature (e.g., 100 degrees Celsius) and has a low dielectric constant of 1 to 3 to prevent damage to the OLED emitter layer, which includes high-temperature sensitive organic materials. For example, the touch buffer film 251 can be formed of acrylic resin, epoxy resin, or siloxane material. The planarization properties of the touch buffer film 251, with its organic insulating material, can prevent damage to the encapsulation layer 220 due to bending of the organic light-emitting display device and breakage of the touch sensor metal formed on the touch buffer film 251.

[0175] According to the mutual capacitance-based touch sensor structure, touch electrodes 255 and 256 are arranged on touch buffer film 251, and touch electrodes 255 and 256 can be arranged to intersect each other.

[0176] Touch electrode connecting wires 252 and 254 can be electrically connected between touch electrodes 255 and 256. Touch electrode connecting wires 252 and 254 and touch electrodes 255 and 256 can be located on different layers, with a touch insulating film 253 inserted between them.

[0177] The touch electrode connection lines 252 and 254 are arranged to overlap with the dike layer 165 to prevent a decrease in the opening ratio.

[0178] Meanwhile, touch electrodes 255 and 256 can be electrically connected to the touch drive circuit (not shown) via the touch panel PAD through a portion of the touch electrode connection line 252 passing through the upper and side surfaces of the encapsulation layer 220 and the upper and side surfaces of the dam section DAM.

[0179] This portion of the touch electrode connection line 252 can receive touch drive signals from the touch drive circuit and transmit them to the touch electrodes 255 and 256, and can also transmit touch sensing signals from the touch electrodes 255 and 256 to the touch drive circuit.

[0180] Touch protection film 257 may be located on touch electrodes 255 and 256. In the figure, touch protection film 257 is shown as being located only on touch electrodes 255 and 256, and touch protection film 257 may extend before or after the dam section DAM, or may be located on touch electrode connection line 252.

[0181] In addition, a color filter (not shown in the figure) may be provided on the encapsulation layer 220. The color filter may be located on the touch layer or between the encapsulation layer 220 and the touch layer.

[0182] Figure 5 This is a diagram illustrating a gate driver according to an embodiment of this specification.

[0183] refer toFigure 5 The gate driver may include a plurality of gate drivers configured to output gate signal pulses. According to one embodiment, the gate driver may include a first gate driver 310 that outputs a first gate signal SC1, a second gate driver 320 that outputs a second gate signal SC2, a third gate driver 330 that outputs a third gate signal SC3, a fourth gate driver 340 that outputs a fourth gate signal EM1, and a fifth gate driver 350 that outputs a fifth gate signal EM2.

[0184] Some of the multiple gate drivers can be implemented as shift register circuits, and the remainder can be implemented as edge-triggered circuits. For example, the first gate driver 310 can be implemented as a shift register circuit, and the second to fifth gate drivers 320 can be implemented as edge-triggered circuits. The shift register circuit can output a gate signal to only one pixel line, while the edge-triggered circuits can collectively output gate signals to two or more pixel lines. Therefore, the first gate driver 310, implemented as a shift register circuit, can be connected to each of the odd-numbered and even-numbered pixel lines.

[0185] Furthermore, the second gate driver 320 to the fifth gate driver 350, which are implemented as edge-triggered circuits, can be connected together to the two pixel lines.

[0186] In one embodiment, the fourth gate signal EM1 and the fifth gate signal EM2 may be transmit control signals, and the first gate signal SC1, the second gate signal SC2 and the third gate signal SC3 may be scan signals.

[0187] The fifth gate driver 350, which outputs the fifth gate signal EM2 as a transmit control signal, can be located at the outermost gate driver. Furthermore, the second gate driver 320, which outputs the second gate signal SC2 as a scan signal, and the third gate driver 330, which outputs the third gate signal SC3, can be located between the fourth gate driver 340 and the fifth gate driver 350, which output the fourth gate signal EM1.

[0188] The fourth gate driver 340, which outputs the fourth gate signal EM1, can be located between the first gate driver 310 and the second gate driver 320, which output the first gate signal SC1 as a scan signal. However, this specification is not limited thereto.

[0189] As shown in the figure, the gate drivers 340 and 350 that output the transmit control signal and the gate drivers 310, 320 and 330 that output the scan signal are shown to be arranged symmetrically to the left and right with respect to the display area AA. However, the embodiments in this specification are not limited to this. For example, the gate drivers 340 and 350 that output the transmit control signal and the gate drivers 310, 320 and 330 that output the scan signal may be arranged asymmetrically to the left and right with respect to the display area AA.

[0190] Figure 6 This is a circuit diagram illustrating the pixel circuit. Figure 7 This describes the driver. Figure 6 Waveform diagram of the pixel circuit method.

[0191] refer to Figure 6 and Figure 7 The pixel circuit may include a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, multiple switching elements M1 to M5, a first capacitor C1, and a second capacitor C2. The driving element DT and the switching elements M1, M2, M3, M4, and M5 can be implemented using n-channel transistors. The pixel circuit may further include multiple nodes.

[0192] The gate signal may include a first scan pulse (or a first gate electrode pulse SC1), a second scan pulse (or a second gate electrode pulse SC2), a third scan pulse (or a third gate electrode pulse SC3), a first EM pulse (or a fourth gate electrode pulse EM1), and a second EM pulse (or a fifth gate electrode pulse EM2).

[0193] The gate driver may include a first shift register that sequentially outputs a first scan pulse SC1, a second shift register that sequentially outputs a second scan pulse SC2, a third shift register that sequentially outputs a third scan pulse SC3, a fourth shift register that sequentially outputs a first EM pulse EM1, and a fifth shift register that sequentially outputs a second EM pulse EM2.

[0194] A constant voltage can be applied to the pixel circuit, such as the pixel drive voltage ELVDD, the low-level supply voltage ELVSS, the reference voltage Vref, and the initialization voltage Vinit. The pixel drive voltage ELVDD can be higher than the low-level supply voltage ELVDD.

[0195] The gate on-state voltages VGH and VEH can be set higher than the pixel drive voltage ELVDD. The gate off-state voltages VGL and VEL can be set lower than the low-level supply voltage ELVDD. However, this specification is not limited thereto. In this specification, the gate on-state voltages VGH and VEH are sometimes referred to as gate on-state voltage ON, and the gate off-state voltages VGL and VEL are sometimes referred to as gate off-state voltage OFF.

[0196] The initialization voltage Vinit can be set to a low-level voltage higher than the low-level supply voltage ELVSS. The reference voltage Vref can be set to the voltage at which the drive element DT can be turned on. The reference voltage Vref can be set to a voltage within the range of the data voltage Vdata output by the data driver. The maximum data voltage Vdata can be lower than the pixel drive voltage ELVDD, and the minimum data voltage Vdata can be higher than the low-level supply voltage ELVSS.

[0197] To sample the threshold voltage Vth of the driving element DT during the sampling phase, the reference voltage Vref is preferably set to a voltage higher than the initialization voltage Vinit. The voltage difference between the reference voltage Vref and the initialization voltage Vinit can be set to a voltage higher than the threshold voltage Vth of the driving element DT. To achieve the minimum brightness of the pixel, i.e., the brightness of the black grayscale, the initialization voltage Vinit may have to be set to a voltage lower than the threshold voltage of the light-emitting element EL.

[0198] The method of driving the pixel circuit may include an initialization phase INIT, a sampling phase SMPL set after the initialization phase INIT, an addressing phase WR set after the sampling phase SMPL, and an emission phase EMIS set after the addressing phase WR.

[0199] The first scan pulse SC1 can be generated as the gate on-state voltage VGH synchronously with the pixel data voltage Vdata during the addressing phase WR. The first scan pulse SC1 can also be the gate off-state voltage VGL during the initialization phase INIT, the sampling phase SMPL, and the emission phase EMIS.

[0200] The second scan pulse SC2 can be generated as the gate on-state voltage VGH during the initialization phase (INIT) and the sampling phase (SMPL). The second scan pulse SC2 can also be the gate off-state voltage VGL during the addressing phase (WR) and the emitter phase (EMIS).

[0201] The third scan pulse SC3 can be generated as the gate on-state voltage VGH during the initialization phase (INIT). The third scan pulse SC3 can also be the gate off-state voltage VGL during the sampling phase (SMPL), the addressing phase (WR), and the emitter phase (EMIS).

[0202] The first EM pulse EM1 can be the gate cutoff voltage VEL in the initialization phase INIT and the addressing phase WR. However, this specification is limited to this, and the first EM pulse EM1 can also be generated as the gate on-state voltage VEH in the initialization phase INIT. The first EM pulse EM1 can also be the gate on-state voltage VEH in the sampling phase SMPL and the emitter phase EMIS.

[0203] A second EM pulse EM2 can be generated as the gate turn-on voltage VEH during the initialization phase (INIT) and the emission phase (EMIS). The second EM pulse EM2 can also be the gate turn-off voltage VEL during the sampling phase (SMPL) and the addressing phase (WR).

[0204] Each of the switching elements M1 to M5 can be turned on when gate on-voltages VGH and VEH are applied to its gate electrode, and can be turned off when gate off-voltages VGL and VEL are applied to its gate electrode. The driving element DT can be turned on when the gate-source voltage Vgs is higher than the threshold voltage Vth, and can generate current according to the gate-source voltage Vgs to drive the light-emitting element EL.

[0205] The light-emitting element (EL) can be implemented as an OLED. An OLED may include an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0206] The anode of the light-emitting element EL can be connected to the fourth node n4, and the cathode can be connected to the VSS node where a low-potential power supply voltage ELVSS is applied. The VSS node can be connected to the VSS line.

[0207] When a voltage is applied to the anode and cathode electrodes of a light-emitting element (EL), holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) can move to the emitter layer (EML) to form excitons. In this case, light can be emitted from the emitter layer (EML). The wavelength of the light can be the visible light band.

[0208] The driving element DT may include a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD, and a third electrode connected to the third node DRS. Therefore, the voltage applied to each electrode of the driving element DT may be equal to the voltages of the first node DRD, DRG, and the third node DRS.

[0209] The first capacitor C1 is connected between the second node DRG and the third node DRS. The first capacitor C1 can store the gate-source voltage Vgs of the driving element DT.

[0210] The second capacitor C2 can be connected between the third node DRS and the VDD line. The pixel drive voltage ELVDD can be applied to the VDD line.

[0211] The transmission rate of the data voltage Vdata can be determined from the gate-source voltage Vgs of the driving element DT based on the capacitance ratio of the first capacitor C1 and the second capacitor C2. The capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be appropriately selected based on the voltage range of the data voltage Vdata and the driving characteristics of the display panel.

[0212] In the pixel circuit, the gate-source voltage Vgs of the driving element DT in the emission phase EMIS can be given by Vgs = 1 - C' × (Vdata - Vref) + Vth. This can be expressed as C' = C1 / (C1 + C2). If C2 = 0, then C' = 1, and in the above formula, 1 - C' becomes 0 (zero), resulting in Vgs = Vth. Therefore, a second capacitor C2 may be needed to change the gate-source voltage Vgs of the driving element DT according to the pixel data voltage Vdata.

[0213] During the addressing phase WR, the first switching element M1 can be turned on according to the gate on-state voltage VGH of the first scan pulse SC1 to provide the data voltage Vdata to the second node DRG. The first switching element M1 may include a gate electrode connected to the first gate line to which the first scan pulse SC1 is applied, a first electrode connected to the data line DL to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0214] The second switching element M2 can be turned on according to the gate on-state voltage VGH of the second scan pulse SC2 to provide a reference voltage Vref to the second node DRG during the initialization phase INIT and the sampling phase SMPL. The second switching element M2 may include a gate electrode connected to the second gate line to which the second scan pulse SC2 is applied, a first electrode connected to the reference line to which the reference voltage Vref is applied, and a second electrode connected to the second node DRG.

[0215] When the data voltage Vdata and reference voltage Vref are applied to the pixel circuit via the data line DL, the number of transitions applied to the data line DL can be increased. Therefore, the frequency can be increased, and the power consumption of the display device can be increased.

[0216] Conversely, in this embodiment, since the data line DL to which the data voltage Vdata is applied and the reference line to which the reference voltage Vref is applied are separated, the frequency of the voltage applied to the data line DL is reduced, thereby reducing power consumption.

[0217] During the initialization phase INIT, the third switching element M3 can be turned on according to the gate on-state voltage VGH of the third scan pulse SC3 to apply the initialization voltage Vinit to the third node DRS. The third switching element M3 may include a gate electrode connected to the third gate line to which the third scan pulse SC3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the INIT line to which the initialization voltage Vinit is applied.

[0218] The fourth switching element M4 can be turned off according to the gate cutoff voltage VEL of the first EM pulse EM1 to block the current path between the VDD line applied by the pixel drive voltage ELVDD and the first node DRD during the initialization phase (INIT) and the addressing phase (WR). During the sampling phase (SMPL) and the emission phase (EMIS), the fourth switching element M4 can be turned on according to the gate turn-on voltage VEH of the first EM pulse EM1 to connect the VDD line to the first node DRD. The fourth switching element M4 may include a gate electrode connected to the fourth gate line to which the first EM pulse EM1 is applied, a first electrode connected to the VDD line, and a second electrode connected to the first node DRD.

[0219] The fifth switching element M5 can be turned off according to the gate cutoff voltage VEL of the second EM pulse EM2 to block the current path between the third node DRS and the fourth node n4 during the sampling phase SMPL and the addressing phase WR. The fifth switching element M5 can be turned on according to the gate turn-on voltage VEH of the second EM pulse EM2 to form a current path between the driving element DT and the light-emitting element EL during the initialization phase INIT and the emission phase EMIS. The fifth switching element M5 may include a gate electrode connected to the fifth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the fourth node n4.

[0220] Figure 8 This is shown in the initialization phase according to Figure 6 A diagram of the current flowing in the pixel circuit.

[0221] refer to Figure 8 During the initialization phase (INIT), the second, third, and fifth switching elements M2, M3, and M5 can be turned on. During the initialization phase (INIT), the first switching element M1 and the fourth switching element M4 can be turned off. During the initialization phase (INIT), the voltage of the master node is given by DRD = Vref + Vth, DRG = Vref, and DRS = Vinit. Here, "Vth" is the threshold voltage of the driving element DT. Therefore, since the gate-source voltage Vgs of the driving element DT is greater than the threshold voltage Vth in the initialization phase (INIT), the driving element DT can be turned on.

[0222] Figure 9 This shows that during the sampling phase, according to Figure 6 A diagram of the current flowing in the pixel circuit.

[0223] refer to Figure 9 During the sampling phase SMPL, the second switching element M2 and the fourth switching element M4 can be turned on, while the other switching elements M1, M3, and M5 can be turned off. During the sampling phase SMPL, when the voltage of the third node DRS rises and the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the driving element DT can be turned off. At the end of the sampling phase SMPL, the voltage of the master node is given by DRD = ELVDD, DRG = Vref, and DRS = Vref - Vth. Therefore, at the end of the sampling phase SMPL, the gate-source voltage Vgs of the driving element DT is Vgs = Vth. The threshold voltage Vth of the driving element DT sampled in this way can be charged to the first capacitor C1.

[0224] Figure 10 This indicates that during the addressing phase, according to Figure 6 A diagram of the current flowing in the pixel circuit.

[0225] refer to Figure 10 During the addressing phase WR, the first switching element M1 can be turned on, allowing the pixel data voltage Vdata to be applied to the second node DRG. In this case, other switching elements M2, M3, M4, and M5 can be turned off. At the end of the addressing phase WR, the voltage of the master node changes to DRD = ELVDD, DRG = Vdata, and DRS = Vref - Vth + C' × (Vdata - Vref). Here, C' = C1 / (1 + C2). During the addressing phase WR, the gate-source voltage Vgs of the driving element DT changes to Vgs = (1 - C') × (Vdata - Vref) + Vth.

[0226] In the sampling phase SMPL and the addressing phase WR, the third node DRS can be electrically decoupled from the fourth node n4. As a result, the threshold voltage sampling and data addressing of the driving element DT are not affected by the resistance of the light-emitting element EL and the process deviation of the light-emitting element EL, thus eliminating the influence of the light-emitting element EL on the pixel brightness.

[0227] Figure 11 This shows that during the launch phase, according to Figure 6 A diagram of the current flowing in the pixel circuit.

[0228] refer to Figure 11In the EMIS during the emission phase, the fourth switching element M4 and the fifth switching element M5 can be turned on, while the other switching elements M1, M2, and M3 can be turned off. During the EMIS during the emission phase, the voltage changes at the main node are as follows: DRD = ELVDD, DRG = Vdata, DRS = Vref - Vth + C' × (Vdata - Vref). During the EMIS during the emission phase, the voltage at the third node DRS is equal to the anode voltage Vel of the light-emitting element EL. The gate-source voltage Vgs of the driving element DT in the EMIS during the emission phase is given by Vgs = (1 - C') × (Vdata - Vref) + Vth.

[0229] Figure 12 This is a diagram illustrating the driving cycle of a display device.

[0230] refer to Figure 12 The driving period of the display device may include a first non-display period X1, a second non-display period X2, and an image display period X0. The first non-display period X1 may be defined as the interval from power-on to the start of the first frame. The second non-display period X2 may be defined as the interval from power-off to power-on.

[0231] The image display period X0 may include an effective interval AT for writing data voltage to sub-pixels and a vertical blanking interval VB for which no image data is written. The compensation period may be located outside the effective interval AT. The compensation period may belong to the first non-display period X1, the second non-display period X2, or the vertical blanking interval VB. During the compensation period, the data driver may extract the threshold voltage of the driving transistor and calculate the change in the threshold voltage based on the extracted threshold voltage to generate the compensation data voltage. The compensation cycle may include a programming cycle, a sensing cycle, a sampling cycle, etc.

[0232] The effective interval AT can include frame (N) FR(N) and frame (N+1) FR(N+1) (N is a natural number greater than or equal to 1). The vertical blanking interval VB can be located between frame (N) FR(N) and frame (N+1) FR(N+1).

[0233] According to the embodiment, the display device can control the time interval between power activation signals generated from the power control circuit based on the result sensed in the (N)th frame FR(N).

[0234] Figure 13 It is a waveform diagram showing the timing signal synchronized with the image signal.

[0235] refer to Figure 13The vertical synchronization signal Vsync defines a frame interval of 1 frame. A frame interval of 1 frame can be the sum of the active interval AT and the vertical blanking interval VB. The vertical blanking interval VB can be allocated as a predetermined time between the active interval AT of the Nth frame interval and the active interval AT of the (N+1)th frame interval. The timing controller can receive the data enable signal DE and the input image data during the active interval AT. The data enable signal DE and the input image data may not exist in the vertical blanking interval VB. During the active interval AT, the control circuit can receive the amount of one frame of data to be written to the pixels.

[0236] The horizontal synchronization signal Hsync defines a horizontal period (one horizontal time, 1H). The data enable signal DE defines the effective pixel data range synchronously with the pixel data to be displayed on the display panel. One pulse period of the data enable signal DE is one horizontal period 1H, and the high logic range of the data enable signal DE represents the pixel data input range of one pixel line. One horizontal period 1H is the time required to write data to the pixels of one pixel line on the display panel. Pixel lines can be arranged along the gate line direction and can include pixels connected to the same gate line. Pixels of a pixel line share the gate line to which the gate signal or scan signal is applied, allowing them to be simultaneously addressed to receive pixel data voltages according to the scan signal.

[0237] As can be seen from the data enable signal DE, the display does not need to receive input data during the vertical blanking interval VB. The vertical blanking interval VB can include the vertical synchronization time VS, the vertical leading edge FP, and the vertical trailing edge BP.

[0238] Figure 14 This is a waveform diagram illustrating the method of driving the first EM pulse during the transmission phase. Figure 15 and Figure 16 It is a diagram used to illustrate the cloud-like patterns that occur in a display device. Figure 17 This is a graph showing how the driving current of a pixel line changes over time.

[0239] refer to Figure 14 In the emitter phase EMIS, the on-time of the gate on-voltage ON applied to the first EM pulse EM1 can be controlled. In some embodiments, the first EM pulse EM1 in the emitter phase EMIS may be generated solely by the gate on-voltage ON. In some embodiments, the first EM pulse EM1 can be generated by repeating a period T including the gate on-voltage ON and the gate off-voltage OFF in the emitter phase EMIS. This driving method can be referred to as pulse width modulation (PWM) driving.

[0240] According to the PWM drive, the switching element to which the first EM pulse EM1 is applied during the transmit phase EMIS can repeatedly switch between on and off states. In one embodiment, the switching element to which the first EM pulse EM1 is applied can have a period T including on and off states.

[0241] During PWM driving, brightness can be controlled differently by adjusting the on-time and off-time ratio of the switching element to which the first EM pulse EM1 is applied, while maintaining the same data voltage. Depending on this ratio, the brightness of the pixel can vary.

[0242] refer to Figure 15 and Figure 16 The display device may include a display area AA. For illustrative purposes, it is assumed that the display area AA according to an embodiment of this specification includes first pixel lines to seventh pixel lines PXL1 to PXL7. However, embodiments of this specification are not limited thereto, and the number of pixel lines is not limited to those described below. The symbol “VB” refers to a vertical blanking interval on the time axis and is shown for better understanding.

[0243] Pixels on a single pixel line can share the same gate line to which a gate signal or scan signal is applied. Assuming during the emission phase, the first EM pulse EM1 can be applied simultaneously to pixels in the same pixel row. Therefore, all pixels in the same pixel line can be simultaneously turned on according to the gate on-voltage ON, or turned off according to the gate off-voltage OFF.

[0244] The gate on-state voltage ON and the gate off-state voltage OFF can be sequentially applied to each of the plurality of pixel lines PXL1 to PXL7 shown.

[0245] For example, during the emission phase, four gate cutoff voltages OFF1, OFF2, OFF3, and OFF4 can be applied to the fifth pixel line PXL5. During the emission phase, three gate cutoff voltages OFF1, OFF2, and OFF3 can be applied to the sixth pixel line PXL6. During the emission phase, four gate cutoff voltages OFF1, OFF2, OFF3, and OFF4 can be applied to the seventh pixel line PXL7.

[0246] The gate driver that applies a gate signal, including a first EM pulse EM1, to the pixel circuit may include a shift register. This shift register may include multiple cascaded stages. Depending on the operating sequence of the connected stages, after applying a first gate cutoff voltage OFF1 to the fifth pixel line PXL5, the first gate cutoff voltage OFF1 may be applied to the sixth pixel line PXL6. After applying the first gate cutoff voltage OFF1 to the sixth pixel line PXL6, a second gate cutoff voltage OFF2 may be applied to the seventh pixel line PXL7.

[0247] Since four gate cutoff voltages OFF1, OFF2, OFF3 and OFF4 are applied to the seventh pixel line PXL7, the first gate cutoff voltage OFF1 can be applied to the seventh pixel line PXL7 before the second gate cutoff voltage OFF2 is applied to it.

[0248] The display area AA, which includes multiple pixel lines PXL1 to PXL7, may include a first pixel line PXL1, a third pixel line PXL3, a fifth pixel line PXL5, and a seventh pixel line PXL7, to which four gate cutoff voltages OFF1, OFF2, OFF3, and OFF4 are applied.

[0249] The display area AA may include a second pixel line PXL2, a fourth pixel line PXL4, and a sixth pixel line PXL6, and three gate cutoff voltages OFF1, OFF2, and OFF3 are applied to the second pixel line PXL2, the fourth pixel line PXL4, and the sixth pixel line PXL6.

[0250] For example, in any frame interval, four gate cutoff voltages OFF1, OFF2, OFF3 and OFF4 can be applied to some pixel lines PXL1, PXL3, PXL5 and PXL7, and three gate cutoff voltages OFF1, OFF2 and OFF3 can be applied to other pixel lines PXL2, PXL4 and PXL6.

[0251] When the fourth switching element M4 is driven by the first EM pulse EM1 during the emission phase, there may be a time deviation between the gate cutoff voltages OFF applied to the pixel lines arranged along the scanning direction due to the sequential driving between stages.

[0252] Therefore, among the multiple pixel lines PXL1 to PXL7 arranged along the scanning direction, the number of gate cutoff voltages OFF for "the first EM pulse EM1 applied during the emission phase in any frame interval" may differ.

[0253] As described above, in PWM driving, when the on-time ratio of the switching element applying the first EM pulse EM1 is adjusted, this adjustment may cause brightness variations in multiple pixel lines PXL1 to PXL7, which may result in brightness deviations between the multiple pixel lines PXL1 to PXL7. For example, this brightness deviation can manifest as moiré patterns in a display device. For example, this brightness deviation can be referred to as HBM (Horizontal Band Moiré) phenomenon.

[0254] refer to Figure 17For example, the first EM pulse applied to the first pixel line PXL1 can have a number of gate cutoff voltages that vary over time. For example, during the emission phase, the first pixel line PXL1 can have four gate cutoff voltages OFF1, OFF2, OFF3, and OFF4 at one moment and three gate cutoff voltages OFF1, OFF2, and OFF3 at another moment.

[0255] The difference in the number and / or ratio of gate cutoff voltage OFFs caused by PWM drive during the transmit phase may occur over time, which may affect the drive current Id flowing to the drive element.

[0256] For example, at four time points with gate cutoff voltages (OFF1, OFF2, OFF3, and OFF4), a relatively low drive current Id can flow to the drive element during the emit phase. Conversely, at three time points with gate cutoff voltages (OFF1, OFF2, and OFF3), a relatively high drive current Id can flow to the drive element during the emit phase.

[0257] Due to the variation in the gate cutoff voltage, the drive current Id can vary over time. For example, relatively high currents and relatively low currents can flow alternately.

[0258] Figure 18 This is a graph showing the changes in pixel drive voltage and gate-source voltage over time. Figure 19 This is a graph showing the sampling error. Figure 20 This is a circuit diagram showing the pixels performing the emission phase at a specific time. Figure 21 This is a circuit diagram showing the pixels performing the sampling phase at a specific time.

[0259] refer to Figure 18 As the driving current Id applied to the pixel circuit repeatedly rises and falls, the pixel driving voltage ELVDD can change. The pixel driving voltage ELVDD can be a high potential voltage, or it can be a constant voltage supplied across the display area.

[0260] For example, since an increase in the drive current Id means that the drive element carries a relatively large amount of current, it may consume a relatively large amount of current in the pixel drive voltage ELVDD. This may lead to a decrease in the pixel drive voltage ELVDD.

[0261] For example, since a decrease in the drive current Id means that the drive element carries a relatively small amount of current, a relatively small amount of current may be consumed in the pixel drive voltage ELVDD. This may lead to an increase in the pixel drive voltage ELVDD.

[0262] For example, the pixel drive voltage ELVDD can be repeatedly decreased and increased by the drive current Id.

[0263] Referring to the pixel circuit described above, the third node DRS in the pixel circuit provided in this embodiment can be disposed between the VDD line providing the pixel driving voltage ELVDD and the second capacitor C2. In one embodiment, when the pixel driving voltage ELVDD decreases, the potential of the third node DRS can be reduced by coupling the second capacitor C2. As a result, the gate-source voltage can have a relatively increased value.

[0264] refer to Figure 19 The pixel circuits arranged on multiple pixel lines PXL1 to PXL7 in the display device can repeatedly execute the initialization phase (INIT), sampling phase (SMPL), addressing phase (WR), and emission phase (EMIS) during the driving steps. Typically, the initialization phase (INIT), sampling phase (SMPL), addressing phase (WR), and emission phase (EMIS) can be executed at least once in any frame interval.

[0265] As described above, the gate driver that applies gate signals, including scan signals and transmit control signals, to each of pixel lines PXL1 to PXL7 may include a shift register. The shift register may include multiple cascaded stages and may apply gate signals in the scan direction. The gate signals may be applied sequentially to each row of pixels.

[0266] In one embodiment, one of the pixel lines PXL1 to PXL7 (e.g., the first pixel line PXL1) may be in the emission phase EMIS, and another pixel line among the pixel lines PXL1 to PXL7 (e.g., the third pixel line PXL3) may be in the sampling phase SMPL.

[0267] By sequentially applying gate signals to multiple pixel lines PXL1 to PXL7 over time, the pixel lines PXL1 to PXL7 can be performed in different stages (e.g., any of the initialization stage INIT, sampling stage SMPL, addressing stage WR, and emission stage EMIS). For example, at time t0, when the emission stage EMIS is performed on the first pixel line PXL1, the sampling stage SMPL can be performed on the third pixel line PXL3.

[0268] In the pixel circuit driving method according to the embodiments of this specification, the pixel circuit driving steps performed on the plurality of pixel lines PXL1 to PXL6 may be in different stages (e.g., any one of the initialization stage INIT, sampling stage SMPL, addressing stage WR, and emission stage EMIS).

[0269] For example, during the emission phase, EMIS occurs at time t0 on the first pixel line PXL1, and this emission phase EMIS can affect the pixel drive voltage ELVDD. The pixel drive voltage ELVDD can be a constant voltage that is typically applied not only to the first pixel line PXL1 but also to the other pixel lines PXL2 to PXL7.

[0270] Since the driving stages on each pixel line PXL1-PXL7 are different, if the pixel driving voltage ELVDD is affected by any pixel line (e.g., the first pixel line PXL1), the affected pixel driving voltage ELVDD may be applied to another pixel line where the driving step is in progress (e.g., the third pixel line PXL3), resulting in an error.

[0271] refer to Figure 20 In the driving of pixel circuits, when driving any pixel line (e.g., the first pixel line PXL1) during the emission phase EMIS(t0) at a specific time point t0, a difference in the amount of gate cutoff voltage OFF can occur. This can cause the drive current Id to rise and fall.

[0272] refer to Figure 21 This difference can affect the drive current Id, which in turn can affect the pixel drive voltage ELVDD based on the coupling mechanism of the second capacitor C2 as described above. The pixel drive voltage ELVDD may cause sampling errors on another pixel line (e.g., the third pixel line PXL3), where the sampling phase SMPL(t0) occurs at the same time point t0. These errors can prevent the pixel circuitry from functioning properly and cause brightness deviations, also known as HBM (Horizontal Band Mosaic) phenomena.

[0273] The embodiments described in this specification can solve the aforementioned driving problems in pixel circuits to overcome the HBM phenomenon.

[0274] Figure 22 This is a circuit diagram illustrating a pixel circuit according to a first embodiment of this specification. Figure 23 This is a waveform diagram illustrating a driving method for a pixel circuit according to a first embodiment of this specification. The same reference numerals are assigned to configurations performing substantially the same functions as the aforementioned pixel circuit, and repeated detailed descriptions are omitted.

[0275] refer to Figure 22 and Figure 23 The pixel circuit may include a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, multiple switching elements M1 to M5, a first capacitor C1, and a second capacitor C2. The driving element DT and the switching elements M1, M2, M3, M41, M42, and M5 may be implemented as n-channel transistors.

[0276] The first EM pulses EM11 and EM12 and the fourth switching elements M41 and M42 can be implemented in multiple ways. For example, the fourth switching elements M41 and M42 may include a fourth-first switching element M41 to which the first-first EM pulse EM11 is applied to its gate electrode and a fourth-second switching element M42 to which the first-second EM pulse EM12 is applied to its gate electrode.

[0277] In one embodiment, EMIS1 and EMIS2 during the emission phase can be driven by PWM.

[0278] The emission phases EMIS1 and EMIS2 can be implemented in multiple stages. Emission phases EMIS1 and EMIS2 may include a first emission phase EMIS1, in which a first-1 EM pulse EM11 including the gate on-state voltage VEH and a first-2 EM pulse EM12 including only the gate off-state voltage VEL are applied. Emission phases EMIS1 and EMIS2 may include a second emission phase EMIS2, in which a first-2 EM pulse EM12 including the gate on-state voltage VEH and a first-1 EM pulse EM11 including only the gate off-state voltage VEL are applied. In the driving steps of the pixel circuit provided in this embodiment, the first emission phase EMIS1 and the second emission phase EMIS2 can be repeated alternately.

[0279] The fourth switching element M4 may include a fourth-first switching element M41, which is turned on in the first emission phase EMIS1 according to the gate turn-on voltage VEH of the first-first EM pulse EM11 and turned off in the second emission phase EMIS2 according to the gate turn-off voltage VEL of the first-first EM pulse EM11.

[0280] The 4-1 switching element M41 may include a gate electrode for applying the 1-1 EM pulse EM11, a first electrode connected to the VDD line for applying the pixel drive voltage ELVDD, and a second electrode connected to the first node DRD.

[0281] The fourth switching element M4 may include a fourth-second switching element M42, which is turned off in the first emission phase EMIS1 according to the gate cutoff voltage VEL of the first-second EM pulse EM12, and turned on in the second emission phase EMIS2 according to the gate turn-on voltage VEH of the first-second EM pulse EM12.

[0282] The 4-2 switching element M42 may include a gate electrode for applying the 1-2 EM pulse EM12, a first electrode connected to the VDD line for applying the pixel drive voltage ELVDD, and a second electrode connected to the first node DRD.

[0283] Figure 24 This is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the initialization phase. Figure 25 This is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the sampling phase. Figure 26 This is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the addressing phase. Figure 27 This is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the first emission phase. Figure 28 This is a diagram showing the current flowing in the pixel circuit according to the first embodiment during the second emission phase.

[0284] refer to Figure 24 During the initialization phase (INIT), the second switching element M2, the third switching element M3, the third switching element M41, the third switching element M42, and the fifth switching element M5 can be turned on.

[0285] refer to Figure 25 During the sampling phase SMPL, the second switching element M2, the fourth switching element M41 and the fourth switching element M42 can be turned on, while the other switching elements M1, M3 and M5 can be turned off.

[0286] refer to Figure 26 During the addressing phase WR, the first switching element M1 is turned on, allowing the pixel data voltage Vdata to be applied to the second node DRG. Switching elements M41 and M42, which are 4-1 and 4-2 respectively, can be turned off.

[0287] refer to Figure 27 In the first transmission phase EMIS1, the fourth switching element M41 and the fifth switching element M5 can be turned on, while the other switching elements M1, M2, M3 and M42 can be turned off.

[0288] refer to Figure 28 In the second transmission phase EMIS2, the fourth and fifth switching elements M42 and M5 can be turned on, while the other switching elements M1, M2, M3 and M41 are turned off.

[0289] Figure 29 This is a waveform diagram showing the period of the first EM pulse.

[0290] refer to Figure 29 In the case of PWM driving via the first EM pulse EM1 in the EMIS during the emission phase, the brightness can be changed by adjusting the ratio of the on and off times of the switching element applying the first EM pulse EM1, as described above. Depending on this ratio, the brightness of the pixel can vary.

[0291] When the first EM pulse EM1 is divided into the first-1 EM pulse EM11 and the first-2 EM pulse EM12 to adjust the difference in the number of gate cutoff voltages OFF, the brightness of the pixel can vary depending on the on or off time of the switching element to which the EM pulses EM11 and EM12 are applied.

[0292] In one embodiment, the period T of the first EM pulse EM11 can be substantially the same as the period T of the first EM pulse EM1. The period T of the first EM pulse EM12 can be substantially the same as the period T of the first EM pulse EM1.

[0293] During the cycle, the first EM pulse EM11 can be driven to a first gate on voltage ON1 and a first gate off voltage OFF1. During the cycle, the first EM pulse EM12 can be driven to a second gate on voltage ON2 and a second gate off voltage OFF2.

[0294] In one embodiment, when the first-1 EM pulse EM11 is within the range of the first gate on-voltage ON1, the first-2 EM pulse EM12 may be within the range of the second gate off-voltage OFF2. When the first-2 EM pulse EM12 is within the range of the second gate on-voltage ON2, the first-1 EM pulse EM11 may be within the range of the first gate off-voltage OFF1.

[0295] In one embodiment, when the first-1 EM pulse EM11 is within the range of the first gate cutoff voltage OFF1, the first-2 EM pulse EM12 may include a range within the range of the second gate on voltage ON2 and a range within the range of the second gate cutoff voltage OFF2. When the first-2 EM pulse EM12 is within the range of the second gate cutoff voltage OFF2, the first-1 EM pulse EM11 may include a range within the range of the first gate on voltage ON1 and a range within the range of the first gate cutoff voltage OFF1.

[0296] For example, the sum of the time during which the first EM pulse EM11 is driven to the first gate on-voltage ON1 and the time during which the first EM pulse EM12 is driven to the second gate on-voltage ON2 during a period T can be equal to the time during which the first EM pulse EM1 is driven to the gate on-voltage ON during a period T.

[0297] For example, the first EM pulse EM1 can have a duty cycle of 100k%. k can be any real number greater than or equal to 0 and less than or equal to 1.

[0298] The duty cycle of the first-1 EM pulse EM11 and the first-2 EM pulse EM12 can be 100k / 2%.

[0299] In one embodiment, the time kT / 2 during which the second gate on-voltage ON2 is applied by the first-second EM pulse EM12 may overlap with the time (1-k / 2)T during which the first gate off-voltage OFF1 is applied. For example, the time (1-k)T / 2 during which the second gate on-voltage ON2 is applied may be equal to the time (1-k / 2)T during which the first gate off-voltage OFF1 is applied, but the embodiments described herein are not limited thereto.

[0300] For example, k can be 0.8. The first EM pulse EM1 has an 80% duty cycle. The duty cycles of the first-1 EM pulse EM11 and the first-2 EM pulse EM12 are 40%. The first gate cutoff voltage OFF1 is applied for 0.6 T. The second gate turn-on voltage ON2 is applied for the same time as the first gate turn-on voltage ON1, each time being 0.4 T. As shown, starting from the time the first gate cutoff voltage OFF1 is applied, excluding the time the second gate turn-on voltage ON2 is applied (which is 0.4 T), the total time the first gate cutoff voltage OFF1 is applied is 0.2 T, which is equal to the time the gate cutoff voltage OFF is applied in the first-1 EM pulse EM1 (which is 0.2 T). When the 0.2 T time the first gate cutoff voltage OFF1 is applied, obtained by excluding the time the second gate turn-on voltage ON2 is applied, is uniformly distributed within time T, each is 0.1 T. However, this is not limited to this and can be non-uniformly distributed.

[0301] In the embodiments of this specification, if the sum of the time during which the first EM pulse EM11 is driven to the first gate on-voltage ON1 and the time during which the first EM pulse EM12 is driven to the second gate on-voltage ON2 is equal to the time during which the first EM pulse EM1 is driven to the gate on-voltage ON within the period, then the ratio of the gate on-voltage ON1 and ON2 driven in the EMIS during the entire emission phase can be substantially the same as the duty cycle in the first EM pulse EM1.

[0302] Therefore, the amount of variation in gate cutoff voltage can be reduced without changing the brightness of the pixels, and a display device with improved moiré patterns can be provided.

[0303] Figure 30 This is a diagram used to illustrate a display device with improved cloud-like patterns. Figure 31 This is a schematic diagram showing how the driving current of a pixel line changes over time. Figure 32 This is a graph showing the changes in pixel drive voltage and gate-source voltage over time.

[0304] refer to Figure 30The display device may include a display area AA. For ease of explanation, it is assumed that the display area AA according to an embodiment of this specification includes first pixel lines to seventh pixel lines PXL1 to PXL7. However, embodiments of this specification are not limited thereto, and the number of pixel lines is not limited, as described below. The symbol "VB" refers to the vertical blanking interval on the time axis, shown for better understanding.

[0305] The display area AA may include first pixel line PXL1 to seventh pixel line PXL7, and seven gate cutoff voltages OFF1, OFF2, OFF3, OFF4, OFF5, OFF6 and OFF7 are applied to the first pixel line PXL1 to the seventh pixel line PXL7.

[0306] The display area AA may include first pixel line PXL1 to seventh pixel line PXL7, and seven gate cutoff voltages OFF1 to OFF7 are applied to first pixel line PXL1 to seventh pixel line PXL7 during the emission phase.

[0307] For example, in any frame interval, seven gate cutoff voltages OFF1 to OFF7 can be applied to the first pixel line PXL1 to the seventh pixel line PXL7.

[0308] Among the multiple pixel lines PXL1 to PXL7 arranged along the scanning direction, the number of gate cutoff voltages OFF for "the first EM pulse EM1 applied during the emission phase in any frame interval" may be the same.

[0309] For example, when repeating the first and second emission phases, the number of gate cutoff voltages OFF1, OFF3, OFF5, and OFF7 in the first-1 EM pulse can be four, and the number of gate cutoff voltages OFF2, OFF4, and OFF6 in the first-1 EM pulse can be three. Alternatively, the number of gate cutoff voltages OFF2, OFF4, and OFF6 in the first-1 EM pulse can be three, and the number of gate cutoff voltages OFF1, OFF3, OFF5, and OFF7 in the first-1 EM pulse can be four. However, this is not a limitation.

[0310] With the formation of the 4-1 and 4-2 switching elements, from the perspective of connecting or blocking the current path between the VDD line and the first node, the number of gate cutoff voltages OFF1 to OFF7 may not differ.

[0311] refer to Figure 31 The driving current Id between multiple pixel lines PXL1 to PXL7 can remain unchanged.

[0312] refer to Figure 32The drive current Id can be constant and does not change over time. Furthermore, the pixel drive voltage ELVDD remains unchanged, and the gate-source voltage can also remain constant.

[0313] Figure 33 This is a graph used to illustrate the relationship between the number of pixel rows and the number of cutoffs for the 1-1 EM pulse. Figure 34 It is a graph illustrating how the driving current of a pixel line changes over time.

[0314] refer to Figure 33 The display device may include a display area AA. The display area AA may include first to Nth pixel lines PXL1, PXL2, ..., PXL(N-1) and PXL(N).

[0315] When applying the pixel circuit according to the embodiments of this specification, M gate cutoff voltages OFF1, OFF2, ... and OFF(M) can be applied to each pixel line driven by PWM during the emission phase.

[0316] refer to Figure 33 and Figure 34 The time t1 corresponding to the vertical blanking VB can be proportional to the value obtained by dividing N pixel lines by M. N can be set as a multiple of M, but the embodiments in this specification are not limited thereto. In a preferred embodiment, both N and M can be integers. In this case, M gate cutoff voltages OFF1, OFF2, ..., OFF(M-1) and OFF(M) can be applied to the first pixel line PXL1 for a time obtained by multiplying the time t1 corresponding to the vertical blanking VB by M.

[0317] For example, N can be 2660. The display device can have a vertical resolution of 2660. Preferably, M can be set to 7. However, it is not limited to this, and M can also be 8. If M is 7, then the time t1 corresponding to the vertical blanking VB can be proportional to 380, where 380 is 2660 divided by 7. For example, the time required to scan 2660 pixel rows can be proportional to 2660.

[0318] For example, if the time required to drive one pixel line is "a", then the time AT required to drive 2660 pixel lines could be 2660a. The driving time can be set by taking into account the fact that the driving of each pixel line overlaps with each other (see [link to documentation]). Figure 15 and Figure 19 ).

[0319] If M is 7, then the time t1 corresponding to the vertical blanking VB can be proportional to 380a, which is 2660a divided by 7.

[0320] For example, N can be 2640. The display device can have a vertical resolution of 2640. Preferably, M can be set to 8. If M is 8, then the time t1 corresponding to the vertical blanking VB can be proportional to 380, where 380 is 2640 divided by 8. For example, the time required to scan 2640 pixel rows can be proportional to 2640.

[0321] For example, if the time required to drive one pixel line is 'a', then the time AT required to drive 2640 pixel lines could be 2640a. If M is 8, then the time t1 corresponding to the vertical blanking VB can be proportional to 380a, which is 2640a divided by 8.

[0322] When applying the pixel circuit according to the embodiments of this specification, it is possible to consider N pixel lines and set the number M of gate cutoff voltages OFF1, OFF2, ..., OFF(M-1) and OFF(M) to be applied to each pixel line during the emission phase.

[0323] During the emission phase, substantially the same number M of gate cutoff voltages are applied to all pixel lines, and the drive current Id can be substantially constant. Therefore, variations in the pixel drive voltage supplied during the sampling phase can be avoided, thereby providing improved moiré patterns for the display device.

[0324] Figure 35 This is a circuit diagram illustrating a pixel circuit according to a second embodiment of this specification. Figure 36 This is a waveform diagram illustrating a driving method for a pixel circuit according to a second embodiment of this specification.

[0325] refer to Figure 35 and Figure 36 Compared with the first embodiment described above, the fifth switching element arranged between the third node DRS and the fourth node n4 may not be included.

[0326] Referring to the driving method of the first embodiment described above, the third scan pulse SC3 is generated as the gate on-state voltage VGH during the sampling phase SMPL and the addressing phase WR, but due to the presence of the fifth switching element, it does not significantly affect the driving element DT.

[0327] The difference in this embodiment is that it does not include a fifth switching element, but instead generates a third scan pulse SC3 as the gate cutoff voltage VGL during the sampling phase SMPL and the addressing phase WR.

[0328] Figure 37 This is a circuit diagram illustrating a pixel circuit according to a third embodiment of this specification. Figure 38 This is a view illustrating a driving method for a pixel circuit according to a third embodiment of this specification.

[0329] refer to Figure 37 and 38 This embodiment can be a pixel circuit implemented in the form of diode connections.

[0330] During the sampling / addressing phase SMPL / WR, the first switching element M1 can be turned on according to the gate on-state voltage VGH of the first scan pulse SC1 to provide the data voltage Vdata to the third node DRS. The first switching element M1 may include a gate electrode connected to the first gate line to which the first scan pulse SC1 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the data line DL to which the data voltage Vdata is applied.

[0331] During the initialization phase (INIT) and the sampling / addressing phase (SMPL / WR), the second switching element M2 can be turned on according to the gate on-state voltage (VGH) of the second scan pulse (SC2) to connect its first electrode and the gate electrode of the first driving element (DT1). The second switching element M2 may include a gate electrode connected to the second gate line to which the second scan pulse (SC21) is applied, a first electrode connected to the second node (DRG), and a second electrode connected to the first node (DRD).

[0332] The first capacitor C1 can be connected between the second node DRG and the fourth node n4.

[0333] A second EM pulse EM2 can be generated as a gate high voltage VEH during the initialization phase INIT and the sampling / addressing phase SMPL / WR. The second EM pulse EM2 can also be generated at the gate low voltage VEL during the emit phases EMIS1 and EMIS2.

[0334] In one embodiment, the fifth switching element M5 can be implemented as a p-channel transistor, and the third switching element M3 can be implemented as an n-channel transistor.

[0335] When the second EM pulse EM2 is generated as a high gate voltage VEH, the fifth switching element M5 can be turned off and the third switching element M3 can be turned on. When the second EM pulse EM2 is generated as a low gate voltage VEL, the fifth switching element M5 can be turned on and the third switching element M3 can be turned off.

[0336] The third switching element M3 can be turned on according to the gate high voltage VEH of the second EM pulse EM2 to apply the initialization voltage Vinit to the fourth node n4 during the initialization phase INIT (sampling / addressing phase SMPL / WR). The third switching element M3 may include a gate electrode connected to the fifth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the INIT line to which the initialization voltage Vinit is applied.

[0337] During the initialization phase INIT (Sampling / Addressing Phase SMPL / WR), the fifth switching element M5 can be turned off based on the gate high voltage VEH of the second EM pulse EM2 to prevent current from flowing between the third node DRS and the fourth node n4. The fifth switching element M5 can be turned on based on the gate low voltage VEL of the second EM pulse EM2 to generate current flowing between the driving element DT and the light-emitting element EL during the emission phases EMIS1 and EMIS2. The fifth switching element M5 may include a gate electrode connected to the fifth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the fourth node n4.

[0338] Although embodiments of this specification have been described in more detail with reference to the accompanying drawings, this specification is not necessarily limited to such embodiments, and various modifications may be made within its scope without departing from the technical spirit of this specification.

[0339] Therefore, the embodiments disclosed herein are provided for illustrative purposes and are not intended to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited to these embodiments.

[0340] Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

[0341] The scope of protection of this specification shall be interpreted based on the appended claims, and all technical concepts within the equivalent scope shall be understood to fall within the scope of this specification.

Claims

1. A pixel circuit comprising: a first node connected to a VDD line configured to be applied with a first constant voltage; a third node connected to a fourth node connected with a light emitting element; a 4-1 switching element arranged between the VDD line and the first node; and a 4-2 switching element arranged between the VDD line and the first node, wherein an initialization phase, a sampling phase, an addressing phase, and an emission phase are configured to be repeatedly performed during a driving step, and wherein, in the emission phase, the 4-1 switching element and the 4-2 switching element are configured to be PWM-driven. the emission phase includes:

2. The pixel circuit of claim 1, wherein, a first emission phase in which a 1-1 EM pulse including a gate-on voltage and a 1-2 EM pulse including only a gate-off voltage are applied, and a second emission phase in which the 1-2 EM pulse including the gate-on voltage and the 1-1 EM pulse including only the gate-off voltage are applied. the 1-1 EM pulse is configured to be applied to a gate electrode of the 4-1 switching element, and 3. The pixel circuit of claim 2, wherein, the 1-2 EM pulse is configured to be applied to a gate electrode of the 4-2 switching element. the emission phase is performed by alternately repeating the first emission phase and the second emission phase.

4. The pixel circuit of claim 2, wherein, the 4-1 switching element includes a gate electrode connected to receive the 1-1 EM pulse, a first electrode connected with the VDD line, and a second electrode connected with the first node, and 5. The pixel circuit of claim 2, wherein, the 4-2 switching element includes a gate electrode connected to receive the 1-2 EM pulse, a first electrode connected with the VDD line, and a second electrode connected with the first node. the emission phase is performed by alternately repeating the first emission phase and the second emission phase, and 6. The pixel circuit of claim 5, wherein, the 1-1 EM pulse includes the gate-on voltage and the gate-off voltage in the first emission phase, and the gate-off voltage in the second emission phase. the emission phase is performed by alternately repeating the first emission phase and the second emission phase, and 7. The pixel circuit of claim 5, wherein, the 1-2 EM pulse includes the gate-off voltage in the first emission phase, and the gate-on voltage and the gate-off voltage in the second emission phase.

8. The pixel circuit according to claim 5, wherein: in an interval in which the 1-1 EM pulse is at the gate-on voltage, the 1-2 EM pulse is at the gate-off voltage, and in an interval in which the 1-2 EM pulse is at the gate-on voltage, the 1-1 EM pulse is at the gate-off voltage.

9. The pixel circuit according to claim 5, wherein: in an interval in which the 1-1 EM pulse is at the gate-off voltage, the 1-2 EM pulse includes an interval at the gate-on voltage and an interval at the gate-off voltage, and in an interval in which the 1-2 EM pulse is at the gate-off voltage, the 1-1 EM pulse includes an interval at the gate-on voltage and an interval at the gate-off voltage. The first-1 EM pulse includes a section at a gate-on voltage and a section at a gate-off voltage in a section where the first-2 EM pulse is at the gate-off voltage.

10. The pixel circuit of claim 1, wherein, The first constant voltage is a pixel driving voltage.

11. A display device comprising: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, a plurality of power supply lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power supply lines are provided; a data driver configured to supply a data voltage of pixel data to the data lines; and a gate driver configured to supply a gate signal to the gate lines, wherein each of the plurality of pixel circuits includes: a first node connected to a VDD line configured to be applied with a first constant voltage; a third node connected to a fourth node connected to a light emitting element; a fourth-1 switching element arranged between the VDD line and the first node; and a fourth-2 switching element arranged between the VDD line and the first node, wherein the pixel circuit is configured to repeatedly perform, in a driving step, an initialization phase, a sampling phase, an addressing phase, and an emission phase, and wherein, in the emission phase, the fourth-1 switching element and the fourth-2 switching element are configured to be PWM-driven.

12. The display device according to claim 11, wherein: the display panel includes a plurality of pixel lines, each of the plurality of pixel lines includes a plurality of pixels, each of the plurality of pixels includes the pixel circuit, and each of the plurality of pixel lines shares one of the gate lines.

13. The display device of claim 12, wherein, during the driving step, the emission phase is performed on one of the plurality of pixel lines, and the sampling phase is performed on another of the plurality of pixel lines.

14. The display device of claim 11, wherein, each of the plurality of pixel circuits further includes: a driving element including a gate electrode connected to a second node, a first electrode connected to the first node, and a second electrode connected to the third node.

15. The display device of claim 14, wherein, each of the plurality of pixel circuits further includes: a third switching element including a gate electrode, a first electrode connected to the fourth node, and a second electrode configured to be applied with a third constant voltage.

16. The display device of claim 15, wherein, each of the plurality of pixel circuits further includes: a first switching element including a gate electrode connected to a first gate line configured to be applied with a first scan pulse, a first electrode connected to a data line configured to be applied with a data voltage, and a second electrode connected to the second node; and a second switching element including a gate electrode connected to a second gate line configured to be applied with a second scan pulse, a first electrode connected to a reference line configured to be applied with a second constant voltage, and a second electrode connected to the second node.

17. The display device of claim 16, wherein, Each of the plurality of pixel circuits further includes: a second capacitor connected between the third node and the VDD line.

18. The display device of claim 16, wherein, Each of the plurality of pixel circuits further includes: a fifth switching element including a gate electrode connected to a fifth gate line configured to be applied with a second EM pulse, a first electrode connected to the third node, and a second electrode connected to the fourth node, wherein the gate electrode of the third switching element is connected to a third gate line configured to be applied with a third scan pulse.

19. The display device of claim 15, wherein, Each of the plurality of pixel circuits further includes: a first switching element including a gate electrode connected to a first gate line configured to be applied with a first scan pulse, a first electrode connected to the third node, and a second electrode connected to a data line configured to be applied with a data voltage; and a second switching element including a gate electrode connected to a second gate line configured to be applied with a second scan pulse, a first electrode connected to the second node, and a second electrode connected to the first node.

20. The display device of claim 19, wherein, Each of the plurality of pixel circuits further includes: a fifth switching element including a gate electrode connected to a fifth gate line configured to be applied with a second EM pulse, a first electrode connected to the third node, and a second electrode connected to the fourth node, and wherein the gate electrode of the third switching element is connected to the fifth gate line.

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