Gate driving circuit and display panel and display device including the same

Abstract

The invention discloses a gate driving circuit, and a display panel and a display device including the same. The gate driving circuit includes: a first switching transistor connected between a first gate line and an output node of a first signal transmitter from which a first gate signal is output; a second switching transistor connected to an output node of the first signal transmitter; a first diode connected between the second switching transistor and the first gate line; a third switching transistor connected between a second gate line and an output node of a second signal transmitter from which a second gate signal is output; a fourth switching transistor connected to an output node of the second signal transmitter; and a second diode connected between the fourth switching transistor and the second gate line.

Description

Technical Field

[0001] This disclosure relates to a gating drive circuit, and more specifically, for example, but not limited to, a gating drive circuit capable of reducing power consumption, and a display panel and display device including the gating drive circuit. Background Technology

[0002] Electroluminescent display devices offer advantages such as high responsivity, excellent luminous efficiency, high brightness, and wide viewing angles by positioning self-emissive elements, such as organic light-emitting diodes (hereinafter referred to as "OLEDs"), in each sub-pixel. In addition to high responsivity, excellent luminous efficiency, high brightness, and wide viewing angles, electroluminescent display devices also exhibit excellent contrast and high color reproduction rates because they can represent black grayscale as perfect black. These electroluminescent display devices do not require a backlight unit and can be implemented on flexible materials, such as plastic substrates, thin glass substrates, and metal substrates.

[0003] Various research efforts are underway to further reduce power consumption in electroluminescent display devices. For example, variable refresh rate (VRR) technology can be applied to electroluminescent display devices.

[0004] The description provided in the Background section should not be assumed to be prior art simply because it is mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit this disclosure. Summary of the Invention

[0005] The inventors have recognized that implementing VRR technology requires adding numerous circuit elements to the gating drive circuit, which may lead to a decrease in the yield of the display panel and an increase in the non-display area of ​​the display panel. Therefore, this disclosure aims to address the aforementioned necessity and / or drawbacks.

[0006] This disclosure provides a gating drive circuit that can reduce power consumption, as well as a display panel and display device including the gating drive circuit.

[0007] The purpose of this disclosure is not limited to the issues described above, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] A gating drive circuit according to an exemplary embodiment of the present disclosure includes: a first switching transistor connected between a first gating line and an output node of a first signal transmitter from which a first gating signal is output; a second switching transistor connected to the output node of the first signal transmitter; a first diode connected between the second switching transistor and the first gating line; a third switching transistor connected between a second gating line and an output node of a second signal transmitter from which a second gating signal is output; a fourth switching transistor connected to the output node of the second signal transmitter; and a second diode connected between the fourth switching transistor and the second gating line.

[0009] The first signal transmitter and the second signal transmitter can be cascaded via carry signal wiring.

[0010] Each of the first signal transmitter and the second signal transmitter includes: a first input node that receives a start pulse or carry signal, a second input node connected to a clock wiring that receives a clock signal, and an output node that outputs a strobe signal to sequentially output pulses of the strobe signal.

[0011] In response to selection signals input to the gate electrodes of the first switching transistor and the second switching transistor, respectively, the output node of the first signal transmitter can be selectively connected to the first gating line and the first diode.

[0012] In response to selection signals input to the gate electrodes of the third and fourth switching transistors respectively, the output node of the second signal transmitter can be selectively connected to the second gating line and the second diode.

[0013] The first diode may include a cathode electrode connected to the second switching transistor and an anode electrode connected to the first gate line. The second diode may include a cathode electrode connected to the fourth switching transistor and an anode electrode connected to the second gate line.

[0014] The first diode may include an anode connected to the second switching transistor and a cathode connected to the first gate line. The second diode may include an anode connected to the fourth switching transistor and a cathode connected to the second gate line.

[0015] Each of the first diode and the second diode may include a transistor having a gate electrode connected to one of the first electrode and the second electrode.

[0016] A first signal transmitter may include: a first-first input node to which a start pulse or carry signal is input; and a second-first input node to which a first clock is input. A first strobe signal and a first carry signal can be output through the output node of the first signal transmitter. A second signal transmitter may include a first-second input node to which a first carry signal is input; and a second-second input node to which a second clock having a different phase from the first clock is input. A second strobe signal and a second carry signal can be output through the output node of the second signal transmitter.

[0017] At least one of the first and second gate lines can branch into two gate lines.

[0018] A display panel according to an exemplary embodiment of the present disclosure includes: a display area wherein a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are arranged; and a plurality of gate drivers providing gate signals to the gate lines. At least one of the gate drivers includes: a first switching transistor connected between an output node of a first signal transmitter from which it outputs a first gate signal and a first gate line; a second switching transistor connected to an output node of the first signal transmitter; a first diode connected between the second switching transistor and the first gate line; a third switching transistor connected between an output node of a second signal transmitter from which it outputs a second gate signal and a second gate line; a fourth switching transistor connected to an output node of the second signal transmitter; and a second diode connected between the fourth switching transistor and the second gate line.

[0019] A display device according to an exemplary embodiment of the present disclosure includes: a display panel including a display area having a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels arranged thereon; and a plurality of gate drivers for which gate signals are supplied by the gate lines; and a data driver connected to the data lines. The display area includes at least a first pixel area and a second pixel area having different refresh rates, wherein the sub-pixels of the first pixel area are driven at a first refresh rate, and the sub-pixels of the second pixel area are driven at a second refresh rate lower than the first refresh rate. At least one of the gate drivers includes: a first switching transistor connected between an output node of a first signal transmitter from which it outputs a first gate signal and a first gate line; a second switching transistor connected to an output node of the first signal transmitter; a first diode connected between the second switching transistor and the first gate line; a third switching transistor connected between an output node of a second signal transmitter from which it outputs a second gate signal and the second gate line; a fourth switching transistor connected to an output node of the second signal transmitter; and a second diode connected between the fourth switching transistor and the second gate line.

[0020] According to this disclosure, the refresh rate of a pixel can be varied for each location in the display area by different control of the voltage level or waveform of the gating signal between refresh pixels and skip pixels. Therefore, this disclosure can minimize or reduce power consumption without degrading image quality, thereby achieving low-power driving and long lifespan of the display device.

[0021] According to this disclosure, when the waveform of the strobe signal changes according to the refresh rate, a diode can be used to prevent or reduce strobe signal waveform errors and pixel faults.

[0022] According to this disclosure, the number of transistors added to reduce the waveform of the gating signal and the number of wires connected to these transistors can be reduced by using diodes. Therefore, this disclosure can reduce the area occupied by the gating driver on the display panel.

[0023] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand from the following description and the appended claims other effects not mentioned. Attached Figure Description

[0024] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0025] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 2This is a diagram showing multiple pixel regions in which the pixel driving frequency is independently controlled;

[0027] Figure 3 This is a diagram illustrating a multi-frequency control method for a timing controller;

[0028] Figure 4 This is a circuit diagram illustrating a pixel circuit according to a first exemplary embodiment of the present disclosure;

[0029] Figure 5 This indicates the force applied during the refresh cycle. Figure 4 The waveform diagram of an example of the gating signal for the pixel circuit shown;

[0030] Figure 6 This is a circuit diagram showing the transistors that are turned on / off during the data write step in the refresh cycle;

[0031] Figure 7 This shows the force applied during the frame skip period. Figure 4 The waveform diagram of an example of the gating signal for the pixel circuit shown;

[0032] Figure 8 This is a circuit diagram showing the transistors that are turned on / off during the data skipping step;

[0033] Figure 9 This is a circuit diagram illustrating a pixel circuit according to a second exemplary embodiment of the present disclosure;

[0034] Figure 10 This indicates the force applied during the refresh cycle. Figure 9 The waveform diagram of an example of the gating signal for the pixel circuit shown;

[0035] Figure 11 This is a circuit diagram showing the transistors that are turned on / off during the sampling step in the refresh cycle;

[0036] Figure 12 This is a circuit diagram showing the transistors that are turned on / off during the data write step in the refresh cycle;

[0037] Figure 13 This shows the force applied during the frame skip period. Figure 9 A waveform diagram of an example of the gating signal of the pixel circuit 101 shown;

[0038] Figure 14 This is a circuit diagram showing the transistor in the cutoff state during the hold and data skipping steps of the frame skipping cycle;

[0039] Figure 15 This is a circuit diagram illustrating a pixel circuit according to a third exemplary embodiment of the present disclosure;

[0040] Figure 16 This indicates the force applied during the refresh cycle. Figure 15 The waveform diagram of an example of the gating signal for the pixel circuit shown;

[0041] Figure 17 This is a circuit diagram showing the transistors that are turned on / off during the initialization step in the refresh cycle;

[0042] Figure 18 This is a circuit diagram showing the transistors that are turned on / off during the data write step in the refresh cycle;

[0043] Figure 19 This shows the force applied during the frame skip period. Figure 15 The waveform diagram of an example of the gating signal for the pixel circuit shown;

[0044] Figure 20 This is a circuit diagram showing the transistors in the off state during the hold and data skipping steps in the frame skipping cycle;

[0045] Figure 21 This diagram illustrates the connection structure of sub-pixels and signal wiring that facilitates the simultaneous driving of adjacent pixel rows to ensure sampling time.

[0046] Figure 22 This shows the drive. Figure 4 The diagram shows the first to fourth gating drivers of the pixel circuit.

[0047] Figure 23 This shows the input to Figure 22 The waveforms of the clock and start pulse of the strobe driver are shown below;

[0048] Figure 24 This is a circuit diagram illustrating a signal transmitter circuit of a gating driver according to an exemplary embodiment of the present disclosure;

[0049] Figure 25 This is a circuit diagram showing the switching circuit and diodes of a gating driver according to a first exemplary embodiment of the present disclosure;

[0050] Figure 26 It is shown Figure 25 The waveform diagram of the input / output signals of the gating driver is shown below;

[0051] Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 31A and Figure 31B It is shown step by step on the timeline. Figure 25 The diagram shows the operation of the strobe driver;

[0052] Figure 32 This is a circuit diagram showing the switching circuit and diodes of a gating driver according to a second exemplary embodiment of the present disclosure;

[0053] Figure 33 This is a circuit diagram illustrating the switching circuit and diodes of a gating driver according to a third exemplary embodiment of the present disclosure; and

[0054] Figure 34 It is shown Figure 33 The waveform diagram of the input and output signals of the gating driver is shown.

[0055] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Implementation

[0056] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is illustrative; however, the order of steps and / or operations is not limited to that described herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following explanation may have been chosen merely for convenience in drafting the specification and may therefore differ from the names used in actual products.

[0057] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will make the disclosure complete and allow those skilled in the art to fully understand its scope. This disclosure is limited only to the scope of the appended claims.

[0058] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc., shown in the accompanying drawings used to illustrate embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this disclosure, similar reference numerals generally denote similar elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0059] The dimensions of the various components shown in the accompanying drawings, including size and thickness, are shown for ease of description, and this disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions of the components shown in the various accompanying drawings, including relative size, position, and thickness, are part of this disclosure.

[0060] Terms used herein such as “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed of,” and “composed of” are generally intended to allow for the addition of additional component parts, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0061] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0062] When describing the location or interconnection between two components, terms such as “on top of,” “above,” “above,” “below,” “below,” “next to,” “under,” “near,” “close to,” “adjacent to,” “on the side of,” “close to,” “connected or linked,” “crossing,” “intersecting,” etc., unless “exactly” or “directly” is used, may indicate that one or more other components are inserted between them.

[0063] It should be understood that, in addition to the orientations shown in the figures, spatial relative terms may also include different orientations of elements in use or operation. For example, if an element in the figure is inverted, an element described as "below" or "under" other elements or features would be oriented as "above" other elements or features. Thus, the exemplary term "below" can include both below and above orientations. Similarly, the exemplary terms "above" or "above" can include both "above" and "below" orientations.

[0064] When describing time precedence relationships, terms such as “after,” “following,” “next,” and “before” may not be sequential on a temporal basis unless “immediately” or “directly” is used.

[0065] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or name preceding the component.

[0066] The term "at least one" should be understood to include all possible combinations that can be suggested from one or more related projects. For example, "at least one of the first, second, or third projects" can mean each of the first, second, or third projects, and can also mean all possible combinations that can be suggested from two or more of the first, second, and third projects.

[0067] As used herein, the term "device" can refer to a display device that includes a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. Additionally, examples of devices may include laptops, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as assemblies of electronic devices (or equipment) or assemblies (or devices) that include light-emitting elements, etc., as complete products or end products, such as mobile electronic devices like smartphones or tablets, but embodiments of this disclosure are not limited thereto.

[0068] The following implementation methods may be combined or integrated with each other in part or in whole, and may be linked and operated in different technical ways. The implementation methods may be performed independently or in connection with each other.

[0069] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0070] In the specification, when adding reference numerals to elements in each figure, care should be taken to ensure that, whenever possible, the same reference numerals used to denote the element in other figures are used for that element. Furthermore, for ease of description, the scale of the constituent elements shown in the figures may differ from the actual scale. That is, the scale of the constituent elements shown in the figures should not be interpreted as the same as the scale shown in the figures.

[0071] The pixel circuitry and gating drive circuitry of a display device may include multiple transistors. These transistors may be implemented as thin-film transistors (TFTs).

[0072] The active layer of a thin-film transistor (TFT) can be formed from semiconductor materials, such as oxide semiconductors, amorphous semiconductors, or polycrystalline semiconductors, but is not limited to these.

[0073] Oxide semiconductor materials offer excellent leakage current prevention and relatively low manufacturing costs. Oxide semiconductors can be made from metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals and their oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). Specifically, oxide semiconductors can include, but are not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0074] Polycrystalline semiconductor materials exhibit high mobility due to the fast movement speed of charge carriers such as electrons and holes, resulting in low energy consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited to this.

[0075] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited to this.

[0076] For example, a transistor can be implemented as an oxide thin-film transistor (oxide TFT) including oxide semiconductors, a low-temperature polycrystalline silicon TFT (LTPS TFT) including low-temperature polycrystalline silicon, etc.

[0077] A transistor is a three-electrode device comprising a gate electrode, a source electrode, and a drain electrode. The source electrode is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers initially flow from the source electrode. The drain electrode is the electrode from which charge carriers flow out of the transistor. In a transistor, charge carriers flow from the source electrode to the drain electrode. In the case of an n-channel transistor, since the charge carriers are electrons, the source electrode voltage is lower than the drain electrode voltage, allowing electrons to flow from the source electrode to the drain electrode. An n-channel transistor has a current direction from the drain electrode to the source electrode. In the case of a p-channel transistor, since the charge carriers are holes, the source electrode voltage is higher than the drain electrode voltage, allowing holes to flow from the source electrode to the drain electrode. In a p-channel transistor, since holes flow from the source electrode to the drain electrode, current flows from the source electrode to the drain electrode. It should be noted that the source and drain electrodes of a transistor are not fixed. For example, the source and drain electrodes can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain electrodes of a transistor. In the following description, the source electrode and drain electrode of the transistor will be referred to as the first electrode and the second electrode.

[0078] The gating signal oscillates between a gating on voltage and a gating off voltage. The transistor turns on in response to the gating on voltage and turns off in response to the gating off voltage. In the case of an n-channel transistor, the gating on voltage can be the high gating voltage VGH, and the gating off voltage can be the low gating voltage VGL. In the case of a p-channel transistor, the gating on voltage can be the low gating voltage VGL, and the gating off voltage can be the high gating voltage VGH.

[0079] In the following, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0080] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0081] Reference Figure 1 The display device according to an exemplary embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit.

[0082] Display panel 100 may include a display area (active area) AA for displaying an input image on the screen. A non-display area (passive area) NA may be located outside the display area AA. For example, the non-display area NA may be an area adjacent to the display area AA. Further, the non-display area NA may be an area adjacent to the display area AA and configured to surround the display area AA. The non-display area NA may also be referred to as a non-display area or a border (or border region). The non-display area NA may include a pad area located outside the display area AA in the column direction (e.g., spaced apart from the display area AA). For example, the pad area may be a portion of the non-display area NA. The non-display area NA may completely or only partially surround the display area AA.

[0083] For example, the non-display area NA may include a first non-display area, a second non-display area, a third non-display area, and a fourth non-display area. The first non-display area may be located outside the display area AA in the column direction. The second non-display area may be located outside the display area AA in the row direction. The third non-display area may be located outside the display area AA in the column direction and opposite to the first non-display area. The fourth non-display area may be located outside the display area AA in the row direction and opposite to the second non-display area. The first non-display area among the first to fourth non-display areas may include pad areas for connecting or bonding drive circuitry. The second to fourth non-display areas, excluding pad areas, may have very small dimensions, but this disclosure is not limited thereto.

[0084] In one or more aspects, the boundary region between the display area AA and the non-display area NA may be curved, and in this structure, the non-display area NA may be located below the display area AA.

[0085] The substrate of the display panel 100 can be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited thereto. For example, the substrate may include a flexible polymer film. For example, the flexible polymer film may be made of any of the following: polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyaryl ester (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and this disclosure is not limited thereto. The display panel 100 may be a rectangular panel having a length along the X-axis (or a first direction), a width along the Y-axis (or a second direction), and a thickness along the Z-axis (or a third direction), but is not limited thereto. For example, at least a portion of the display panel 100 may have a curved outer portion.

[0086] Display panel 100 includes wiring such as multiple data lines DL, multiple gate lines GL intersecting the data lines DL, and multiple power lines. The gate lines GL may be parallel to a first direction X on display panel 100, and the data lines DL may be parallel to a second direction Y on display panel 100. Pixel PXL in display area AA is connected to the data lines DL, gate lines GL, and power lines. The power lines may be connected together to pixel PXL to supply the constant voltage required to drive pixel PXL. The power lines may be implemented as elongated wiring in the first or second direction, or as a mesh wiring on display panel 100 electrically connecting the wiring in the first and second directions.

[0087] The display area AA comprises multiple pixel rows L1 to Ln. Here, n can be a real number such as a positive integer. Each of the pixel rows L1 to Ln comprises a row of sub-pixels arranged along a first direction X of the display panel 100. Pixels arranged in a pixel row may share a gating line GL. Sub-pixels arranged in a column along a second direction Y share the same data line DL. A horizontal period is the time obtained by dividing a frame period by the total number of pixel rows L1 to Ln.

[0088] The display panel 100 can be implemented using a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device in which an image is displayed on a screen and an actual object in the background is visible. The display panel 100 can be manufactured as a flexible display panel.

[0089] Each of the multiple subpixels is the smallest unit constituting the display area, and n subpixels form one pixel. Each of the multiple subpixels can emit light with a different wavelength from each other. The multiple subpixels can include a first subpixel, a second subpixel, and a third subpixel that emit light of different colors from each other. For example, each pixel PXL can be divided into red subpixels, green subpixels, and blue subpixels for color implementation. Each pixel can also include a white subpixel. The multiple subpixels can be modified in various ways in terms of color and configuration as needed. However, this disclosure is not limited thereto.

[0090] For example, multiple sub-pixels may include red, green, and blue sub-pixels, wherein the red, green, and blue sub-pixels may be arranged in a repeating manner. Alternatively, multiple sub-pixels may include red, green, blue, and white sub-pixels, wherein the red, green, blue, and white sub-pixels may be arranged in a repeating manner, or the red, green, blue, and white sub-pixels may be arranged in a quadrilateral pattern. For example, the red, blue, and green sub-pixels may be arranged sequentially along the row direction, or the red, blue, green, and white sub-pixels may be arranged sequentially along the row direction. However, in embodiments of this disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not limited and can be configured in various forms according to light-emitting characteristics, device lifetime, and device specifications.

[0091] Furthermore, depending on their light-emitting characteristics, sub-pixels can have different light-emitting areas. For example, a sub-pixel that emits light of a different color than the blue sub-pixel can have a different light-emitting area than the blue sub-pixel. For example, red, blue, and green sub-pixels, or red, blue, white, and green sub-pixels, can each have different light-emitting areas.

[0092] Each subpixel may include pixel circuitry for driving a light-emitting element. Each pixel circuitry may be connected to data lines, gating lines, and power lines. In the following text, "pixel" may be interpreted as "subpixel." Each subpixel includes pixel circuitry for driving a light-emitting element such as an OLED.

[0093] For example, the pixel circuitry of each of the plurality of sub-pixels may include a capacitor, at least one thin-film transistor, and a light-emitting element such as an OLED. For example, the at least one thin-film transistor may include a driving transistor, a first switching transistor, and a second switching transistor. Furthermore, the light-emitting element may include a first electrode / second electrode (or anode electrode, pixel electrode), an inorganic light-emitting layer (or organic light-emitting layer), and a second electrode / first electrode (or cathode electrode, common electrode). However, the pixel circuitry of each of the plurality of sub-pixels is not limited thereto, and each of the plurality of sub-pixels may further include compensation circuitry. In this case, each of the plurality of sub-pixels may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0094] Pixel PXL can be arranged as true-color pixels and pentile pixels, but exemplary embodiments of this disclosure are not limited thereto. By using a preset pixel rendering algorithm to drive two sub-pixels of different colors into a single pixel PXL, pentile pixels can achieve higher resolution than true-color pixels. The pixel rendering algorithm can utilize the colors of light emitted from adjacent pixels PXL to compensate for insufficient color representation in each pixel PXL.

[0095] The driving circuitry of the display panel 100 may include a data driver 110, a gating driver 120, a timing controller 130, a power supply 140, and a level shifter 150. Furthermore, the driving circuitry of the display panel 100 may also include a touch sensor driver. The data driver 110 and the touch sensor driver can be integrated into a single driver integrated circuit (IC). In mobile terminals or wearable terminals, the timing controller 130, power supply 140, level shifter 150, data driver 110, touch sensor driver, etc., can be integrated into a single driver IC.

[0096] The driving circuit of the display panel 100 can be driven at a variable refresh rate (VRR) under the control of the timing controller 130. For example, the timing controller 130 can analyze the input image and reduce the power consumption of the display device by reducing the refresh rate when the input image does not change within a predetermined amount of time. In this case, the driving circuit of the display panel 100 can control the data write cycle of the pixel PXL to become longer by reducing the refresh rate of the pixel PXL when a still image is input for a certain period of time or longer under the control of the timing controller 130, thereby reducing the power consumption of the display device. When the display device operates in standby mode or in response to user commands, the refresh rate of the driving circuit of the display panel 100 can be lower. In addition, the refresh rate can be lower on an always-on display (AOD) screen. An AOD screen is a portion of the pixel area of ​​the display area AA in which predetermined information, such as brief information such as remaining battery power and time, is displayed in standby mode. The refresh rate can be interpreted as the driving frequency of the pixel PXL used to update the data of the pixel.

[0097] The timing controller 130 can control the operation timing of the drivers 110 and 120 of the display panel 100 at a frame rate of input frame rate × i Hz by multiplying the frame rate of the input image by a factor i (where i is a natural number). The timing controller 130 can support variable refresh rates. For example, in low-speed drive mode, the timing controller 130 can reduce the drive frequency of pixel PXL to a frequency between 1 Hz and 30 Hz to reduce the refresh rate of pixel PXL.

[0098] The timing controller 130 can receive pixel data of the input image and timing signals synchronized with the pixel data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, and a data enable signal DE. One period of the vertical synchronization signal Vsync can be one frame period. One period of the horizontal synchronization signal Hsync and the data enable signal DE can be one horizontal period 1H. The pulse of the data enable signal DE can be synchronized with a line of data of pixel PXL to be written to a pixel row. Since the frame period and horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The timing controller 130 can transmit the pixel data of the input image to the data driver 110 and control the timing of the operation of the data driver 110 and the strobe driver 120.

[0099] The timing controller 130 can be configured to connect to various processors, such as microprocessors, mobile processors, application processors, etc., depending on the device installed therein.

[0100] The host system used in the timing controller 130 can be one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0101] The timing controller 130 can be implemented in a separate component from the data driver 110, or integrated with the data driver 110, so that the timing controller 130 and the data driver 110 can be implemented in a single integrated circuit.

[0102] The timing controller 130 may be a timing controller used in typical display technologies, or a control device / apparatus capable of performing additional control functions beyond the typical functions of a timing controller. In one or more embodiments, the timing controller 130 may be one or more other control circuits different from the timing controller, or circuits or components within the control device / apparatus. The timing controller 130 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0103] The timing controller 130 can be mounted on a printed circuit board or flexible printed circuit, and can be electrically connected to the data driver 110 and the strobe driver 120 via the printed circuit board or flexible printed circuit.

[0104] The timing controller 130 can send signals to and receive signals from the data driver 110 via one or more predetermined interfaces. Such interfaces may include, for example, a low-voltage differential signaling (LVDS) interface, an embedded point-to-point clock interface (EPI), a serial peripheral interface (SPI), etc. However, this disclosure is not limited thereto.

[0105] The strobe timing control signal generated from the timing controller 130 can be input to the strobe driver 120 via the level shifter 150.

[0106] The level shifter 150 receives the gating timing control signal and outputs a start pulse, a clock signal, and a selection signal, such as... Figures 22 to 34 As shown. The input signal of level shifter 150 can be a digital signal voltage level signal, and the output signal of level shifter 150 can be an analog voltage signal that swings between a gating high voltage VGH and a gating low voltage VGL. Level shifter 150 can convert a low-level voltage of the gating timing signal output from timing controller 130 to a gating low voltage VGL, and a high-level voltage to a gating high voltage VGH. The output signal of level shifter 150 is input to gating driver 120.

[0107] The output signal of the level shifter 150 can be provided to the gating driver 120 through signal wiring 121. Signal wiring 121 may include clock wiring through which start pulses and clock signals are transmitted, and selection signal wiring through which selection signals are transmitted.

[0108] Data driver 110 can receive pixel data of the input image as a digital signal from timing controller 130 and output a data voltage. Data driver 110 can use a digital-to-analog converter (hereinafter referred to as "DAC") to convert the video data of the input image into a gamma-compensated voltage and output the data voltage. The gamma reference voltage GMA output from power supply 140 can be divided into gamma-compensated voltages for each grayscale level by the voltage distribution circuit of data driver 110 and supplied to the DAC. The DAC can output a data voltage as a gamma-compensated voltage corresponding to the grayscale value of the pixel data. The data voltage output from the DAC can be output from each data output channel of data driver 110 to data line DL via an output buffer.

[0109] The driving circuitry of the display panel 100 may also include a demultiplexer DEMUX located between the data driver 110 and the data line DL. As another example, the demultiplexer can be omitted. The demultiplexer sequentially distributes the data voltages output from the channels of the data driver 110 to the data line DL. Adding a demultiplexer can reduce the number of channels in the data driver 110.

[0110] The gating driver 120 may be located on the display panel 100. The gating driver 120 may be located in a non-display area NA outside the display area AA in the display panel 100, or may be at least partially located in the display area AA. The gating driver 120 may supply a gating signal to the gating line GL in a single-feed manner. In a single-feed manner, the gating signal may be applied to one end of the gating line GL. In a dual-feed manner, the gating signal may be applied from both ends of the gating line GL simultaneously.

[0111] The gating driver 120 may include one or more shift registers and / or edge triggers. The gating driver 120 can control each of the pixel rows L1 to LN as a pixel row in a pixel region with a high refresh rate or as a pixel row in a pixel region with a low refresh rate by changing the frequency of the gating signal applied to the gating line under the control of the timing controller 130.

[0112] Power supply 140 may include a charge pump, regulator, buck converter, and boost converter, but exemplary embodiments of the invention are not limited thereto. Power supply 140 may receive a DC input voltage from host system 200 and generate the power required to drive display panel 100 and its drivers. Power supply 140 may output a constant voltage (or DC voltage), such as a gamma reference voltage GMA, a gating high voltage VGH, and a gating low voltage VGL. Additionally, power supply 140 may output a constant voltage to the pixel circuitry. The gamma reference voltage GMA may be supplied to data driver 110. The gating high voltage VGH and gating low voltage VGL may be supplied to level shifter 150 and gating driver 120. The constant voltage input to the pixel circuitry may be supplied to the pixel via a power line commonly connected to pixel PXL.

[0113] The display device disclosed herein supports a multi-frequency driving method to reduce power consumption without degrading image quality. In the multi-frequency driving method, the display area AA of the display panel 100 can be divided into multiple pixel areas that can be driven at different pixel driving frequencies.

[0114] Figure 2 It is a diagram representing multiple pixel regions where the pixel driving frequency is independently controlled.

[0115] Reference Figure 2 The display area AA may include two or more pixel areas A, B, C, and D. Each pixel area A, B, C, and D may include one or more rows of pixels. The timing controller 130 can independently control the refresh rate of the pixels in each pixel area by controlling the data driver 110 and the strobe driver 120. The timing controller 130 can increase the pixel drive frequency of pixel areas that require high-frequency data updates, while decreasing the pixel drive frequency of pixel areas where image quality degradation cannot be detected even with low-frequency data updates.

[0116] For example, such as Figure 2 As shown, the refresh rates of the first pixel region A and the third pixel region C can be higher than the refresh rates of the second pixel region B and the fourth pixel region D. The pixel driving frequency of the first pixel region A and the third pixel region C can be 120Hz. The pixel driving frequency of the second pixel region B can be 10Hz, and the pixel driving frequency of the fourth pixel region D can be 30Hz. The refresh rate of each of pixel regions A, B, C, and D is not limited to... Figure 2 Each pixel region A, B, C, and D can have a variable refresh rate under the control of the timing controller 130.

[0117] Figure 3 This is a diagram illustrating a multi-frequency control method using a timing controller. In Figure 3In this context, Vsync represents the vertical synchronization signal, SKL represents the skip logic signal generated within the timing controller 130, and Vdata represents the data voltage output from the data driver 110. 1FR is a frame period.

[0118] Reference Figure 3 The timing controller 130 can control frame skipping for each pixel region. A frame cycle may include one or more refresh cycles during which pixel data DATA is updated for pixels, and one or more frame skip cycles during which pixel data is not updated for pixels. Hereinafter, a refreshed pixel region is a pixel region where pixel data DATA is written during a refresh cycle by a strobe signal synchronized with the data voltage. During a refresh cycle, pixel data DATA can be updated for pixels in the refreshed pixel region during the corresponding frame cycle. Furthermore, a skipped pixel region is a pixel region where pixel data DATA is not written during a frame skip cycle and the previous data voltage is maintained. Pixel data DATA is not updated because pixel data is not written to pixels in the skipped pixel region.

[0119] The first logic value of the skip logic signal SKP, such as "1", indicates the area to be refreshed. During the refresh cycle, frame skipping is deactivated, allowing pixel data to be written to the pixel normally. During the refresh cycle, under the control of the timing controller 130, the data driver 110 outputs the data voltage Vdata of the pixel data DATA, and the strobe driver 120 outputs a strobe signal.

[0120] The second logic value of the skip logic signal SKP, such as "0 (zero)," indicates a skipped pixel region. During the frame skip period, frame skipping is activated, allowing pixel data DATA not to be written to pixels in the selected skipped pixel region. During the frame skip period, under the control of the timing controller 130, the data driver 110 does not output the data voltage Vdata, and the gating driver 120 does not output at least one gating signal. Therefore, power consumption can be reduced during the frame skip period because pixels in the skipped pixel region and the data driver are not driven, and at least one gating driver is not driven.

[0121] Figure 4 This is a circuit diagram illustrating a pixel circuit according to a first exemplary embodiment of the present disclosure. Figure 4 The pixel circuit shown can be a pixel circuit of a sub-pixel existing in the nth (n is a natural number) pixel row.

[0122] Reference Figure 4The pixel circuit 101 includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M01 to M07, and a capacitor Cst. Each of the first switching element M01 and the fifth switching element M05 can be implemented as an n-channel oxide TFT with low cutoff current. Cutoff current is the leakage current flowing through the semiconductor channel of the transistor in the off state. Each of the driving element DT, the second switching element M02, the third switching element M03, the fourth switching element M04, the sixth switching element M06, and the seventh switching element M07 can be implemented as a p-channel LTPS TFT with high on-current.

[0123] The pixel circuit 101 is connected to the data line DL, to which the data voltage Vdata of the pixel data is applied, and to the gating lines GL1 to GL5, to which gating signals SC1(n) to SC4(n) and EM(n) are applied.

[0124] The pixel circuit 101 can be connected to power supply nodes that apply constant voltages, such as constant voltage node PL1 applying the pixel drive voltage ELVDD, constant voltage node PL2 applying the cathode voltage ELVSS, constant voltage node PL3 applying the initialization voltage Vini, constant voltage node PL4 applying the anode reset voltage VAR, and constant voltage node PL5 applying the conduction bias voltage VOBS. The cathode voltage ELVSS can be the pixel ground voltage. On the display panel 100, the power lines connected to the constant voltage nodes can be connected to all pixels.

[0125] The pixel drive voltage ELVDD and cathode voltage ELVSS can be set to voltages that allow the drive element DT to operate in the saturation region. The pixel drive voltage ELVDD can be set between 2V and 3V (e.g., the pixel drive voltage ELVDD can be greater than or equal to 2V and less than or equal to 3V), and the cathode voltage ELVSS can be set between -8V and -10V, but is not limited thereto. The gating high voltage VGH can be set to a voltage higher than the pixel drive voltage ELVDD, and the gating low voltage VGL can be set to a voltage lower than the cathode voltage ELVSS, but is not limited thereto.

[0126] The anode reset voltage VAR can be a voltage between -4V and -8V (e.g., the anode reset voltage VAR can be less than or equal to 4V and greater than or equal to -8V), but is not limited to this. The anode reset voltage VAR can initialize the anode electrode of the light-emitting element EL. The conduction bias voltage VOBS can be between 4V and 8V (e.g., the conduction bias voltage VOBS can be greater than or equal to 4V and less than or equal to 8V), but is not limited to this. The conduction bias voltage VOBS can improve the hysteresis of the drive element DT by changing the direction of the current flowing to the drive element DT.

[0127] The initialization voltage Vinit can be set below the lower limit of the data voltage Vdata and above the cathode voltage ELVSS, but is not limited to this. For example, when the lower limit of the data voltage Vdata is 2V and the cathode voltage ELVSS is -9V, the initialization voltage Vinit can be set between -5V and -7V (e.g., the initialization voltage Vinit can be less than or equal to -5V and greater than or equal to -7V), but is not limited to this. The data voltage Vdata can have a dynamic range between 2V and 6V (e.g., the data voltage Vdata can be greater than or equal to 2V and less than or equal to 6V), but is not limited to this. Within this dynamic range, the voltage level of the data voltage Vdata can be selected based on the grayscale value of the pixel data.

[0128] The gating signals SC1(n) to SC4(n) and EM(n) may include pulses that oscillate between a gating high voltage VGH and a gating low voltage VGL. The gating signals SC1(n) to SC4(n) and EM(n) may include a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), and an EM signal EM(n).

[0129] The driving element DT generates current based on the gate-source voltage Vgs to drive the light-emitting element EL. The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0130] A light-emitting element (EL) can be implemented as an OLED. The EL includes an anode electrode, a cathode electrode, and an organic compound layer interposed between these electrodes. The anode electrode of the EL is connected to a fourth node n4, and the cathode electrode is connected to a second constant voltage node PL2 to which a cathode voltage ELVSS is applied. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode of the EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML) to form excitons. In this case, visible light is emitted from the emissive layer (EML). The EL can also be implemented as an OLED with a tandem structure, where multiple emissive layers are stacked on top of each other. OLEDs with a tandem structure can improve pixel brightness and lifetime.

[0131] Capacitor Cst is connected between the first constant voltage node PL1 and the first node n1, to which the pixel driving voltage ELVDD is applied.

[0132] A first switching element M01 is connected between the first node n1 and the third node n3. The first switching element M01 can be turned on in response to a high-voltage VGH of a first gating signal SC1(n). When the first switching element M01 is turned on, the first node n1 and the third node n3 are electrically connected. The first switching element M01 includes a gate electrode connected to a first gating line GL1 to which the first gating signal SC1(n) is applied, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0133] A second switching element M02 is connected between the data line DL and the second node n2. The second switching element M02 can be turned on in response to a low-voltage VGL applied by the second strobe signal SC2(n). When the second switching element M02 is turned on, the data line DL, to which the pixel data data voltage Vdata is applied, is electrically connected to the second node n2, such that the data voltage Vdata is applied to the second node n2. The second switching element M02 includes a gate electrode connected to the second strobe line GL2 to which the second strobe signal SC2(n) is applied, a first electrode connected to the data line DL, and a second electrode connected to the second node n2.

[0134] A third switching element M03 is connected between a first constant voltage node PL1 and a second node n2 to which a pixel driving voltage ELVDD is applied. The third switching element M03 can be turned on in response to a low selection voltage VGL of a fifth strobe signal EM(n). When the third switching element M03 is turned on, the first constant voltage node PL1 and the second node n2 are electrically connected. The third switching element M03 has a gate electrode connected to a fifth strobe line GL5 to which the fifth strobe signal EM(n) is applied, a first electrode connected to the first constant voltage node PL1, and a second electrode connected to the second node n2.

[0135] Four switching elements M04 are connected between the third node n3 and the fourth node n4. The fourth switching element M04 can be turned on in response to the low-voltage VGL of the fifth gating signal EM(n). When the fourth switching element M04 is turned on, the third node n3 and the fourth node n4 are electrically connected. The fourth switching element M04 includes a gate electrode connected to the fifth gating line GL5, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0136] A fifth switching element M05 is connected between the first node n1 and the third constant voltage node PL3, to which an initialization voltage Vini is applied. The fifth switching element M05 can be turned on in response to a high-voltage VGH applied by a fourth gating signal SC4(n). When the fifth switching element M05 is on, the first node n1 and the third constant voltage node PL3 are electrically connected. The fifth switching element M05 includes a gate electrode connected to a fourth gating line GL4 to which the fourth gating signal SC4(n) is applied, a first electrode connected to the first node n1, and a second electrode connected to the third constant voltage node PL3.

[0137] A sixth switching element M06 is connected between the fourth node n4 and the fourth constant voltage node PL4 to which the anode reset voltage VAR is applied. The sixth switching element M06 can be turned on in response to a low-voltage VGL applied by the third-second gating signal SC3(n+1). When the sixth switching element M06 is turned on, the fourth node n4 is electrically connected to the fourth constant voltage node PL4, and the anode reset voltage VAR is applied to the fourth node n4. The sixth switching element M06 includes a gate electrode connected to the third-second gating line GL32 to which the third-second gating signal SC3(n+1) is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth constant voltage node PL4.

[0138] A seventh switching element M07 is connected between the second node n2 and the fifth constant voltage node PL5, to which an on-bias voltage VOBS is applied. The seventh switching element M07 can be turned on in response to a low-voltage VGL applied by a third-first gating signal SC3(n). When the seventh switching element M07 is turned on, the second node n2 is electrically connected to the fifth constant voltage node PL5, to which the on-bias voltage VOBS is applied, and the on-bias voltage VOBS is applied to the second node n2. The seventh switching element M07 includes a gate electrode connected to the third-first gating line GL31 to which the third-first gating signal SC3(n) is applied, a first electrode connected to the second node n2, and a second electrode connected to the fifth constant voltage node PL5.

[0139] The pulses of the third-first strobe signal SC3(n) and the third-second strobe signal SC3(n+1) are generated sequentially using a low strobe voltage VGL. The pulse of the third-first strobe signal SC3(n) is applied to the gate electrode of the sixth switching element M06 in the pixel of the nth pixel row, and simultaneously to the gate electrode of the seventh switching element M07 in the pixel of the (n-1)th pixel row. Subsequently, the pulse of the third-second strobe signal SC3(n+1) is applied to the gate electrode of the seventh switching element M07 in the pixel of the nth pixel row, and simultaneously to the gate electrode of the sixth switching element M06 in the pixel of the nth pixel row. Therefore, in each pixel row, the seventh switching element M07 can be turned on after the sixth switching element M06 in the pixel circuit 101 is turned on.

[0140] Figure 5 This indicates the force applied during the refresh cycle. Figure 4 The waveform diagram shows an example of the gating signal for the pixel circuit. Figure 6 This is a circuit diagram showing the transistors that are turned on / off during the data writing step in the refresh process.

[0141] Reference Figure 4 and Figure 5 The pixel circuit 101 can be driven in the following order during the refresh cycle: first initialization step P1, second initialization step P2, sampling step P3 of sampling the threshold voltage of the driving element DT in capacitor Cst, data writing step Pwr of writing pixel data, third initialization step P4, fourth initialization step P5, and light emission step P6 of driving the light-emitting element EL with the current from the driving element DT.

[0142] In the first initialization step P1 and the third initialization step P4, the initialization voltage Vini is applied to the first node n1 and the third node n3, and the conduction bias voltage VOBS is applied to the second node n2. In the second initialization step P2 and the fourth initialization step P5, the anode reset voltage VAR is applied to the fourth node n4.

[0143] The data writing step can be interpreted as a programming step. In the data writing step Pwr, such as... Figure 6 As shown, the first switching element M01 and the second switching element M02 are turned on in response to the gate turn-on voltage, while the third to seventh switching elements M03, M04, M05, M06 and M07 are turned off in response to the gate cut-off voltage. In the data writing step Pwr, as... Figure 6As shown, the pixel data voltage Vdata is applied to the first node n1 via the first switching element M01 and the second switching element M02, and is charged to the capacitor Cst. As a result, the pixel data input in the current frame period can be written into the pixel circuit 101 of the sub-pixel corresponding to the refresh period. Figure 5 In the diagram, "X" represents a transistor in the off state.

[0144] Figure 7 This shows the force applied during the frame skip period. Figure 4 The waveform diagram shows an example of the gating signal of the pixel circuit 101. Figure 8 This is a circuit diagram showing the transistors that are turned on / off during the data skipping step.

[0145] Reference Figure 7 and Figure 8 The pixel circuit 101 can be driven in the following order during the frame skipping period: first initialization step P1, second initialization step P2, holding step Ph, data skipping step Psk, third initialization step P4, fourth initialization step P5, and emission step P6. When viewed on the timeline, the holding step Ph corresponds to the sampling step Psam of the refresh period. When viewed on the timeline, the data skipping step Psk corresponds to the data writing step Pwr of the refresh period.

[0146] During the holding step Ph, since the voltages of the gating signals SC1(n), SC2(n), SC3(n), SC3(n+1), and EM(n) are the gating cutoff voltages, the switching elements M01 to M07 are turned off. Therefore, during the holding step Ph, the first to fourth nodes n1 to n4 are floating, so that the voltages of nodes n1 to n4 are maintained at the voltages at the end of the second initialization step P2, and thus the voltage of capacitor Cst does not change.

[0147] In the data skipping step Psk, such as Figure 8 As shown, the second switching element M02 is turned on in response to the gating voltage, while the first switching element M01 and the third to seventh switching elements M03, M04, M05, M06, and M07 are turned off in response to the gating voltage. In the data skipping step Psk, since the first switching element M01 and the fifth switching element M05 are turned off, the pixel data voltage Vdata is not applied to the first node n1, and the first node n1 is floated and not discharged. Therefore, during the frame skipping period, the voltage of the first node n1, i.e., the data voltage Vdata charged in the capacitor Cst, hardly discharges and can be maintained until the next frame period.

[0148] like Figure 5 and Figure 7As shown, based on the voltage levels of the gating signals, particularly the first gating signal SC1(n) and the fourth gating signal SC4(n), Figure 4 The pixel circuit 101 shown can be used as a sub-pixel operation to refresh the pixel region, or as a sub-pixel operation to skip the pixel region. In the data skip cycle Psk of the frame skip cycle corresponding to the data write cycle Pwr, when the voltages of the first strobe signal SC1(n) and the fourth strobe signal SC4(n) are the low strobe voltage VGL, which serves as the strobe cutoff voltage, the pixel circuit 101 performs a sub-pixel operation to skip the pixel region.

[0149] Figure 9 This is a circuit diagram illustrating a pixel circuit according to a second exemplary embodiment of the present disclosure. Figure 9 In this context, descriptions overlapping with the first exemplary embodiment described above may be omitted or briefly discussed.

[0150] Reference Figure 9 The pixel circuit 101 includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M11 to M16, a first capacitor Cst, and a second capacitor Ca. Each of the driving element DT and the switching elements M11 to M16 can be implemented as an n-channel oxide TFT, but is not limited thereto.

[0151] The driving element DT includes a gate electrode connected to the first node n1, a first electrode connected to the second node n2, and a second electrode connected to the third node n3. The anode electrode of the light-emitting element EL is connected to the fourth node n4. The cathode voltage ELVSS is applied to the cathode electrode of the light-emitting element EL.

[0152] The first capacitor Cst is connected between the first node n1 and the third node n3. The second capacitor Ca is connected between the third node n3 and the first electrode of the sixth switching element M16.

[0153] A first switching element M11 is connected between a first node n1 and a data line DL to which a data voltage Vdata is applied. The first switching element M11 can be turned on in response to a high-voltage VGH applied by a first strobe signal SC1. When the first switching element M11 is turned on, the first node n1 is electrically connected to the data line DL, and the data voltage Vdata is applied to the first node n1. The first switching element M11 has a gate electrode connected to a first strobe line GL1 to which the first strobe signal SC1 is applied, a first electrode connected to the first node n1, and a second electrode connected to the data line DL.

[0154] A second switching element M12 is connected between a first node n1 and a third constant voltage node PL3 to which a reference voltage Vref is applied. The second switching element M12 can be turned on in response to a high-voltage VGH applied by a second gating signal SC2. When the second switching element M12 is on, the first node n1 is electrically connected to the third constant voltage node PL3, and the reference voltage Vref is applied to the first node n1. The second switching element M12 includes a gate electrode connected to a second gating line GL2 to which the second gating signal SC2 is applied, a first electrode connected to the third constant voltage node PL3, and a second electrode connected to the first node n1.

[0155] A third switching element M13 is connected between the fourth node n4 and the fourth constant voltage node PL4 to which an anode reset voltage VAR is applied. The third switching element M13 can be turned on in response to a high-voltage VGH applied by the third gating signal SC3. When the third switching element M13 is on, the fourth node n4 is electrically connected to the fourth constant voltage node PL4. The third switching element M13 includes a gate electrode connected to the third gating line GL3 to which the third gating signal SC3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the fourth constant voltage node PL4.

[0156] A fourth switching element M14 is connected between a first constant voltage node PL1 and a second node n2 to which a pixel driving voltage ELVDD is applied. The fourth switching element M14 can be turned on in response to a high-voltage gate VGH of a fourth strobe signal EM1. When the fourth switching element M14 is on, the first constant voltage node PL1 and the second node n2 are electrically connected. The fourth switching element M14 has a gate electrode connected to a fourth strobe line GL4 to which the fourth strobe signal EM1 is applied, a first electrode connected to the first constant voltage node PL1, and a second electrode connected to the second node n2.

[0157] A fifth switching element M15 is connected between the third node n3 and the fourth node n4. The fifth switching element M15 can be turned on in response to a high-voltage VGH applied by the first gating signal EM2. When the fifth switching element M15 is turned on, the third node n3 and the fourth node n4 are electrically connected. The fifth switching element M15 includes a gate electrode connected to a first gating line GL1 to which the first gating signal EM2 is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0158] A sixth switching element M16 is connected between the third node n3 and the third constant voltage node PL3, to which a reference voltage Vref is applied. The sixth switching element M16 can be turned on in response to a high-voltage VGH applied by the third gating signal SC3. When the sixth switching element M16 is on, the third node n3 is electrically connected to the third constant voltage node PL3. The sixth switching element M16 has a gate electrode to which the third gating signal SC3 is applied, a first electrode connected to the third node n3, and a second electrode to which the reference voltage Vref is applied.

[0159] Figure 10 This indicates the force applied during the refresh cycle. Figure 9 The waveform diagram shows an example of the gating signal for the pixel circuit. Figure 11 This is a circuit diagram showing the transistors that are turned on / off during the sampling step in the refresh cycle. Figure 12 This is a circuit diagram showing the transistors that are turned on / off during the data write step in the refresh process. Figure 11 and Figure 12 In the diagram, "X" represents a transistor in the off state.

[0160] Reference Figure 9 and Figure 10 The pixel circuit 101 can be driven in the following order: initialization step Pi during the refresh cycle, sampling step Psam to sample the threshold voltage of the driving element DT, data writing step Pwr to write pixel data, and light emission step Pem to drive the light-emitting element EL.

[0161] like Figure 11 As shown, in the sampling step Psam of the refresh cycle, the second switching element M12, the third switching element M13, the fourth switching element M14, and the sixth switching element M16 are turned on, while the first switching element M11 and the fifth switching element M15 are turned off. In the sampling step Psam, the reference voltage Vref is applied to the first node n1, and ELVDD-Vth is applied to the third node n3. Here, "Vth" is the threshold voltage of the driving element DT. Therefore, in the sampling step Psam during the refresh cycle, the voltage Vref-(VDD-Vth), which reflects the threshold voltage Vth of the driving element DT, is sampled and stored in the first capacitor Cst.

[0162] like Figure 12As shown, during the data writing step Pwr in the refresh cycle, the first switching element M11, the third switching element M13, and the sixth switching element M16 are turned on, while the second switching element M12, the fourth switching element M14, and the fifth switching element M15 are turned off. In the data writing step Pwr, the pixel data voltage Vdata is applied to the first node n1 via the first switching element M11 and is charged to the capacitor Cst. In this case, the voltage of the third node n3 is ELVDD-Vth+a, where "a" is Vdata-Vref.

[0163] Figure 13 This shows the force applied during the frame skip period. Figure 9 The waveform diagram shows an example of the gating signal for the pixel circuit. Figure 14 This is a circuit diagram showing the transistors in the hold and cut-off states during the frame skipping and data skipping steps.

[0164] Reference Figure 13 and Figure 14 The pixel circuit 101 can be driven in the following order: initialization step Pi, holding step Ph, data skipping step Psk, and emission step Pem during the frame skipping period. When viewed on the timeline, the holding step Ph corresponds to the sampling step Psam of the refresh period. When viewed on the timeline, the data skipping step Psk corresponds to the data writing step Pwr of the refresh period.

[0165] By setting the voltage of the strobe signal differently, the initialization step Pi, holding step Ph, and data skipping step Psk of the frame skipping cycle are controlled differently from the initialization step Pi, sampling step Psam, and data writing step Pwr of the refresh cycle.

[0166] During the initialization step Pi in the frame skipping period, the voltages of the first strobe signal to the fourth strobe signal SC1, SC2, SC3 and EM1 are the strobe low voltage VGL, which serves as the strobe cutoff voltage. Therefore, during initialization step Pi, the first switching element M11, the second switching element M12, the third switching element M13, the fourth switching element M14 and the sixth switching element M16 are turned off, causing the first node n1 to the fourth node n4 to float, so that the voltages of the first node n1 to the fourth node n4 and the voltages of capacitors Cst and Ca do not change.

[0167] In the hold step Ph and data skip step Psk of the frame skip cycle, the voltages of the gating signals SC1, SC2, SC3, EM1, and EM2 are the gating low voltage VGL, which serves as the gating cutoff voltage. Therefore, in the hold step Ph, as... Figure 14As shown, switching elements M11 to M14 are turned off, causing the first node n1 to the fourth node n4 to float and maintain the voltage set in the initialization step. In this case, the voltages of capacitors Cst and Ca do not change.

[0168] like Figure 10 and Figure 13 As shown, based on the strobe signals, particularly the voltage levels of the first strobe signal SC1, the second strobe signal SC2, the third strobe signal SC3, and the fourth strobe signal EM1, Figure 9 The pixel circuit 101 shown can be used as a sub-pixel operation to refresh the pixel region or as a sub-pixel operation to skip the pixel region. When the voltages of the first strobe signal SC1, the second strobe signal SC2, the third strobe signal SC3, and the fourth strobe signal EM1 are controlled by the strobe cutoff voltage during the hold period (hold step) Ph and the data skip period (data skip step) Psk of the frame skip period, the pixel circuit 101 operates as a sub-pixel operation to skip the pixel region.

[0169] Figure 15 This is a circuit diagram illustrating a pixel circuit according to a third exemplary embodiment of the present disclosure. Figure 15 In this document, descriptions that overlap with the above exemplary embodiments may be omitted.

[0170] Reference Figure 15 The pixel circuit 101 includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M21 to M26, and a capacitor Cst. Each of the driving element DT and the switching elements M21 to M26 can be implemented as a p-channel LTPS TFT, but is not limited thereto.

[0171] The driving element DT includes a gate electrode connected to a first node n1, a first electrode connected to a second node n2, and a second electrode connected to a third node n3. The anode electrode of the light-emitting element EL is connected to a fourth node n4. A cathode voltage ELVSS is applied to the cathode electrode of the light-emitting element EL. A capacitor Cst is connected between the first node n1 and a first constant voltage node PL1 to which the pixel driving voltage ELVDD is applied.

[0172] A first switching element M21 is connected between the first node n1 and the third node n3. The first switching element M21 can be turned on in response to a low-voltage VGL of the second strobe signal SCAN2. When the first switching element M21 is turned on, the first node n1 and the third node n3 are electrically connected. The first switching element M21 includes a gate electrode connected to a second strobe line GL2 to which the second strobe signal SCAN2 is applied, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0173] The pulses of the first strobe signal SCAN1 and the second strobe signal SCAN2 are generated as a low strobe voltage VGL. After the pulse of the first strobe signal SCAN1, the pulse of the second strobe signal SCAN2 is input to the pixel circuit 101.

[0174] The second switching element M22 is connected between the second node n2 and the data line DL to which the data voltage Vdata is applied. The second switching element M22 can be turned on in response to a low-voltage VGL applied by the second strobe signal SCAN2. When the second switching element M22 is turned on, the second node n2 is electrically connected to the data line DL, and the data voltage Vdata is applied to the second node n2. The second switching element M22 includes a gate electrode to which the second strobe signal SCAN2 is applied, a first electrode connected to the second node n2, and a second electrode connected to the data line DL.

[0175] A third switching element M23 is connected between a first constant voltage node PL1 and a second node n2 to which a pixel driving voltage ELVDD is applied. The third switching element M23 can be turned on in response to a low-voltage VGL of a third gating signal EM. When the third switching element M23 is on, the first constant voltage node PL1 and the second node n2 are electrically connected. The third switching element M23 includes a gate electrode connected to a third gating line GL3 to which the third gating signal EM is applied, a first electrode connected to the first constant voltage node PL1, and a second electrode connected to the second node n2.

[0176] A fourth switching element M24 is connected between the third node n3 and the fourth node n4. The fourth switching element M24 can be turned on in response to a low-voltage VGL applied by the third gating signal EM. When the fourth switching element M24 is turned on, the third node n3 and the fourth node n4 are electrically connected. The fourth switching element M24 includes a gate electrode connected to the third gating line GL3 to which the third gating signal EM is applied, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0177] A fifth switching element M25 is connected between the first node n1 and the third constant voltage node PL3, to which an initialization voltage Vini is applied. The fifth switching element M25 can be turned on in response to a low-voltage VGL applied by the first strobe signal SCAN1. When the fifth switching element M25 is on, the first node n1 and the third constant voltage node PL3 are electrically connected. The fifth switching element M25 includes a gate electrode to which the first strobe signal SCAN1 is applied, a first electrode connected to the first node n1, and a second electrode to which a reference voltage Vref is applied.

[0178] A sixth switching element M26 is connected between the fourth node n4 and the third constant voltage node PL3. The sixth switching element M26 can be turned on in response to a low-voltage VGL applied by the second strobe signal SCAN2. When the sixth switching element M26 is on, the fourth node n4 and the third constant voltage node PL3 are electrically connected. The sixth switching element M26 includes a gate electrode connected to the second strobe line GL2 to which the second strobe signal SCAN2 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the third constant voltage node PL3.

[0179] The first switching element M21 and the fifth switching element M25 are susceptible to leakage current due to their long off-cycles. Therefore, the first switching element M21 and the fifth switching element M25 can be transistors with a dual-gating structure and low leakage current, such as... Figure 15 As shown, for example, the first switching element M21 and the fifth switching element M25 can be p-channel LTPS TFTs with a dual-gated structure having low leakage current, but are not limited thereto.

[0180] Figure 16 This indicates the force applied during the refresh cycle. Figure 15 The waveform diagram shows an example of the gating signal for the pixel circuit. Figure 17 This is a circuit diagram showing the transistors that are turned on / off during the initialization step in the refresh process. Figure 18 This is a circuit diagram showing the transistors that are turned on / off during the data write step in the refresh cycle. Figure 17 and 18 In the diagram, "X" represents a transistor in the off state.

[0181] Reference Figure 16 and Figure 17 The pixel circuit 101 can be driven in the following order during the refresh cycle: the pixel circuit 101 is initialized in the initialization step Pini, the data writing step Pwr in which the threshold voltage of the driving element DT is sampled and the pixel data is written, and the light-emitting step Pem in which the light-emitting element EL is driven.

[0182] In the initialization step of the refresh cycle, in the Pini, the voltage of the first strobe signal SCAN1 is the low voltage VGL, while the voltages of the second strobe signal SCAN2 and the third strobe signal EN are the high voltage VGH. Therefore, in the initialization step Pini, as follows... Figure 17 As shown, the fifth switching element M25 is turned on, while the other switching elements M21, M22, M23, M24 and M26 are turned off, and the initialization voltage Vini is applied to the first node n1.

[0183] In the data writing step Pwr of the refresh cycle, the voltage of the second strobe signal SCAN2 is the low strobe voltage VGL, while the voltages of the first strobe signal SCAN1 and the third strobe signal EN are the high strobe voltage VGH. Therefore, as Figure 18 As shown, in the data writing step Pwr, the first switch element M21, the second switch element M22, and the sixth switch element M26 are turned on, while the third switch element M23, the fourth switch element M24, and the fifth switch element M25 are turned off. In the data writing step Pwr, the pixel data voltage Vdata is applied to the first node n1 via the first switch element M21 and the second switch element M22, and the initialization voltage Vini is applied to the fourth node n4.

[0184] Figure 19 This shows the force applied during the frame skip period. Figure 15 The waveform diagram shows an example of the gating signal of the pixel circuit 101. Figure 20 This is a circuit diagram showing the transistors in the off state during the hold and data skipping steps in the frame skipping cycle.

[0185] Reference Figure 19 and Figure 20 The pixel circuit 101 can be driven during the frame skipping period in the data skipping step Psk after the holding step Ph. When viewed on the timeline, the holding step Ph corresponds to the initialization step Pini of the refresh period. When viewed on the timeline, the data skipping step Psk corresponds to the data writing step Pwr of the refresh period.

[0186] By setting the voltages of the first strobe signal SCAN1 and the second strobe signal SCAN2 differently, the hold step Ph and the data skip step Psk of the frame skip cycle are controlled differently from the initialization step Pini and the data write step Pwr of the refresh cycle.

[0187] In the hold step Ph and data skip step Psk of the frame skip cycle, the voltages of the gating signals SCAN1, SCAN2, and EM are the gating high voltage VGH, which serves as the gating cutoff voltage. Therefore, in the hold step Ph and data skip step Psk, all switching elements M21 to M26 are turned off, causing the first node n1 to the fourth node n4 to float, and the voltages of the first node n1 to the fourth node n4 and the voltage of the capacitor Cst remain unchanged.

[0188] like Figure 16 and Figure 19 As shown, based on the voltage levels of the strobe signals, particularly the first strobe signal SCAN1 and the second strobe signal SCAN2, Figure 15The pixel circuit 101 shown can be used as a sub-pixel operation to refresh the pixel region or as a sub-pixel operation to skip the pixel region. During the hold period Ph and data skip period Psk of the frame skip cycle, when the voltages of the first strobe signal SCAN1 and the second strobe signal SCAN2 are controlled by the strobe cutoff voltage, the pixel circuit 101 operates as a sub-pixel operation to skip the pixel region.

[0189] In a display panel 100 according to an exemplary embodiment of the present disclosure, subpixels can be, for example... Figure 21 The structure shown connects to the data line and the strobe line. (As shown...) Figure 21 As shown, sub-pixels P11, P12, P21, P22, P31, P32, P41, and P42 are positioned in the area where data lines DL1, DL2, DL3, and DL4 intersect with gate lines CGL1 and CGL2. However, the arrangement of data lines, gate lines, and sub-pixels is not limited to this. For example... Figure 21 The structure of the display panel is advantageous for ensuring the threshold voltage sampling time of the driving element DT when driving subpixels at high speed in a high-resolution display panel.

[0190] Reference Figure 21 At least one of the gate lines arranged on the display panel can branch into two gate lines, which are connected together to the sub-pixels of different pixel rows.

[0191] For example, sub-pixels P11, P12, P31, and P32 located on odd-numbered pixel rows L1 and L3 can be connected to the nearby odd-numbered data lines DL1 and DL3 to receive data voltages Vdata1 and Vdata3 via the odd-numbered data lines DL1 and DL3. Conversely, sub-pixels P21, P22, P41, and P42 located on even-numbered pixel rows L2 and L4 can be connected to the nearby even-numbered data lines DL2 and DL4 to receive data voltages Vdata2 and Vdata4 via the even-numbered data lines DL2 and DL4.

[0192] Subpixels located in adjacent pixel rows share the same common gating signal. For example, subpixels P11, P12, P21, and P22 located in the first pixel row L1 and the second pixel row L2 are connected to the first common gating line CGL1 to receive the first common gating signal. Subpixels P31, P32, P41, and P42 located in the third pixel row L3 and the fourth pixel row L4 are connected to the second common gating line CGL2 to receive the second common gating signal. Therefore, since subpixels located in adjacent pixel rows are driven simultaneously and charged using different data voltages Vdata1 to Vdata4, the sampling time required for the threshold voltage of the sensing driving element DT can be sufficiently ensured. For example, when two adjacent pixel rows are driven simultaneously, the sampling time can be ensured to be two horizontal cycles.

[0193] Figure 22 This shows the drive. Figure 4 The diagram shows the first to fourth gating drivers of the pixel circuit. Figure 23 This shows the input to Figure 22 The waveform diagrams of the clock and start pulse of the strobe driver are shown.

[0194] Reference Figure 4 , Figure 22 and Figure 23 The gating driver 120 may include a first gating driver GIP1 that sequentially outputs pulses of the first gating signals SC1(n-1), SC1(n), and SC1(n+1); a second gating driver GIP2 that sequentially outputs pulses of the second gating signals SC21 to SC26; a third gating driver GIP3 that sequentially outputs pulses of the third gating signals SC3(n-1), SC3(n), and SC3(n+1); a fourth gating driver GIP4 that sequentially outputs pulses of the fourth gating signals SC4(n-1), SC4(n), and SC4(n+1); and a fifth gating driver GIP5 that outputs pulses of the fifth gating signals EM(n-1), EM(n), and EM(n+1). The second gating driver GIP2 may be implemented as a shift register, and the other gating drivers GIP1, GIP3, GIP4, and GIP5 may be implemented as edge-triggered flip-flops, but are not limited thereto.

[0195] Each of the first gating driver GIP1, the third gating driver GIP3, the fourth gating driver GIP4, and the fifth gating driver GIP5 can receive a start pulse and two phase-shifted clocks with different phases. The two phase-shifted clocks can be out of phase with each other. The pulses and phases of the gating signals can be controlled according to the start pulse and the clocks. The first gating driver GIP1 includes multiple signal transmitters 310 cascaded together. The first gating driver GIP1 receives the start pulse G1VST and clocks G1CLK1 and G1CLK2, and sequentially outputs the pulses of the first gating signals SC1(n-1), SC1(n), and SC1(n+1). The third gating driver GIP3 includes multiple signal transmitters 330 cascaded together. The third gating driver GIP3 receives the start pulse G3VST and clocks G3CLK1 and G3CLK2, and sequentially outputs the pulses of the third gating signals SC3(n-1), SC3(n), and SC3(n+1). The fourth gating driver GIP4 includes multiple signal transmitters 340 cascaded together. The fourth gating driver GIP4 receives a start pulse G4VST and clocks G4CLK1 and G4CLK2, and sequentially outputs pulses of the fourth gating signals SC4(n-1), SC4(n), and SC4(n+1).

[0196] The second gating driver GIP2 receives a first start pulse G2VST(ODD) and a second start pulse G2VST(EVEN), as well as four phase-shift clocks G2CLK1 to G2CLK4. The second gating driver GIP2 includes multiple signal transmitters 321 cascaded together. These signal transmitters 321, by receiving the first start pulse G2VST(ODD) and clocks G2CLK1 and G2CLK2, sequentially output pulses of second gating signals SC21, SC23, and SC25 to supply the sub-pixels PXL1, PXL3, and PXL5 of the odd-numbered pixel rows. Additionally, the second gating driver GIP2 also includes multiple signal transmitters 322 cascaded together. These transmitters, by receiving the second start pulse G2VST(EVEN) and clocks G2CLK3 and G2CLK4, sequentially output pulses of second gating signals SC22, SC24, and SC26 to supply the sub-pixels PXL2, PXL4, and PXL6 of the even-numbered pixel rows.

[0197] Figure 24 This is a circuit diagram illustrating a signal transmitter circuit of a gating driver according to an exemplary embodiment of the present disclosure. The signal transmitter circuit of this gating driver can be used as a circuit that outputs a gating signal for driving the aforementioned pixel circuit; however, the gating driver circuit of the present disclosure is not limited to... Figure 24 The circuit shown.

[0198] Reference Figure 24 The signal transmitter includes first to seventh transistors T1 to T7. The active layer of the transistor TFT can be formed of a semiconductor material such as, but is not limited to, polycrystalline semiconductors. Polycrystalline semiconductor materials have fast carrier mobility, such as electrons and holes, and therefore high mobility, as well as low power consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited to. For example, transistors T1 to T7 can be p-channel LTPSTFTs, but are not limited to. The signal transmitter can operate as an edge-triggered flip-flop, wherein when the clock CLK(N) drops to the gating low voltage VGL, the output voltage is equal to the voltage of the first input node n01.

[0199] A first transistor T1 is connected between a first input node n01 and a first-first control node Q1. A start pulse VST or a pulse from a carry signal from a previous signal transmitter is input to the first input node n01. The first transistor T1 can be turned on in response to a gating voltage, such as a low voltage VGL, of the clock CLK(N) input to the second input node n02. When the first transistor T1 is on, the first input node n01 is electrically connected to the first-first control node Q1. The first transistor T1 includes a gate electrode connected to the second input node n02 connected to the input clock CLK(N), a first electrode connected to the first input node n01, and a second electrode connected to the first-first control node Q1.

[0200] A second transistor T2 is connected between buffer node n03 and VGH node. A gate cutoff voltage, such as a gate high voltage VGH, is applied to VGH node. When the voltage at the first input node n01 is the gate low voltage VGL, the second transistor T2 is turned on to electrically connect buffer node n03 to VGH node. The second transistor T2 includes a gate electrode connected to the first input node n01, a first electrode connected to buffer node n03, and a second electrode connected to VGH node.

[0201] The third transistor T3 is connected between the second input node n02 and the second control node QB. When the voltage of the buffer node n03 is the gate low voltage VGL, the third transistor T3 is turned on to electrically connect the second input node n02 to the second control node QB. The third transistor T3 includes a gate electrode connected to the buffer node n03, a first electrode connected to the second input node n02, and a second electrode connected to the second control node QB.

[0202] The first capacitor C1 is connected between the second input node n02 and the buffer node n03. If the first capacitor C1 is not present, and the voltage of the first input node n01 is the gate low voltage VGL, the second input node n02 of the input clock CLK(N) may be short-circuited with the VGH node, which may cause a fault.

[0203] A fourth transistor T4 is connected between the second control node QB and the VGH node. When the voltage of the first-first control node Q1 is the gate low voltage VGL, the fourth transistor T4 is turned on to electrically connect the second control node QB to the VGH node. The fourth transistor T4 controls the voltage of the second control node QB to be opposite to the voltages of the first-first control node Q1 and the first-second control node Q2. For example, when the voltage of the first-first control node Q1 is the gate low voltage VGL, the fourth transistor T4 can be turned on, allowing the second control node Q2 to be charged to the gate high voltage VGH. The fourth transistor T4 includes a gate electrode connected to the first-first control node Q1, a first electrode connected to the second control node QB, and a second electrode connected to the VGH node.

[0204] The fifth transistor T5 includes a gate electrode connected to the VGL node, a first electrode connected to the first-first control node Q1, and a second electrode connected to the first-second control node Q2.

[0205] When the voltage of the first-second control node Q2 is the low gate voltage VGL, the sixth transistor T6 is turned on, electrically connecting the VGL node to the output node n04. The sixth transistor T6 includes a gate electrode connected to the first-second control node Q2, a first electrode connected to the VGL node, and a second electrode connected to the output node n04. The second capacitor C2 is connected between the Q node and the output node.

[0206] When the voltage of the second control node QB is the gate low voltage VGL, the seventh transistor T7 is turned on to electrically connect the VGH node to the output node n04. The seventh transistor T7 includes a gate electrode connected to the second control node QB, a first electrode connected to the output node n04, and a second electrode connected to the VGH node. A third capacitor C3 is connected between the second control node QB and the VGH node.

[0207] When the voltage at the first input node n01 is the low gate voltage VGL, the second transistor T2 turns on, and the voltage at the buffer node n03 rises to the high gate voltage VGH. Therefore, when the voltage at the first input node n01 is the low gate voltage VGL, the third transistor T3 turns off. The third transistor T3 can turn on based on the voltage at the second input node n02, only when the voltage at the first input node n01 is the high gate voltage VGH. In other words, when the voltage at the first input node n01 is the high gate voltage VGH and the voltage at the second input node n02 is the low gate voltage, the third transistor T3 turns on to electrically connect the second control node QB to the second input node n02 and discharge the voltage of the second control node QB to the low gate voltage VGL.

[0208] To control the pixel rows that serve as refresh pixel areas or skip pixel areas, the gating driver 120 may include a switching circuit 500 and diodes D1 to D5, such as Figure 22 As shown.

[0209] Figure 25 This is a circuit diagram illustrating the switching circuit and diodes of a gating driver according to a first exemplary embodiment of the present disclosure. Figure 26 It is shown Figure 25 The waveform diagram of the input / output signals of the strobe driver is shown.

[0210] Reference Figure 25 and Figure 26 The gating driver GIP includes multiple signal transmitters ST1 to ST5, a switching circuit 500 connected to the signal transmitters ST1 to ST5, and multiple diodes D1 to D5 connected between the switching circuit 500 and the gating line 512.

[0211] Signal transmitters ST1 to ST5 are cascaded via carry signal wiring. Each signal transmitter includes a first input node receiving a start pulse VST or carry signals C(N) to C(N+4), a second input node connected to clock wirings 501 and 502 connected to input clocks CLK1 and CLK2, and output nodes 511 and 513 that output strobe signals sequentially. The output node of the (N)th signal transmitter (where N is a natural number) is connected to the strobe line via multiple switching transistors S1 to S4 of the switching circuit 500, and is also connected to the first input node of the (N+1)th signal transmitter. The strobe signal output from the (N)th signal transmitter can be applied to strobe line 512 via the switching circuit 500, and can be input as a carry signal to the first input node of the (N+1)th signal transmitter, which is the next stage.

[0212] The switching circuit 500 uses multiple switching transistors S1 to S4 to selectively connect the output nodes 511 and 513 of each of the signal transmitters ST1 to ST5 to gating lines 512 and 514 and diodes D1 to D5 in response to selection signals SEL1 to SEL4. The switching circuit 500 selects the refresh pixel region A and the skip pixel region B under the control of the timing controller 130. The timing controller 130 can freely control the refresh rate, size, position, etc. of the refresh pixel region A and the skip pixel region B pixel-by-pixel in each frame cycle by using the selection signals SEL1 to SEL4 of the switching transistors S1 to S4 of the switching circuit 500.

[0213] The switching circuit 500 includes a first switching transistor S1 connected between the output node 511 of a first signal transmitter ST1, which outputs a first (N) gating signal G(N), and the Nth gating line 512; a second switching transistor S2 connected between the output node 513 of the first signal transmitter ST1 and a first diode D1; a third switching transistor S3 connected between the output node 511 of a second signal transmitter ST2, which outputs a second (N+1) gating signal G(N+1), and the Nth gating line 512; and a fourth switching transistor S4 connected between the output node 513 of the second signal transmitter ST2 and a second diode D2. The second (N) gating signal G(N) can be a first gating signal, and the second (N+1) gating signal G(N+1) can be a second gating signal. The active layer of the switching transistor can be formed of a semiconductor material such as a polycrystalline semiconductor, but is not limited thereto. Polycrystalline semiconductor materials have fast carrier mobility, such as electrons and holes, and therefore high mobility, low power consumption, and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited to this. For example, switching transistors S1 to S4 can be implemented as p-channel LTPS TFTs, but are not limited to this.

[0214] Diodes D1 through D5 are used as switching elements, conducting when the voltage at the output node of the signal transmitter is the gate cutoff voltage and the voltage at the gate line is the gate on voltage. Diodes D1 through D5 are connected between the output node of the signal transmitter and the gate line to satisfy the above conduction conditions. For example, in the case where the switching transistor in the pixel circuit is an n-channel oxide TFT, such as... Figure 25 As shown, the anode electrodes of diodes D1 to D5 are connected to gate lines 512 and 514, and the cathode electrodes of diodes D1 to D5 are connected to the output nodes 511 and 513 of the signal transmitter. In the case of an n-channel oxide TFT, the gate cutoff voltage is the low gate voltage VGL, and the gate on voltage is the high gate voltage VGH, as shown. Figure 26 As shown.

[0215] Diodes D1 to D5 can be implemented as transistors with essentially the same structure as the transistors in the pixel circuit, such as p-channel LTPS TFTs or n-channel oxide TFTs. When the gate electrode is connected to the first or second electrode, the transistor can operate as a diode. Therefore, the switching transistors S1 to S4 and diodes D1 to D5 of the switching circuit 500 can be located on the display panel 100 together with the pixel circuit.

[0216] The first switching transistor S1 is connected between the output node 511 of the (N) signal transmitter and the Nth gating line 512, and is turned on in response to the first selection signal SEL1. When the first switching transistor S1 is a p-channel transistor, it is turned on at the gating low voltage VGL of the first selection signal SEL1. When the first switching transistor S1 is turned on, the output node 511 of the (N) signal transmitter is connected to the Nth gating line 512. In this case, a pulse of the gating signal output from the (N) signal transmitter can be applied to the Nth gating line 512. The first switching transistor S1 includes a first electrode connected to the output node 511 of the (N) signal transmitter, a gate electrode connected to the first selection signal wiring 503 to which the first selection signal SEL1 is applied, and a second electrode connected to the Nth gating line 512.

[0217] The second switching transistor S2 is connected between the output node 511 of the (N) signal transmitter and the Nth diodes D1, D3, and D5, and is turned on in response to the low selection voltage VGL of the second selection signal SEL2. When the second switching transistor S2 is turned on, the output node 511 of the (N) signal transmitter is connected to the Nth diodes D1, D3, and D5. When the second switching transistor S2 and the Nth diodes D1, D3, and D5 are turned on, the Nth gating line 512 can be electrically connected to the output node of the (N) signal transmitter. The second switching transistor S2 includes a first electrode connected to the output node 511 of the (N) signal transmitter, a gate electrode connected to the second selection signal wiring 504 to which the second selection signal SEL2 is applied, and a second electrode connected to the Nth gating line 512.

[0218] The third switching transistor S3 is connected between the output node 513 of the (N+1) signal transmitter and the (N+1) gating line 514, and is turned on in response to the third selection signal SEL3. When the third switching transistor S3 is a p-channel transistor, it is turned on at the gating low voltage VGL of the third selection signal SEL3. When the third switching transistor S3 is turned on, the output node 513 of the (N+1) signal transmitter is connected to the (N+1) gating line 514. In this case, a pulse of the gating signal output from the (N+1) signal transmitter can be applied to the (N+1) gating line 514. The third switching transistor S3 includes a first electrode connected to the output node 513 of the (N+1) signal transmitter, a gate electrode connected to the third selection signal wiring 505 to which the third selection signal SEL3 is applied, and a second electrode connected to the (N+1) gating line 514.

[0219] A fourth switching transistor S4 is connected between the output node 513 of the (N+1) signal transmitter and the (N+1) diodes D2 and D4, and is turned on in response to the low gate voltage VGL of the fourth selection signal SEL4. When the fourth switching transistor S4 is on, the output node 513 of the (N+1) signal transmitter is connected to the N+1 diodes D2 and D4. When the fourth switching transistor S4 and the (N+1) diodes D2 and D4 are on, the (N+1) gate line 514 can be electrically connected to the output node of the (N+1) signal transmitter. The fourth switching transistor S4 includes a first electrode connected to the output node 513 of the (N+1) signal transmitter, a gate electrode connected to the fourth selection signal wiring 506 to which the fourth selection signal SEL4 is applied, and a second electrode connected to the (N+1) gate line 514.

[0220] According to the input Figure 4 The voltages of the first strobe signal SC1(n) and the fourth strobe signal SC4(n) of the pixel circuit shown indicate that the pixel circuit can be used to refresh the pixel area or skip sub-pixels in the pixel area. Figure 25 The strobe driver shown can output a first strobe signal SC1(n) and a fourth strobe signal SC4(n). Figure 25 In this context, G(n), G(n+1), and G(n+4) can be at least one of the first gating signal SC1(n) and the fourth gating signal SC4(n) input to the pixel circuit of the refresh pixel region A with a high refresh rate. G(n+2) and G(n+3) can be at least one of the first gating signal SC1(N) and the fourth gating signal SC4(N) input to the pixel circuit of the skip pixel region B with a low refresh rate.

[0221] According to the input Figure 9 The voltages of the first strobe signal SC1, the second strobe signal SC2, the third strobe signal SC3, and the fourth strobe signal EM1 of the pixel circuit shown indicate that the pixel circuit can be used to refresh the pixel area or skip sub-pixels of the pixel area. Figure 25 The strobe driver shown can output a first strobe signal SC1, a second strobe signal SC2, a third strobe signal SC3, and a fourth strobe signal EM1. Figure 25 In this context, G(N), G(N+1), and G(N+4) can be at least one of the first gating signal SC1, the second gating signal SC2, the third gating signal SC3, and the fourth gating signal EM1 input to the pixel circuit of the refresh pixel region A with a high refresh rate. G(N+2) and G(N+3) can be at least one of the first gating signal SC1, the second gating signal SC2, the third gating signal SC3, and the fourth gating signal EM1 input to the pixel circuit of the skip pixel region B with a low refresh rate.

[0222] Combining Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 31A and Figure 31B explain Figure 25 The operation of the strobe driver is shown in the figure.

[0223] Reference Figure 27A and Figure 27B During period t01, the voltage of the initial pulse VST is the high-gated voltage VGH. During period t01, the voltage of the first clock CLK1 is the low-gated voltage VGL, and the voltage of the second clock CLK2 is the high-gated voltage VGH. During period t01, the voltages of the first selection signal SEL1 and the third selection signal SEL3 are the low-gated voltage VGL, and the voltages of the second selection signal SEL2 and the fourth selection signal SEL4 are the high-gated voltage VGH. When the switching transistors S1 to S4 of the switching circuit 500 are p-channel transistors, the first switching transistor S1 and the third switching transistor S3 are turned on during period t01, and the second switching transistor S2 and the fourth switching transistor S4 are turned off during period t01.

[0224] During period t01, the first signal transmitter ST1 receives the start pulse VST for selecting the high voltage VGH and the first clock CLK1 for selecting the low voltage VGL. Therefore, the voltage of the (N)th gating signal G(N) output from the first signal transmitter ST1 is reversed at the beginning of period t01 to become the high voltage VGH. The voltages of the gating signals G(N+1) to G(N+4) output from the second signal transmitter ST2 to the fifth signal transmitter ST5 are the low voltage VGL during period t01.

[0225] Reference Figure 28A and Figure 28B During period t02, the voltage of the initial pulse VST is the low-gated voltage VGL. During period t02, the voltage of the first clock CLK1 is the high-gated voltage VGH, and the voltage of the second clock CLK2 is the low-gated voltage VGL. During period t02, the voltages of the first selection signal SEL1 and the third selection signal SEL3 are the low-gated voltage VGL, and the voltages of the second selection signal SEL2 and the fourth selection signal SEL4 are the high-gated voltage VGH. Therefore, the first switching transistor S1 and the third switching transistor S3 are in the on state during period t02, and the second switching transistor S2 and the fourth switching transistor S4 are in the off state during period t02.

[0226] The voltage of the (N)th strobe signal G(N) output from the first signal transmitter ST1 is a high strobe voltage VGH during period t02. The second signal transmitter ST2 receives the (N)th carry signal C(N) of the high strobe voltage VGH and the second clock CLK2 of the low strobe voltage VGL during period t02. Therefore, the voltage of the (N+1)th strobe signal G(N+1) output from the second signal transmitter ST2 reverses to a high strobe voltage VGH at the beginning of period t02. The voltages of the strobe signals G(N+2), G(N+3), and G(N+4) output from the third to the fifth signal transmitters ST3, ST4, and ST5 are low strobe voltages VGL during period t02.

[0227] Reference Figure 29A and Figure 29B During period t03, the voltage of the initial pulse VST is the low-gating voltage VGL. During period t03, the voltage of the first clock CLK1 is the low-gating voltage VGL, and the voltage of the second clock CLK2 is the high-gating voltage VGH. During period t03, the voltages of the first selection signal SEL1 and the third selection signal SEL3 are the high-gating voltage VGH, and the voltages of the second selection signal SEL2 and the fourth selection signal SEL4 are the low-gating voltage VGL. Therefore, the second switching transistor S2 and the fourth switching transistor S4 are turned on during period t03, and the first switching transistor S1 and the third switching transistor S3 are turned off during period t03.

[0228] During period t03, the first signal transmitter ST1 receives the start pulse VST of the low-gating voltage VGL and the first clock CLK1 of the low-gating voltage VGL. Consequently, the output voltage of the first signal transmitter ST1 is inverted to the low-gating voltage VGL at the start of period t03. The output voltage of the first signal transmitter ST1 is supplied to the first diode D1 via the second switching transistor S2. In this case, the anode voltage of the first diode D1 is the high-gating voltage VGH, and the cathode voltage is the low-gating voltage VGL; therefore, the first diode D1 is turned on, and the voltage of the (N)th gating signal G(N) is inverted from the high-gating voltage VGH to the low-gating voltage VGL at the start of period t03. If the first diode D1 is absent, the voltage of the (N)th gating signal G(N) remains at the high-gating voltage VGH during period t03, and abnormal gating signal pulses are applied to the pixel circuit of the refresh pixel region A, which may cause a malfunction.

[0229] The voltage of the (N+1)th strobe signal G(N+1) is the strobe high voltage VGH during period t03. The third signal transmitter ST3 receives the (N)th carry signal C(N+1) of the strobe high voltage VGH and the first clock CLK1 of the strobe low voltage VGL during period t03. Therefore, the output voltage of the third signal transmitter ST3 is reversed to the strobe high voltage VGH at the beginning of period t03. The output voltage of the third signal transmitter ST3 is supplied to the third diode D3 via the second switching transistor S2, but since the third diode D3 is not conducting, the voltage of the (N+2)th strobe signal G(N+2) remains at the strobe low voltage during period t03. If the third diode D3 is absent, the voltage of the (N+2)th strobe signal G(N+2) becomes the strobe high voltage VGH during period t03, and an abnormal strobe signal pulse is applied to the pixel circuit skipping pixel region B, which may cause a malfunction. The voltages of the (N+3)th gating signal G(N+3) and the (N+4)th gating signal G(N+4) are the low gating voltage VGL during the period t03.

[0230] Reference Figure 30A and Figure 30B During period t04, the voltage of the initial pulse VST is the low-gating voltage VGL. During period t04, the voltage of the first clock CLK1 is the high-gating voltage VGH, and the voltage of the second clock CLK2 is the low-gating voltage VGL. During period t04, the voltages of the first selection signal SEL1 and the third selection signal SEL3 are the high-gating voltage VGH, and the voltages of the second selection signal SEL2 and the fourth selection signal SEL4 are the low-gating voltage VGL. Therefore, the second switching transistor S2 and the fourth switching transistor S4 are in the on state during period t04, and the first switching transistor S1 and the third switching transistor S3 are in the off state during period t04.

[0231] The voltage of the Nth gating signal G(N) is a low gating voltage VGL during period t04. The second signal transmitter ST2 receives the Nth carry signal C(N) and the second clock CLK2 for the low gating voltage VGL during period t04. Consequently, the output voltage of the second signal transmitter ST2 reverses to the low gating voltage VGL at the beginning of period t04. The output voltage of the second signal transmitter ST2 is supplied to the second diode D2 via the fourth switching transistor S4. In this case, the anode voltage of the second diode D2 is the high gating voltage VGH, and the cathode voltage is the low gating voltage VGL; therefore, the second diode D2 is turned on, and the voltage of the (N+1)th gating signal G(N+1) reverses from the high gating voltage VGH to the low gating voltage VGL at the beginning of period t04.

[0232] The third signal transmitter ST3 receives the (N+1)th carry signal C(N+1) for strobing the low voltage VGL and the first clock CLK1 for strobing the high voltage VGH during period t04. The voltage of the (N+2)th strobe signal G(N+2) is the low voltage VGL during period t04.

[0233] During period t04, the fourth signal transmitter ST4 receives the (N+2)th carry signal C(N+2) that gating the high voltage VGH and the second clock CLK2 that gating the low voltage VGL. Therefore, the output voltage of the fourth signal transmitter ST4 at the beginning of period t04 is the high voltage VGH, which is supplied to the fourth diode D4 via the fourth switching transistor S4. In this case, since the fourth diode D4 is in the off state, the voltage of the (N+3)th gating signal G(N+3) is the low voltage VGL during period t04. The voltage of the (N+4)th gating signal G(N+4) is the low voltage VGL during period t04.

[0234] Reference Figure 31A and Figure 31B During period t05, the voltage of the initial pulse VST is the low-gating voltage VGL. During period t05, the voltage of the first clock CLK1 is the low-gating voltage VGL, and the voltage of the second clock CLK2 is the high-gating voltage VGH. During period t05, the voltages of the first selection signal SEL1 and the fourth selection signal SEL4 are the low-gating voltage VGL, and the voltages of the second selection signal SEL2 and the third selection signal SEL3 are the high-gating voltage VGH. Therefore, the first switching transistor S1 and the fourth switching transistor S4 are in the on state during period t05, and the second switching transistor S2 and the third switching transistor S3 are in the off state during period t05.

[0235] The voltages of the Nth gating signal G(N) and the (N+1)th gating signal G(N+1) are at a low gating voltage VGL during period t05. The third signal transmitter ST3 receives the (N+1)th carry signal C(N+1) and the first clock CLK1 of the low gating voltage VGL during period t05. Therefore, during period t05, the low gating voltage VGL output from the third signal transmitter ST3 is supplied to the (N+2)th gating line via the first switching transistor S1. Thus, the voltage of the (N+2)th gating signal G(N+2) is at a low gating voltage VGL during period t05. In this case, the second diode D2 is in the off state.

[0236] The fourth signal transmitter ST4 receives the (N+2)th carry signal C(N+2), which changes from a high gating voltage VGH to a low gating voltage VGL, and the second clock CLK2, which is also a high gating voltage VGH, during period t05. When the voltage of the (N+2)th carry signal C(N+2) is the high gating voltage VGH, the fourth diode D4 is in the off state. Therefore, the voltage of the (N+3)th gating signal G(N+3) is the low gating voltage VGL during period t05.

[0237] During period t05, the fifth signal transmitter ST5 receives the (N+3)th carry signal C(N+3) for the high-gating voltage VGH and the first clock CLK1 for the low-gating voltage VGL. Therefore, during period t05, the high-gating voltage VGH output from the fifth signal transmitter ST5 is supplied to the (N+4)th gating line via the first switching transistor S1. Consequently, the voltage of the (N+4)th gating signal G(N+4) is the low-gating voltage VGL during period t05.

[0238] Figure 32 This is a circuit diagram illustrating the switching circuit and diodes of a gating driver according to a second exemplary embodiment of the present disclosure. In this exemplary embodiment, components that are substantially the same as those in the above exemplary embodiments are labeled with the same reference numerals, and repeated descriptions are omitted. Figure 32 In this context, G(N) to G(N+9) are gating signals.

[0239] Reference Figure 32 The output nodes of signal transmitters ST1 to ST5 can be electrically connected to a gating line that is branched into two parts by the switching circuit 500. Therefore, the gating signals output from signal transmitters ST1 to ST5 can be supplied to the gating line shared by the sub-pixels of the two pixel rows.

[0240] For example, the gating signal output from the first signal transmitter ST1 can be supplied to the sub-pixel of the (N)th pixel row as the (N)th gating signal G(N) via the switching circuit 500, and can also be supplied to the sub-pixel of the (N+1)th pixel row as the (N+1)th gating signal G(N+1). The gating signal output from the second signal transmitter ST2 can be supplied to the sub-pixel of the (N+2)th pixel row as the (N+2)th gating signal G(N+2), and can also be supplied to the sub-pixel of the (N+3)th pixel row as the (N+3)th gating signal G(N+3). The gating signal output from the third signal transmitter ST3 can be supplied to the sub-pixel of the (N+4)th pixel row as the (N+4)th gating signal G(N+4), and can also be supplied to the sub-pixel of the (N+5)th pixel row as the (N+5)th gating signal G(N+5). The gating signal output from the fourth signal transmitter ST4 can be supplied as the (N+6)th gating signal G(N+6) to the sub-pixels of the (N+6)th pixel row, and simultaneously as the (N+7)th gating signal G(N+7) to the sub-pixels of the (N+7)th pixel row. The gating signal output from the fifth signal transmitter ST5 can be supplied as the (N+8)th gating signal G(N+8) to the sub-pixels of the (N+8)th pixel row, and simultaneously as the (N+9)th gating signal G(N+9) to the sub-pixels of the (N+9)th pixel row. However, this disclosure is not limited thereto.

[0241] Figure 32 The strobe driver shown can supply the strobe signal to Figure 15 The sub-pixels shown.

[0242] Figure 33 This is a circuit diagram illustrating the switching circuit and diodes of a gating driver according to a third exemplary embodiment of the present disclosure. Figure 34 It is shown Figure 33 The diagram shows the waveforms of the input / output signals of the gating driver. In this exemplary embodiment, components that are substantially the same as those in the above exemplary embodiments are labeled with the same reference numerals, and repeated descriptions are omitted or briefly discussed.

[0243] Reference Figure 33 and Figure 34 In response to selection signals SEL1 to SEL4, switching circuit 500 selectively connects the output nodes 511 and 513 of each of signal transmitters ST1 to ST5 to gating lines 512 and 514 and diodes D331 to D335.

[0244] Diodes D331 through D335 are used as switching elements, conducting when the voltage at the output node of the signal transmitter is the gate cutoff voltage and the voltage at the gate line is the gate on voltage. Diodes D331 through D335 are connected between the output node of the signal transmitter and the gate line to satisfy the above conduction conditions. For example, when the switching transistor of the pixel circuit is a p-channel LTPS TFT, such as... Figure 33 As shown, the cathode electrodes of diodes D331 to D335 are connected to gate lines 512 and 514, and the anode electrodes of diodes D331 to D335 are connected to the output nodes 511 and 513 of the signal transmitter. In the case of a p-channel LTPS TFT, the gate cutoff voltage is the high gate voltage VGH, and the gate on voltage is the low gate voltage VGL, as shown. Figure 34 As shown. Diodes D331 to D335 can be implemented as transistors with essentially the same structure as the transistors in the pixel circuit, such as p-channel LTPS TFTs or n-channel oxide TFTs.

[0245] According to the input Figure 15 The voltages of the strobe signals SCAN1 and SCAN2 shown in the pixel circuit allow the pixel circuit to operate as a refresh of the pixel region or to skip sub-pixels in the pixel region. Figure 33 The strobe driver shown can output strobe signals SCAN1 and SCAN2. Figure 33 In this context, G(N), G(N+1), and G(N+4) can be strobe signals SCAN1 and SCAN2 input to the pixel circuit of the refresh pixel region A with a high refresh rate. G(N+2) and G(N+3) can be strobe signals SCAN1 and SCAN2 input to the pixel circuit of the skip pixel region B with a low refresh rate.

[0246] The display devices according to exemplary embodiments of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle display devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptops, monitors, cameras, camcorders, home appliances, etc. Furthermore, the display devices according to one or more exemplary embodiments of this disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0247] The objectives to be achieved by this disclosure, the means to achieve these objectives, and the effects of this disclosure do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the content of this disclosure.

[0248] Although exemplary embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and do not limit the present disclosure.

[0249] Cross-references to related applications

[0250] This application claims priority and benefit to Korean Patent Application No. 10-2024-0121273, filed on September 6, 2024, the entire contents of which are hereby expressly incorporated herein for all purposes.

Claims

1. A gate drive circuit, the gate drive circuit comprising: a first switching transistor connected between a first gate line and an output node of a first signal transmitter from which a first gate signal is output; a second switching transistor connected to the output node of the first signal transmitter; a first diode connected between the second switching transistor and the first gate line; a third switching transistor connected between a second gate line and an output node of a second signal transmitter from which a second gate signal is output; a fourth switching transistor connected to the output node of the second signal transmitter; and a second diode connected between the fourth switching transistor and the second gate line. in response to selection signals input to gates of the first and second switching transistors, respectively, the output node of the first signal transmitter is selectively connected to the first gate line and the first diode.

2. A gating drive circuit according to claim 1, wherein, in response to selection signals input to gates of the third and fourth switching transistors, respectively, the output node of the second signal transmitter is selectively connected to the second gate line and the second diode.

3. A gating drive circuit according to claim 2, wherein, the first diode includes a cathode electrode connected to the second switching transistor and an anode electrode connected to the first gate line, and 4. The gating drive circuit of claim 1, wherein, wherein the second diode includes a cathode electrode connected to the fourth switching transistor and an anode electrode connected to the second gate line. the first diode includes an anode electrode connected to the second switching transistor and a cathode electrode connected to the first gate line, and 5. The gating drive circuit of claim 1, wherein, wherein the second diode includes an anode electrode connected to the fourth switching transistor and a cathode electrode connected to the second gate line. each of the first and second diodes includes a transistor having a gate electrode connected to one of a first electrode and a second electrode of the transistor.

6. The gating drive circuit of claim 1, wherein, the first signal transmitter includes:

7. The gating drive circuit of claim 1, wherein, a first-first input node to which a start pulse or a carry signal is input; and a second-first input node to which a first clock is input, wherein the first gate signal and a first carry signal are output through the output node of the first signal transmitter, wherein the second signal transmitter includes: a first-second input node to which the first carry signal is input; and a second-second input node to which a second clock having a phase different from a phase of the first clock is input, and wherein the second gate signal and a second carry signal are output through the output node of the second signal transmitter. at least one of the first and second gate lines is branched into two gate lines.

8. The gating drive circuit of claim 1, wherein, ​ 9. A display panel, comprising: a display area in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are arranged; and a plurality of gate drivers that supply gate signals to the gate lines, wherein at least one of the gate drivers includes the gate drive circuit according to any one of claims 1 to 8.

10. The display panel of claim 9, wherein, Each of the sub-pixels connected to the first gate line and the second gate line includes an n-channel transistor including a gate electrode to which the first gate signal or the second gate signal is applied.

11. The display panel of claim 9, wherein, Each of the sub-pixels connected to the first gate line and the second gate line includes a p-channel transistor including a gate electrode to which the first gate signal or the second gate signal is applied.

12. The display panel of claim 9, wherein, The sub-pixels include: a first sub-pixel connected to a first data line; and a second sub-pixel connected to a second data line, and wherein the first sub-pixel and the second sub-pixel are connected to the same gate line, and wherein at least one of the first gate line and the second gate line is branched into two gate lines and connected to the first sub-pixel and the second sub-pixel, respectively.

13. A display device, comprising: a display panel including a display area in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are arranged; and a plurality of gate drivers that supply gate signals to the gate lines; and a data driver connected to the data lines, wherein the display area includes at least a first pixel area and a second pixel area having different refresh rates, and wherein the sub-pixels of the first pixel area are driven at a first refresh rate while the sub-pixels of the second pixel area are driven at a second refresh rate lower than the first refresh rate, and wherein at least one of the gate drivers includes the gate drive circuit according to any one of claims 1 to 8.

14. The display device of claim 13, wherein, Each of the sub-pixels connected to the first gate line and the second gate line includes an n-channel transistor including a gate electrode to which the first gate signal or the second gate signal is applied.

15. The display device of claim 13, wherein, Each of the sub-pixels connected to the first gate line and the second gate line includes a p-channel transistor including a gate electrode to which the first gate signal or the second gate signal is applied.

16. The display device of claim 13, wherein, The sub-pixels include: a first sub-pixel connected to a first data line among the data lines; and a second sub-pixel connected to a second data line among the data lines, and wherein the first sub-pixel and the second sub-pixel are connected to the same gate line, and wherein at least one of the first gate line and the second gate line is branched into two gate lines and connected to the first sub-pixel and the second sub-pixel, respectively. At least one of the first and second gate lines is branched into two gate lines and connected to the first and second sub-pixels, respectively.

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