System for enhancing data writing function
By introducing enhancement circuitry into the magnetoresistive random access memory (RAM) to provide source line and bit line compensation voltages, the problem of reduced write capability is solved, enabling more efficient write operations and a wider operating range, while reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2026-03-10
AI Technical Summary
In traditional magnetoresistive random access memory, the accumulated internal resistance of the bit lines and source lines reduces the write capability, especially at low temperatures where the write operation range shrinks, affecting data write efficiency.
An enhancement circuit is introduced to reduce the equivalent internal resistance of memory cells and improve write efficiency by providing source line compensation voltage and bit line compensation voltage, and to provide voltage compensation in different write states.
It effectively reduces the equivalent internal resistance of memory cells, improves write efficiency, expands the write operation range, and reduces power consumption, ensuring good write performance at different process angles and low temperatures.
Smart Images
Figure CN121641097A_ABST
Abstract
Description
Technical Field
[0001] This invention describes a system for enhancing data writing functionality, and more particularly relates to a system for enhancing data writing functionality by reducing equivalent resistance to slow down write voltage decay. Background Technology
[0002] Magnetoresistive Random Access Memory (MRAM) is a novel type of non-volatile memory composed of numerous magnetic tunnel junctions (MTJs). A MTJ is a three-layer structure consisting of two ferromagnetic layers sandwiching an insulating layer; its resistance changes with the relative magnetization directions of the two ferromagnetic layers. MRAM offers advantages such as non-volatility, high speed, durability, and low power consumption, and is therefore increasingly used in flash memory, dynamic random-access memory (DRAM), and static random-access memory (SRAM). Furthermore, read / write operations on the MTJs are achieved by measuring their resistance.
[0003] In traditional magnetoresistive random access memory (MRAM), when the write voltage is applied from one side of the MRAM array, the internal resistance of the bit lines and source lines increases with their length, leading to a decrease in the write capability of some memory cells. Furthermore, this increased internal resistance also increases the write voltage requirement of the memory cells, resulting in a smaller write operation range at low temperatures.
[0004] Therefore, developing a system that reduces equivalent resistance to slow down write voltage decay and enhances data write functionality is an important design issue. Summary of the Invention
[0005] One embodiment of the present invention provides a system for enhancing data writing functionality. The system includes a magnetoresistive random access memory (MRMemory) array, a first driving circuit, a second driving circuit, and an enhancement circuit. The first driving circuit is coupled to the MRMemory array to provide multiple word line voltages to the MRMemory array. The second driving circuit is coupled to one side of the MRMemory array to provide multiple source line voltages and multiple bit line voltages to that side of the MRMemory array. The enhancement circuit is coupled to the other side of the MRMemory array to provide multiple source line compensation voltages and multiple bit line compensation voltages to the other side of the MRMemory array. Attached Figure Description
[0006] Figure 1 This is a block diagram of an embodiment of the system for enhancing data writing functionality according to the present invention.
[0007] Figure 2 for Figure 1 The architecture diagram of the magnetoresistive random access memory array and enhancement circuitry in a system with enhanced data writing capabilities.
[0008] Figure 3A for Figure 1 A schematic diagram of the enhancement circuit settings in a system with enhanced data write functionality, where the memory cell operates in the first write state.
[0009] Figure 3B for Figure 3A A schematic diagram of the equivalent circuit of memory cell operation in the first write state in a system with enhanced data writing capabilities.
[0010] Figure 4A for Figure 1 A schematic diagram of the enhancement circuit setting in a system with enhanced data writing functionality, where the memory cell operates in the second write state.
[0011] Figure 4B for Figure 4A A schematic diagram of the equivalent circuit of memory cell operation in the second write state in a system with enhanced data writing capabilities.
[0012] Figure 5 for Figure 1 The simulation results of the equivalent resistance value in different modes in a system with enhanced data writing capabilities.
[0013] Figure 6 for Figure 1 In systems with enhanced data writing capabilities, simulated results of writing voltage and current under different modes are obtained.
[0014] Figure 7 for Figure 1 A schematic diagram of the write operation range at low temperature in a system with enhanced data writing capabilities, under different process angles and modes.
[0015] [Symbol Explanation]
[0016] 100: Systems with enhanced data writing capabilities
[0017] 10: Magnetoresistive Random Access Memory Array
[0018] 11: First driving circuit
[0019] 12: Second drive circuit
[0020] 13: Enhancement Circuit
[0021] 10a: Memory unit
[0022] BL1 to BLN: Bit lines
[0023] SL1 to SLN: Source Line
[0024] WL1 to WLM: Word Lines
[0025] 13a: Source line enhancement unit
[0026] 13b: Bit line enhancement unit
[0027] T1: First transistor
[0028] T2: Second transistor
[0029] M1: Magnetic tunneling interface element
[0030] T3: Third transistor
[0031] T4: Fourth transistor
[0032] T5: Fifth transistor
[0033] T6: Sixth transistor
[0034] SL1 to SLN: Source Line
[0035] BL1 to BLN: Bit lines
[0036] WL1 to WLM: Word Lines
[0037] RsL1 to RsLM: Source line internal resistance
[0038] RbL1 to RbLM: Bit line internal resistance
[0039] P13a and P13b, P13a' and P13b': Path
[0040] Vwr' and Vwr: Write voltage (high voltage)
[0041] Vss' and Vss: Write voltage (low voltage)
[0042] msL: Source line node
[0043] (Mm)×RsL: First equivalent source line internal resistance
[0044] m×RsL: Second equivalent source line internal resistance
[0045] mbL: Bitline node
[0046] (Mm)×RbL: Resistance within the first equivalent potential line
[0047] m×RsL: Second equivalent potential line internal resistance
[0048] I: Current
[0049] C1 to C4, D1 to D4: Simulation Results Detailed Implementation
[0050] Figure 1 This is a block diagram of an embodiment of the system 100 for enhanced data writing functionality according to the present invention. The system 100 for enhanced data writing functionality can improve the write efficiency of magnetoresistive random access memory (MRAM). However, it should be understood that the principles and concepts of the system 100 for enhanced data writing functionality can be applied to any memory, and therefore the present invention is not limited to the application of magnetoresistive random access memory. For ease of understanding, the following description will still use the application of magnetoresistive random access memory to describe the system 100 for enhanced data writing functionality of the present invention. Please refer to... Figure 1The system 100 for enhancing data writing functionality includes a magnetoresistive random access memory (RAM) array 10, a first driving circuit 11, a second driving circuit 12, and an enhancement circuit 13. The RAM array 10 may include multiple memory cells 10a. For example, the RAM array 10 may have dimensions of M×N, containing M×N memory cells 10a. M and N are positive integers. The first driving circuit 11 is coupled to the RAM array 10 to provide multiple word line voltages to the RAM array 10. For example, the first driving circuit 11 can input these word line voltages to the RAM array 10 via multiple word lines WL1 to WLM. The second driving circuit 12 is coupled to one side of the RAM array 10 to provide multiple source line voltages and multiple bit line voltages to that side of the RAM array 10. For example, the second drive circuit 12 is coupled to the lower side of the magnetoresistive random access memory array 10, and inputs these source line voltages to the lower side of the magnetoresistive random access memory array 10 through multiple source lines SL1 to SLN. Furthermore, the second drive circuit 12 inputs these bit line voltages to the lower side of the magnetoresistive random access memory array 10 through multiple bit lines BL1 to BLN. The enhancement circuit 13 is coupled to the other side of the magnetoresistive random access memory array 10 to provide multiple source line compensation voltages and multiple bit line compensation voltages to the other side of the magnetoresistive random access memory array 10. For example, the enhancement circuit 13 is coupled to the upper side of the magnetoresistive random access memory array 10, and inputs these source line compensation voltages to the upper side of the magnetoresistive random access memory array 10 through multiple source lines SL1 to SLN. The enhancement circuit 13 inputs these bit line compensation voltages to the upper side of the magnetoresistive random access memory array 10 through multiple bit lines BL1 to BLN.
[0051] In other words, in the enhanced data write system 100, the magnetoresistive random access memory array 10 includes word lines WL1 to WLM, source lines SL1 to SLN, and bit lines BL1 to BLN. The word lines WL1 to WLM receive word line voltages generated by the first driving circuit 11. The endpoints of the source lines SL1 to SLN receive source line voltages generated by the second driving circuit 12. Similarly, the endpoints of the bit lines BL1 to BLN receive bit line voltages generated by the second driving circuit 12. Since the enhanced data write system 100 incorporates an enhancement circuit 13, the other endpoints of the source lines SL1 to SLN can receive source line compensation voltages generated by the enhancement circuit 13. The other endpoints of the bit lines BL1 to BLN can also receive bit line compensation voltages generated by the enhancement circuit 13.
[0052] As mentioned above, the magnetoresistive random access memory array 10 may include a plurality of memory cells 10a. Furthermore, since the source line voltage and source line compensation voltage can be fed in from both ends of the source line, each of these memory cells can receive the source line voltage and source line compensation voltage through the source line. Similarly, since the bit line voltage and bit line compensation voltage can be fed in from both ends of the bit line, each of these memory cells can receive the bit line voltage and bit line compensation voltage through the bit line.
[0053] Figure 2 The system 100 for enhancing data writing functionality includes an architecture diagram of a magnetoresistive random access memory array 10 and an enhancement circuit 13. Each memory cell 10a in the magnetoresistive random access memory array 10 can be a dual-transistor single magnetic tunneling junction (MTJ) element (abbreviated as 2T / 1M) architecture, as described below. Each memory cell may include a first transistor T1, a second transistor T2, and a MJ element M1. The first transistor T1 includes a first terminal coupled to the source line, a second terminal coupled to the source line, and a control terminal coupled to the word line. The second transistor T2 includes a first terminal coupled to the source line, a second terminal coupled to the second terminal of the first transistor T1, and a control terminal coupled to the word line. The MJ element M1 includes a first terminal coupled to the second terminal of the second transistor T2 and a second terminal coupled to the bit line. The first transistor T1 and the second transistor T2 are N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). Since memory cell 10a is a 2T / 1M architecture, each memory cell corresponds to two word lines, one source line, and one bit line. For example, when the magnetoresistive random access memory array 10 contains M×N memory cells, the (1,1)th memory cell corresponds to two word lines WL1, one source line SL1, and one bit line BL1. The (2,1)th memory cell corresponds to two word lines WL2, one source line SL1, and one bit line BL1, and so on, with the (M,N)th memory cell corresponding to two word lines WLM, one source line SLN, and one bit line BLN.
[0054] In the system 100 for enhanced data writing, the enhancement circuit 13 includes multiple source line enhancement units 13a and multiple bit line enhancement units 13b. Each source line enhancement unit 13a is coupled to a corresponding source line. Each bit line enhancement unit 13b is coupled to a corresponding bit line. The source line enhancement unit 13a includes a third transistor T3 and a fourth transistor T4. The third transistor T3 includes a first terminal for receiving a source line compensation voltage, a second terminal coupled to a source line, and a control terminal for receiving an inverting start signal EN'. The fourth transistor T4 includes a first terminal coupled to the first terminal of the third transistor T3, a second terminal coupled to the second terminal of the third transistor T3, and a control terminal for receiving the inverting start signal EN'. Furthermore, the third transistor is an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the fourth transistor is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET).
[0055] Bit line enhancement unit 13b includes a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 includes a first terminal for receiving a bit line compensation voltage, a second terminal coupled to the bit line, and a control terminal for receiving a start signal EN. The sixth transistor T6 includes a first terminal coupled to the first terminal of the fifth transistor T5, a second terminal coupled to the second terminal of the fifth transistor T5, and a control terminal for receiving the start signal EN. Furthermore, the fifth transistor is an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the sixth transistor is a P-type MOSFET.
[0056] It should be understood that each source line and each bit line has its internal resistance. For example, in Figure 2 In this example, assume there are M memory cells in a row. The internal resistance of the source line SL1 can include source line internal resistances RsL1 to RsLM. The internal resistance of the bit line BL1 can include bit line internal resistances RbL1 to RbLM. Excessive internal resistance can cause voltage drop (IR drop), thus affecting the write efficiency of the memory. The following section will explain the configuration details of the enhancement circuit 13 and the principle of reducing the equivalent internal resistance for various write states of memory cell 10a.
[0057] Figure 3AThis is a schematic diagram showing the setup of the enhancement circuit 13 in the system 100 for enhancing data writing functionality, where the memory cell 10a operates in a first write state. In the system 100 for enhancing data writing functionality, the memory cell 10a can operate in a first write state, also known as the Write to High (W2H) state. In this state, the inverting start signal EN' in the enhancement circuit 13 is a low voltage. Therefore, the fourth transistor T4 is turned on, and the third transistor T3 is turned off. The source line compensation voltage is a high voltage Vwr', and it is transmitted to one end of the source line in the memory cell 10a through the fourth transistor T4. Therefore, for the source line enhancement unit 13a, the high voltage Vwr' is transmitted to one end of the source line through path P13a. Furthermore, since the fourth transistor T4 is a P-type metal-oxide-semiconductor field-effect transistor, it has better conductivity when receiving high voltage. In the first write state, the source line voltage received at the other end of the source line in the memory cell 10a is the high voltage Vwr generated by the second drive circuit 12. In one embodiment, the source line compensation voltage is nearly equal to the source line voltage, i.e., Vwr' = Vwr.
[0058] For bit line enhancement unit 13b, the activation signal EN is a high voltage. Therefore, the fifth transistor T5 is turned on, and the sixth transistor T6 is turned off. The bit line compensation voltage is a low voltage Vss', and it is transmitted to one end of the bit line in memory cell 10a through the fifth transistor T5. Therefore, for bit line enhancement unit 13b, the low voltage Vss' is transmitted to one end of the bit line through path P13b. In the first write state, the bit line voltage received at the other end of the bit line in memory cell 10a is the low voltage Vss generated by the second drive circuit 12. In one embodiment, the bit line compensation voltage is approximately equal to the bit line voltage, i.e., Vss' = Vss.
[0059] Based on the above settings, the source line voltage and source line compensation voltage of memory cell 10a are high voltages (i.e., Vwr' = Vwr). Furthermore, the bit line voltage and bit line compensation voltage of memory cell 10a are low voltages (i.e., Vss' = Vss). Memory cell 10a operates in the first write state, i.e., the W2H state.
[0060] Figure 3B In system 100 for enhanced data writing functionality, a schematic diagram of the equivalent circuit for memory cell operation in the first write state is provided. As mentioned earlier, in the first write state, the fourth transistor T4 is turned on, the third transistor T3 is turned off, the fifth transistor T5 is turned on, and the sixth transistor T6 is turned off. Therefore, the third transistor T3 and the sixth transistor T6 are open circuits and are thus omitted. Figure 3BFurthermore, the internal resistance of source line SL1 can include source line internal resistances RsL1 to RsLM. The internal resistance of bit line BL1 can include bit line internal resistances RbL1 to RbLM. Therefore, for source line node msL, the equivalent source line internal resistance between source line node msL and source line compensation voltage (high voltage Vwr') is (Mm)×RsL, hereinafter referred to as the first equivalent source line internal resistance (Mm)×RsL. The first equivalent source line internal resistance (Mm)×RsL is equivalent to connecting the source line internal resistances of Mm memory cells in series. Furthermore, the equivalent source line internal resistance between source line node msL and source line voltage (high voltage Vwr) is m×RsL, hereinafter referred to as the second equivalent source line internal resistance m×RsL. The second equivalent source line internal resistance m×RsL is equivalent to connecting the source line internal resistances of m memory cells in series. Specifically, since the source line compensation voltage (high voltage Vwr') provided by the enhancement unit 13b is almost the same as the source line voltage (high voltage Vwr) provided by the second drive circuit 12, the first equivalent source line internal resistance (Mm)×RsL and the second equivalent source line internal resistance m×RsL are connected in parallel at the source line node msL. Therefore, the equivalent internal resistance value at the source line node msL and the two ends of the source line can be effectively reduced. In other words, when operating in the first write state, the equivalent source line internal resistance value of each source line at the source line node is less than the sum of the multiple source line internal resistance values M×RsL corresponding to multiple memory cells (e.g., M memory cells) in a row in the magnetoresistive random access memory array 10.
[0061] For a bitline node mbL, the equivalent internal resistance of the bitline between bitline node mbL and the bitline compensation voltage (low voltage Vss') is (Mm) × RbL, hereinafter referred to as the first equivalent internal resistance of the bitline (Mm) × RbL. The first equivalent internal resistance of the bitline (Mm) × RbL is equivalent to connecting the internal resistances of the bitlines in Mm memory cells in series. Furthermore, the equivalent internal resistance of the bitline between bitline node mbL and the bitline voltage (low voltage Vss) is m × RbL, hereinafter referred to as the second equivalent internal resistance of the bitline m × RbL. The second equivalent internal resistance of the bitline m × RbL is equivalent to connecting the internal resistances of the bitlines in m memory cells in series. Specifically, since the bit line compensation voltage (low voltage Vss') provided by the enhancement unit 13b is almost the same as the bit line voltage (low voltage Vss) provided by the second driving circuit 12, the first equivalent bit line internal resistance (Mm) × RbL and the second equivalent bit line internal resistance m × RbL are connected in parallel at the bit line node mbL. Therefore, the equivalent internal resistance values at the bit line node mbL and both ends of the bit line can be effectively reduced. In other words, when operating in the first write state, the equivalent bit line internal resistance value of each bit line at the bit line node is less than the sum of the multiple bit line internal resistance values M × RbL corresponding to multiple memory cells (e.g., M memory cells) in a row in the magnetoresistive random access memory array 10.
[0062] Furthermore, in the first write state (W2H), if the source line voltage and source line compensation voltage are high voltages (Vwr'=Vwr), and the bit line voltage and bit line compensation voltage are low voltages (Vss'=Vss), the current I can be transmitted from the source line SL1 through the first end of the magnetic tunneling junction element M1 to the second end of the magnetic tunneling junction element M1.
[0063] Figure 4A for Figure 1 This is a schematic diagram showing the setup of the enhancement circuit in a system with enhanced data write functionality, where the memory cell operates in the second write state. In the enhanced data write system 100, the memory cell 10a is operable in the second write state, also known as the Write to Low (W2L) state. In this state, the inverting start signal EN' in the enhancement circuit 13 is high. Therefore, the fourth transistor T4 is off, and the third transistor T3 is on. The source line compensation voltage is low, Vss', and is transmitted to one end of the source line in the memory cell 10a via the third transistor T3. Therefore, for the source line enhancement unit 13a, the low voltage Vss' is transmitted to one end of the source line via path P13a'. In the second write state, the source line voltage received at the other end of the source line in the memory cell 10a is the low voltage Vss generated by the second drive circuit 12. In one embodiment, the source line compensation voltage is nearly equal to the source line voltage, i.e., Vss' = Vss.
[0064] For bit line enhancement unit 13b, the start signal EN is a low voltage. Therefore, the fifth transistor T5 is off, and the sixth transistor T6 is on. The bit line compensation voltage is a high voltage Vwr', and it is transmitted to one end of the bit line in memory cell 10a through the sixth transistor T6. Therefore, for bit line enhancement unit 13b, the high voltage Vwr' is transmitted to one end of the bit line through path P13b'. Furthermore, since the sixth transistor T6 is a P-type metal-oxide-semiconductor field-effect transistor, it has better conductivity when receiving high voltage. In the second write state, the bit line voltage received at the other end of the bit line in memory cell 10a is the high voltage Vwr generated by the second drive circuit 12. In one embodiment, the bit line compensation voltage is nearly equal to the bit line voltage, that is, Vwr' = Vwr.
[0065] Based on the above settings, the source line voltage and source line compensation voltage of memory cell 10a are low voltages (i.e., Vss' = Vss). Furthermore, the bit line voltage and bit line compensation voltage of memory cell 10a are high voltages (i.e., Vwr' = Vwr). Memory cell 10a operates in the second write state, i.e., the W2L state.
[0066] Figure 4B In system 100 for enhanced data writing functionality, a schematic diagram of the equivalent circuit for memory cell operation in the second write state is provided. As mentioned earlier, in the second write state, the fourth transistor T4 is off, the third transistor T3 is on, the fifth transistor T5 is off, and the sixth transistor T6 is on. Therefore, the fourth transistor T4 and the fifth transistor T5 are open circuits and are thus omitted. Figure 4BFurthermore, for the source line node msL, the equivalent source line internal resistance between the source line node msL and the source line compensation voltage (low voltage Vss') is (Mm) × RsL, hereinafter referred to as the first equivalent source line internal resistance (Mm) × RsL. The first equivalent source line internal resistance (Mm) × RsL is equivalent to connecting the source line internal resistances of Mm memory cells in series. Furthermore, the equivalent source line internal resistance between the source line node msL and the source line voltage (low voltage Vss) is m × RsL, hereinafter referred to as the second equivalent source line internal resistance m × RsL. The second equivalent source line internal resistance m × RsL is equivalent to connecting the source line internal resistances of m memory cells in series. Specifically, since the source line compensation voltage (low voltage Vss') provided by the enhancement unit 13b is almost the same as the source line voltage (low voltage Vss) provided by the second drive circuit 12, the first equivalent source line internal resistance (Mm)×RsL and the second equivalent source line internal resistance m×RsL are connected in parallel at the source line node msL. Therefore, the equivalent internal resistance value at the source line node msL and the two ends of the source line can be effectively reduced. In other words, when operating in the second write state, the equivalent source line internal resistance value of each source line at the source line node is less than the sum of the multiple source line internal resistance values M×RsL corresponding to multiple memory cells (e.g., M memory cells) in a row in the magnetoresistive random access memory array 10.
[0067] For a bitline node mbL, the equivalent internal resistance of the bitline between bitline node mbL and the bitline compensation voltage (high voltage Vwr') is (Mm) × RbL, hereinafter referred to as the first equivalent internal resistance of the bitline (Mm) × RbL. The first equivalent internal resistance of the bitline (Mm) × RbL is equivalent to connecting the internal resistances of the bitlines in Mm memory cells in series. Furthermore, the equivalent internal resistance of the bitline between bitline node mbL and the bitline voltage (high voltage Vwr) is m × RbL, hereinafter referred to as the second equivalent internal resistance of the bitline m × RbL. The second equivalent internal resistance of the bitline m × RbL is equivalent to connecting the internal resistances of the bitlines in m memory cells in series. Specifically, since the bit line compensation voltage (high voltage Vwr') provided by the enhancement unit 13b is almost the same as the bit line voltage (high voltage Vwr) provided by the second driving circuit 12, the first equivalent bit line internal resistance (Mm)×RbL and the second equivalent bit line internal resistance m×RbL are connected in parallel at the bit line node mbL. Therefore, the equivalent internal resistance values at the bit line node mbL and both ends of the bit line can be effectively reduced. In other words, when operating in the second write state, the equivalent bit line internal resistance value of each bit line at the bit line node is less than the sum of the multiple bit line internal resistance values M×RbL corresponding to multiple memory cells (e.g., M memory cells) in a row in the magnetoresistive random access memory array 10.
[0068] Furthermore, in the second write state (W2L), if the source line voltage and source line compensation voltage are low (Vss'=Vss), and the bit line voltage and bit line compensation voltage are high (Vwr'=Vwr), the current I can be transmitted from the bit line BL1 through the second end of the magnetic tunneling junction element M1 to the first end of the magnetic tunneling junction element M1.
[0069] Figure 5 In system 100, designed to enhance data writing capabilities, simulation results of equivalent resistance values are presented under different modes. The X-axis represents nodes, and the Y-axis represents the equivalent resistance value in ohms. With enhancement circuit 13 disabled (no boost function), the simulation results of the equivalent bit line resistance values at different nodes A to F are represented by C1. With enhancement circuit 13 disabled (no boost function), the simulation results of the equivalent source line resistance values at different nodes A to F are represented by C2. With enhancement circuit 13 enabled (using boost function), the simulation results of the equivalent bit line resistance values at different nodes A to F are represented by C3. With enhancement circuit 13 enabled (using boost function), the simulation results of the equivalent source line resistance values at different nodes A to F are represented by C4. (Example...) Figure 5 As shown in simulation results C1 and C3, when the enhancement circuit 13 is turned on, the equivalent bit line resistance values of nodes A to F at different locations will be significantly reduced due to the voltage boosting function. Similarly, as Figure 5 As shown in simulation results C2 and C4, when the enhancement circuit 13 is turned on, the equivalent source line resistance values of nodes A to F at different locations will be significantly reduced due to the boost function.
[0070] Figure 6 This section presents simulation results of write voltage and current in different modes within a system with data writing functionality. The X-axis represents the write voltage, denoted as high voltage Vwr, in volts. The Y-axis represents the current, in amperes. The voltage and current simulation results in the W2L state (with enhancement circuit 13 off, without boost function) are represented by D1. The voltage and current simulation results in the W2H state (with enhancement circuit 13 off, without boost function) are represented by D2. The voltage and current simulation results in the W2L state (with enhancement circuit 13 on, using boost function) are represented by D3. The voltage and current simulation results in the W2H state (with enhancement circuit 13 on, using boost function) are represented by D4. (Example...) Figure 6 As shown in simulation results D3 and D1, when enhancement circuit 13 is turned on, only a small write voltage is needed to enter the W2L state due to the boost function. Similarly, as... Figure 6As shown in simulation results D4 and D2, when enhancement circuit 13 is turned on, due to the boost function, only a small write voltage is needed to enter the W2H state. In other words, when enhancement circuit 13 is turned on, the speed of entering the W2H or W2L state can be accelerated.
[0071] Figure 7 This diagram illustrates the write operation range at low temperatures in System 100, which enhances data writing functionality, under different process angles and modes. Figure 7 In this context, process corners are considered in three configurations: Typical-Typical, Slow-Slow, and Fast-Fast. It should be understood that, to comprehensively consider the reliability of memory cells in any process corner configuration, the write operation range of the memory cells will be represented by the Slow-Slow configuration, which has poorer operating conditions. At a low temperature of -40 degrees Celsius, when enhancement circuit 13 is turned on, according to... Figure 7 As shown, a write voltage (represented by the high voltage Vwr) of 1.1 volts or higher and a word line voltage VWL of 1.3 volts or higher are sufficient for a memory cell to enter a good write operation range. However, at a low temperature of -40 degrees Celsius, when the enhancement circuit 13 is off (i.e., in its original state), according to Figure 7 As shown, a write voltage (represented by the high voltage Vwr) of 1.2 volts or higher and a word line voltage VWL of 1.4 volts or higher are sufficient for a memory cell to enter a good write operation range. Therefore, when the enhancement circuit 13 is turned on, the write operation range of the memory cell can be expanded due to the voltage boosting function.
[0072] In summary, this invention provides a system for enhancing data writing functionality, applicable to magnetoresistive random access memory (RAM). The system introduces an enhancement circuit that effectively reduces the equivalent internal resistance of memory cells during write operations, thereby improving data writing efficiency. Furthermore, the enhancement circuit provides source line compensation voltage and bit line compensation voltage, enabling voltage compensation for memory cells under different write states, thus reducing the requirement for write voltage. Specifically, the system for enhancing data writing functionality of this invention has the following advantages: 1. Improved write efficiency: Reduced equivalent internal resistance, reduced voltage drop, and faster write speed; 2. Expanded write operation range: Maintains good write performance under different process angles and low temperatures; 3. Reduced power consumption: Reduced write voltage requirement to increase the speed of entering different write states (W2H or W2L).
[0073] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.
Claims
1. A system for enhancing data write function, comprising: a magnetoresistive random access memory array; a first driver circuit coupled to the magnetoresistive random access memory array for providing a plurality of word line voltages to the magnetoresistive random access memory array; a second driver circuit coupled to one side of the magnetoresistive random access memory array for providing a plurality of source line voltages and a plurality of bit line voltages to the one side of the magnetoresistive random access memory array; and an enhancement circuit coupled to another side of the magnetoresistive random access memory array for providing a plurality of source line compensation voltages and a plurality of bit line compensation voltages to the another side of the magnetoresistive random access memory array.
2. The system of claim 1, wherein the magnetoresistive random access memory array comprises a plurality of word lines for receiving the word line voltages generated by the first driver circuit, a plurality of source lines having end points for receiving the source line voltages generated by the second driver circuit, and a plurality of bit lines having end points for receiving the bit line voltages generated by the second driver circuit.
3. The system of claim 2, wherein the source lines have another end points for receiving the source line compensation voltages generated by the enhancement circuit, and the bit lines have another end points for receiving the bit line compensation voltages generated by the enhancement circuit.
4. The system of claim 3, wherein each of the source lines has an equivalent source line internal resistance at a source line node that is less than a sum of a plurality of source line internal resistances corresponding to a plurality of memory cells in a row of the magnetoresistive random access memory array.
5. The system of claim 3, wherein each of the bit lines has an equivalent bit line internal resistance at a bit line node that is less than a sum of a plurality of bit line internal resistances corresponding to a plurality of memory cells in a row of the magnetoresistive random access memory array.
6. The system of claim 1, wherein the magnetoresistive random access memory array comprises a plurality of memory cells, each of the memory cells receiving a source line voltage and a source line compensation voltage through a source line, and receiving a bit line voltage and a bit line compensation voltage through a bit line.
7. The system of claim 6, wherein the memory cell operates in a first write state if the source line voltage and the source line compensation voltage of the memory cell are high voltages, and the bit line voltage and the bit line compensation voltage are low voltages.
8. The system of claim 6, wherein the memory cell operates in a second write state if the source line voltage and the source line compensation voltage of the memory cell are low voltages, and the bit line voltage and the bit line compensation voltage are high voltages.
9. The system of claim 1, wherein the enhancement circuit is controlled by an enable signal and an inverted enable signal such that the source line voltages are substantially equal to the source line compensation voltages, and the bit line voltages are substantially equal to the bit line compensation voltages. 10. The system of claim 1, wherein the magnetoresistive random access memory array comprises a plurality of memory cells, each of the memory cells comprising: a first transistor comprising: a first terminal coupled to a source line; a second terminal; and a control terminal coupled to a word line; a second transistor comprising: a first terminal coupled to the source line; and a second end; coupled to the second end of the first transistor; a control terminal coupled to the word line; and a magnetic tunnel junction element comprising: a first terminal coupled to the second terminal of the second transistor; and a second terminal coupled to a bit line; wherein the first transistor and the second transistor are N-type Metal Oxide Semiconductor Field Effect Transistors (NMOS FETs).
11. The system of claim 10, wherein one end of the source line receives a source line voltage, another end of the source line receives a source line compensation voltage, one end of the bit line receives a bit line voltage, and another end of the bit line receives a bit line compensation voltage.
12. The system of claim 11, wherein if the source line voltage and the source line compensation voltage are high voltages, and the bit line voltage and the bit line compensation voltage are low voltages, current is conducted from the source line, through the first terminal of the magnetic tunnel junction element, to the second terminal of the magnetic tunnel junction element.
13. The system of claim 11, wherein if the source line voltage and the source line compensation voltage are low voltages, and the bit line voltage and the bit line compensation voltage are high voltages, current is conducted from the bit line, through the second terminal of the magnetic tunnel junction element, to the first terminal of the magnetic tunnel junction element.
14. The system of claim 10, wherein the boost circuit comprises a plurality of source line boost cells and a plurality of bit line boost cells, each of the source line boost cells coupled to the source line, and each of the bit line boost cells coupled to the bit line.
15. The system of claim 14, wherein the source line boost cell comprises: a third transistor comprising: a first terminal to receive a source line compensation voltage; a second terminal coupled to the source line; and a control terminal to receive an inverted enable signal; and a fourth transistor comprising: a first terminal coupled to the first terminal of the third transistor; a second terminal coupled to the second terminal of the third transistor; and a control terminal to receive the inverted enable signal; wherein the third transistor is an N-type Metal Oxide Semiconductor Field Effect Transistor (NMOS FET), and the fourth transistor is a P-type Metal Oxide Semiconductor Field Effect Transistor (PMOS FET). 16. The system of claim 15, wherein when the inverted enable signal is low voltage, the fourth transistor is on, the third transistor is off, the source line compensation voltage is high voltage, and is delivered to one end of the source line in the memory cell through the fourth transistor.
17. The system of claim 15, wherein when the inverted enable signal is high voltage, the fourth transistor is off, the third transistor is on, the source line compensation voltage is low voltage, and is delivered to one end of the source line in the memory cell through the third transistor.
18. The system of claim 14, wherein the bit line boosting unit comprises: a fifth transistor comprising: a first end to receive a bit line compensation voltage; a second end coupled to the bit line; and a control end to receive an enable signal; and a sixth transistor comprising: a first end coupled to the first end of the fifth transistor; a second end coupled to the second end of the fifth transistor; and a control end to receive the enable signal; wherein the fifth transistor is an N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) and the sixth transistor is a P-type Metal Oxide Semiconductor Field Effect Transistor (PMOSFET).
19. The system of claim 18, wherein when the enable signal is low voltage, the fifth transistor is off, the sixth transistor is on, the bit line compensation voltage is high voltage, and is delivered to one end of the bit line in the memory cell through the sixth transistor.
20. The system of claim 18, wherein when the enable signal is high voltage, the fifth transistor is on, the sixth transistor is off, the bit line compensation voltage is low voltage, and is delivered to one end of the bit line in the memory cell through the fifth transistor.