Memory, access control method thereof and electronic equipment
By using a multi-layer memory cell array and gating sub-circuit control, the problem of large common bit line coupling capacitance in memory is solved, achieving more efficient wiring and lower resistance, improving device performance and reducing production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2026-03-10
AI Technical Summary
In existing technologies, the common bit line coupling capacitance of memory is relatively large, which leads to complex wiring and increases resistance and coupling capacitance, affecting device performance and production costs.
It adopts a multi-layer memory cell array structure, with local bit lines and local word lines interspersed, and common bit lines connected through a sensing amplifier. Local bit lines and common bit lines are not adjacent. The voltage of the common bit line is controlled by a gating sub-circuit, which reduces the coupling capacitance and wiring length of the common bit line.
The reduced coupling capacitance of the common bit line simplifies wiring, reduces the number of sense amplifiers, improves device performance, and lowers production costs.
Smart Images
Figure CN121641101A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the field of semiconductor technology, and in particular to a memory and a manufacturing method thereof, and an electronic device. BACKGROUND
[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.
[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY
[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0005] The present application provides a memory and an access control method thereof, and an electronic device, which reduces the coupling capacitance of a common bit line.
[0006] The present application provides a memory, comprising: at least one memory array, a plurality of common word lines, and a plurality of common bit lines, the memory array comprising a plurality of memory cell arrays stacked along a direction perpendicular to a substrate, a plurality of local bit lines extending along a direction perpendicular to the substrate and arranged along a first direction and a second direction;
[0007] The memory cell array comprises: a plurality of memory cells arranged along the first direction and the second direction, a plurality of local word lines extending along the second direction corresponding to each column of memory cells arranged along the second direction, and the local word lines connecting the corresponding column of memory cells; the local bit lines connect a plurality of memory cells at the same position of different layers, and the first direction and the second direction are parallel to the substrate and intersect each other;
[0008] The plurality of local word lines of the same memory cell array are divided into a plurality of word line groups, each word line group connecting one common word line, and different word line groups connecting different common word lines; each word line group comprises two local word lines, and the two local word lines in the same word line group are connected to the memory cells of different columns, respectively;
[0009] Each row of local bit lines distributed along the first direction corresponds to four common bit lines. Each local bit line is connected to one common bit line. Among the multiple local bit lines in the same row, every four consecutively distributed local bit lines are connected to different common bit lines among the four common bit lines corresponding to the local bit lines in that row. The common bit lines connected to the memory cells connected to the local bit lines of the same word line group are not adjacent. The common bit lines are connected to the sense amplifier, and the common bit lines connected to the two input ports of the sense amplifier are two common bit lines of the same memory array. The memory cells connected to the two common bit lines connected to the same sense amplifier are connected to different common word lines.
[0010] In some embodiments, the two common bit lines connected to the same sensing amplifier are two adjacent common bit lines among the four common bit lines corresponding to each row of local bit lines.
[0011] In some embodiments, the orthographic projection of the sensing amplifier onto the substrate is located within the orthographic projection of the memory array containing the common bit line to which the sensing amplifier is connected, and overlaps with the orthographic projection of at least one common bit line to which the sensing amplifier is connected onto the substrate.
[0012] In some embodiments, each of the common bit lines is also connected to a second preset voltage terminal via a first gating sub-circuit. The first gating sub-circuit is connected to a first gating control line and is configured to electrically connect or disconnect the common bit line and the second preset voltage terminal under the control of the first gating control line.
[0013] In some embodiments, multiple first gating sub-circuits connected to multiple common bit lines that are respectively connected to local bit lines in the same column are connected to the same first gating control line.
[0014] In some embodiments, the memory further includes a control circuit configured to:
[0015] Based on the word line group to which the local word line connected to the target storage cell to be operated is located, an activation signal is loaded on the common word line connected to the word line group. The target storage cell includes two columns of storage cells, and the two columns of storage cells are respectively connected to two local word lines of the same word line group.
[0016] A shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the two columns of target local bit lines that are respectively connected to the target memory cell;
[0017] During the charge sharing phase, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the non-target common bit line; during the signal amplification phase, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the non-target common bit line; wherein, the common bit line connected to the two columns of target local bit lines is called the target common bit line, and the other common bit lines of the memory cell array where the target memory cell is located are called non-target common bit lines.
[0018] In some embodiments, the word line group containing the local word lines connected to the storage cells in the odd-numbered columns is called the odd-numbered column word line group, the word line group containing the local word lines connected to the storage cells in the even-numbered columns is called the even-numbered column word line group, the common bit line connected to the local bit lines connected to the storage cells in the odd-numbered columns is called the odd-numbered column common bit line, and the common bit line connected to the local bit lines connected to the storage cells in the even-numbered columns is called the even-numbered column common bit line; the control circuit is further configured to:
[0019] When the target storage cell is an odd-numbered column storage cell, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column; during the charge sharing stage, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column; during the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column.
[0020] When the target storage cell is an even-numbered column storage cell, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column; during the charge sharing stage, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column; and during the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column.
[0021] This disclosure provides an access control method applied to any of the above-described memories, including:
[0022] During the data read / write phase, an activation signal is loaded on the common word line connected to the word line group to which the local word line to be operated is located, according to the word line group to which the target storage unit to be operated is located. The target storage unit includes two columns of storage units, and the two columns of storage units are respectively connected to two local word lines of the same word line group.
[0023] A shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the two columns of target local bit lines that are respectively connected to the target memory cell;
[0024] During the charge sharing phase, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the non-target common bit line; during the signal amplification phase, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the non-target common bit line; wherein, the common bit line connected to the two columns of target local bit lines is called the target common bit line, and the other common bit lines of the memory cell array where the target memory cell is located are called non-target common bit lines.
[0025] In some embodiments, the word line group containing the local word lines connected to the storage cells in the odd-numbered columns is called the odd-numbered column word line group, the word line group containing the local word lines connected to the storage cells in the even-numbered columns is called the even-numbered column word line group, the common bit line connected to the local bit lines connected to the storage cells in the odd-numbered columns is called the odd-numbered column common bit line, and the common bit line connected to the local bit lines connected to the storage cells in the even-numbered columns is called the even-numbered column common bit line; the method further includes:
[0026] When the target storage cell is an odd-numbered column storage cell, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column; during the charge sharing stage, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column; during the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column.
[0027] When the target storage cell is an even-numbered column storage cell, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column; during the charge sharing stage, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column; and during the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column.
[0028] This disclosure provides an electronic device including any of the memory described above.
[0029] This application includes a memory and an access control method thereof. The memory includes: at least one memory array, the memory array including a multilayer memory cell array stacked along a direction perpendicular to a substrate, and multiple local bit lines extending along a direction perpendicular to the substrate and distributed along a first direction and a second direction; the memory cell array includes: multiple memory cells distributed along the first direction and the second direction, and multiple local word lines extending along the second direction corresponding one-to-one with each column of memory cells distributed along the second direction, and the local word lines connecting to a corresponding column of memory cells; the local bit lines connecting multiple memory cells at the same position in different layers, the first direction and the second direction being parallel to the substrate and intersecting; the multiple local word lines of the same memory cell array are divided into multiple word line groups, and each word line group is connected to a common word line. The system uses a word line array, where different word line groups connect to different common word lines. Each word line group includes two local word lines, and the two local word lines within the same word line group are respectively connected to memory cells in adjacent columns. Each row of local bit lines distributed along a first direction corresponds to four common bit lines, and each local bit line is connected to one common bit line. Among multiple local bit lines in the same row, every four consecutively distributed local bit lines are respectively connected to different common bit lines among the four common bit lines corresponding to the local bit lines in that row. The common bit lines connected to the memory cells connected to the local bit lines of the same word line group are not adjacent. The common bit lines are connected to a sense amplifier, and the common bit lines connected to the two input ports of the sense amplifier are respectively two common bit lines of the same memory array. The memory cells connected to the two common bit lines connected to the same sense amplifier are connected to different common word lines. The solution provided in this embodiment has a large spacing between the bit lines operating simultaneously, which reduces the coupling capacitance between bit lines, reduces the interference between bit lines, and can reduce the wiring length of the common bit lines and reduce the coupling capacitance of the common bit lines.
[0030] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.
[0031] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0032] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0033] Figure 1 A schematic diagram of the logic circuit of a memory provided for some embodiments;
[0034] Figure 2A schematic diagram of bit lines and common bit lines connections provided for some embodiments;
[0035] Figure 3 A schematic diagram (top view) of the layout of the storage array and sense amplifier;
[0036] Figure 4 Schematic diagrams of bit line and common bit line connections provided for other embodiments;
[0037] Figure 5 A timing diagram of control signals provided for some embodiments;
[0038] Figure 6 Control signal timing diagrams provided for other embodiments;
[0039] Figure 7 A schematic diagram of the control circuit provided for some embodiments;
[0040] Figure 8 for Figure 7 The timing diagram of the control circuit shown is shown. Detailed Implementation
[0041] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.
[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.
[0043] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values shown in the drawings.
[0044] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.
[0045] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.
[0046] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.
[0047] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0048] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.
[0049] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0050] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0051] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
[0052] In memory, the common bit line connecting memory cells is typically connected to a sense amplifier (SA). The SA determines the data stored in the memory cell by detecting changes in the signal on the common bit line. Typically, one SA is shared by two memory arrays; that is, the two input ports of the SA are connected to the common bit line from different memory arrays. One of the two input ports can serve as a signal detection terminal, and the other as a signal reference terminal. Both can function as either a signal detection terminal or a signal reference terminal, allowing detection of the data stored in the memory cells connected by the common bit lines (CBLs) of the two memory arrays. Memory arrays are typically large, resulting in long CBL wirings and significant coupling capacitance. Furthermore, the long CBL wirings also burden the layout of the wafer where the SA is located. In this embodiment, the two input ports of one SA are connected to the CBL from the same memory array, thereby reducing the CBL wiring length and lowering the CBL resistance and coupling capacitance.
[0053] Figure 1 A schematic diagram of the logic circuit of a memory provided for an exemplary embodiment. For example... Figure 1 As shown, the memory may include at least one memory array. When multiple memory arrays exist, they may be arranged along the second direction Y. The memory array includes a multilayer memory cell array stacked perpendicular to the substrate direction and multiple local bit lines (LBLs) extending perpendicular to the substrate direction. The memory cell array may include multiple memory cells 11 distributed along the first direction X and the second direction Y, and multiple local word lines (LWLs) extending along the second direction Y. Memory cells in the same column of the same layer distributed along the second direction Y are connected to the same LWL. Memory cells 11 in different columns are connected to different LWLs. Memory cells 11 at the same position in different layers are connected to the same LBL. Multiple LBLs are distributed along the first direction X and the second direction Y. The memory may also include multiple common word lines (CWLs) and multiple common bit lines (CBLs). The CBLs may extend along the first direction X. Multiple CBLs of the same memory cell array may be spaced apart along the second direction Y.
[0054] The storage cell 11 may include a transistor and a capacitor. The transistor includes a gate electrode, a first electrode, and a second electrode. The gate electrode of the transistor is connected to LWL, the first electrode of the transistor is connected to LBL, and the second electrode of the transistor is connected to a first terminal of the capacitor. The second terminal of the capacitor is connected to a first preset voltage terminal V. PL The first preset voltage terminal V PLFor example, it could be a fixed potential, such as the value between the voltage corresponding to logic data "0" and the voltage corresponding to logic data "1". For instance, the voltage corresponding to logic data "0" is "0", and the voltage corresponding to logic data "1" is VDD, then V PL It can be 1 / 2VDD.
[0055] Multiple LWLs in the same memory cell array are divided into multiple groups, called word line groups. Each LWL belongs to only one word line group. Each word line group includes two LWLs, and the two LWLs in the same word line group are separated by one LWL. The LWLs in the same word line group are connected to the same CWL. For example, if the memory cell array includes N rows of memory cells and 2M columns of memory cells, that is, N*2M memory cells, then it includes 2M LWLs. The j-th LWL is connected to the j-th column of memory cells, where j is 1 to 2M. The first LWL and the third LWL form the first word line group, and the LWL of this word line group is connected to the first common word line CWL_0; the second LWL and the fourth LWL form the second word line group, and are connected to the second common word line CWL_1; the fifth LWL and the seventh LWL form the third word line group, and are connected to the third common word line CWL_2; the sixth LWL and the eighth LWL form the fourth word line group, and are connected to the fourth common word line CWL_3; and so on, the 2M-3 LWL and the 2M-1 LWL form the M-1 word line group, and are connected to the M-1 common word line CWL_M-2; the 2M-2 LWL and the 2M LWL form the M word line group, and are connected to the M common word line CWL_M-1. Compared to the CWL scheme that connects four word lines to the same memory cell array, the solution provided in this embodiment allows each LWL to connect more memory cells and is easier to route.
[0056] Each row of LBLs distributed along the first direction X corresponds to 4 CBLs. Each LBL is connected to one CBL. In multiple LBLs within the same row, every 4 consecutively distributed LBLs are connected to different CBLs within the 4 CBLs corresponding to that row. Among LBLs connected to the same CBL, adjacent LBLs (here referring to adjacent LBLs within a group of LBLs connected to the same CBL) are separated by 3 LBLs, and the CBLs connected to the memory cells connected to by LWLs in the same word line group are not adjacent. For example, as... Figure 2As shown, the multiple LBLs in the (i+1)th row correspond to four common bit lines CBL_i_0, CBL_i_1, CBL_i_2, and CBL_i_3, where i is from 0 to N-1. Specifically, the LBLs in columns 1, 5, ..., 2M-3 of the (i+1)th row are connected to the first common bit line CBL_i_0 of that row; the LBLs in columns 2, 6, ..., 2M-2 of the (i+1)th row are connected to the second common bit line CBL_i_1 of that row; the LBLs in columns 3, 7, ..., 2M-1 of the (i+1)th row are connected to the third common bit line CBL_i_2 of that row; and the LBLs in columns 4, 8, ..., 2M of the (i+1)th row are connected to the fourth common bit line CBL_i_3 of that row. In other embodiments, the LBLs in columns 1, 5, ..., 2M-3 of row i+1 can be connected to the 4th common bit line CBL_i_3 of that row; the LBLs in columns 2, 6, ..., 2M-2 of row i+1 can be connected to the 3rd common bit line CBL_i_2 of that row; the LBLs in columns 3, 7, ..., 2M-1 of row i+1 can be connected to the 2nd common bit line CBL_i_1 of that row; and the LBLs in columns 4, 8, ..., 2M of row i+1 can be connected to the 1st common bit line CBL_i_0 of that row. The above connection method is merely an example; other connection methods are possible. For instance, the LBL in columns 1, 5, ..., 2M-3 of row i+1 could be connected to the 3rd common bit line CBL_i_2 of that row; the LBL in columns 2, 6, ..., 2M-2 of row i+1 could be connected to the 2nd common bit line CBL_i_1 of that row; the LBL in columns 3, 7, ..., 2M-1 of row i+1 could be connected to the 1st common bit line CBL_i_0 of that row; the LBL in columns 4, 8, ..., 2M of row i+1 could be connected to the 4th common bit line CBL_i_3 of that row, and so on. It is ensured that the LBLs connected to memory cells within the same word line group are not adjacent to the CBLs connected to, thus preventing adjacent CBLs from operating simultaneously.
[0057] Of the M CWLs connected to each memory cell array, only one CWL is active at any given time. For example, with the connection method of LBL and CBL as follows: Figure 1 and Figure 2Taking the example shown, when the common word line CWL_0 is activated, the transistors of the first and third column memory cells connected to the first and third LWLs are turned on. The corresponding LBLs connected to the first and third column memory cells respectively read or write data through charge sharing. That is, the LBLs working at this time are the LBLs connected to the first and third column memory cells. The two are not adjacent LBLs. The first and third column LBLs are separated by two memory cells and are far apart. The coupling between them is very small. In addition, the second column LBL can shield the first and third column LBLs, which can further reduce the coupling between the first and third column LBLs. Therefore, a common bit line can connect more LBLs, and the corresponding memory can use fewer common bit lines, which reduces the number of sense amplifiers connected to the common bit line. At this time, among the four CBLs corresponding to the same row of LBLs, only the two non-adjacent CBLs connected to the two LBLs in the column where the two active local word lines are located are working. The other two CBLs are not working and can act as shielding lines between the working CBLs. The shielding lines can shield adjacent CBLs, reduce the coupling capacitance between adjacent CBLs, so that one CBL can connect more LBLs, and the corresponding memory can use fewer CBLs, as well as fewer sense amplifiers. For example, when the common word line CWL_0 is activated, the LBLs connected to the first and third column memory cells respectively read or write data through charge sharing. The LBL connected to the memory cell in row i+1, column 1 is connected to the common bit line CBL_i_0, and the LBL connected to the memory cell in row i+1, column 3 is connected to the common bit line CBL_i_2. At this time, CBL_i_1 and CBL_i_3 are not working. CBL_i_1 can act as a shield between CBL_i_0 and CBL_i_2, and CBL_i_3 can act as a shield between CBL_i_2 and the adjacent CBL on the other side (i.e., the CBL corresponding to the LBL in the adjacent row).
[0058] In some embodiments, the CBL can be connected to the SA, and the CBLs connected to the two input ports of the same SA are two CBLs of the same memory array. Each input port connects to one CBL, and the memory cells connected to the two CBLs connected to the same SA are connected to different CWLs. The solution provided in this embodiment, where the SA connects to two CBLs of the same memory array, can reduce the CBL wiring length, CBL resistance, and coupling capacitance. Compared to connecting the two input ports of the SA to CBLs from different memory arrays, the solution provided in this embodiment results in shorter CBL traces, smaller coupling capacitance, lower resistance, and reduced wiring complexity.
[0059] In some embodiments, every two adjacent CBLs of the four CBLs corresponding to each row of LBLs can be connected to two input ports of the same SA, with one CBL connected to the signal detection terminal and the other CBL connected to the signal reference terminal. However, this embodiment is not limited to this; the CBLs corresponding to each row of LBLs can be non-adjacent, or...
[0060] In some embodiments, the orthographic projection of the SA onto the substrate lies within the orthographic projection of the memory array containing the CBL connected to the SA onto the substrate. For example, the SA can be located directly above the memory array, and the connection between the SA and the CBL can be made directly through vias. Compared to related technologies where the SA is located between two memory arrays, the solution provided in this embodiment has shorter wiring. The orthographic projection of the SA onto the substrate may overlap with the orthographic projection of at least one CBL connected to the SA onto the substrate.
[0061] Figure 3 This is a schematic diagram of the SA and storage array layout provided for an exemplary embodiment. Figure 3 As shown, a die 200 is disposed directly above the storage array 100, and the die 200 is provided with multiple SAs (such as...). Figure 3 SA1 to SA8 shown in the diagram). Storage array 100 includes multiple storage cells ( Figure 3 (Not shown in the diagram) and multiple CBLs, with each pair of adjacent CBLs connected to an SA via pads 101. For example, the first and second CBLs are connected to SA1, the third and fourth CBLs are connected to SA2, and so on, with the fifteenth and sixteenth CBLs connected to SA8. The orthographic projection of the SA onto the substrate can be within the orthographic projection of the substrate onto the memory array 100 where the connected CBLs are located.
[0062] In some embodiments, such as Figure 4 As shown, each of the CBLs can also be connected to a second preset voltage terminal VEQ via a first gating sub-circuit 21. The first gating sub-circuit 21 can also be connected to a first gating control line. The first gating sub-circuit 21 is configured to connect or disconnect the CBL and the second preset voltage terminal VEQ under the control of the first gating control line (i.e., to electrically connect or disconnect the CBL and the second preset voltage terminal VEQ). The solution provided in this embodiment, by setting the first gating sub-circuit, can connect non-target CBLs to preset voltage terminals, avoiding interference from voltage changes in non-target LBLs to target LBLs. However, this embodiment is not limited to this; in other embodiments, the first gating sub-circuit 21 may not be provided.
[0063] In some embodiments, the voltage of the second preset voltage terminal VEQ can be the voltage between the voltage corresponding to logic data "0" and the voltage corresponding to logic data "1". For example, the voltage corresponding to logic data "0" is 0, and the voltage corresponding to logic data "1" is VDD, then the voltage of the second preset voltage terminal VEQ can be 1 / 2VDD, etc.
[0064] In some embodiments, the four first gating sub-circuits 21 connected by the four CBLs corresponding to the same row are respectively connected to different first gating control lines. Among the multiple CBLs corresponding to multiple rows, the multiple first gating sub-circuits 21 connected by the multiple CBLs respectively connected to the multiple LBLs in the same column are connected to the same first gating control line, that is, as shown in the example. Figure 4 As shown, the storage cell array includes N*2M bit lines. The LBL in the i-th row and j-th column is LBL_i-1_j-1, where i is 1 to N and j is 1 to 2M, i.e., LBL_0_0 to LBL_N-1_2M-1. The multiple first gating sub-circuits 21 connected to the multiple CBLs respectively connected to the LBLs in the first column are all connected to the first first gating control line Ctrl_0. The multiple first gating sub-circuits 21 connected to the multiple CBLs respectively connected to the LBLs in the second column are all connected to the second first gating control line Ctrl_1. The multiple first gating sub-circuits 21 connected to the multiple CBLs respectively connected to the LBLs in the third column are all connected to the third first gating control line Ctrl_2. The multiple first gating sub-circuits 21 connected to the multiple CBLs respectively connected to the LBLs in the fourth column are all connected to the fourth first gating control line Ctrl_3. The solution provided in this embodiment can simultaneously control the CBLs connected to the LBLs in the same column, which facilitates connecting the LBLs in the same column to the second preset voltage terminal VEQ simultaneously when they are not working, avoiding interference with the working LBLs (i.e., the LBLs connected to the memory units to be read and written). However, this embodiment is not limited to this. The multiple first gating sub-circuits 21 connected to the multiple CBLs respectively connected to the LBLs in the same column can be connected to different first gating control lines.
[0065] In some embodiments, the first gating sub-circuit 21 may include a first transistor T1, the gate electrode of the first transistor T1 being connected to the first gating control line, the first electrode being connected to the CBL, and the second electrode being connected to the second preset voltage terminal VEQ. The structure of the first gating sub-circuit 21 described in this embodiment is merely an example and may be other circuits capable of gating, such as those comprising multiple transistors.
[0066] In some embodiments, the first gating sub-circuit 21 may be an N-type transistor, but the embodiments disclosed herein are not limited thereto, and the first gating sub-circuit 21 may be a P-type transistor.
[0067] In some embodiments, the memory may further include a control circuit, the control circuit being configured to:
[0068] Based on the target word line group to which the target memory cell to be operated is connected, an activation signal is loaded on the CWL connected to the target word line group. The target memory cell includes two columns of memory cells, and the two columns of memory cells are respectively connected to two LWLs of the same word line group.
[0069] A shutdown level signal is applied to the first gating control line of the first gating sub-circuit 21 connected to the CBL connected to the two columns of target LBLs that are respectively connected to the target storage unit;
[0070] During the charge sharing phase, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the non-target common bit line; during the signal amplification phase, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the non-target common bit line; wherein, the CBLs connected to the two columns of target local bit lines are called target common bit lines, and the other CBLs of the memory cell array where the target memory cell is located are called non-target common bit lines.
[0071] The storage cell array can be divided into multiple subarrays. Each subarray consists of four consecutive columns of storage cells. The four columns of storage cells in each subarray are connected to four LWLs. The four LWLs are divided into two word line groups. The word line group containing the LWLs connected to the storage cells in odd-numbered columns is called the odd-numbered word line group. The word line group containing the LWLs connected to the storage cells in even-numbered columns is called the even-numbered word line group. The CBL connected to the LBLs connected to the storage cells in odd-numbered columns is called the odd-numbered CBL. The CBL connected to the LBLs connected to the storage cells in even-numbered columns is called the even-numbered CBL.
[0072] In some embodiments, the control circuit is further configured to:
[0073] When the target storage cell is an odd-numbered column storage cell, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the odd-numbered column CBL; during the charge sharing stage, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the even-numbered column common bit line; during the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the even-numbered column common bit line.
[0074] When the target storage cell is an even-numbered column storage cell, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the even-numbered column common bit line; during the charge sharing stage, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the odd-numbered column common bit line; and during the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the odd-numbered column common bit line.
[0075] The control circuit may include a driver that generates an activation signal or a deactivation signal to the common word line, an enable circuit that generates a control signal to the first gating sub-circuit 21, etc.
[0076] When the activation signal is applied to CWL_m, m is any value from 0 to M-1. At this time, the two word lines connected to CWL_m are respectively connected to two columns of memory cells, which are the target memory cells. A shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit 21 of the two columns of LBLs (called target LBLs, and the CBLs connected to the target LBLs are called target CBLs) to disconnect the two columns of target CBLs from the second preset voltage terminal VEQ. Other CBLs in the memory cell array where the target memory cells are located are called non-target CBLs. During the charge sharing phase, the non-target CBLs are connected to... A conduction level signal is applied to the first gating control line connected to the first gating sub-circuit 21, causing the non-target CBL to connect to the second preset voltage terminal VEQ. This stabilizes the voltage of the non-target CBL, preventing interference with the target CBL, and ensures that the voltage of the non-target CBL is stable at the second preset voltage terminal, unaffected by coupling from other CBLs. At this time, the voltage of the CBL connected to the reference voltage terminal of SA is the second preset voltage, thus providing a stable reference voltage for SA. During the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit 21 connected to the non-target CBL to prevent interference with SA. The charge sharing stage includes the turn-on time of the transistor controlling CWL and the charge sharing time between the CBL and the capacitor of the memory cell.
[0077] The solution provided in this embodiment can shield the target CBL during the charge sharing phase to avoid being affected by other CBLs, stabilize the voltage of non-target CBLs, avoid being affected by other CBLs, and provide a stable reference voltage for SA.
[0078] For example, with Figure 4For example, when the common word line CWL_0 is activated, the target LBL is the first column LBL and the third column LBL. At this time, the first gating control line Ctrl_0 connected to the first gating sub-circuit 21 connected to CBL_i_0 connected to the first column LBL and the first gating control line Ctrl_2 connected to the first gating sub-circuit 21 connected to CBL_i_2 connected to the third column LBL are loaded with a turn-off level signal. The target CBL includes CBL_i_0 and CBL_i_2, where i is 0 to N-1. The non-target CBL includes CBL_i_1 and CBL_i_3, where i is 0 to N-1. Then, during the charge sharing stage, the first gating control line Ctrl_1 and Ctrl_3 connected to the first gating sub-circuit 21 connected to the LBL connected to the non-target CBL are loaded with a turn-on level signal, so that CBL_i_1 and CBL_i_3, where i is 0 to N-1, are connected to the second preset voltage terminal VEQ. During the signal amplification stage, the first gating control line Ctrl_1 and Ctrl_3 connected to the first gating sub-circuit 21 connected to the non-target CBL are loaded with a turn-off level signal, so that CBL_i_1 and CBL_i_3, i is 0 to N-1, are disconnected from the second preset voltage terminal VEQ.
[0079] If the first gating control line of the first gating sub-circuit 21 connected to the LBL in odd-numbered CBL sequences is loaded with the first gating control line, and the second gating control line of the first gating control line of the LBL in even-numbered CBL sequences is loaded with the second gating control line, then:
[0080] When the signal CWL_Even loaded on the even-numbered column word line group is the active signal (only one CWL_Even is active at any given time), the second control signal BLEQ_Even loaded on the first gating control line connected to the first gating sub-circuit 21 connected to the even-numbered column CBL is a turn-off level signal. The first control signal BLEQ_Odd loaded on the first gating control line connected to the first gating sub-circuit 21 connected to the odd-numbered column CBL is a conduction level signal during the charge sharing phase and a turn-off level signal during the signal amplification phase. Figure 5 As shown, Figure 5 The signal SA_ON indicates whether SA is enabled. In the scheme provided in this embodiment, during the charge sharing phase, BLEQ_Odd is a conduction level signal, which allows the odd-numbered CBL columns to be connected to the second preset voltage terminal VEQ, stabilizing the voltage of the odd-numbered CBL columns and preventing interference with the even-numbered CBL columns. Furthermore, the odd-numbered CBL columns are connected to the reference voltage terminal of SA, providing a stable reference voltage for SA. During the signal amplification phase, BLEQ_Odd is a shutdown level signal, disconnecting the odd-numbered CBL columns from the second preset voltage terminal VEQ, thus avoiding any impact on SA.
[0081] When the signal CWL_Odd loaded on the odd-numbered column word line group is the activation signal, the first control signal BLEQ_Odd loaded on the first gating control line connected to the first gating sub-circuit 21 connected to the odd-numbered column CBL is the off-level signal. The second control signal BLEQ_Even loaded on the first gating control line connected to the first gating sub-circuit 21 connected to the even-numbered column CBL is the on-level signal during the charge sharing phase and the off-level signal during the signal amplification phase. Figure 6 As shown, Figure 6 The signal SA_ON indicates whether SA is enabled. In the scheme provided in this embodiment, when the local word line of the odd-numbered column word line group is loaded with an activation signal, during the charge sharing phase, BLEQ_Even is a conducting level signal, which allows the even-numbered column CBL to be connected to the second preset voltage terminal VEQ, stabilizing the voltage of the even-numbered column CBL and preventing interference with the odd-numbered column CBL. Furthermore, the even-numbered column CBL is connected to the reference voltage terminal of SA, providing a stable reference voltage for SA. During the signal amplification phase, BLEQ_Even is a turning-off level signal, disconnecting the even-numbered column CBL from the second preset voltage terminal VEQ, thus avoiding any impact on SA.
[0082] The above embodiments are illustrated using the example of a high-level conduction signal and a low-level turn-off signal. However, the embodiments of this disclosure are not limited to this; the conduction signal can be low and the turn-off signal can be high.
[0083] The first control signal BLEQ_Odd and the second control signal BLEQ_Even can be generated by the first enable signal BLEQ_Odd_en and the second enable signal BLEQ_Even_en, respectively. For example, when the first enable signal BLEQ_Odd_en is a high-level signal, the level of the first control signal BLEQ_Odd switches from high to low, or from low to high; when the second enable signal BLEQ_Even_en is a high-level signal, the level of the second control signal BLEQ_Even switches from high to low, or from low to high.
[0084] Figure 7 A schematic diagram of an enable circuit provided for an exemplary embodiment. (See diagram below.) Figure 7As shown, the enabling circuit may include a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5; a first inverter N1, a second inverter N2, a third inverter N3, a fourth inverter N4, a fifth inverter N5, a sixth inverter N6; a first non-inverting buffer D1, a second non-inverting buffer D2, a third non-inverting buffer D3, and a fourth non-inverting buffer D4. The second transistor T2 and the fourth transistor T4 can be N-type transistors, and the third transistor T3 and the fifth transistor T5 can be P-type transistors. The first electrodes of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are connected to the first control terminal ACT. The second electrodes of the second transistor T2 and the third transistor T3 are connected to the first node PG1. The second electrodes of the fourth transistor T4 and the fifth transistor T5 are connected to the second node PG2. The second control terminal A0_Latch is connected to the input terminal of the first inverter N1, the gate electrode of the third transistor T3, and the gate electrode of the fourth transistor T4. The output terminal of the first inverter N1 is connected to the gate electrode of the second transistor T2. The control terminal A0_Latch is connected to the input terminal of the second inverter N2. The output terminal of the second inverter N2 is connected to the gate electrode of the fifth transistor T5. The first node PG1 is connected to the input terminal of the third inverter N3. The output terminal of the third inverter N3 is connected to the input terminal of the fourth inverter N4. The output terminal of the fourth inverter N4 outputs the second enable signal BLEQ_Even_en. The first node PG1 is also connected to the input terminal of the first non-inverting buffer D1. The output terminal of the first non-inverting buffer D1 is connected to the input terminal of the second non-inverting buffer D2. The output terminal of the second non-inverting buffer D2 outputs the first enable signal BLEQ_Odd_en.
[0085] The second node PG2 is connected to the input of the fifth inverter N5, and the output of the fifth inverter N5 is connected to the input of the sixth inverter N6. The output of the sixth inverter N6 outputs the first enable signal BLEQ_Odd_en. The second node PG2 is also connected to the input of the third non-inverting buffer D3, and the output of the third non-inverting buffer D3 is connected to the input of the fourth non-inverting buffer D4. The output of the fourth non-inverting buffer D4 outputs the second enable signal BLEQ_Even_en.
[0086] Figure 8 for Figure 7 The timing diagram of the circuit is shown. The signal of the second control terminal A0_Latch can indicate whether the odd-numbered column word line group and the even-numbered column word line group are active. When the even-numbered column word line group is activated, the second control terminal A0_Latch is low; when the odd-numbered column word line group is activated, the second control terminal A0_Latch is high. Figure 8 As shown, the working process is as follows:
[0087] When the second control terminal A0_Latch is loaded with a low-level signal (i.e., when the even-numbered column word line group is loaded with an activation signal), the second transistor T2 and the third transistor T3 are turned on, and the fourth transistor T4 and the fifth transistor T5 are turned off. The signal from the first control terminal ACT is loaded to the output of the fourth inverter N4, outputting the second enable signal BLEQ_Even_en. After a delay time t1, the signal from the first control terminal ACT is loaded to the output of the second non-inverting buffer D2, outputting the first enable signal BLEQ_Odd_en; that is, the second enable signal BLEQ_Even_en is a high-level signal, and the second control signal BLEQ_ The BLEQ_Even level switches, meaning BLEQ_Even changes from high to low. After time t1, the first enable signal BLEQ_Odd_en is high, and the first control signal BLEQ_Odd switches, meaning the first control signal BLEQ_Odd changes from high to low. During the preceding time t1, the first control signal BLEQ_Odd remained high. That is, during the charge sharing phase, the first control signal BLEQ_Odd was high (here, the on level signal), and during the signal amplification phase, the first control signal BLEQ_Odd was low (here, the off level signal).
[0088] When the second control terminal A0_Latch is loaded with a high-level signal (i.e., when the odd-numbered column word line group is loaded with an activation signal), the second transistor T2 and the third transistor T3 are turned off, and the fourth transistor T4 and the fifth transistor T5 are turned on. The signal of the first control terminal ACT is loaded to the output terminal of the sixth inverter N6, outputting the first enable signal BLEQ_Odd_en. After a delay time t1, the signal of the first control terminal ACT is loaded to the output terminal of the fourth non-inverting buffer D4, outputting the second enable signal BLEQ_Even_en. That is, when the first enable signal BLEQ_Odd_en is a high-level signal, the level of the first control signal BLEQ_Odd switches, i.e., BLEQ_Odd changes from high level to low level; after a time t1, the second enable signal BLEQ_Even_en is a high-level signal, and the level of the second control signal BLEQ_Even switches, i.e., the second control signal BLEQ_Even changes from high level to low level. During the previous time t1, the second control signal BLEQ_Even remains at a high level. That is, during the charge sharing phase, the second control signal BLEQ_Even is at a high level (the on level signal); during the signal amplification phase, the second control signal BLEQ_Even is at a low level (the off level signal).
[0089] This disclosure provides an access control method applied to the aforementioned memory, comprising:
[0090] During the data read / write phase, an activation signal is loaded on the common word line connected to the word line group to which the local word line to be operated is located, according to the word line group to which the target storage unit to be operated is located. The target storage unit includes two columns of storage units, and the two columns of storage units are respectively connected to two local word lines of the same word line group.
[0091] A shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the two columns of target local bit lines that are respectively connected to the target memory cell;
[0092] During the charge sharing phase, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit that is connected to the non-target common bit line; during the signal amplification phase, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit that is connected to the non-target common bit line.
[0093] In some embodiments, the method further includes:
[0094] When the target storage cell is an odd-numbered column storage cell, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column; during the charge sharing stage, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column; during the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column.
[0095] When the target storage cell is an even-numbered column storage cell, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the even-numbered column; during the charge sharing stage, a conduction level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column; and during the signal amplification stage, a shutdown level signal is applied to the first gating control line connected to the first gating sub-circuit connected to the common bit line of the odd-numbered column.
[0096] This disclosure also provides an electronic device, including the memory described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0097] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.
Claims
1. A memory, comprising: The memory comprises: at least one memory array, a plurality of common word lines and a plurality of common bit lines, the memory array comprising a plurality of memory cell arrays stacked along a direction perpendicular to a substrate, a plurality of local bit lines extending along a direction perpendicular to the substrate and arranged in an array along a first direction and a second direction; the memory cell array comprises: a plurality of memory cells arranged in an array along the first direction and the second direction, a plurality of local word lines extending along the second direction corresponding to each column of memory cells arranged along the second direction, and the local word lines connecting the corresponding column of memory cells; the local bit lines connect a plurality of memory cells at the same position of different layers, and the first direction and the second direction are parallel to the substrate and intersect each other; a plurality of local word lines of the same memory cell array are divided into a plurality of word line groups, each word line group is connected to one common word line, and different word line groups are connected to different common word lines; each word line group comprises two local word lines, and the two local word lines in the same word line group are respectively connected to the memory cells of the adjacent columns; each row of local bit lines arranged along the first direction corresponds to four common bit lines, each local bit line is connected to one common bit line, and in the same row of local bit lines, every four continuously arranged local bit lines are respectively connected to different common bit lines of the four common bit lines corresponding to the row of local bit lines, and the common bit lines connected by the local bit lines of the memory cells connected by the local word lines of the same word line group are not adjacent; the common bit lines are connected to a sense amplifier, and the common bit lines connected to two input ports of the sense amplifier are two common bit lines of the same memory array, and the memory cells connected by the two common bit lines connected to the same sense amplifier are connected to different common word lines.
2. The memory of claim 1, wherein, The two common bit lines connected to the same sense amplifier are adjacent two common bit lines of the four common bit lines corresponding to each row of local bit lines.
3. The memory of claim 1, wherein, The sense amplifier is located in the projection of the substrate within the projection of the memory array on the substrate where the common bit lines connected to the sense amplifier are located, and there is an overlap between the projection of at least one common bit line connected to the sense amplifier on the substrate.
4. The memory of any one of claims 1 to 3, wherein, Each common bit line is also connected to a second preset voltage terminal through a first gating sub-circuit, the first gating sub-circuit is connected to a first gating control line, and the first gating sub-circuit is configured to electrically connect or disconnect the common bit line and the second preset voltage terminal under the control of the first gating control line.
5. The memory of claim 4, wherein, The plurality of first gating sub-circuits connected by the plurality of common bit lines respectively connected to the same column of local bit lines are connected to the same first gating control line.
6. The memory of claim 5, wherein, The memory further comprises a control circuit, and the control circuit is configured to: load an activation signal on the common word line connected to the word line group in which the local word line connected to the target memory cell to be operated is located according to the word line group in which the local word line connected to the target memory cell to be operated is located, wherein the target memory cell comprises two columns of memory cells, and the two columns of memory cells are respectively connected to two local word lines of the same word line group; load an off level signal on the first gating control line connected to the first gating sub-circuit connected to the common bit line connected to the two columns of target local bit lines respectively connected to the target memory cell; In the charge sharing stage, a turn-on level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the non-target common bit line; in the signal amplification stage, a turn-off level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the non-target common bit line; wherein the common bit line connected to the two local bit lines of the target local bit line is called the target common bit line, and the other common bit line of the storage unit array where the target storage unit is located is called the non-target common bit line.
7. The memory of claim 6, wherein, The word line group where the local word line connected to the storage unit of the odd column is located is called the odd column word line group, the word line group where the local word line connected to the storage unit of the even column is located is called the even column word line group, the common bit line connected to the local bit line connected to the storage unit of the odd column is called the odd column common bit line, and the common bit line connected to the local bit line connected to the storage unit of the even column is called the even column common bit line; the control circuit is further configured to: when the target storage unit is an odd column storage unit, a turn-off level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the odd column common bit line; in the charge sharing stage, a turn-on level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the even column common bit line, and in the signal amplification stage, a turn-off level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the even column common bit line; when the target storage unit is an even column storage unit, a turn-off level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the even column common bit line; in the charge sharing stage, a turn-on level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the odd column common bit line, and in the signal amplification stage, a turn-off level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the odd column common bit line.
8. An access control method characterized by, Applied to the memory of any one of claims 4 to 7, comprising: in the data read / write stage, according to the word line group where the local word line connected to the target storage unit to be operated is located, an activation signal is loaded on the common word line connected to the word line group, wherein the target storage unit includes two columns of storage units, and the two columns of storage units are respectively connected to two local word lines of the same word line group; a turn-off level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the common bit line connected to the two target local bit lines respectively connected to the target storage unit; in the charge sharing stage, a turn-on level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the non-target common bit line; in the signal amplification stage, a turn-off level signal is loaded on the first gating control line connected to the first gating sub-circuit connected to the non-target common bit line; wherein the common bit line connected to the two local bit lines of the target local bit line is called the target common bit line, and the other common bit line of the storage unit array where the target storage unit is located is called the non-target common bit line.
9. The access control method of claim 8, wherein, the word line group in which the local area word line connected with the storage unit of the odd number column is called as the odd number column word line group, the word line group in which the local area word line connected with the storage unit of the even number column is called as the even number column word line group, the common bit line in which the local area bit line connected with the storage unit of the odd number column is connected is called as the odd number column common bit line, the common bit line in which the local area bit line connected with the storage unit of the even number column is connected is called as the even number column common bit line; the method further comprises: when the target storage unit is the odd number column storage unit, a turn-off level signal is loaded on the first gating control line connected with the first gating sub-circuit connected with the odd number column common bit line; in the charge sharing stage, a turn-on level signal is loaded on the first gating control line connected with the first gating sub-circuit connected with the even number column common bit line, and in the signal amplification stage, a turn-off level signal is loaded on the first gating control line connected with the first gating sub-circuit connected with the even number column common bit line; when the target storage unit is the even number column storage unit, a turn-off level signal is loaded on the first gating control line connected with the first gating sub-circuit connected with the even number column common bit line; in the charge sharing stage, a turn-on level signal is loaded on the first gating control line connected with the first gating sub-circuit connected with the odd number column common bit line, and in the signal amplification stage, a turn-off level signal is loaded on the first gating control line connected with the first gating sub-circuit connected with the odd number column common bit line.
10. An electronic device, comprising: The memory comprising the memory as claimed in any one of claims 1 to 7.