One-time programmable memory and writing method and reading method thereof
By employing a structure in which bit lines and source lines are arranged crosswise in a one-time programmable memory and ensuring the consistency of the conduction direction of the unipolar selector, the problem of insufficient integration density is solved, thereby achieving improved storage density and simplified circuitry.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2026-03-10
AI Technical Summary
Existing one-time programmable memories have insufficient integration density and cannot meet the growing demand for integration.
The storage cell employs a cross-arrangement of bit lines and source lines. It includes a series-connected unipolar selector and a magnetic tunnel junction, with all unipolar selectors having the same conduction direction. It operates by writing and reading using a specific voltage method.
Without increasing the device area, the number of memory cells was increased, the integration density was improved, the circuit structure was simplified, and the production difficulty and cost were reduced.
Smart Images
Figure CN121641102A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory manufacturing, and in particular to a one-time programmable memory and its writing and reading methods. Background Technology
[0002] One-time programmable memory (OTP) can only be programmed once. Once programmed, the data is permanently valid and ideally can be read an unlimited number of times. It is typically used to store configuration information when a chip is powered on, such as tuning information, failure addresses, device ID, and manufacturing ID.
[0003] In magnetic random access memory (MRAM) chips, the breakdown property of magnetic tunnel junctions (MTJs) is utilized. A high voltage is applied to selected MTJs in the OTP array to break them down, so that specific data information is not altered. When reading information, the resistance value of MTJs in the non-breakdown state (AP&P state) is higher, representing the logic state "0", while the resistance of MTJs in the breakdown state is lower, representing the logic state "1".
[0004] In traditional MRAM OTP cells, MOS transistors are used as turn signals. MOS transistors have a large area. Replacing them with unipolar selectors would greatly increase integration density and reduce power consumption. However, given the increasing demand for miniaturization and the growth of stored data, the current integration density is still somewhat insufficient.
[0005] Therefore, how to further improve the integration density of current one-time programmable memories has become an urgent problem to be solved by those skilled in the art. Summary of the Invention
[0006] The purpose of this invention is to provide a one-time programmable memory and its writing and reading methods, so as to solve the problem of insufficient integration density of one-time programmable memories in the prior art.
[0007] To address the aforementioned technical problems, this invention provides a one-time programmable memory, comprising bit lines, source lines, and memory cells;
[0008] The storage cell includes a unipolar selector and a magnetic tunnel junction connected in series; multiple storage cells are arranged in an array in the storage area of the one-time programmable memory;
[0009] In the logic area of the one-time programmable memory, a single bit line is divided into an upper bit line and a lower bit line in the vertical direction of the storage area.
[0010] The source line is arranged to intersect with the bit line and is located between the upper bit line and the lower bit line in the vertical direction;
[0011] The memory cells are connected in series between the upper bit line and the source line, and between the lower bit line and the source line;
[0012] All the unipolar selectors in the memory cells have the same conduction direction.
[0013] Optionally, in the one-time programmable memory, the unipolar selector is located below the magnetic tunnel junction.
[0014] Optionally, in the one-time programmable memory, the bit lines are perpendicular to the source lines.
[0015] Optionally, in the one-time programmable memory, the upper bit line and the lower bit line, which are derived from the same bit line of the logic area, overlap in the vertical direction.
[0016] Optionally, in the one-time programmable memory, the unipolar selector is a diode.
[0017] A method for writing to a one-time programmable memory, the method being used for any of the one-time programmable memories described above, comprising:
[0018] Determine the target storage unit to be written to;
[0019] A breakdown voltage is applied to the first line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell, and no voltage is applied to the second line corresponding to the target memory cell; the voltage applied to the bit line and source line other than the first line and the second line is a non-zero voltage less than the breakdown voltage.
[0020] Optionally, in the writing method of the one-time programmable memory, the non-zero voltage applied to the bit lines and the source lines is the same, except for the first line and the second line.
[0021] A method for reading a one-time programmable memory, the method being used with any of the one-time programmable memories described above, comprising:
[0022] Determine the target storage unit to be read;
[0023] A read voltage is applied to the first line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell, and no voltage is applied to the second line corresponding to the target memory cell; the voltage applied to the bit line and source line other than the first line and the second line is a non-zero voltage less than the read voltage.
[0024] Optionally, in the method for reading the one-time programmable memory, all memory cells other than the target memory cell are not turned on during the reading process.
[0025] Optionally, in the method for reading the one-time programmable memory, the first line is the first bit line and the second line is the second source line;
[0026] Accordingly, the application of a read voltage to the first line corresponding to the forward-biased terminal of the unipolar selector of the target memory cell, and the absence of a voltage applied to the second line corresponding to the target memory cell; the application of a non-zero voltage less than the read voltage to the bit lines and source lines other than the first and second lines includes:
[0027] A read voltage is applied to the first bit line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell, and no voltage is applied to the second source line corresponding to the target memory cell; a first intermediate voltage is applied to the bit lines other than the first bit line, and a second intermediate voltage is applied to the source lines other than the second source line; the voltage difference between the read voltage and the second intermediate voltage, the voltage difference between the first intermediate voltage and the second intermediate voltage, and the first intermediate voltage are all less than the forward conduction voltage of the unipolar selector;
[0028] or
[0029] The first line is the first source line, and the second line is the second bit line;
[0030] Accordingly, the application of a read voltage to the first line corresponding to the forward-biased terminal of the unipolar selector of the target memory cell, and the absence of a voltage applied to the second line corresponding to the target memory cell; the application of a non-zero voltage less than the read voltage to the bit lines and source lines other than the first and second lines includes:
[0031] A read voltage is applied to the first source line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell, and no voltage is applied to the second bit line corresponding to the target memory cell; a third intermediate voltage is applied to the source lines other than the first source line, and a fourth intermediate voltage is applied to the bit lines other than the second bit line; the voltage difference between the read voltage and the fourth intermediate voltage, the voltage difference between the third intermediate voltage and the fourth intermediate voltage, and the third intermediate voltage are all less than the forward conduction voltage of the unipolar selector.
[0032] The one-time programmable memory provided by this invention includes bit lines, source lines, and memory cells. Each memory cell includes a cascaded unipolar selector and a magnetic tunnel junction. Multiple memory cells are arranged in an array within the memory region of the one-time programmable memory. A single bit line in the logic region of the one-time programmable memory is divided into an upper bit line and a lower bit line in the vertical direction of the memory region. The source line is arranged intersecting the bit lines and is located vertically between the upper and lower bit lines. Memory cells are connected in series between the upper bit line and the source line, and between the lower bit line and the source line. The unipolar selectors in all memory cells have the same conduction direction. This invention stacks memory cells, which, compared to existing related technologies, can increase the number of memory cells by up to double without changing the device area, greatly improving the storage density of the one-time programmable memory. Furthermore, this invention uses unipolar selectors with consistent conduction directions, avoiding the use of direction selectors in the circuit, thereby simplifying the circuit structure, reducing circuit redundancy, and lowering production difficulty and cost. The present invention also provides a method for writing to a one-time programmable memory and a method for reading from a one-time programmable memory, which have the above-mentioned beneficial effects. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 A schematic diagram of a specific embodiment of the one-time programmable memory provided by the present invention;
[0035] Figure 2 A flowchart illustrating a specific embodiment of the writing method for a one-time programmable memory provided by the present invention;
[0036] Figure 3 This is a flowchart illustrating a specific embodiment of the one-time programmable memory reading method provided by the present invention.
[0037] In the diagram, SL1 and SL2 are used to indicate the source lines, BL1 and BL2 are used to indicate the bit lines, MTJ1 and MTJ2 are used to indicate the two magnetic tunnel junctions between the same bit line and the source line, and D1 and D2 are used to indicate the unipolar selectors corresponding to the two magnetic tunnel junctions. Detailed Implementation
[0038] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] The core of this invention is to provide a one-time programmable memory, the structural diagram of which is shown in a specific embodiment. Figure 1 As shown, this is referred to as Specific Implementation Method 1, which includes bit lines, source lines, and memory cells;
[0040] The storage cell includes a unipolar selector and a magnetic tunnel junction connected in series; multiple storage cells are arranged in an array in the storage area of the one-time programmable memory;
[0041] In the logic area of the one-time programmable memory, a single bit line is divided into an upper bit line and a lower bit line in the vertical direction of the storage area.
[0042] The source line is arranged to intersect with the bit line and is located between the upper bit line and the lower bit line in the vertical direction;
[0043] The memory cells are connected in series between the upper bit line and the source line, and between the lower bit line and the source line;
[0044] All the unipolar selectors in the memory cells have the same conduction direction.
[0045] Can be combined Figure 1 To understand this invention, such as Figure 1 As shown in this specific embodiment, the horizontal plane where the upper bit line is located and the horizontal plane where the source line is located form the upper layer of the one-time programmable memory, and the horizontal plane where the lower bit line is located and the horizontal plane where the source line is located form the lower layer of the one-time programmable memory. Of course, not all upper bit lines are in the same horizontal plane, not all lower bit lines are in the same horizontal plane, and not all source lines are in the same horizontal plane; they can all be adjusted according to actual needs.
[0046] In this invention, the direction of the connection between the upper bit line, the source line, and the lower bit line is called the vertical direction. The direction within the upper layer of the one-time programmable memory mentioned above is the horizontal direction. The conduction direction of the unipolar selector refers to the upward or downward conduction in space. The direction in actual production can be changed or adjusted accordingly, and this invention does not limit it. Figure 1In this diagram, SL1 and SL2 represent the two source lines, BL1 and BL2 represent the two bit lines, MTJ1 and MTJ2 represent the two magnetic tunnel junctions between the same bit line and the source line, and D1 and D2 represent the unipolar selectors corresponding to the two magnetic tunnel junctions, respectively.
[0047] Preferably, the unipolar selector is located below the magnetic tunnel junction.
[0048] Placing the unipolar selector below the magnetic tunnel junction simplifies the manufacturing process and reduces the difficulty of connecting the unipolar selector and the magnetic tunnel junction. Of course, the positions of the unipolar selector and the magnetic tunnel junction can also be interchanged, and corresponding changes can be made according to the actual situation.
[0049] Furthermore, the bit lines are perpendicular to the source lines. This perpendicularity simplifies the location calculation method for the memory cells, improves production efficiency, and minimizes the area occupied by the same number of memory cells, thereby further increasing integration density.
[0050] Furthermore, the upper bit line and the lower bit line, which are derived from the same bit line of the logic region, overlap in the vertical direction. This overlap in the vertical direction of the upper and lower bit lines derived from the same bit line of the logic region means that the projections of the upper-layer memory cells and the lower-layer memory cells connected to the same bit line of the logic region overlap. This facilitates design and manufacturing while further improving integration density.
[0051] In one specific implementation, the unipolar selector is a diode. Diodes are inexpensive, simple in structure, and reliable. Furthermore, their vertical projection size is smaller than that of the magnetic tunnel junction. Therefore, while improving device reliability and reducing production costs, they minimize space occupation and further increase the storage density of the one-time programmable memory.
[0052] The one-time programmable memory provided by this invention includes bit lines, source lines, and memory cells. Each memory cell includes a cascaded unipolar selector and a magnetic tunnel junction. Multiple memory cells are arranged in an array within the memory region of the one-time programmable memory. A single bit line in the logic region of the one-time programmable memory is divided into an upper bit line and a lower bit line in the vertical direction of the memory region. The source line is arranged intersecting the bit lines and is located vertically between the upper and lower bit lines. Memory cells are connected in series between the upper bit line and the source line, and between the lower bit line and the source line. The unipolar selectors in all memory cells have the same conduction direction. This invention stacks memory cells, which, compared to existing related technologies, can increase the number of memory cells by up to double without changing the device area, greatly improving the storage density of the one-time programmable memory. Furthermore, this invention uses unipolar selectors with consistent conduction directions, avoiding the use of direction selectors in the circuit, thereby simplifying the circuit structure, reducing circuit redundancy, and lowering production difficulty and cost.
[0053] The present invention also provides a method for writing to a one-time programmable memory, and a flowchart of one specific embodiment is shown below. Figure 2 As shown, referred to as Specific Implementation Method Two, the writing method of the one-time programmable memory is used for the one-time programmable memory as described in any of the above embodiments, including:
[0054] S101: Determine the target storage unit to be written to.
[0055] The target storage unit is a specific storage unit in the preceding text that will be written.
[0056] S102: Apply a breakdown voltage to the first line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell, and do not apply a voltage to the second line corresponding to the target memory cell; apply a non-zero voltage less than the breakdown voltage to the bit line and source line other than the first line and the second line.
[0057] The first line and the second line are the bit line and source line respectively connected to the target storage cell. Assuming the target storage cell is... Figure 1 If the target memory cell is MTJ1, then the first line connected to the forward conduction terminal of the corresponding unipolar selector is SL1, and the second line connected to the other end of MTJ is BL1 in the figure; if the target memory cell is MTJ2, then the first line is BL1 and the second line is SL1.
[0058] The breakdown voltage is the voltage that can break down the unipolar selector. After breakdown, the unipolar selector can be equivalent to a wire. In this specific embodiment, the bit lines and source lines other than the first line and the second line (still using MTJ1 and MTJ2 as examples, the bit lines and source lines other than the first line and the second line correspond to...) Figure 1 A non-zero voltage less than the breakdown voltage is applied to both SL2 and BL2 in the memory. This protects the memory cells located between other bit lines and source lines, ensuring that the voltage across these memory cells is insufficient to break down the corresponding unipolar selector. This improves the safety of the writing process, avoids unintended unipolar selector breakdown, and improves the yield of the finished product.
[0059] Preferably, the non-zero voltage applied to the bit lines and source lines, except for the first and second lines, is the same.
[0060] In this preferred embodiment, applying the same voltage to all bit lines and source lines except for the first and second lines can greatly simplify the writing process and improve the yield of finished products.
[0061] The present invention also provides a method for reading a one-time programmable memory, the flowchart of one specific embodiment of which is shown below. Figure 3 As shown, referred to as Specific Implementation Method Three, the method for reading the one-time programmable memory is used for any of the one-time programmable memories described above, including:
[0062] S201: Determine the target storage unit to be read.
[0063] The target storage unit is a specific storage unit mentioned earlier that will be read.
[0064] S202: A read voltage is applied to the first line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell, and no voltage is applied to the second line corresponding to the target memory cell; the voltage applied to the bit line and source line other than the first line and the second line is a non-zero voltage less than the read voltage.
[0065] The definitions of the first and second lines are provided above and will not be repeated here. In this specific embodiment, applying a non-zero voltage less than the read voltage to the bit lines and source lines other than the first and second lines can prevent accidental conduction of memory cells other than the target memory cell, and can greatly improve the accuracy of the read operation.
[0066] In a preferred embodiment, all storage units other than the target storage unit are not powered on during the reading process.
[0067] In this preferred embodiment, by adjusting the voltage of each bit line and each source line, the memory cells other than the target memory cell are not turned on during the reading process. This not only avoids damage to the memory cells due to abnormal voltage at both ends of each memory cell, but also greatly reduces useless power consumption and saves energy costs because no storage power supply has current flowing through it except for the target memory cell.
[0068] In one specific implementation, the first line is the first source line, and the second line is the second source line;
[0069] Accordingly, the application of a read voltage to the first line corresponding to the forward-biased terminal of the unipolar selector of the target memory cell, and the absence of a voltage applied to the second line corresponding to the target memory cell; the application of a non-zero voltage less than the read voltage to the bit lines and source lines other than the first and second lines includes:
[0070] A read voltage is applied to the first bit line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell, and no voltage is applied to the second source line corresponding to the target memory cell; a first intermediate voltage is applied to the bit lines other than the first bit line, and a second intermediate voltage is applied to the source lines other than the second source line; the voltage difference between the read voltage and the second intermediate voltage, the voltage difference between the first intermediate voltage and the second intermediate voltage, and the first intermediate voltage are all less than the forward conduction voltage of the unipolar selector.
[0071] In this specific embodiment, considering that the first line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell is a bit line, the second line is the source line. The two lines are referred to as the first source line and the second source line, respectively. For ease of understanding, please refer to [the documentation / reference needed]. Figure 1 The corresponding situation in this specific embodiment is as follows: Figure 1 In the diagram, MTJ2 is used. The read voltage Vr is applied to BL1, no voltage is applied to SL1, a first intermediate voltage Vm1 is applied to BL2, and a second intermediate voltage Vm2 is applied to SL2. Therefore, the voltage differences across the other memory cells (excluding MTJ2) include Vr-Vm2, Vm1-0, Vm1-Vm2, and their opposites. Since the voltage applied in reverse to the unipolar selector will definitely prevent the memory cell from conducting, only the absolute values of the results of the above three equations need to be considered, ensuring that the difference between these three is less than the forward conduction voltage of the unipolar selector. In other words, in this specific embodiment, the comparison between the voltage difference between the read voltage and the second intermediate voltage, the voltage difference between the first intermediate voltage and the second intermediate voltage, and the forward conduction voltage of the unipolar selector only considers the magnitude of the voltage, without considering the direction.
[0072] In another specific implementation, the first line is a first source line, and the second line is a second bit line;
[0073] Accordingly, the application of a read voltage to the first line corresponding to the forward-biased terminal of the unipolar selector of the target memory cell, and the absence of a voltage applied to the second line corresponding to the target memory cell; the application of a non-zero voltage less than the read voltage to the bit lines and source lines other than the first and second lines includes:
[0074] A read voltage is applied to the first source line corresponding to the forward conduction terminal of the unipolar selector of the target memory cell, and no voltage is applied to the second bit line corresponding to the target memory cell; a third intermediate voltage is applied to the source lines other than the first source line, and a fourth intermediate voltage is applied to the bit lines other than the second bit line; the voltage difference between the read voltage and the fourth intermediate voltage, the voltage difference between the third intermediate voltage and the fourth intermediate voltage, and the third intermediate voltage are all less than the forward conduction voltage of the unipolar selector.
[0075] This specific implementation differs from the previous implementation. It considers the case where the first line corresponding to the forward-biased terminal of the unipolar selector of the target memory cell is the source line, and the second line is the bit line. The two lines are referred to as the first source line and the second bit line, respectively. For ease of understanding, please refer to [link to previous text]. Figure 1 The corresponding situation in this specific embodiment is as follows: Figure 1 In the diagram, MTJ1 is the MTJ1. The read voltage Vr is applied to SL1, no voltage is applied to BL1, a third intermediate voltage Vm3 is applied to SL2, and a fourth intermediate voltage Vm4 is applied to BL2. In addition to MTJ1, the voltage difference between the two ends of other memory cells includes Vr-Vm4, Vm3-0, Vm3-Vm4 and their opposites. For the rest, please refer to the previous text. This specific embodiment will not be repeated.
[0076] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0077] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0078] The foregoing has provided a detailed description of the one-time programmable memory and its writing and reading methods provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
Claims
1. A one-time programmable memory, characterized by, The memory cell includes a unipolar selector and a magnetic tunnel junction in series. The memory cell is arranged in an array of memory regions of the OTP memory. A single bit line in a logic region of the OTP memory is divided into an upper bit line and a lower bit line in the vertical direction of the memory region. The source lines and the bit lines are arranged in a cross manner, and are located between the upper bit line and the lower bit line in the vertical direction. The memory cell is in series between the upper bit line and the source line, and between the lower bit line and the source line. The unipolar selector of all memory cells has the same conduction direction.
2. The one-time programmable memory of claim 1, wherein, The unipolar selector is located below the magnetic tunnel junction.
3. The one-time programmable memory of claim 1, wherein, The bit lines and the source lines are perpendicular to each other.
4. The one-time programmable memory of claim 1, wherein, The projection of the upper bit line and the lower bit line in the vertical direction overlaps.
5. The one-time programmable memory of claim 1, wherein, The unipolar selector is a diode.
6. A write method for a one-time programmable memory, characterized by, The writing method of the OTP memory is used for the OTP memory as claimed in any one of claims 1 to 5, and includes: Determining a target memory cell to be written; Applying a breakdown voltage to a first line corresponding to the forward conduction end of the unipolar selector of the target memory cell, and not applying voltage to a second line corresponding to the target memory cell; and applying a non-zero voltage less than the breakdown voltage to the bit lines and the source lines other than the first line and the second line.
7. The write method of the one-time programmable memory according to claim 6, wherein, The non-zero voltage applied to the bit lines and the source lines other than the first line and the second line is the same.
8. A read method of a one-time programmable memory, characterized by, The reading method of the OTP memory is used for the OTP memory as claimed in any one of claims 1 to 5, and includes: Determining a target memory cell to be read; Applying a reading voltage to a first line corresponding to the forward conduction end of the unipolar selector of the target memory cell, and not applying voltage to a second line corresponding to the target memory cell; and applying a non-zero voltage less than the reading voltage to the bit lines and the source lines other than the first line and the second line.
9. The method of reading a one-time programmable memory according to claim 8, wherein, The unipolar selector of all memory cells has the same conduction direction.
10. The method of reading a one-time programmable memory according to claim 9, wherein, The unipolar selector is a diode. The first line is a first bit line, and the second line is a second source line. Correspondingly, the applying of the reading voltage to the first line corresponding to the forward conduction end of the unipolar selector of the target memory cell, and not applying voltage to the second line corresponding to the target memory cell; and the applying of the non-zero voltage less than the reading voltage to the bit lines and the source lines other than the first line and the second line include: Applying a reading voltage to a first bit line corresponding to the forward conduction end of the unipolar selector of the target memory cell, and not applying voltage to a second source line corresponding to the target memory cell; applying a first intermediate voltage to the bit lines other than the first bit line, and applying a second intermediate voltage to the source lines other than the second source line; the difference voltage between the reading voltage and the second intermediate voltage, the difference voltage between the first intermediate voltage and the second intermediate voltage, and the first intermediate voltage are all less than the forward conduction voltage of the unipolar selector; or Applying a reading voltage to a first bit line corresponding to the forward conduction end of the unipolar selector of the target memory cell, and not applying voltage to a second source line corresponding to the target memory cell; applying a first intermediate voltage to the bit lines other than the first bit line, and applying a second intermediate voltage to the source lines other than the second source line; the difference voltage between the reading voltage and the second intermediate voltage, the difference voltage between the first intermediate voltage and the second intermediate voltage, and the first intermediate voltage are all less than the forward conduction voltage of the unipolar selector. The first line is a first source line, and the second line is a second bit line; Correspondingly, a read voltage is applied to a first line corresponding to a positive conduction end of a unipolar selector of the target storage unit, and no voltage is applied to a second line corresponding to the target storage unit; and a non-zero voltage less than the read voltage is applied to bit lines and source lines other than the first line and the second line. Correspondingly, a read voltage is applied to a first line corresponding to a positive conduction end of a unipolar selector of the target storage unit, and no voltage is applied to a second line corresponding to the target storage unit; and a non-zero voltage less than the read voltage is applied to bit lines and source lines other than the first line and the second line. Correspondingly, a read voltage is applied to a first line corresponding to a positive conduction end of a unipolar selector of the target storage unit, and no voltage is applied to a second line corresponding to the target storage unit; and a non-zero voltage less than the read voltage is applied to bit lines and source lines other than the first line and the second line.