Efuse memory
By setting a fuse structure in the active region and merging MOS transistors, the problem of excessively large efuse cell area is solved, resulting in smaller cell size and higher layout efficiency, while reducing the idle area of the array structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2026-03-10
AI Technical Summary
The existing efuse cell has a large layout area, mainly occupied by MOS transistors, which increases the chip area and makes it difficult to improve the layout area utilization and working efficiency.
The fuse structure is set in the active region layer, and programming is achieved by the melting of the active region fuse. The MOS transistor is combined with the fuse structure to reduce the cell size and the idle area of the array structure. The array layout is carried out using centrally symmetrical efuse cells.
It effectively reduces the area of efuse cells, improves the layout area utilization and working efficiency, reduces the idle area of the array structure, and realizes more efficient layout design.
Smart Images
Figure CN121641133A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a primary electronic fuse (efuse) memory. Background Technology
[0002] An efuse cell typically consists of a fuse and a MOS transistor as its control transistor. Based on the electromigration (EM) principle, it achieves highly reliable on-chip programming by blowing the fuse. The chip area, a key indicator of efuse performance, is primarily determined by the array of efuse cells. Therefore, improving the layout of efuse cells is a crucial way to reduce the overall area of the efuse array.
[0003] A typical efuse cell layout includes a fuse (link) and an NMOS control transistor. The fuse is typically made of polysilicon or metal. For example... Figure 1 The diagram shown is an array layout diagram of an existing efuse memory; the array layout diagram 101 contains a layout 201 of multiple efuse cell structures.
[0004] like Figure 2 As shown, is Figure 1 Layout 102 of the efuse unit structure; by Figure 2 As shown, the eFuse cell structure includes a MOS transistor 103 and a fuse 104. The MOS transistor 103 is typically an NMOS transistor and is located in the NMOS region. The fuse 104 is located in the fuse region.
[0005] Depend on Figure 2 In the diagram, the dashed lines in the fuse area illustrate the structure of fuse 104. Fuse 104 consists of pads formed by two metal layers and a metal wire connecting the two pads. During programming, the metal wire is melted by applying voltage between the two pads via an EM (Electromagnetic Electromagnetic) method.
[0006] Depend on Figure 2 In the existing efuse cell structure shown, the area of MOS transistor 103 occupies most of the entire cell area, which is the main area in the efuse cell layout. MOS transistor 103 is the core factor that determines the overall area of efuse.
[0007] Figure 2 The image also shows the size of the efuse cell, which corresponds to the size of the efuse cell formed by the 28HK process, i.e., the 28nm high dielectric constant (HK) process. The area obtained by multiplying the length and width is 14.4 square micrometers. Summary of the Invention
[0008] The technical problem to be solved by the present invention is to provide an efuse memory that can reduce cell size, reduce idle area in array structure and thus reduce array layout area, thereby improving layout area utilization and layout efficiency.
[0009] To solve the above-mentioned technical problems, the efuse memory provided by the present invention includes: an efuse cell structure.
[0010] The efuse unit structure includes: a control transistor composed of MOS transistors and a fuse structure.
[0011] The MOS transistor is formed in the first active region (AA).
[0012] The fuse structure is formed in the second active region, and the first active region and the second active region are parallel.
[0013] The fuse structure includes a first fuse connection area, an active fuse area, and a second fuse connection area.
[0014] The active fuse is located between the first fuse connection area and the second fuse connection area.
[0015] The top of the first fuse connection area is connected to the drain line of the MOS transistor through a contact hole (CT).
[0016] The top of the second fuse connection area is connected to the bit line through a contact hole.
[0017] The active zone fuse has two states: on and off.
[0018] When the efuse unit structure is in its initial state, the active region fuse is in the conducting state, and the drain and the bit line are electrically connected together.
[0019] When the efuse cell structure is in the programming state, the active region fuse is in the blown state, and the electrical connection between the drain and the bit line is broken.
[0020] A further improvement is that the MOS transistor includes a gate structure, a source region, and a drain region.
[0021] The gate structure is strip-shaped and parallel to the strip shape of the second active region.
[0022] The source region and the drain region are self-aligned and formed in the first active region on both sides of the gate structure.
[0023] The drain region is connected to the drain line of the MOS transistor through a contact hole.
[0024] A further improvement is that the first active region and the second active region are connected together through a third active region.
[0025] The first side of the third active region is connected to the adjacent drain region formed in the first active region.
[0026] The second side of the third active region is connected to one of the first fuse connection region and the second fuse connection region.
[0027] The top of the third active region is also connected to the drain line via a contact hole.
[0028] A further improvement is that the drain region extends simultaneously into the third active region, or the drain region extends simultaneously into the third active region and the first fuse connection region or the second fuse connection region adjacent to the third active region. The active region fuse comprises a metal silicide formed on the surface of the second active region.
[0029] A further improvement is that the source region is connected to the source electrode line through a contact hole.
[0030] The gate structure is connected to the word line via a contact hole.
[0031] A further improvement is that the gate structure includes a gate dielectric layer and a gate conductive material layer stacked sequentially.
[0032] A further improvement is that the material of the gate dielectric layer includes a high dielectric constant material; and the material of the gate conductive material layer includes polysilicon or metal.
[0033] A further improvement is that the MOS transistor is composed of multiple MOS transistor units connected in parallel.
[0034] The gate structures of each of the MOS transistor units are arranged in parallel.
[0035] The source region located between the two gate structures is shared by the two MOS transistor units.
[0036] The drain region located between the two gate structures is shared by the two MOS transistor units.
[0037] A further improvement is that two of the aforementioned efuse unit structures form an efuse unit pair.
[0038] On the top view, the two efuse unit structures are centrally symmetrical.
[0039] A further improvement is that the efuse unit structure also includes a fourth active region, which serves as an active region dummy structure.
[0040] The fourth active region is parallel to and spaced apart from the second active region, and the first active region and the fourth active region are located on both sides of the second active region.
[0041] A further improvement is that, in the efuse unit pair, the two efuse unit structures share a fourth active region.
[0042] A further improvement is that the two efuse unit structures of the efuse unit pair are respectively a first efuse unit structure and a second efuse unit structure.
[0043] The two efuse cell structures share the same bit line.
[0044] Each of the gate structures in the first efuse cell structure is connected to the first word line through a corresponding contact hole.
[0045] Each of the gate structures in the second efuse cell structure is connected to the second word line through a corresponding contact hole.
[0046] Each of the source regions in the first efuse cell structure is connected to the first source line.
[0047] Each of the source regions in the second efuse cell structure is connected to the second source line.
[0048] Each of the drain regions in the first efuse cell structure is connected to the first drain line.
[0049] Each of the drain regions in the second efuse cell structure is connected to the second drain line.
[0050] On a top-down view, the first character line and the bit line are perpendicular.
[0051] The first word line, the second word line, the first source line, and the first drain line are parallel, and the first source line and the first drain line are located between the first word line and the second word line.
[0052] The first source line and the second drain line are located on the same straight line and are spaced apart.
[0053] The first drain line and the second source line are located on the same straight line and are spaced apart.
[0054] A further improvement is that each of the word lines, each of the source lines, and each of the drain lines are composed of a patterned second metal layer.
[0055] The bit line consists of a patterned third metal layer.
[0056] A further improvement is that each of the efuse cell structures has three electrode ports for connection to external circuits, namely the source port, word line port, and bit line port.
[0057] The word line is connected to the corresponding word line port, the source line is connected to the corresponding source port, and the bit line is connected to the corresponding bit line port.
[0058] A further improvement is that the efuse array structure is formed by repeating the efuse cell pairs.
[0059] A further improvement is that the number of MOS transistor units included in the MOS transistor is three or more.
[0060] A further improvement is that the MOS transistor is an NMOS.
[0061] Unlike the existing technology where the fuse structure of the efuse cell structure is set in the metal layer, the fuse structure of the present invention is set in the active region layer. Programming is achieved by melting the active region fuse. The fuse structure with the active region fuse only needs to add a second active region that is adjacent to and parallel to the first active region of the MOS transistor. This makes the area of the fuse structure of the present invention significantly reduced compared to the existing metal layer fuse structure, thereby reducing the cell size and the area of the efuse cell structure.
[0062] The fuse structure of the present invention facilitates the combination and layout of efuse cell structures. For example, two efuse cell structures can form a centrally symmetrical efuse cell pair, and then the efuse cell pairs are arranged in an efuse array. This can reduce the idle area in the array structure and thus reduce the layout area, thereby improving the layout area utilization and layout work efficiency. Attached Figure Description
[0063] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0064] Figure 1 This is an array layout diagram of the existing efuse memory;
[0065] Figure 2 yes Figure 1 Layout of the efuse cell structure;
[0066] Figure 3 This is a layout diagram of the efuse cell structure of the efuse memory according to an embodiment of the present invention;
[0067] Figure 4 yes Figure 3 Circuit diagram of the efuse unit structure;
[0068] Figure 5 This is a layout of the efuse cell pairs of the efuse memory in an embodiment of the present invention;
[0069] Figure 6 Is Figure 5 A layout with a metal layer superimposed on top of it;
[0070] Figure 7 This is a circuit diagram of the efuse cell pair of the efuse memory in an embodiment of the present invention. Detailed Implementation
[0071] like Figure 3 The diagram shown is a layout of the efuse cell structure 201 of the efuse memory according to an embodiment of the present invention. Figure 4 yes Figure 3 The circuit diagram of the efuse cell structure 201 in this embodiment of the invention; the efuse memory includes: efuse cell structure 201.
[0072] like Figure 4 As shown, the efuse unit structure 201 includes: a control tube composed of a MOS transistor 301 and a fuse structure 302.
[0073] like Figure 3 As shown, the MOS transistor 301 is formed in the first active region 202a.
[0074] The fuse structure 302 is formed in the second active region 202b, and the first active region 202a and the second active region 202b are parallel.
[0075] The fuse structure 302 includes a first fuse connection area 203a, an active fuse area 203, and a second fuse connection area 203b.
[0076] The active region fuse 203 is located between the first fuse connection region 203a and the second fuse connection region 203b.
[0077] The top of the first fuse connection region 203a is connected to the drain line D of the MOS transistor 301 through the contact hole 207. Please refer to [reference needed] for the drain line D of the MOS transistor 301. Figure 4 As shown.
[0078] The top of the second fuse connection area 203b is connected to the bit line BL via contact hole 207. Please refer to [reference needed for bit line BL]. Figure 4 As shown.
[0079] The active area fuse 203 has two states: on and off.
[0080] When the efuse unit structure 201 is in its initial state, the active region fuse 203 is in the conducting state, and the drain and the bit line BL are electrically connected together.
[0081] When the efuse unit structure 201 is in the programming state, the active region fuse 203 is in the blown state, and the electrical connection between the drain and the bit line BL is broken.
[0082] like Figure 3 As shown, the MOS transistor 301 includes a gate structure 204, a source region 205, and a drain region 206.
[0083] The gate structure 204 is strip-shaped and parallel to the strip shape of the second active region 202b.
[0084] The source region 205 and the drain region 206 are self-aligned and formed in the first active region 202a on both sides of the gate structure 204.
[0085] The drain region 206 is connected to the drain line D of the MOS transistor 301 through the contact hole 207.
[0086] In this embodiment of the invention, the first active region 202a and the second active region 202b are connected together through the third active region 202c.
[0087] The first side of the third active region 202c is connected to the adjacent drain region 206 formed in the first active region 202a.
[0088] The second side of the third active region 202c is connected to one of the first fuse connection region 203a and the second fuse connection region 203b. Figure 3 The image shows the second side of the third active region 202c connected to the first fuse connection region 203a.
[0089] In the field of semiconductor integrated circuit manufacturing, the active region is formed by creating field oxygen, such as shallow trench isolation (STI), in a semiconductor substrate, and consisting of a semiconductor substrate surrounded by field oxygen. Figure 3 As shown, the first active region 202a, the second active region 202b, and the third active region 202c form a connected integral structure.
[0090] The top of the third active region 202c is also connected to the drain line D via contact hole 207.
[0091] In this embodiment of the invention, the source region 205 is connected to the source line S through a contact hole 207.
[0092] The gate structure 204 is connected to the word line WL through the contact hole 207.
[0093] The gate structure 204 includes a gate dielectric layer and a gate conductive material layer stacked sequentially.
[0094] In some embodiments, the gate dielectric layer is made of a high dielectric constant material; the gate conductive material layer is made of a metal, and the gate structure 204 is HKMG. In other embodiments, the gate dielectric layer may be made of silicon dioxide, and the gate conductive material layer may be made of polysilicon.
[0095] like Figure 3 As shown in the embodiment of the present invention, the MOS transistor 301 is composed of multiple MOS transistor units connected in parallel.
[0096] The gate structures 204 of each of the MOS transistor units are arranged in parallel.
[0097] The source region 205 located between the two gate structures 204 is shared by the two MOS transistor units.
[0098] The drain region 206 located between the two gate structures 204 is shared by the two MOS transistor units.
[0099] In some embodiments, the number of MOS transistor units included in the MOS transistor 301 is three or more.
[0100] Figure 3 The diagram shows three gate structures 204, therefore the MOS transistor 301 includes three MOS transistor units. The area covered by the gate structure 204 serves as the channel region of the corresponding MOS transistor unit. Figure 3 In this configuration, the three gate structures 204 divide the first active region 202a outside the area covered by the gate structures 204 into four regions, namely, two source regions 207 and two drain regions 208. Figure 3 In the middle, from left to right, source region 205, drain region 206, source region 205, and drain region 206 are formed in four regions of the first active region 202a outside the area covered by the gate structure 204, respectively. The drain region 208 on the far right is in first-side contact with the third active region 202c.
[0101] In some embodiments, the MOS transistor 301 is an NMOS. Both the source region 205 and the drain region 206 are N+ doped. In other embodiments, the MOS transistor 301 can also be a PMOS.
[0102] Figure 4In this context, the MOS transistor 301 is also represented by NMOS, and the fuse structure 302 is also represented by AA link.
[0103] In some embodiments, the drain region 206 extends simultaneously into the third active region 202c or the drain region 206 extends simultaneously into the third active region 202c and the first fuse connection region 203a or the second fuse connection region 203b adjacent to the third active region 202c.
[0104] In this embodiment of the invention, the active region fuse 203 comprises a metal silicide formed on the surface of the second active region 202b. In some embodiments, the metal silicide comprising the active region fuse 203 comprises NiSi, and the metal silicide can be melted by electromigration, thereby enabling the melting programming of the active region fuse 203. The second active region 202b at the bottom of the metal silicide in the active region fuse 203 serves as the fuse medium.
[0105] In some embodiments, metal silicides are also formed on the surfaces of each of the source regions 205 and each of the drain regions 206.
[0106] In this embodiment of the invention, the efuse unit structure 201 further includes a fourth active region 202d, which serves as an active region pseudo-structure.
[0107] The fourth active region 202d and the second active region 202b are parallel and spaced apart, and the first active region 202a and the fourth active region 202d are located on both sides of the second active region 202b.
[0108] In this embodiment of the invention, each of the efuse unit structures 201 has three electrode ports for connecting to external circuits, namely a source port, a word line port, and a bit line port.
[0109] The word line is connected to the corresponding word line port, the source line is connected to the corresponding source port, and the bit line is connected to the corresponding bit line port.
[0110] The drain line does not directly form a port connected to the outside; if the active region fuse 204 is in the on state, the drain line will be connected to the bit line port.
[0111] like Figure 5 The diagram shown is a layout of the efuse cell pair 401 of the efuse memory in an embodiment of the present invention. Figure 6 Is Figure 5 A layout with a metal layer superimposed on top of it; Figure 7This is a circuit diagram of the efuse cell pair 401 of the efuse memory according to an embodiment of the present invention. In this embodiment of the present invention, two efuse cell structures 201 form an efuse cell pair 401.
[0112] The two efuse unit structures 201 form an efuse unit pair 401. Figure 5 In the above, the two efuse unit structures 201 of the efuse unit pair 401 are the first efuse unit structure 201a and the second efuse unit structure 201b, respectively.
[0113] On the top view, the two efuse unit structures 201 are centrally symmetrical.
[0114] In the efuse unit pair 401, the two efuse unit structures 201 share a fourth active region 202d.
[0115] like Figure 6 As shown, the two efuse unit structures 201 share the same bit line BL.
[0116] Each of the gate structures 204 of the first efuse cell structure 201a is connected to the first word line WL1 through a corresponding contact hole 207.
[0117] Each of the gate structures 204 of the second efuse cell structure 201b is connected to the second word line WL2 through a corresponding contact hole 207.
[0118] Each of the source regions 205 of the first efuse cell structure 201a is connected to the first source line S1.
[0119] Each of the source regions 205 of the second efuse cell structure 201b is connected to the second source line S2.
[0120] Each of the drain regions 206 in the first efuse cell structure 201a is connected to the first drain line D1.
[0121] Each of the drain regions 206 in the second efuse cell structure 201b is connected to the second drain line D2.
[0122] On the top view, the first character line WL1 and the bit line BL are perpendicular.
[0123] The first word line WL1, the second word line WL2, the first source line S1, and the first drain line D1 are parallel, and the first source line S1 and the first drain line D1 are located between the first word line WL1 and the second word line WL2.
[0124] The first source line S1 and the second drain line D2 are located on the same straight line and are spaced apart.
[0125] The first drain line D1 and the second source line S2 are located on the same straight line and are spaced apart.
[0126] Each of the word lines WL, each of the source lines S and each of the drain lines D are composed of a patterned second metal layer (M2).
[0127] The bit line BL consists of a patterned third metal layer (M3).
[0128] Figure 7 In the first efuse cell structure 201a, the first MOS transistor 301a is also represented by NMOS1;
[0129] The first drain line is also represented by D1;
[0130] The first source line is also represented by S1;
[0131] The first character line is also represented by WL1;
[0132] The first fuse structure 302a is also represented by Link1.
[0133] The second MOS transistor 301b of the second efuse cell structure 201b is also represented by NMOS2;
[0134] The second drain line is also represented by D2;
[0135] The second source line is also represented by S2;
[0136] The second alphanumeric line is also represented by WL2;
[0137] The second fuse structure 302b is also represented by Link2.
[0138] In this embodiment of the invention, the efuse array structure is formed by repeating the efuse unit pairs 401.
[0139] Unlike the prior art where the fuse structure 302 of the efuse cell structure 201 is disposed in the metal layer, the fuse structure 302 of this embodiment is disposed in the active region layer. Programming is achieved by melting the active region fuse 203. The fuse structure 302 with the active region fuse 203 only needs to add a second active region 202b that is adjacent to and parallel to the first active region 202a of the MOS transistor 301. This makes the area of the fuse structure 302 of this embodiment of the invention significantly smaller than that of the fuse structure 302 in the metal layer of the prior art, thereby reducing the cell size and the area of the efuse cell structure 201.
[0140] The fuse structure 302 in this embodiment of the invention facilitates the combination and layout of efuse unit structures 201. For example, two efuse unit structures 201 can form a centrally symmetrical efuse unit pair 401, and then the efuse unit pair 401 can be arranged into an efuse array. This can reduce the idle area in the array structure and thus reduce the layout area of the array, thereby improving the layout area utilization and layout work efficiency.
[0141] As can be seen from the above, the embodiment of the present invention uses the AA layer as the fuse medium, forming a device comprising one NMOS transistor and one AA layer fuse. The efuse cell is a three-port (WL, BL, S) device. The efuse cell consists of one AA layer fuse (AA-link) and one NMOS transistor. The gate of the NMOS transistor forms port WL. The NMOS transistor is located on one side of the AA layer fuse, and its drain end is parallel to the AA layer fuse and connected to one end of the fuse. The connection between the AA layer and the M1 layer is formed by a CT at the connection point. An AA dummy is provided on the other side of the AA layer fuse, which serves as a guard line. The other end of the AA layer fuse is connected to the M1 layer through three CTs to form port BL. In efuse cell pair 401, the two efuse cells adopt an inverted layout and share the same BL port. The efuse memory array area is composed of efuse cells, that is, it is composed of the layout of individual cells.
[0142] In this embodiment of the invention, an AA layer is used as the fuse medium, and the AA fuse and the AA of the MOS transistor are integrated into one, that is, the AA layer fuse and the AA layer of the drain terminal of the MOS transistor are directly connected together, which reduces the area of the efuse cell, also helps to reduce the idle area in the efuse cell array, and improves the working efficiency of the efuse layout.
[0143] Compared to existing conventional efuse cells, the layout of this embodiment combines the AA dielectric fuse and the AA portion of the NMOS transistor, which not only reduces the area of the efuse cell, but also allows for convenient and direct combination layout, significantly improving layout efficiency and effectively saving idle area in the array layout. Figure 2 The area of the existing efuse cell (NMOS transistor and fuse) shown is 14.4 μm. 2 Furthermore, by designing the efuse layout according to the embodiments of the present invention, the actual area of the efuse cell can be reduced to 11% of the original area corresponding to the existing efuse cell.
[0144] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. An efuse memory, comprising: The application relates to an efuse cell structure. The efuse cell structure comprises a control transistor composed of a MOS transistor and a fuse structure. The MOS transistor is formed in a first active region. The fuse structure is formed in a second active region, and the first active region and the second active region are parallel. The fuse structure comprises a first fuse connection region, an active region fuse and a second fuse connection region. The active region fuse is located between the first fuse connection region and the second fuse connection region. The top of the first fuse connection region is connected to a drain line of the MOS transistor through a contact hole. The top of the second fuse connection region is connected to a bit line through a contact hole. The active region fuse comprises two states of conduction and fusing. When the efuse cell structure is in an initial state, the active region fuse is in the conduction state, and the drain and the bit line are electrically connected together. When the efuse cell structure is in a programming state, the active region fuse is in the fusing state, and the electrical connection between the drain and the bit line is disconnected. The MOS transistor comprises a gate structure, a source region and a drain region.
2. The efuse memory of claim 1, wherein: The gate structure is in a strip shape and parallel to the strip shape of the second active region. The source region and the drain region are self-aligned and formed in the first active region on both sides of the gate structure. The drain region is connected to a drain line of the MOS transistor through a contact hole. The first active region and the second active region are connected together through a third active region.
3. The efuse memory of claim 2, wherein: A first side of the third active region is connected to the drain region formed in the first active region. A second side of the third active region is connected to one of the first fuse connection region and the second fuse connection region. The top of the third active region is also connected to the drain line through a contact hole. The drain region simultaneously extends to the third active region or the drain region simultaneously extends to the third active region and the first fuse connection region or the second fuse connection region adjacent to the third active region.
4. The efuse memory of claim 3, wherein: A component of the active region fuse comprises a metal silicide formed on the surface of the second active region. The source region is connected to a source line through a contact hole.
5. The efuse memory of claim 3, wherein: The gate structure is connected to a word line through a contact hole. The gate structure comprises a gate dielectric layer and a gate conductive material layer which are sequentially stacked.
6. The efuse memory of claim 5, wherein: The material of the gate dielectric layer comprises a high dielectric constant material; and the material of the gate conductive material layer comprises polysilicon or metal.
7. The efuse memory of claim 6, wherein: The MOS transistor is composed of a plurality of MOS transistor units in parallel.
8. The efuse memory of claim 7, wherein: The gate structures of the MOS transistor units are arranged in parallel. The source region between the two gate structures is shared by the two MOS transistor units. The drain region between the two gate structures is shared by the two MOS transistor units. Two efuse cell structures form an efuse cell pair.
9. The efuse memory of claim 8, wherein: In a top view, the two efuse cell structures are center-symmetric. The efuse cell structure further comprises a fourth active region which serves as an active region pseudo structure.
10. The efuse memory of claim 9, wherein: The fourth active region and the second active region are parallel and have a spacing, and the first active region and the fourth active region are located on both sides of the second active region.
11. The efuse memory of claim 10, wherein: In the pair of efuse cells, the two efuse cell structures share one fourth active region.
12. The efuse memory of claim 9, wherein: The two efuse cell structures of the pair of efuse cells are a first efuse cell structure and a second efuse cell structure respectively. The two efuse cell structures share one bit line. The gate structure of the first efuse cell structure is connected to a first word line through a corresponding contact hole. The gate structure of the second efuse cell structure is connected to a second word line through a corresponding contact hole. The source region of the first efuse cell structure is connected to a first source line. The source region of the second efuse cell structure is connected to a second source line. The drain region of the first efuse cell structure is connected to a first drain line. The drain region of the second efuse cell structure is connected to a second drain line. The first word line and the bit line are perpendicular in a top view. The first word line, the second word line, the first source line and the first drain line are parallel, and the first source line and the first drain line are located between the first word line and the second word line. The first source line and the second drain line are located on the same line and have a spacing. The first drain line and the second source line are located on the same line and have a spacing.
13. The efuse memory of claim 12, wherein: The word line, the source line and the drain line are composed of a second metal layer after patterning. The bit line is composed of a third metal layer after patterning.
14. The efuse memory of claim 12, wherein: The efuse cell structure has three electrode ports for connecting with external circuits, which are a source port, a word line port and a bit line port. The word line is connected to the corresponding word line port, the source line is connected to the corresponding source port, and the bit line is connected to the corresponding bit line port.
15. The efuse memory of claim 12, wherein: The efuse array structure is formed by repeating the pair of efuse cells.