Current limiting solid state circuit breaker device

Abstract

The invention relates to a current limiting solid state circuit breaker device. The invention relates to a device (101) and a method for limiting a current in the event of a short circuit. The device (101) comprises: a main switch arranged in series between a device input (ain) and a device output (aout); a first parallel diode (D1) in the backward direction and a second parallel diode (D2) in the forward direction, wherein there is a first central node (N1) between the first and second parallel diodes. The device (101) further comprises a first branch diode (Da1) in the forward direction and a second branch diode (Da2) in the backward direction, wherein there is a second center node (N2) between the first branch diode and the second branch diode. And the device comprises a chopper circuit (CC), the chopper circuit (CC) comprising a chopper capacitor (Cb) and a chopper semiconductor (Sb).

Description

Technical Field

[0001] This invention relates to the field of solid-state circuit breakers (SSCBs), and more particularly to devices and methods for limiting current in the event of a short circuit. The invention also relates to an application. Background Technology

[0002] In many systems, such as DC power grids, solid-state circuit breakers (SSCBs) can play a crucial role in system protection. However, the typically high interruption speed of SSCBs can have some drawbacks, at least in some configurations. An example of an SSCB configuration according to the prior art could be a combination of two series semiconductors and a parallel rheostat used to dissipate energy stored in, for example, in inductive elements within the system. However, for practical systems, this can cause excessive wear on the rheostat and semiconductors during the "open" or "trip" phase. This can result in high thermal stress on these components, thus increasing the risk of failure. Summary of the Invention

[0003] The purpose of this disclosure is to provide an improved SSCB device.

[0004] This objective is achieved through the subject matter of the independent claims. Further embodiments will be apparent from the dependent claims and the following description.

[0005] One aspect relates to a device for limiting current in the event of a short circuit, the device comprising:

[0006] The main switch is connected in series between the device input and the device output.

[0007] A first parallel diode in the backward direction and a second parallel diode in the forward direction are arranged in series and in parallel with the main switch, wherein there is a first central node between the first parallel diode and the second parallel diode;

[0008] A first branch diode in the forward direction and a second branch diode in the backward direction, the first branch diode and the second branch diode being connected in series between the device input and the device output, wherein a second center node is present between the first branch diode and the second branch diode; and

[0009] A chopper circuit, arranged between a first center node and a second center node, includes:

[0010] A chopper capacitor is arranged between the first center node and the second center node, and

[0011] A chopper semiconductor, which, together with a chopper resistor, is arranged in series between the first center node and the second center node.

[0012] This allows the sub-circuit, which includes a branch diode and a chopper circuit, to limit current by guiding current through the sub-circuit in the event of a short circuit.

[0013] Short circuits can occur, for example, in a power grid or a so-called microgrid. The grid or microgrid can be a DC-based system, but the device can also be used in an AC-based system. The device can be positioned between the power-generating equipment or plant and the load, with the device input on the power-generating side and the device output on the power-consuming side or the load side. The "load" can be implemented as multiple loads.

[0014] The device's "main switch" can be one or more switches or components through which power is directed during normal operation. During a "disconnect" or "trip" phase, these main switches are disconnected, thereby interrupting power flow from the power generation section to the load. The main switch can include, for example, a mechanical switch, a reverse blocking IGCT, or a first and second semiconductor arranged in series between the device input and output. In the case of the first and second semiconductors, the semiconductors are arranged in an "anti-sequence" manner.

[0015] When the semiconductor is a bipolar semiconductor or an IGBT, the first and second semiconductors can be arranged as a common-emitter or common-collector configuration. When the semiconductor is a MOSFET, the first and second semiconductors can be arranged as a common-drain or common-source configuration. A first center node is located between the first and second semiconductors.

[0016] In the case where the main switch includes a first semiconductor and a second semiconductor, a first parallel diode is arranged in parallel with the first semiconductor in the backward direction, and a second parallel diode is arranged in parallel with the second semiconductor in the forward direction. Therefore, the node between the first and second parallel diodes is the same "first center node" (having the same potential) as the first center node between the first and second semiconductors. The term "forward direction" means that current can flow from the device input through the diode to the device output, while "backward direction" or "reverse direction" means that the diode prevents current from flowing from the device input to the device output. In some types of semiconductors, the parallel diode can be implemented as a so-called "body diode."

[0017] The device also includes a first branch diode in the forward direction and a second branch diode in the backward direction. These diodes are arranged in series between the device input and the device output, with a second center node between these diodes.

[0018] The device also includes a chopper circuit arranged between the first center node and the second center node. The chopper circuit includes a chopper capacitor arranged between the first and second center nodes. Therefore, the voltage between the first and second center nodes can also be referred to as the "chopper capacitor voltage." The chopper circuit also includes a chopper semiconductor arranged in series with a chopper resistor. The chopper semiconductor and the chopper resistor are arranged in series between the first and second center nodes.

[0019] In one embodiment, the chopper circuit may further include a chopper diode in the backward direction. The chopper diode is arranged in parallel with the chopper resistor. This chopper diode, designed as a freewheeling diode, can be advantageous when the chopper resistor has a non-negligible parasitic inductance.

[0020] Therefore, the sub-circuit, including the branch diode and chopper circuit, is advantageously configured to limit current by guiding current through the sub-circuit in the event of a short circuit. Compared with other methods, this device has at least the following advantages:

[0021] This device avoids using a freewheeling path that connects the positive and negative potentials of the bus voltage. Such a freewheeling path can be problematic for compliance with certain circuit breaker standards and tests.

[0022] This device enables long-duration (tens of milliseconds) current limiting with minimal hardware changes and is simply a simple extension of at least some existing SSCB devices. It allows for coordination with slower mechanical or hybrid types of downstream circuit breakers with disconnection times of several milliseconds.

[0023] This method avoids switching the main semiconductor during current-limited operation. Only the chopper switch is operated, and the switching frequency of the chopper switch is quite low. This allows the use of high-current devices with high switching losses (such as IGCTs or RB-IGCTs) as the main switch, and the use of cheaper devices (such as IGBTs) as the chopper switch.

[0024] This method uses a chopper resistor, a device commonly used as a braking resistor in unidirectional motor drives. Operating in a repetitive chopping mode avoids the misuse of out-of-specification variable resistors (MOVs).

[0025] This method allows for selective exit from current-limited mode and safely interrupts fault current within tens of microseconds.

[0026] The method may additionally or alternatively allow precharging of “dead” buses (i.e., buses without voltage, such as during system startup) and the input capacitors of the converter with a limited and controlled charging current.

[0027] In various embodiments, the main switch includes a first reverse blocking IGCT and a second reverse blocking IGCT, which are arranged in antiparallel between the device input and the device output.

[0028] This variant can be advantageously used in conjunction with an integrated gate commutation thyristor (IGCT) or a reverse blocking integrated gate commutation thyristor (RB-IGCT).

[0029] In various embodiments, the main switch includes a mechanical switch arranged between the device input and the device output.

[0030] This variant can be advantageously combined with mechanical switches to implement what is known as a "hybrid circuit breaker." The mechanical switch can be a relay, trip switch, contactor switch, or circuit breaker.

[0031] In various embodiments, the chopper circuit may also include a chopper diode in the backward direction. The chopper diode is arranged in parallel with the chopper resistor. This chopper diode, designed as a freewheeling diode, can be advantageous when the chopper resistor has a non-negligible parasitic inductance.

[0032] In various embodiments, the device further includes an inductor disposed between the device output and the load. Additionally or alternatively, the inductor may be disposed on the input side of the device. The inductor may have an inductance between 1 μH and 500 μH, particularly between 15 μH and 150 μH. The inductor advantageously limits the maximum rate of change of fault current.

[0033] In various embodiments, the device further includes a mechanical switch disposed between the device output and the load. Additionally or alternatively, the mechanical switch may be disposed on the input side of the device. Additionally or alternatively, the device also includes a mechanical switch disposed before the device input. The mechanical switches (one or more) may allow current isolation on the input side and / or the output side of the device.

[0034] In various embodiments, the device also includes an auxiliary pre-charge circuit to keep the voltage at Cb close to the nominal bus voltage.

[0035] In various embodiments, the device also includes small inductors at the input and / or output sides. These can be advantageous for limiting maximum di / dt and for current control purposes. In one embodiment, the device also includes current sensors at the input and output sides for current control purposes and / or voltage sensors across a chopper capacitor for control purposes.

[0036] One aspect relates to a method for limiting current in the event of a short circuit using a device according to any one of the preceding claims, the method comprising the steps of:

[0037] Set the device to normal operating mode, in which the main switch is closed;

[0038] When an overcurrent occurs, the device is set to a current-limiting mode in which the main switch is turned off and a sub-circuit including a branch diode and a chopper circuit mitigates the current in the event of a short circuit by guiding current through the sub-circuit. The current-limiting mode is executed for a predefined period of time. After the predefined period of time, the device is set to a fast interrupt mode in which the main switch is turned off and the chopper circuit is turned off by turning off the chopper semiconductor Sb.

[0039] The device's "main switch" can be one or more switches or components through which power is directed during normal operation. During a "disconnect" or "trip" phase, these main switches are disconnected, thereby interrupting power flow from the power generation section to the load. The main switch may include a first semiconductor and a second semiconductor, arranged in series between the device input and the device output. The main switch may also include a first IGCT and a second IGCT, arranged anti-parallel between the device input and the device output. Finally, the main switch may include a mechanical switch arranged between the device input and the device output.

[0040] In various embodiments, the duration of the predefined time frame is between 0.1 ms and 100 ms, particularly between 0.5 ms and 20 ms. This short time frame can help the device to be used in both DC-based and AC-based systems.

[0041] In various embodiments, the oscillation mode frequency of the chopper circuit is between 1 kHz and 20 kHz, particularly between 2 kHz and 5 kHz. This relatively low frequency can contribute to low switching losses in the chopper semiconductor, even under overcurrent conditions.

[0042] One aspect relates to the use of a device as described above and / or below for limiting current under short-circuit conditions within a DC grid, a DC microgrid, an AC grid, and / or an AC microgrid. The term "grid" can, for example, refer to a large power distribution system. The term "microgrid" can, for example, refer to a power distribution system connected to a system, such as in the case of a renewable energy system, or a charging system for electric vehicles.

[0043] One aspect relates to the use of a device as described above and / or below for limiting overcurrents occurring at the device input and / or device output. The device is fully bidirectional, meaning it can limit and / or interrupt current in both directions. In complex power grids, energy may also be connected downstream, i.e., at the device output. A short circuit at the device input can cause a high fault current in the reverse direction. The device described above and / or below can also limit and interrupt the high fault current in the reverse direction.

[0044] One aspect relates to the use of a device as described above and / or as described below for limiting the current within a DC bus during a black start. A "black start" can be a system restart in a power system when there is no current and / or voltage.

[0045] To further illustrate this disclosure, embodiments shown in the accompanying drawings are used to describe the present disclosure. These embodiments are considered examples only and are not intended to limit the scope of the disclosure. Attached Figure Description

[0046] The attached diagram depicts:

[0047] Figure 1 An embodiment of a solid-state circuit breaker according to the prior art is illustrated schematically;

[0048] Figure 2 It schematically shows the following based on Figure 1 A diagram of the current in the embodiment;

[0049] Figure 3 It schematically shows the following based on Figure 1 A diagram of power loss in the embodiment;

[0050] Figure 4 The device according to an embodiment is illustrated schematically;

[0051] Figures 5a-5c It schematically shows the following based on Figure 4 Current flow in the embodiments;

[0052] Figures 6a-6c It schematically shows the following based on Figure 4 Current flow in the embodiments;

[0053] Figure 7 It schematically shows the following based on Figure 4 A diagram of the current in the embodiment;

[0054] Figure 8 It schematically shows the following based on Figure 4 A diagram of the voltages in the embodiments;

[0055] Figure 9 It schematically shows the following based on Figure 4 A diagram of the current in the embodiment;

[0056] Figure 10 It schematically shows the following based on Figure 4 A diagram of the voltages in the embodiments;

[0057] Figure 11 It schematically shows the following based on Figure 4 A diagram of the current in the embodiment;

[0058] Figure 12 It schematically shows the following based on Figure 4 A diagram of the voltages in the embodiments;

[0059] Figures 13 to 16 An example of an embodiment is illustrated schematically;

[0060] Figure 17 This is a flowchart based on one embodiment.

[0061] Figure 18 A sub-circuit according to an embodiment is schematically shown;

[0062] Figure 19 This schematically illustrates the situation under black start conditions. Figure 4 A graph of current and voltage in the embodiment. Detailed Implementation

[0063] Figure 1 An embodiment of a solid-state circuit breaker (SSCB) 105 according to the prior art is schematically illustrated. The SSCB 105 has two semiconductors S1 and S2, which are arranged in series (or “anti-series”) at the device input a. in With device output a out Between. The SSCB 105 also features a variable resistor Z1, which is arranged in parallel with semiconductors S1 and S2. At the device output a out Previously, inductor L was installed. out Current I out The current flows through the inductor L out Inductor L outThis can be a physical component of the SSCB, and / or it can represent the total inductance in the microgrid due to wiring and filtering components. Some exemplary values ​​are used to illustrate the effect of the SSCB 105 quantitatively. To limit current during fault overcurrent using the SSCB 105, tolerance band control can be used. Figure 2 and Figure 3 The diagram assumes a current limit of 110A, with a tolerance range of 20A, and an inductance L. out The value is 100 μH. Furthermore, it is assumed that the upstream line inductance (not shown) is 2 μH. An ideal short-circuit fault (described as a flash) is applied at the end of the line after 1 ms, at the device output a out area.

[0064] Figure 2 The current I is shown out The final behavior. When the current I out When the upper threshold is reached (here: 110A), semiconductors S1 and S2 are turned off, and the current is switched to the variable resistor Z1. The variable resistor generates a clamping voltage U. Z1 This voltage is typically several hundred volts higher than the nominal system voltage Uout. The difference between the nominal voltage and the resistor voltage (several hundred volts, with opposite signs) is applied to the line inductance L. out :

[0065] U Lout =U out -U Z1 =L out • di / dt ≈ -200V.

[0066] This will rapidly reduce the fault current. The current will reach the lower limit threshold of the tolerance band within tens of microseconds (here: 110A - 20A = 90A), and semiconductors S1 and S2 will thus be turned on again.

[0067] Therefore, a series of turn-off and turn-on events will occur at a very high repetition rate. This results in a high switching frequency (40 kHz in this example) for semiconductors S1 and S2, which in turn generates high switching losses in the semiconductors. Furthermore, for each turn-off event, a major portion of the energy stored in the line inductance is burned in the rheostat, such as... Figure 3 As shown. Due to the high repetition rate, the average loss in the rheostat can reach very high values ​​(35kW in this example). Most rheostats (MOVs) are not designed to operate in repetitive mode, i.e., this chopping mode would cause the rheostat to exceed its specifications. This can cause high thermal stress on the component and thus increase the risk of failure.

[0068] This behavior of the existing SSCB 105 causes the following major problems, which limit the feasible current-limiting phase to only a few hundred microseconds:

[0069] The rheostat operates outside its specifications, especially since most rheostats are not designed to operate in repetitive mode.

[0070] The maximum energy dissipation of the rheostat is reached within tens of microseconds, and without the application of a costly, high-performance cooling concept, the rheostat Z1 can overheat and fail.

[0071] High switching frequencies will generate high switching losses in semiconductors S1 and S2. This can lead to excessively high temperatures and increase the risk of failure, especially if high-cost, high-performance cooling concepts are not applied.

[0072] In high-current SSCBs, the required switching frequency is often not achievable, for example when using IGCTs, because the gate driver cells have limited switching capability in the lower kilohertz range.

[0073] Figure 4 A device 101 according to one embodiment is schematically illustrated, which is designed to overcome the aforementioned problem by limiting current in the event of a short circuit. Device 101 includes a first semiconductor S1 and a second semiconductor S2 as main switches. The main switches S1 and S2 are arranged in series at the device input a of device 101. in With device output a out Between. Most of the following explanations assume (but are not limited to) that the DC bus is protected. Equipment input a in It can be the positive electrode.

[0074] The first center node N1 is located between the first semiconductor S1 and the second semiconductor S2. The device 101 also includes a first parallel diode D1 and a second parallel diode D2. The first parallel diode is connected in parallel with the first semiconductor S1 in the backward direction, and the second parallel diode is connected in parallel with the second semiconductor S2 in the forward direction. Therefore, the first center node N1 is also located between the first parallel diode D1 and the second parallel diode D2.

[0075] To limit current in the event of a short circuit, the sub-circuit is arranged in parallel with semiconductors S1 and S2. This sub-circuit includes a first branch diode Da1 in the forward direction and a second branch diode Da2 in the backward direction. Branch diodes Da1 and Da2 are arranged in series at device input a. in With device output a outThe second center node N2 is located between branch diodes Da1 and Da2. The sub-circuit also includes a chopper circuit CC, which is arranged between the first center node N1 and the second center node N2. The chopper circuit CC includes a chopper capacitor Cb and a chopper semiconductor Sb. The chopper capacitor is arranged between the first center node N1 and the second center node N2, and the chopper semiconductor and chopper resistor Rb are connected in series between the first center node N1 and the second center node N2.

[0076] The chopper resistor Rb can be selected such that when the chopper switch Sb is turned on at the nominal bus voltage VN, the current flowing through it is higher than the maximum limiting fault current.

[0077] Rb <VN / I lim,max

[0078] This design is robust in the following sense: if the fault current exceeds the chopper resistor current while Sb remains on, the voltage at Cb will continue to rise. Therefore, the increased voltage is inserted in series into the fault, and the fault current will begin to decrease naturally.

[0079] Furthermore, the chopper circuit CC includes an optional chopper diode Db in the backward direction. The chopper diode Db is arranged in parallel with the chopper resistor Rb. The chopper diode Db can be advantageous when the chopper resistor Rb has a non-negligible parasitic inductance.

[0080] Figure 7 An example of a current-limiting mode is shown. Again, assume a current limit of 110A, with a tolerance band of 20A. Assume the downstream line inductance L... out The current is 100 μH, and the upstream line inductance (not shown) is assumed to be 2 μH. In normal operating mode, main switches S1 and S2 are closed. Figure 5a The generated current is described in the figure.

[0081] for Figure 4 Device 101, after 1ms, outputs a. out A short circuit fault occurred in the area (described as a flash). From Figure 7 As can be seen, this causes the short-circuit fault to occur 1ms later, through inductor L out Current I out It increases immediately and significantly. Current I out The current increases from approximately 20A to approximately 110A. Upon detection of a fault, semiconductor switches S1 and S2 are permanently turned off, and the device enters a current-limiting mode. In current-limiting mode, current is diverted to the parallel branch diode Da1, capacitor Cb, and diode D2; see [link to relevant documentation]. Figure 5bThe voltage across capacitor Cb is accumulating and is being connected in series between the bus voltage and the fault. Once the capacitor voltage reaches the bus voltage, the fault current I... out It then stops rising and begins to decay. To limit and control the fault current within a given frequency band, the chopper switch Sb is turned on when the fault current reaches the lower current threshold; see [link to relevant documentation]. Figure 5c This will begin discharging capacitor Cb through chopper resistor Rb. The voltage at Cb then drops below the nominal bus voltage, and the fault current will begin to rise again. If the upper current threshold is reached, chopper switch Sb is turned off again, and the voltage at capacitor Cb rises until the fault current begins to decrease again. This sequence is repeated whenever current limiting is required. The final switching frequency of the chopper switch depends primarily on capacitor Cb, chopper resistor Rb, and the width of the current control tolerance band, and can be easily adjusted to within a few kilohertz. After the current limiting period, the fault can be quickly interrupted by continuously turning off chopper switch Sb. This... Figure 7 The reading is shown as 6ms. The voltage at capacitor Cb will then rise above the nominal bus voltage, and the current will decay to zero within a few microseconds.

[0082] Figure 7 and Figure 8 The example waveform is shown assuming capacitor Cb is pre-charged to a nominal bus voltage of 350V. When entering current-limiting mode, the fault current I... out It is kept within a tolerance band of (90A, 110A). The voltage at capacitor Cb remains close to the nominal bus voltage. When leaving the current limiting mode and the current interruption mode is activated after 6ms, the voltage at capacitor Cb rises to 450V, and the fault current decays to zero after tens of microseconds.

[0083] Figure 9 and Figure 10 The example waveform of a 50μF capacitor Cb assuming no pre-charge is shown. When a fault occurs (at 1ms), the current I... out You can first temporarily exceed the 110A current limit until the voltage U at capacitor Cb is reached. Cb The voltage has reached a sufficiently high level. After the first overshoot, the fault current I... out Returning to the tolerance band of (90A, 110A). The voltage at capacitor Cb remains close to the nominal bus voltage. When leaving current-limiting mode and activating current-interruption mode (at 6ms), the voltage U at capacitor Cb... Cb The voltage rose to 480V, and the fault current I... out It decays to zero after tens of microseconds.

[0084] Depending on the installed capacitor Cb and the mains inductance, during a current interruption, the voltage U at capacitor Cb may need to be reduced. Cb The voltage is limited to an allowable level (i.e., several hundred volts above the nominal bus voltage, but below the nominal voltage of the diodes and semiconductor switches). This can be achieved by briefly turning on the chopper switch Sb again when the upper limit capacitor voltage is reached. Thus, the voltage U at capacitor Cb... Cb The voltage tolerance band is controlled to maintain an elevated level (several hundred volts higher than the nominal bus voltage): if the upper limit capacitor voltage threshold is reached, the chopper switch Sb is turned on to discharge capacitor Cb until the lower limit capacitor voltage threshold is reached. Then the switch Sb is turned off again.

[0085] Figure 11 and Figure 12 An example of capacitor voltage limiting during a current interruption is shown in the figure, with an increased grid inductance of 400 μH. The voltage U at capacitor Cb is... Cb It is limited to 500V by a chopper to protect all semiconductors in the SSCB.

[0086] Figures 6a to 6c The illustration schematically shows the situation under the condition of a short circuit at the device input. Figure 4 The current flow in the embodiments is illustrated. Such events can occur in complex microgrids where energy sources can be connected downstream, i.e., on the output side of the circuit breaker device. In such cases, this energy will cause a fault current to flow through the device in the reverse direction. Since the proposed device is fully bidirectional, the same functions of current limiting and interruption are achieved again in this scenario.

[0087] Figures 13 to 16 Examples of embodiments are illustrated schematically to compare some alternatives applicable to several types of main switches. The same reference numerals denote the same or similar elements. Figure 13 Basically with Figure 4 Same, except without inductor L out . Figure 14 It shows the replacement of the common collector device Figure 13 Implementation of a common emitter device. Figure 15 Embodiment 102 is shown with reverse blocking integrated gate commutated thyristors (RB-IGCT) S11 and S12, which are arranged in anti-parallel at device input a. in With device output a out The first central node N1 is located between diodes Db1 and Db2. Figure 16 Embodiment 103 of the hybrid circuit breaker is shown, wherein the mechanical switch SWm is arranged as the main switch at the equipment input a.in With device output a out The first central node N1 is located between diodes Db1 and Db2.

[0088] Figure 17 A flowchart 200 according to an embodiment is shown. Flowchart 200 illustrates a method for limiting current by means of devices 101, 102, 103 in the event of a short circuit (see, for example...). Figures 13 to 16 In step 205, devices 101, 102, and 103 are set to normal operating mode, in which main switches S1, S2, S11, S12, and SWm are closed, and Sb is open. In step 210, an overcurrent is checked. If not, devices 101, 102, and 103 remain in normal operating mode. When an overcurrent occurs, devices 101, 102, and 103 are set to current limiting mode, in which main switches S1, S2, S11, S12, and SWm are open, and the sub-circuit—including the branch diodes Da1 and Da2 and the chopper circuit CC—limits the current by guiding current through the sub-circuit in the event of a short circuit. The current limiting mode can be executed for a predefined period T. lim This is checked in step 220. When the predefined time period T... lim Once the fault has passed—or any other current interruption condition becomes true—in step 225, devices 101, 102, and 103 are set to a fast interruption mode, in which main switches S1, S2, S11, S12, and SWm remain open, and the chopper circuit CC is turned off by shutting down Sb. The device may also leave current-limiting mode 215 and return to normal mode 205 or 210 when the fault current decays to below the overcurrent threshold, for example, because another downstream circuit breaker in series has isolated the fault.

[0089] Figure 18 The sub-circuit Sb_ control according to an embodiment is schematically shown. The Sb_ control has an input "fast interrupt," i.e., when the flowchart... Figure 17 Request a fast interrupt when state 225 has been reached. Enter I. out That is, the output current of the device; and the input U. Cb This refers to the voltage across the chopper capacitor Cb. The output controlled by Sb_ is connected to the gate of the chopper switch Sb. out and U cb Implement the hysteresis function. The logic for Sb_ control in current limiting mode 215 and fast interrupt mode 225 can be shown in Table 1 below:

[0090] Table 1: Sb_Control Logic

[0091] Fast interrupt <![CDATA[I out ]]> <![CDATA[U Cb ]]> Output no Current Limit Voltage Limits 1 no Current Limit <Voltage limit 0 no <Current limit value Voltage Limits 1 no <Current limit value <Voltage limit 1 yes Current Limit Voltage Limits 1 yes Current Limit <Voltage limit 0 yes <Current limit value Voltage Limits 1 yes <Current limit value <Voltage limit 0

[0092] As mentioned above, input I out Current hysteresis can be considered to establish a current-limiting tolerance band. As mentioned above, the input U Cb Voltage hysteresis can be considered to establish a voltage-limiting tolerance band.

[0093] Figure 19 This schematically illustrates a black-start scenario, i.e., when there is no power on the DC bus (DC bus voltage is zero), for example, after a hardware reset, according to... Figure 4 A graph of current and voltage in the embodiments. Devices 101, 102, 103 (see, for example) Figures 13 to 16 This can also be advantageously used in such situations to reduce current in the system. When the DC bus voltage is zero, the DC bus and the input capacitor C... load The potential load converter can be charged with a current limit. During this pre-charge process, current limiting methods as described above and / or below can be used. Main switches S1 and S2 remain off until the charging current stabilizes and the output voltage reaches near the nominal bus voltage. During this period, current flows through the chopper resistor Rb. Therefore, the chopper resistor Rb acts as a pre-charge resistor. When the output voltage approaches the nominal voltage, main switches S1 and S2 can be safely closed, and subsequent oscillations can therefore be kept within acceptable limits. Cb can be greater than the typical load input capacitance C. load Much smaller.

Claims

1. A device (101) for limiting current in case of short circuit, the device (101) comprising: a main switch, said main switch being arranged in series between a device input (a in ) and a device output (a out ) a first parallel diode (D1) in backward direction and a second parallel diode (D2) in forward direction, the first parallel diode (D1) and the second parallel diode (D2) being arranged in series and in parallel to the main switch, with a first center node (N1) between the first parallel diode and the second parallel diode; a first branch diode (Da1) in a forward direction and a second branch diode (Da2) in a reverse direction, the first branch diode (Da1) and the second branch diode (Da2) being arranged in series between the device input (a in ) and the device output (a out ), with a second central node (N2) between the first branch diode and the second branch diode; and a chopper circuit (CC) arranged between the first center node (N1) and the second center node (N2), the chopper circuit (CC) comprising: a chopper capacitor (Cb) arranged between the first center node (N1) and the second center node (N2), and a chopper semiconductor (Sb) arranged in series with a chopper resistor (Rb) between the first center node (N1) and the second center node (N2), such that a sub-circuit comprising the shunt diode (Da1, Da2) and the chopper circuit (CC) is configured for limiting the current in case of short circuit by directing the current through the sub-circuit.

2. The device (101) according to claim 1, wherein the main switch comprises a first semiconductor (S1) and a second semiconductor (S2), the first semiconductor (S1) being arranged in parallel to the first parallel diode (D1) and the second semiconductor (S2) being arranged in parallel to the second parallel diode (D2), the first semiconductor being arranged in forward direction and the second semiconductor being arranged in backward direction.

3. The device (101) according to claim 2, wherein the first semiconductor (S1) and the second semiconductor (S2) are bipolar semiconductors or IGBTs, the first semiconductor (S1) and the second semiconductor (S2) being arranged in a common emitter arrangement or a common collector arrangement.

4. The device (101) according to claim 2, wherein the first semiconductor (S1) and the second semiconductor (S2) are MOSFETs or JFET semiconductors, the first semiconductor (S1) and the second semiconductor (S2) being arranged in a common drain arrangement or a common source arrangement.

5. The device (102) according to claim 1: wherein said main switch comprises a first reverse blocking IGCT (S11) and a second reverse blocking IGCT (S12), said first and second reverse blocking IGCTs being anti-parallel arranged to each other between said device input (a in ) and said device output (a out ).

6. The device (103) according to claim 1: wherein said main switch comprises a mechanical switch (SWm) arranged between the device input (a in ) and the device output (a out ).

7. The device (101, 102, 103) according to any of the preceding claims, further comprising a chopper diode (Db) in backward direction, the chopper diode (Db) being arranged in parallel to the chopper resistor (Rb).

8. The device according to any one of the preceding claims (101, 102, 103) further includes an inductor (L). out The inductor (L) out ) is arranged at the output of the device (a out Between (L) and load (L).

9. The device (101, 102, 103) of claim 8, wherein the inductor (L out ) has an inductance between 1 pF and 500 pF, in particular between 15 pF and 150 pF.

10. The device according to any one of the preceding claims (101, 102, 103) further includes a mechanical switch (SW). OUT The mechanical switch (SW) OUT ) is arranged at the output of the device (a out Between the load (L) and the load (L).

11. A method for limiting current in case of short circuit by means of the device (101, 102, 103) according to any of the preceding claims, the method comprising the steps of:

12. The method according to claim 11, wherein the main switch comprises a first semiconductor (S1) and a second semiconductor (S2), the first semiconductor (S1) being arranged in parallel to the first parallel diode (D1) and the second semiconductor (S2) being arranged in parallel to the second parallel diode (D2), the first semiconductor being arranged in forward direction and the second semiconductor being arranged in backward direction.

13. The method according to claim 12, wherein the first semiconductor (S1) and the second semiconductor (S2) are bipolar semiconductors or IGBTs, the first semiconductor (S1) and the second semiconductor (S2) being arranged in a common emitter arrangement or a common collector arrangement.

14. The method according to claim 12, wherein the first semiconductor (S1) and the second semiconductor (S2) are MOSFETs or JFET semiconductors, the first semiconductor (S1) and the second semiconductor (S2) being arranged in a common drain arrangement or a common source arrangement.

15. The method according to claim 11:

16. The method according to claim 11:

17. The method according to any of the preceding claims 11 to 16, further comprising a chopper diode (Db) in backward direction, the chopper diode (Db) being arranged in parallel to the chopper resistor (Rb). providing the device (101, 102, 103) in a normal operation mode in which the main switch (S1, S2, S11, S12, SWm) is closed; When an overcurrent occurs, the device (101, 102, 103) is set in a current limiting mode in which the main switch (S1, S2, S11, S12, SWm) is opened and a subcircuit comprising a shunt diode (Dai, Da2) and a chopper circuit (CC) mitigates the current by directing it through the subcircuit in case of a short circuit, the current limiting mode being executed for a predefined time period (T lim ). and after the predefined time period (T lim ) the device (101, 102, 103) is set in a fast interrupt mode in which the main switch (S1, S2, S11, S12, SWm) is opened and the chopper circuit (CC) is switched off by switching off the chopper semiconductor Sb.

12. The method according to claim 11, wherein the predefined time period has a duration between 0.1 ms and 10 ms, in particular between 0.5 ms and 20 ms, and / or wherein the frequency of the oscillation pattern of the chopper circuit is between 1 kHz and 20 kHz, in particular between 2 kHz and 5 kHz.

13. Use of a device (101, 102, 103) according to any one of claims 1 to 10 for limiting the current in case of a short circuit within a DC electrical grid, within a DC microgrid, within an AC electrical grid and / or within an AC microgrid.

14. Use of a device (101, 102, 103) according to any one of claims 1 to 10 for limiting overcurrents occurring at the device input (a in ) and / or at the device output (a out ).

15. Use of a device (101, 102, 103) according to any one of claims 1 to 10 for limiting the current within a DC bus in case of a black start of the DC bus.

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