Super capacitor charging protection circuit of intelligent fusion terminal

Abstract

The invention discloses an intelligent fusion terminal super capacitor charging protection circuit, and relates to the technical field of intelligent fusion terminal charging protection. The circuit comprises a power supply; the input end of the charging voltage detection control circuit is connected with the power supply, the output end of the charging voltage detection control circuit is connected with at least one super capacitor, and the charging voltage detection control circuit is used for performing overcharge protection on the super capacitor; the super capacitors are respectively provided with a self-balancing circuit, and the self-balancing circuit is connected between the charging voltage detection control circuit and the ground end and used for carrying out charging control and voltage balancing on the super capacitors. According to the invention, the charging voltage of the super capacitor is detected and controlled through the charging voltage detection control circuit, the charging voltage is limited in a rated voltage range of the super capacitor, and overcharge protection is carried out on the super capacitor; based on the self-balancing circuit formed by the voltage stabilizer, the self-balancing of the voltage of the charging single body of the super capacitor is realized, and the charging safety of the super capacitor is ensured.

Description

TECHNICAL FIELD

[0001] The application relates to a super capacitor charging protection circuit of an intelligent fusion terminal, and belongs to the technical field of charging protection of the intelligent fusion terminal. BACKGROUND

[0002] The super capacitor is an energy storage device between a battery and a common capacitor, and the energy storage of the super capacitor can make the intelligent fusion terminal maintain operation time meeting the standard requirements after power failure. The super capacitor has the characteristics of long cycle service life, wide working temperature range, fast charging and discharging speed and large power density, but the charging of the super capacitor cannot exceed the withstand voltage value, and overvoltage charging will cause breakdown of the dielectric in the super capacitor, and also cause excessive heat in the super capacitor to cause vaporization of the electrolyte, bulging or cracking of the shell, leakage of the electrolyte, circuit failure and safety hazards. SUMMARY

[0003] The application aims to provide a super capacitor charging protection circuit of an intelligent fusion terminal, which controls the total super capacitor charging voltage in the total rated range through a charging voltage detection control circuit, and ensures that the charging voltages of the super capacitors are equal and do not exceed the rated voltages of the super capacitors through self-balancing circuits of the super capacitors, thereby guaranteeing the charging safety of the super capacitors of the intelligent fusion terminal.

[0004] To achieve the above-mentioned purpose, the application adopts the following technical scheme.

[0005] In one aspect, the application provides a super capacitor charging protection circuit of an intelligent fusion terminal, which comprises:

[0006] a power supply;

[0007] a charging voltage detection control circuit, an input end of which is connected to the power supply, and an output end of which is connected to at least one super capacitor, and which is used for overcharge protection of the super capacitor;

[0008] The super capacitors are respectively provided with self-balancing circuits, which are connected between the charging voltage detection control circuit and a ground end, and are used for charging control and voltage balancing of the super capacitors.

[0009] Optionally, the charging voltage detection control circuit comprises:

[0010] a MOS tube Q1, a source electrode of which is connected to a power supply VDD, a gate electrode of which is pulled up to the power supply VDD through a resistor R1, and a drain electrode of which is connected to a drain electrode of a MOS tube Q2 through a resistor R2; a drain electrode of the MOS tube Q1 is connected to a voltage detector U1 via a diode D2;

[0011] A voltage detector U1, whose input pin VCC is connected to the negative pole of a diode D2, whose output pin is connected to the gate of a MOS transistor Q2 and one end of a resistor R4 and is pulled up to a power supply VDD through a resistor R3, whose ground pin GND is connected to the other end of the resistor R4 and is grounded, and whose other end is connected to the source of the MOS transistor Q2. The resistor R4 is used for discharging the parasitic capacitance charge of the gate and source of the MOS transistor Q2, preventing the MOS transistor Q2 from malfunctioning and the gate and source from being broken down.

[0012] Optionally, the self-balancing circuit comprises:

[0013] A triode Q3, whose emitter is connected to the positive pole of the diode D2 and the positive pole of a super capacitor CF1, and whose collector is connected to the negative pole of the super capacitor CF1;

[0014] A voltage stabilizer U2, whose anode is connected to the collector of the triode Q3, and whose cathode is connected to the base of the triode Q3;

[0015] A voltage dividing resistor network, which is connected between the emitter and the collector of the triode Q3, and whose midpoint is connected to the reference end of the voltage stabilizer U2, and which comprises a resistor R8 and a resistor R9 connected in series;

[0016] The other end of the resistor R8 is connected to the emitter of the triode Q3, and the other end of the resistor R9 is connected to the collector of the triode Q3.

[0017] Optionally, one or more current-limiting resistors and a diode D1 are further arranged in sequence between the drain of the MOS transistor Q1 and the positive pole of the diode D2; the diode D1 prevents the voltage of the super capacitor from being reversed and fed back to the power supply VDD, and the current-limiting resistors are used to reduce the impact of the current on the super capacitor during the initial charging process.

[0018] A filter capacitor C1 is connected in parallel between the input pin VCC and the ground pin GND of the voltage detector U1, which has the function of filtering out high-frequency interference to stabilize the voltage.

[0019] Optionally, a resistor R10 is connected in series between the common end of the emitter of the triode Q3 and the other end of the resistor R8, and the connection point between the cathode of the voltage stabilizer U2 and the base of the triode Q3;

[0020] A resistor R11 is connected in series between the collector of the triode Q3 and the common end of the negative pole of the super capacitor CF1 and the anode of the voltage stabilizer U2. The resistor R10 sets the static working point by providing a direct current bias current, which can prevent the triode from overheating or failing due to excessive current at the collector, and can also prevent the working point from drifting, stabilizing the working state.

[0021] The triode Q3 is a PNP triode.

[0022] Optionally, when the voltage detector U1 detects that the input voltage of its input pin VCC is less than its threshold voltage, its output pin outputs high impedance, the power supply VDD is divided by resistors R3 and R4 to the gate of MOS Q2, MOS Q2 is turned on, so that the power supply VDD is divided by resistors R1 and R2 to make the source voltage of MOS Q1 greater than the gate voltage, so that MOS Q1 is turned on, and the power supply VDD charges the super capacitor.

[0023] Optionally, when the voltage detector U1 detects that the input voltage of its input pin VCC is greater than or equal to its threshold voltage, the sum of the threshold voltage of the voltage detector U1 and the forward voltage drop of the diode D2 is the total rated voltage of the super capacitor.

[0024] The output pin of the voltage detector U1 outputs low level, so that MOS Q2 and MOS Q1 are turned off, and the power supply VDD stops charging the super capacitor.

[0025] Optionally, when the reference voltage of the voltage regulator U2 is less than its reference voltage, the cathode of the voltage regulator U2 is open, the transistor Q3 is turned off, and the super capacitor CF1 continues to charge to its rated working voltage.

[0026] When the reference voltage of the voltage regulator U2 is greater than or equal to its reference voltage, the cathode and anode of the voltage regulator U2 are turned on, and at this time the transistor Q3 is turned on, and the super capacitor CF1 discharges excess voltage to its rated working voltage.

[0027] Optionally, the MOS Q1 is a P-channel MOS, and the MOS Q2 is an N-channel MOS.

[0028] Optionally, when the number of super capacitors is 2, the super capacitor CF1 and the super capacitor CF2 are connected in series, the total rated voltage of the super capacitor is V1, the voltage across the super capacitor CF2 is V2, and the voltage across the super capacitor CF1 is V1-V2; at this time, the super capacitor CF1 and the super capacitor CF2 correspond to one self-balancing circuit respectively, and their circuit structures are the same;

[0029] During charging, the charging voltages of the super capacitor CF1 and the super capacitor CF2 are equal.

[0030] Among them, the reference voltage of the voltage regulator U2 is related to the voltage of the super capacitor CF1, which is obtained by dividing the resistors R8 and R9, and the reference voltage of the voltage regulator U2 is: [R9 / (R8+R9)]*(V1-V2), when there are two super capacitors, the reference voltage of the voltage regulator U3 in the CF2 self-balancing circuit is obtained by dividing the voltage of the two series resistors R12 and R13 in the voltage dividing circuit, which is represented as: [R13 / (R12+R13)]*V2.

[0031] The beneficial effects of this invention are as follows: This invention detects and controls the charging voltage of the supercapacitor through a charging voltage detection and control circuit, limiting the charging voltage within the rated voltage range of the supercapacitor and providing overcharge protection for the supercapacitor; the self-balancing circuit based on the voltage regulator realizes the self-balancing of the charging voltage of the supercapacitor cells, ensuring the charging safety of the supercapacitor. Attached Figure Description

[0032] Figure 1 A schematic diagram of a supercapacitor charging protection circuit for an intelligent fusion terminal provided in an embodiment of the present invention. Detailed Implementation

[0033] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations thereof. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0034] Example 1

[0035] This embodiment provides a supercapacitor charging protection circuit for an intelligent fusion terminal, including:

[0036] Power supply;

[0037] A charging voltage detection and control circuit, whose input terminal is connected to the power supply and whose output terminal is connected to at least one supercapacitor, is used for overcharge protection of the supercapacitor.

[0038] Each supercapacitor is equipped with a self-balancing circuit, which is connected between the charging voltage detection and control circuit and the ground terminal, and is used to control the charging and balance the voltage of the supercapacitor.

[0039] like Figure 1 As shown, the supercapacitor charging protection circuit of the intelligent fusion terminal provided in this embodiment includes two supercapacitors, namely supercapacitor CF1 and supercapacitor CF2, which are connected in series; at the same time, there are two corresponding self-balancing circuits.

[0040] Specifically, the charging voltage detection and control circuit includes:

[0041] The source of the P-channel MOSFET Q1 is connected to the power supply VDD, and the gate is pulled up to the power supply VDD through resistor R1 and connected to the drain of the N-channel MOSFET Q2 through resistor R2; the drain of the P-channel MOSFET Q1 is connected to the voltage detector U1 through Schottky diode D2.

[0042] A voltage detector U1, whose input pin VCC is connected to the negative pole of the Schottky diode D2, whose output pin is connected to the gate of the N-channel MOS Q2 and one end of the resistor R4 and is pulled up to the power supply VDD through the resistor R3, and whose ground pin GND is connected to the other end of the resistor R4 and is grounded, and the other end of the resistor R4 is connected to the source of the N-channel MOS Q2.

[0043] Among them, the drain of the P-channel MOS Q1 and the anode of the Schottky diode D2 are further provided with a Schottky diode D1 and parallel current-limiting resistors R4, R5 and R6 in sequence; the Schottky diode D1 is used to prevent the voltage on the super capacitor from being reversed and fed to the power supply VDD, and the current-limiting resistor is used to reduce the impact of the current on the super capacitor during the initial charging process.

[0044] The input pin VCC and the ground pin GND of the voltage detector U1 are connected in parallel with a filter capacitor C1, which is used to filter out high-frequency interference to stabilize the voltage.

[0045] The self-balancing circuit of the super capacitor CF1 comprises:

[0046] The PNP triode Q3, whose emitter is connected to the anode of the diode D2 and the anode of the super capacitor CF1, and whose collector is connected to the cathode of the super capacitor CF1;

[0047] The controllable precision voltage stabilizer U2, whose anode is connected to the collector of the triode Q3, and whose cathode is connected to the base of the triode Q3;

[0048] The first voltage dividing resistor network, which is connected between the emitter and the collector of the triode Q3, and whose midpoint is connected to the reference end of the voltage stabilizer U2, comprises resistors R8 and R9 connected in series;

[0049] The other end of the resistor R8 is connected to the emitter of the triode Q3, and the other end of the resistor R9 is connected to the collector of the triode Q3.

[0050] Among them, the common end of the emitter of the triode Q3 and the other end of the resistor R8 is connected in series with the resistor R10 between the cathode of the voltage stabilizer U2 and the connection point of the base of the triode Q3;

[0051] The collector of the triode Q3 is connected in series with the resistor R11 between the common end of the cathode of the super capacitor CF1 and the anode of the voltage stabilizer U2.

[0052] The self-balancing circuit of the super capacitor CF2 comprises:

[0053] The PNP triode Q4, whose emitter is connected to the anode of the super capacitor CF2, and whose collector is connected to the cathode of the super capacitor CF2 and is grounded.

[0054] A controllable precision voltage stabilizer U3, whose anode is connected to the collector of the transistor Q4, and whose cathode is connected to the base of the transistor Q4;

[0055] A second voltage dividing resistor network, connected between the emitter and the collector of the transistor Q4, with a point connected to the reference terminal of the voltage stabilizer U3, comprising a resistor R12 and a resistor R13 connected in series with each other;

[0056] The other end of the resistor R12 is connected to the emitter of the transistor Q4, and the other end of the resistor R13 is connected to the collector of the transistor Q4.

[0057] The common terminal of the emitter of the transistor Q4 and the other end of the resistor R12 is connected in series with the resistor R14 between the cathode of the voltage stabilizer U3 and the connection point of the base of the transistor Q4.

[0058] The collector of the transistor Q4 is connected in series with the resistor R15 between the common terminal of the negative electrode of the super capacitor CF2 and the anode of the voltage stabilizer U3.

[0059] When the voltage detector U1 detects that the input voltage of its input terminal VCC is less than its threshold voltage, its output terminal outputs high impedance, so that the MOS transistor Q2 and the MOS transistor Q1 are turned on, and the power supply VDD charges the super capacitor.

[0060] When the voltage detector U1 detects that the input voltage of its input terminal VCC is greater than or equal to its threshold voltage, the sum of the threshold voltage of the voltage detector U1 and the forward voltage drop of the diode D2 serves as the total rated voltage of the super capacitor; at this time, the output terminal of the voltage detector U1 outputs low level, so that the MOS transistor Q2 and the MOS transistor Q1 are turned off, and the power supply VDD stops charging the super capacitor.

[0061] During the charging process, the total rated voltage of the super capacitor is V1, the voltage across the super capacitor CF2 is V2, and the voltage across the super capacitor CF1 is V1-V2.

[0062] When the reference terminal voltage of the voltage stabilizer U2 is less than its reference voltage, the super capacitor CF1 continues to charge to its rated working voltage; when the reference terminal voltage of the voltage stabilizer U2 is greater than or equal to its reference voltage, the super capacitor CF1 discharges the excess voltage to its rated working voltage.

[0063] The reference terminal voltage of the voltage stabilizer U2 is related to the voltage of the super capacitor CF1, which is obtained by dividing the resistance R8 and R9, and the reference terminal voltage of the voltage stabilizer U2 is: [R9 / (R8+R9)]*(V1-V2).

[0064] When the reference terminal voltage of the voltage regulator U3 is less than its reference voltage, the supercapacitor CF2 continues to charge to its rated operating voltage; when the reference terminal voltage of the voltage regulator U3 is greater than or equal to its reference voltage, the supercapacitor CF2 discharges excess voltage to its rated operating voltage.

[0065] The reference voltage of regulator U3 is related to the voltage of supercapacitor CF2 and is obtained by voltage division by resistors R12 and R13. The reference voltage of regulator U3 is: [R13 / (R12+R13)]*V2.

[0066] Based on the above circuit, the following describes the operating status of the supercapacitor charging protection circuit in the intelligent fusion terminal under one working condition.

[0067] This embodiment uses voltage detector U1, model SGM892B-5V, with a threshold voltage of 5V; controllable precision voltage regulators U2 and U3, model CJ431K, with a reference voltage of 2.5V; supercapacitors CF1 and CF2 with specific parameters of 2.7V / 150F; Schottky diode with a forward voltage drop of 0.4V-0.5V; charging current controlled to a maximum of about 2A; resistors R8 and R10 with a resistance of 10KΩ; and resistors R9 and R13 with a resistance of 120KΩ.

[0068] During the supercapacitor charging process, when the total supercapacitor charging voltage V1 is 4V, the voltage across CF1 is V1-V2=2V, and the voltage across CF2 is V2=2V. At this time, the total supercapacitor charging voltage is less than 5V, and the voltage detector U1 outputs high impedance. The power supply is divided by resistors R3 and R4 to the gate of N-channel MOSFET Q2, and N-channel MOSFET Q2 is turned on. Thus, the power supply VDD is divided by resistors R1 and R2, making the source voltage of P-channel MOSFET Q1 greater than the gate voltage, and P-channel MOSFET Q1 is turned on. The power supply VDD charges supercapacitors CF1 and CF2 through P-channel MOSFET Q1, diode D1, and parallel resistors R5, R6, and R7.

[0069] At this time, the voltage across supercapacitors CF1 and CF2 is less than their rated voltage, and the reference voltage of voltage regulator U2 is approximately 1.85V, which is less than its reference voltage of 2.5V. The cathode of voltage regulator U2 is essentially open-circuited, and PNP transistor Q3 is cut off. Supercapacitor CF1 continues to charge to its rated operating voltage.

[0070] The reference voltage of regulator U3 is approximately 1.85V, which is less than its reference voltage of 2.5V. Therefore, the cathode of regulator U3 is essentially open, the PNP transistor Q4 is cut off, and the supercapacitor CF2 continues to charge to its rated operating voltage.

[0071] Example 2

[0072] This embodiment adopts the same concept as Embodiment 1. This embodiment provides a second operating condition to specifically introduce the operating status of the supercapacitor charging protection circuit of the intelligent fusion terminal.

[0073] When the total supercapacitor charging voltage V1 is 5.5V, the voltage across CF1 is V1-V2=2.75V, and the voltage across CF2 is V2=2.75V, if the forward voltage drop of diode D2 is 0.45V, then the voltage at the input of voltage detector U1 is 5.05V, which is greater than its threshold. At this time, voltage detector U1 outputs a low level, and the gate of N-channel MOSFET Q2 is also low, causing N-channel MOSFET Q2 to be cut off. Thus, the source voltage of P-channel MOSFET Q1 equals its gate voltage, and P-channel MOSFET Q1 is also cut off. Therefore, the power supply VDD can no longer charge the supercapacitor, and the total voltage V1 across the supercapacitor will not rise further, protecting the supercapacitor's safety.

[0074] At this time, the reference terminal voltage of regulator U2 [R9 / (R8+R9)]*(V1-V2) is approximately 2.54V, which is greater than its reference voltage of 2.5V. Its cathode and anode are conducting, and PNP transistor Q3 is turned on, discharging excess voltage from supercapacitor CF1 down to its rated operating voltage of 2.7V, thus maintaining voltage balance on supercapacitor CF1.

[0075] The reference voltage of regulator U3 is [R13 / (R12+R13)]*V2, which is approximately 2.54V, greater than its reference voltage of 2.5V. Its cathode and anode are conducting, and at this time, transistor Q4 is conducting, discharging the excess voltage on supercapacitor CF2 until its rated operating voltage of 2.7V is reached, so that the voltage on supercapacitor CF2 is kept balanced.

[0076] Through the above embodiments, the present invention detects and controls the charging voltage of the supercapacitor through a charging voltage detection and control circuit, limiting the charging voltage within the rated voltage range of the supercapacitor and providing overcharge protection for the supercapacitor; the self-balancing circuit based on the voltage regulator realizes the self-balancing of the charging voltage of the supercapacitor cells, ensuring the charging safety of the supercapacitor.

[0077] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A super capacitor charging protection circuit for a smart converged terminal, characterized in that, include: Power supply; A charging voltage detection and control circuit, whose input terminal is connected to the power supply and whose output terminal is connected to at least one supercapacitor, is used for overcharge protection of the supercapacitor. Each supercapacitor is equipped with a self-balancing circuit, which is connected between the charging voltage detection and control circuit and the ground terminal, and is used to control the charging and balance the voltage of the supercapacitor.

2. The intelligent converged terminal supercapacitor charging protection circuit of claim 1, wherein, The charging voltage detection and control circuit includes: The source of MOSFET Q1 is connected to the power supply VDD, and the gate is pulled up to the power supply VDD through resistor R1 and connected to the drain of MOSFET Q2 through resistor R2; the drain of MOSFET Q1 is connected to voltage detector U1 through diode D2. The voltage detector U1 has its input pin VCC connected to the negative terminal of diode D2, its output pin connected to the gate of MOSFET Q2 and one end of resistor R4, and pulled up to the power supply VDD through resistor R3. Its ground pin GND is connected to the other end of resistor R4 and grounded. The other end of resistor R4 is connected to the source of MOSFET Q2.

3. The intelligent converged terminal supercapacitor charge protection circuit of claim 2, wherein, The self-balancing circuit includes: Transistor Q3 has its emitter connected to the positive terminal of diode D2 and the positive terminal of supercapacitor CF1, and its collector connected to the negative terminal of supercapacitor CF1. The voltage regulator U2 has its anode connected to the collector of transistor Q3 and its cathode connected to the base of transistor Q3. A voltage divider resistor network is connected between the emitter and collector of transistor Q3, with its midpoint connected to the reference terminal of regulator U2. It includes resistors R8 and R9 connected in series. The other end of resistor R8 is connected to the emitter of transistor Q3, and the other end of resistor R9 is connected to the collector of transistor Q3.

4. The intelligent converged terminal supercapacitor charge protection circuit of claim 3, wherein, Between the drain of the MOS transistor Q1 and the anode of the diode D2, there is also a diode D1 and one or more parallel current-limiting resistors connected in sequence. A filter capacitor C1 is connected in parallel between the input pin VCC and the ground pin GND of the voltage detector U1.

5. The intelligent converged terminal supercapacitor charge protection circuit of claim 4, wherein, The common terminal of the emitter of the transistor Q3 and the other end of the resistor R8 is connected in series with a resistor R10 between the connection point of the cathode of the voltage regulator U2 and the base of the transistor Q3. A resistor R11 is connected in series between the collector of transistor Q3, the negative terminal of supercapacitor CF1, and the common terminal of the anode of voltage regulator U2.

6. The intelligent converged terminal supercapacitor charge protection circuit of claim 5, wherein, When the voltage detector U1 detects that the input voltage of its input pin VCC is less than its threshold voltage, its output pin outputs a high impedance, causing MOSFETs Q2 and Q1 to conduct, and the power supply VDD charges the supercapacitor.

7. The intelligent converged terminal supercapacitor charge protection circuit of claim 6, wherein, When voltage detector U1 detects that the input voltage of its input pin VCC is greater than or equal to its threshold voltage, the sum of the threshold voltage of voltage detector U1 and the forward voltage drop of diode D2 is used as the total rated voltage of the supercapacitor. The voltage detector U1 outputs a low level, which turns off MOSFETs Q2 and Q1, and stops the power supply VDD from charging the supercapacitor.

8. The intelligent converged terminal supercapacitor charge protection circuit of claim 7, wherein, When the reference terminal voltage of the voltage regulator U2 is less than its reference voltage, the supercapacitor CF1 continues to charge to its rated operating voltage; When the voltage at the reference terminal of the voltage regulator U2 is greater than or equal to its reference voltage, the supercapacitor CF1 discharges excess voltage to its rated operating voltage.

9. The intelligent converged terminal supercapacitor charge protection circuit of claim 8, wherein, The MOS tube Q1 is a P-channel MOS tube, and the MOS tube Q2 is an N-channel MOS tube.

10. The intelligent converged terminal supercapacitor charge protection circuit of claim 9, wherein, When the number of super capacitors is 2, the super capacitor CF1 and the super capacitor CF2 are connected in series, the total rated voltage of the super capacitors is V1, the voltage across the super capacitor CF2 is V2, and the voltage across the super capacitor CF1 is V1-V2. The charging voltages of the super capacitor CF1 and the super capacitor CF2 are equal.

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