Low voltage ripple auto-pulse frequency hopping mode control

Abstract

A low voltage ripple auto-pulse hopping mode control is disclosed in which a voltage converter automatically and dynamically adjusts an on-time of a drive signal for driving a switching circuit such that charge and discharge cycles of an inductor are optimized. The voltage converter includes a pulse hopping modulation (PSM) control circuit duty cycle generator, a switch drive circuit, and a switch circuit. The PSM control circuit is configured to generate a hopping signal based on the drive signal and the frequency signal to dynamically and automatically adjust an on-time of the drive signal.

Description

Technical Field

[0001] This invention relates to a voltage converter, and more specifically, to a voltage converter with low-voltage ripple automatic pulse skipping mode control. Background Technology

[0002] Power supplies and voltage converters are used in a variety of electronic systems. Electricity is typically transmitted over long distances in the form of alternating current (AC) signals. Modern electronic systems often employ devices or components designed to operate using different DC voltages.

[0003] Pulse Skipping Modulation (PSM) is a technique used in voltage converters, particularly under light load conditions, to improve efficiency by reducing switching losses. PSM operates by selectively skipping pulses in the switching waveform, reducing the number of times the power switch turns on and off. Traditionally, voltage converters include PSM control logic to determine when to enter PSM mode. The PSM control logic compares a control voltage corresponding to the output voltage feedback with a fixed threshold voltage. When the control voltage is less than the threshold voltage, the PSM control logic outputs a skip signal to the switch driver to enable PSM mode. However, switching frequencies vary dynamically, and the fixed threshold voltage cannot adapt to frequent changes in the switching frequency. Therefore, the output voltage may have a larger output voltage ripple. Furthermore, the variation in the control voltage may be small. When the difference between the control voltage and the fixed threshold voltage is small, the PSM control logic becomes more susceptible to electrical noise. This electrical noise can generate double pulses, resulting in output voltage ripple. Summary of the Invention

[0004] This invention addresses pulse skip modulation (PSM) control, which reduces switching losses and output voltage ripple by dynamically and automatically adjusting the skip signal that enables the voltage converter's PSM mode.

[0005] In one embodiment of the present invention, a voltage converter includes a duty cycle generator, a switch drive circuit, a switch circuit, and a pulse control circuit. The duty cycle generator is coupled to a frequency signal and a feedback voltage, and generates a duty cycle signal based on the frequency signal and the feedback voltage. The switch drive circuit is coupled to the duty cycle generator and generates a drive signal based on the duty cycle signal and a jump signal. The switch circuit is coupled to the switch drive circuit, an input voltage, and a ground voltage, and generates a switching node voltage provided to an inductor based on the drive signal, wherein the switching node voltage alternates between the input voltage and the ground voltage. The pulse control circuit is coupled to the switch drive circuit and the frequency signal, generates the jump signal based on the frequency signal and the drive signal, and outputs the jump signal to the switch drive circuit to adjust the on-time of the drive signal.

[0006] In one embodiment, the pulse control circuit is configured to adjust the charging and discharging cycles of the inductor within a frequency period by adjusting the jump signal.

[0007] In one embodiment, the pulse control circuit is configured to adjust the number of pulses in the jump signal based on the voltage level of the drive signal at the frequency signal transition.

[0008] In one embodiment, when the pulse control circuit determines that the drive signal is at an inactive voltage level at the rising edge of the frequency signal, the pulse control circuit extends the on-time of the drive signal used to drive the switching circuit by increasing the pulse jump modulation voltage.

[0009] In one embodiment, the pulse control circuit includes an on-time modulator. The on-time modulator includes multiple current sources, a PSM adjustment circuit, a counter, and a comparator. The multiple current sources are coupled in parallel between a voltage source and the ground voltage and are used to output a PSM voltage. The PSM adjustment circuit receives the frequency signal and the drive signal and outputs up / down signals based on the voltage level of the drive signal relative to the frequency signal. The counter is coupled between the PSM adjustment circuit and the multiple current sources and enables a number of the multiple current sources based on the up / down signals. The comparator is connected to the multiple current sources to receive the PSM voltage and generates the jump signal based on the feedback voltage of the PSM voltage.

[0010] In one embodiment, the comparator compares the PSM voltage with a control voltage corresponding to the feedback voltage, wherein the control voltage is generated by comparing the feedback voltage with a predetermined reference voltage.

[0011] In one embodiment, when the PSM voltage is greater than the control voltage, the pulse control circuit starts to output the jump signal.

[0012] In one embodiment, the pulse control circuit further includes a noise margin generator. The noise margin generator is coupled between the on-time modulator and the comparator. The noise margin generator includes an amplifier, a voltage source, a first switch, and a second switch. The amplifier has a first interface, a second interface, and an output interface coupled to the first interface. The voltage source has a predetermined boundary voltage and is coupled between the second interface of the amplifier and the current source of the on-time modulator. The first switch is coupled between the output interface of the amplifier and the second interface of the comparator and has a control interface coupled to the drive signal or the duty cycle signal. The second switch is coupled between the current source of the on-time modulator and the second interface of the comparator and has a control interface coupled to the inverted drive signal or the inverted duty cycle signal.

[0013] One embodiment of the invention includes a voltage converter for receiving an input voltage and generating an output voltage. The voltage converter includes an output inductor, a switching circuit, a switch driver circuit, and a pulse skip mode (PSM) control circuit. The output inductor has a first interface and a second interface and is charged and discharged according to the input voltage. The switching circuit is coupled to the input voltage, the first interface of the output inductor, and a ground voltage, and is configured to switch between a first state and a second state, wherein in the first state the switching circuit couples the input voltage to the output inductor to charge the output inductor, and in the second state the switching circuit couples the output inductor to the ground voltage to discharge the output inductor. The switch driver circuit is configured to output a drive signal to control the switching circuit to switch between the first state and the second state according to a duty cycle signal and a skip signal. The pulse skip mode control circuit is coupled to the second interface of the output inductor and is configured to dynamically generate the skip signal according to a feedback voltage and frequency signal corresponding to the output voltage.

[0014] In one embodiment, the PSM control circuit includes a comparator having a first interface, a second interface, and an output interface, wherein the first interface is coupled to the feedback voltage corresponding to the output voltage, the second interface is coupled to an error amplifier, and the output interface is coupled to the switch drive circuit.

[0015] In one embodiment, the PSM control circuit further includes a PSM adjustment circuit, a plurality of current sources, and an up / down counter. The PSM adjustment circuit receives the frequency signal and the drive signal, and outputs up / down signals according to the frequency signal and the drive signal. The current sources are coupled in parallel between each other between a first source voltage and a second source voltage, and output a PSM voltage according to the number of current sources that are enabled. The up / down counter is coupled to the PSM adjustment circuit and the plurality of current sources, and is configured to enable the number of current sources according to the up / down signals received from the PSM adjustment circuit. In this embodiment, the PSM voltage is coupled to the second interface of the comparator.

[0016] In one embodiment, the PSM control circuit further includes a PSM adjustment circuit, a current source, an amplifier, a voltage source, a first switch, and a second switch. The PSM adjustment circuit is coupled to the frequency signal and the switch drive circuit to receive the drive signal and output an enable signal based on the frequency signal and the drive signal. The current source is used to output a PSM voltage according to the enable signal. The amplifier has a first interface, a second interface, and an output interface coupled to the first interface. The voltage source has a predetermined voltage. The voltage source is coupled between the second interface of the amplifier and the PSM voltage. The first switch is coupled between the output interface of the amplifier and the second interface of the comparator and has a control interface coupled to a duty cycle signal. The second switch is coupled between the current source and the second interface of the comparator. The second switch has a control interface coupled to an inverted duty cycle signal.

[0017] In one embodiment, the voltage converter further includes a duty cycle generator. The duty cycle generator is coupled to the second interface of the frequency signal and the output inductor to receive the feedback voltage. The duty cycle generator is configured to generate the duty cycle signal based on the frequency signal and the feedback voltage, and output the duty cycle signal to the switch drive circuit.

[0018] To make the above features and advantages of the present invention more readily understood, several embodiments accompanied by the accompanying drawings are described in detail below.

[0019] However, it should be understood that this abstract may not contain all aspects and embodiments of the invention, is not intended to limit or constrain in any way, and the invention disclosed herein is to be understood by one of ordinary skill in the art and will contain obvious improvements and modifications thereof. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating a voltage converter, one embodiment of the present invention;

[0021] Figures 2A-2BThis is one embodiment of the present invention illustrating a timing diagram of adjusting the charging and discharging cycle of an inductor based on a drive signal about a frequency signal;

[0022] Figure 3A This is a schematic diagram illustrating a voltage converter, one embodiment of the present invention;

[0023] Figure 3B This is a schematic diagram illustrating a voltage converter, one embodiment of the present invention;

[0024] Figure 4A This is a schematic diagram illustrating a voltage converter, one embodiment of the present invention;

[0025] Figure 4B This is a schematic diagram illustrating a voltage converter, one embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram illustrating one embodiment of the present invention, showing an on-time modulator;

[0027] Figure 6 This is a timing diagram illustrating the PSM voltage VPSM adjustment according to one embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram illustrating the PSM control circuit of one embodiment of the present invention;

[0029] Figure 8 This is a timing diagram illustrating the operation of a noise tolerance generator, one embodiment of the present invention.

[0030] Symbol explanation:

[0031] 11: Inductor

[0032] 12: Frequency Oscillator

[0033] 13: Output voltage feedback circuit

[0034] 15. 7157: Capacitor

[0035] 100, 300, 300B, 400, 400B: Converters

[0036] 110: Pulse control circuit

[0037] 120: Work Cycle Generator

[0038] 130: Switch drive circuit

[0039] 140: Switching circuit

[0040] 300: Voltage Converter

[0041] 310, 311, 410, 411: PSM control circuit

[0042] 313, 413, 513: On-time modulators

[0043] 315, 415, 715: Noise tolerance generator

[0044] 317, 417: Comparators

[0045] 319, 7155: Inverters

[0046] 320: Work Cycle Generator

[0047] 321: Adder

[0048] 323: Error Amplifier

[0049] 325 comparator

[0050] 327: Latch

[0051] 513: On-time modulator

[0052] 601, 801: First curve

[0053] 602, 802: Second curve

[0054] 711: PSM control circuit

[0055] 5131: PSM Adjustment Circuit

[0056] 5133: Up / Down Counter

[0057] 5135: Current Source

[0058] 5137: Resistor

[0059] 7151: Amplifier

[0060] 7153: Voltage Source

[0061] CLK: Frequency signal

[0062] DN: Lower count value

[0063] DRV, PDRV, NDRV: Drive signals

[0064] DUTY: Working cycle signal

[0065] IL: Inductor current

[0066] SKIP: Skip signal

[0067] SW1: First switch

[0068] SW2: Second switch

[0069] UP: Up count value

[0070] VEA: Control Voltage

[0071] VFB: Feedback Voltage

[0072] VPSM, VPSM1, VPSM2: PSM voltage

[0073] Vbias: Bias voltage

[0074] Vg: Grounding voltage

[0075] Vin: Input voltage

[0076] Vout: Output voltage

[0077] Vref: Reference voltage

[0078] VRamp: ramp voltage

[0079] Vs: Source voltage

[0080] Vsense: Sensing voltage

[0081] Vsw: Switching node voltage Detailed Implementation

[0082] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0083] Embodiments of the present invention may include any one or more novel features described herein, including in the detailed description and / or shown in the accompanying drawings. As used herein, “at least one,” “one or more,” and “and / or” are open-ended expressions that are both connective and disjoint in operation. For example, each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” and “A, B, and / or C” means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0084] It should be noted that the term "a" or "an" refers to one or more of the entities in question. Therefore, the terms "a" (or "an"), "one or more", and "at least one" are used interchangeably in this document.

[0085] Figure 1This is a schematic diagram illustrating a voltage converter 100 according to one embodiment of the present invention. The voltage converter 100 includes a pulse skipping modulation (PSM) control circuit 110, a duty cycle generator 120, a switch drive circuit 130, and a switching circuit 140. The voltage converter 100 receives an input voltage Vin and generates a switching node voltage Vsw. The voltage converter 100 is coupled to an inductor 11 to generate an output voltage Vout based on the switching node voltage Vsw. At the output of the inductor 11, the inductor 11 is coupled to an output voltage feedback circuit 13 and a capacitor 15. In this invention, the voltage converter 100 may also be referred to as a power converter or a DC-DC converter.

[0086] The pulse control circuit 110 does not generate a jump signal to enable PSM mode based on a fixed threshold voltage. Instead, it dynamically and automatically generates the jump signal based on the occurrence and / or on-time (pulse width) of the drive signal DRV relative to the frequency signal CLK. In conventional technology, a fixed threshold voltage is compared with a control voltage representing the output voltage of a conventional voltage converter. Because the switching components of a conventional voltage converter switch according to a frequency signal, the inductor may not have enough time to charge or discharge when PSM mode is enabled based on the jump signal generated by the fixed threshold voltage. Therefore, conventional voltage converters suffer from switching losses, output voltage ripple, electrical noise, and other problems. In contrast, the voltage converter 100 of this embodiment optimizes the charging and discharging cycle of the output stage inductor by adjusting the jump signal. Details of the pulse control circuit 110 will be described later.

[0087] The duty cycle generator 120 is coupled to a frequency signal CLK generated by a frequency oscillator (OSC) 12 and a feedback voltage VFB generated by an output voltage feedback circuit 13. Based on the frequency signal CLK and the feedback voltage VFB, the duty cycle generator 120 generates a duty cycle signal DUTY. The duty cycle generator 120 outputs the duty cycle signal DUTY to the switch drive circuit 130.

[0088] The switch drive circuit 130 is coupled to the pulse control circuit 110 and the duty cycle generator 120. Based on the duty cycle signal DUTY and the jump signal SKIP, the switch drive circuit 130 generates a drive signal DRV for driving the switch circuit 140.

[0089] Switching circuit 140 is coupled to switching drive circuit 130, input voltage Vin, and ground voltage Vg. In an embodiment, switching circuit 140 includes a pair of N-channel MOSFETs (NMOS) and P-channel MOSFETs (PMOS) coupled in series between input voltage Vin and ground voltage Vg. Switching drive circuit 130 is controlled by a drive signal DRV output by switching drive circuit 130 and outputs a switching node voltage Vsw. Switching node voltage Vsw alternates between input voltage Vin and ground voltage Vg. Switching node voltage Vsw is provided to inductor 11 for charging and discharging inductor 11, wherein inductor 11 is coupled to output voltage feedback circuit 13 and output capacitor 14. In an embodiment, output voltage feedback circuit 13 may include a voltage divider having two resistors coupled between output voltage Vout and ground voltage Vg to obtain a feedback voltage VFB reflecting output voltage Vout.

[0090] A pulse control circuit 110 is coupled to a frequency signal CLK and a switch drive circuit 130. In one embodiment, the pulse control circuit 110 generates a skip signal SKIP based on the frequency signal CLK and a drive signal DRV. The skip signal SKIP is then output to the switch drive circuit 130 to adjust the on-time of the drive signal DRV. In one embodiment, the pulse control circuit 110 determines the voltage level of the drive signal DRV at the rising edge of the frequency signal CLK. Based on the voltage level of the drive signal DRV at the rising edge of the frequency signal CLK, the pulse control circuit 110 adjusts the occurrence of the skip signal SKIP to adjust the on-time of the drive signal DRV. Adjusting the drive signal DRV may include changing the timing of the skip signal SKIP with respect to the frequency signal CLK. Adjusting the number of occurrences of the skip signal SKIP may also be referred to as adjusting the pulse occurrence (i.e., the frequency of pulse occurrence) within the skip signal. In other embodiments, adjusting the drive signal DRV includes lengthening or shortening the pulse width or on-time of the skip signal SKIP to lengthen or shorten the on-time of the drive signal DRV. It should be noted that these embodiments can also be combined, wherein both the appearance and conduction time of the SKIP signal can be used to adjust the drive signal DRV.

[0091] Figures 2A-2B This is a timing diagram illustrating the adjustment of the charging and discharging cycles of inductor 11 based on a drive signal DRV relative to a frequency signal CLK, according to one embodiment of the present invention. The pulse control circuit 110 monitors the voltage level of the drive signal DRV at the rising edge of the frequency signal CLK. (Refer to...) Figure 2AIf the drive signal DRV is at a voltage level indicating logic low at the rising edge of the frequency signal CLK, then the on-time of the drive signal DRV is too short. In this case, the on-time of the drive signal DRV should be extended to optimize the charging and discharging cycles of inductor 11. (Refer to...) Figure 2B If the drive signal DRV is at a voltage level representing a logic high at the rising edge of the frequency signal CLK, then the on-time of the drive signal DRV is too long. In this case, the on-time of the drive signal DRV should be shortened to optimize the charging and discharging cycles of inductor 11. Note that energy can be represented by the area of ​​the triangular waveform of the inductor current IL flowing through inductor 11. When the on-time of the drive signal DRV with respect to the frequency signal CLK is too short, such as... Figure 2A The area of ​​the triangular waveform shown is smaller than that shown. Figure 2B The area of ​​the triangular waveform shown is an example. That is, when the drive signal DRV is not activated at the optimal start time or the on-time of the drive signal DRV is not optimized, the inductor 11 is not fully charged and discharged within the switching cycle of the switching circuit 140. Therefore, the switching circuit 140 may switch frequently, resulting in switching losses and output voltage ripple. Embodiments of the present invention optimize the charging and discharging cycle of the inductor 11 so that the charging and discharging cycle of the inductor 11 occurs within one frequency cycle. That is, the pulse control circuit 110 adjusts the appearance and / or on-time of the jump signal SKIP to adjust the appearance and on-time of the drive signal DRV that controls the operating timing of the switching circuit 140.

[0092] Figure 3A This is a schematic diagram illustrating a voltage converter 300 according to one embodiment of the present invention. The voltage converter 300 includes a PSM control circuit 310, a duty cycle generator 320, a switch drive circuit 130, and a switch circuit 140. Similar to... Figure 1 The voltage converter 100 shown receives the input voltage Vin and generates a switching node voltage Vsw. Voltage converter 300 is coupled to inductor 11 to generate an output voltage Vout based on the switching node voltage Vsw. Unlike voltage converter 100, the drive signal DRV includes a first drive signal and a second drive signal, where the first drive signal can be referred to as the NMOS drive signal NDRV, and the second drive signal can be referred to as the PMOS drive signal PDRV. The PMOS drive signal PDRV and the NMOS drive signal NDRV control the PMOS transistor and NMOS transistor of the switching circuit 140, respectively.

[0093] In addition, the PSM control circuit 310 and Figure 1The PSM control circuit 110 shown is different. The PSM control circuit 310 includes a PSM control circuit 311, a comparator 317, and an inverter 319. The PSM control circuit 311 receives a frequency signal CLK, an inverted PMOS drive signal PDRV, and an NMOS drive signal NDRV, and outputs a PSM voltage VPSM based on these signals. The inverted PMOS drive signal PDRV is generated by the inverter 319, which is coupled to the PMOS drive signal output from the switch drive circuit 130. The comparator 317 includes a first interface coupled to the output interface of the PSM control circuit 311 for receiving the PSM voltage VPSM, and a second interface coupled to the duty cycle generator 320 for receiving the control voltage VEA. The comparator 317 generates a jump signal SKIP based on the control voltage VEA and the PSM voltage VPSM. As described above, conventional techniques generate the jump signal SKIP based on the control voltage VEA corresponding to the feedback voltage VFB and a fixed threshold voltage. In this embodiment, the SKIP signal is generated based on the control voltage VEA and the PSM voltage VPSM. The PSM voltage VPSM is dynamically generated based on the drive signals NDRV, PDRV, and the frequency signal.

[0094] Reference Figure 3A The PSM control circuit 311 includes an on-time modulator 313 and a noise boundary generator 315, configured to dynamically adjust the on-time of drive signals NDRV and PDRV based on a skip signal SKIP generated by the PSM voltage VPSM. In this embodiment, as... Figures 2A-2B The PSM voltage VPSM is generated based on the drive signals NDRV and PDRV relative to the frequency signal via the on-time modulator 313 and / or noise boundary generator 315. Figures 2A-2B As described above, the on-time modulator 313 and the noise boundary generator 315 can be used independently or in combination to adjust the occurrence and pulse width of the skip signal SKIP. Details of the on-time modulator 313 and the noise boundary generator 315 will be described later.

[0095] Reference Figure 3AThe duty cycle generator 320 includes an adder 321, an error amplifier 323, a comparator 325, and a latch 327. The adder 321 receives a frequency signal CLK and a sensed voltage Vsense, where the sensed voltage Vsense represents the inductor current IL. The adder 321 outputs a ramp voltage VRamp based on the frequency signal CLK and the sensed voltage Vsense. The error amplifier 323 receives a reference voltage Vref and a feedback voltage VFB, where the feedback voltage VFB represents the output voltage Vout of the voltage converter 300. The error amplifier 323 outputs a control voltage VEA. The comparator 325 receives the ramp voltage VRamp and the control voltage VEA. The latch 327 outputs a duty cycle signal DUTY based on the frequency signal CLK and the comparison result of the ramp voltage VRamp and the control voltage VEA. For example, the latch 327 may output a logic high level until the comparator 325 detects that the ramp voltage VRamp is greater than the control voltage VEA. It should be noted that the architecture of the duty cycle generator 320 is only an example. The invention is not intended to be limited thereto. Various architectures used in the technology to generate the duty cycle signal DUTY should still be considered to fall within the scope of this invention.

[0096] The switch drive circuit 130 receives the duty cycle signal DUTY generated by the duty cycle generator 320 and the jump signal SKIP generated by the pulse control circuit 310. Based on the duty cycle signal DUTY and the jump signal SKIP, the switch drive circuit 130 generates switch drive signals PDRV and NDRV for driving the switch circuit 140, wherein the switch circuit 140 generates a switch node voltage Vsw that alternates between the input voltage Vin and the ground voltage Vg.

[0097] It should be noted that Figure 3A The voltage converter 300 is illustrated as a buck converter; however, the adjustment of the drive signal also applies to voltage converters configured as boost converters. Figure 3B This is a schematic diagram illustrating a voltage converter 300B according to one embodiment of the present invention. In the configuration of the boost converter, the PSM control circuit 311 generates the PSM voltage VPSM based on the frequency signal CLK, the PMOS drive signal PDRV, and / or the inverted NMOS drive signal NDRV. Figure 3A In the circuit, inverter 319 is coupled between PSM control circuit 311 and PMOS drive signal PDRV. On the other hand, in... Figure 3B In the circuit, inverter 319 is coupled between PSM control circuit 311 and NMOS drive signal NDRV. Figure 3B The operation of the voltage converter 300B as described in the instructions should be consistent with... Figure 3A The operation of the voltage converter 300 described herein is similar, therefore its details are omitted here.

[0098] Figure 4A This is a schematic diagram of a voltage converter 400 according to one embodiment of the present invention. The voltage converter 400 includes a PSM control circuit 410, a duty cycle generator 320, a switch drive circuit 130, and a switch circuit 140. In this embodiment, the duty cycle generator 320, the switch drive circuit 130, and the switch circuit 140 are similar to those in the above embodiment; therefore, for the sake of simplicity, their details are omitted here.

[0099] Reference Figure 4A The PSM control circuit 410 is coupled to the duty cycle generator 320 to receive the duty cycle signal DUTY. Figure 3A Unlike the embodiment described herein, the PSM control circuit 410 is coupled to the duty cycle signal DUTY, rather than as described above. Figure 3A The inverted PMOS drive signal PDRV is described in the embodiment. That is, the PSM voltage VPSM can be adjusted by the duty cycle signal DUTY generated by the duty cycle generator 320, rather than... Figure 3A The inverted PMOS drive signal PDRV.

[0100] It should be noted that Figure 4A The voltage converter 400 is illustrated as a buck converter; however, the adjustment of the drive signal also applies to voltage converters configured as boost converters. Figure 4B This is a schematic diagram of a voltage converter 400B according to one embodiment of the present invention. Figure 4B The operation of the voltage converter 400B as described in the instructions should be consistent with... Figure 4A The operation of the voltage converter 400 described herein is similar, therefore its details are omitted here.

[0101] Figure 5 This is a schematic diagram of an on-time modulator 513 according to one embodiment of the present invention. The on-time modulator 513 can be applied to the pulse control circuit 110, on-time modulator 313, or on-time modulator 413 described above. In an embodiment, the on-time modulator 513 includes a PSM adjustment circuit 5131, an up / down counter 5133, a plurality of current sources 5135, and a resistor 5137.

[0102] The PSM adjustment circuit 5131 is coupled to an up / down counter 5133. The up / down counter 5133 is coupled to multiple current sources 5135 to enable or disable the number of current sources 5135. The multiple current sources 5135 are coupled to a bias voltage Vbias. The multiple current sources 5135 are coupled between the source voltage Vs and the ground voltage Vg, and output a voltage as the PSM voltage VPSM based on the number of current sources 5135 enabled by the up / down counter 5133. A resistor 5137 is coupled between the multiple current sources 5135 and the ground voltage Vg.

[0103] In this embodiment, the PSM adjustment circuit 5131 receives the frequency signal CLK and the drive signal DRV. For example... Figures 2A-2B As described, the PSM adjustment circuit 5131 adjusts the drive signal DRV according to the transition of the frequency signal CLK. The PSM adjustment circuit 5131 outputs an upper count value UP or a lower count value DN to the upper and lower counters 5133 to adjust the number of current sources 5135, thereby adjusting the PSM voltage VPSM. In this embodiment, the drive signal DRV is compared with the rising edge of the frequency signal CLK. However, the invention is not limited to this; the comparison can be performed based on the falling edge of the frequency signal CLK.

[0104] Figure 6 A timing diagram illustrating PSM voltage VPSM adjustment is provided to illustrate one embodiment of the present invention. Figure 6 In the diagram, the first curve 601 represents the control voltage VEA, and the second curve 602 represents the PSM voltage VPSM.

[0105] Between time t0 and time t1, the inductor charging and discharging cycle, represented by the inductor current IL, is shorter than the frequency period. Therefore, in each frequency period between time t0 and time t1, the output energy (e.g., the area of ​​the triangular waveform of the inductor current IL) is very small. (Reference) Figure 2A , Figure 5 and Figure 6 Between time t0 and time t1, the drive signal DRV is off with respect to the rising edge of the frequency signal. Therefore, the PSM adjustment circuit 5131 outputs an up count value (i.e., UP = 1) to the up and down counters 5133 until the drive signal DRV is on with respect to the rising edge of the frequency signal CLK. Figure 2B When the count value equals 1, the second curve 602 increases. In other words, the PSM voltage VPSM increases due to the activation of a larger number of current sources 5135.

[0106] At time t1, the PSM voltage VPSM becomes greater than the control voltage VEA, and the SKIP signal is activated. (Reference) Figures 3A-3B Or 4A~ Figure 4BComparators 317 and 417 output a skip signal SKIP based on the control voltage VEA and the PSM voltage VPSM. Between time t1 and time t2, the control voltage VEA increases with the PSM voltage VPSM, which increases the on-time of the drive signal DRV (NDRV or PDRV) generated by the switch drive circuit 130. The drive signal DRV controls the switching cycle of the switch circuit 140, which changes the amount of time the switching node voltage Vsw is supplied to the inductor 11. Therefore, the charging and discharging cycle of the inductor 11 is adjusted. During the adjustment period between time t1 and time t2, the occurrence of the skip signal SKIP, the pulse width of the skip signal SKIP, or the number of pulses within the skip signal is adjusted by the adjustment of the drive signal DRV (NDRV or PDRV).

[0107] At time t2, the charging and discharging cycles of inductor 11 fall within one frequency cycle. The PSM adjustment circuit 5131 outputs a down count value (e.g., DN = 1, UP = 0) to reduce the number of activated current sources 5135. Thus, the charging and discharging of inductor 11 is optimized, with the triangular waveform area of ​​the inductor current IL being optimized. In one embodiment, after time t2, the PSM adjustment circuit 5131 alternately outputs up and down count values ​​to maintain the optimized charging and discharging of inductor 11. However, the invention is not limited thereto. In other embodiments, the PSM adjustment circuit 5131 may output zero for both the up and down count values, so that the number of current sources remains the same.

[0108] Figure 7 This is a schematic diagram of a PSM control circuit 711 according to one embodiment of the present invention. The PSM control circuit 711 can be applied to the pulse control circuit 110, PSM control circuit 311, and PSM control circuit 411 described above. In an embodiment, the PSM control circuit 711 further includes a noise margin generator 715 connected to the on-time modulator 513 to fine-tune the PSM voltage VPSM. In an embodiment, the PSM voltage VPSM may include a first PSM voltage VPSM1 and a second PSM voltage VPSM2. The first PSM voltage VPSM1 represents the output of the on-time modulator 513, and the second PSM voltage VPSM2 represents the output of the noise margin generator 715. The noise margin generator 715 is configured to apply a boundary voltage Vmargin having the same phase as the inductor current IL to the first PSM voltage VPSM1 to increase noise margin and reduce the comparator delay time of the pulse control circuit.

[0109] The noise margin generator 715 includes an amplifier 7151, a voltage source 7153, an inverter 7155, a capacitor 7157, and a first switch SW1 and a second switch SW2. The amplifier 7151 includes a first interface coupled to the output interface of the amplifier 7151 and a second interface coupled to the first interface of the voltage source 7153. The voltage source 7153 includes a second interface coupled to a current source 5135 of the on-time modulator 513 and the first interface of the amplifier 7151. The second switch SW2 includes a first interface coupled to the current source 5135, a second interface coupled to a junction node, and a control interface coupled to a drive signal DRV or a duty cycle signal DUTY via the inverter 7155. The first switch SW1 has a first interface coupled to the output interface of the amplifier 7151, a second interface coupled to the junction node, and a control interface coupled to the drive signal DRV or the duty cycle signal DUTY. The capacitor 7157 is coupled between the junction node and the ground voltage Vg. The voltage at the junction node is the output of the noise margin generator 715, which will be the PSM voltage VPSM coupled to comparators 317 and 417.

[0110] Figure 8 A timing diagram illustrating the operation of the noise tolerance generator 715 according to one embodiment of the present invention is provided. Figure 8 In the diagram, the first curve 801 represents the control voltage VEA, and the second curve 802 represents the PSM voltage VPSM. (Reference) Figure 3A (or 3B~) Figure 4A Comparator 317 (or comparator 417) compares the control voltage VEA and the PSM voltage VPSM. However, when the value of the control voltage VEA is close to the value of the first PSM voltage VPSM1, the adjustment of the drive signal DRV may be affected by electrical noise. When the difference between the control voltage VEA and the PSM voltage VPSM may be insufficient, comparator 317 (or comparator 417) may misjudge the situation when electrical noise is added to the signal. Noise margin generator 715 adds a boundary voltage Vmargin to the first PSM voltage VPSM1 to increase the difference between the control voltage VEA and the second PSM voltage VPSM2.

[0111] refer to Figure 7 and Figure 8When the duty cycle signal DUTY or the drive signal DRV is high, the first switch SW1 is enabled and the second switch SW2 is disabled. Therefore, the boundary voltage Vmargin of the voltage source 7153 is applied to the first PSM voltage VPSM1 generated by the on-time modulator 513. In this case, the second PSM voltage VPSM2 is the first PSM voltage VPSM1 plus the boundary voltage Vmargin. On the other hand, when the duty cycle signal DUTY or the drive signal DRV is low, the first switch SW1 is disabled and the second switch SW2 is enabled. The first PSM voltage VPSM1 generated by the on-time modulator 513 is allowed to flow through the second switch SW2 without the application of the boundary voltage Vmargin. In this case, the second PSM voltage VPSM2 is the first PSM voltage VPSM1. In an embodiment, the boundary voltage Vmargin may be approximately 50mV. However, the present invention is not intended to limit the value of the boundary voltage Vmargin. In other embodiments, the boundary voltage Vmargin may range from 1mV to 100mV. Figure 8 The boundary voltage Vmargin increases the first PSM voltage VPSM when the duty cycle signal DUTY or the drive signal DRV is high, in order to create a larger voltage difference between the control voltage VEA (e.g., first curve 801) and the PSM voltage VPSM (e.g., second curve 802).

[0112] In summary, the PSM control circuit of this invention automatically and dynamically adjusts the occurrence of the jump signal, the pulse width of the jump signal, and / or the number of pulses within the jump signal based on the frequency signal and the drive signal used to drive the switching circuit, thereby adjusting the conduction time of the drive signal. Other aspects of this invention include increasing the voltage difference between the control voltage and the PSM voltage to minimize the influence of electrical noise, reducing the delay time of the comparator that generates the jump signal, and reducing output voltage ripple, etc.

[0113] Although the present invention has been described with reference to the embodiments described above, it will be apparent to those skilled in the art that modifications can be made to the embodiments without departing from the spirit of the invention. Therefore, the scope of the invention is defined by the appended claims rather than by the detailed description above.

[0114] The exemplary embodiments previously described in this invention have the aforementioned advantages, which are not essential in all versions of this invention.

[0115] Those skilled in the art will readily recognize that various modifications and variations can be made to the structure of the invention without departing from its scope or spirit. In view of the foregoing, the present invention is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage converter, characterized by comprises: a duty cycle generator coupled to a frequency signal and a feedback voltage, the duty cycle generator generating a duty cycle signal based on the frequency signal and the feedback voltage; a switch driving circuit coupled to the duty cycle generator and generating a driving signal based on the duty cycle signal and a skip signal; a switch circuit coupled to the switch driving circuit, an input voltage and a ground voltage, the switch circuit generating a switch node voltage provided to an inductor based on the driving signal, wherein the switch node voltage alternates between the input voltage and the ground voltage; and a pulse control circuit coupled to the switch driving circuit and the frequency signal, the pulse control circuit generating the skip signal based on the frequency signal and the driving signal, and outputting the skip signal to the switch driving circuit to adjust a turn-on time of the driving signal.

2. The voltage converter of claim 1, wherein, The pulse control circuit is configured to adjust a number of occurrences of a pulse within the skip signal based on a voltage level of the driving signal at a transition of the frequency signal.

3. The voltage converter of claim 2, wherein, The pulse control circuit is configured to adjust the number of occurrences of the pulse within the skip signal based on a voltage level of the driving signal at a transition of the frequency signal.

4. The voltage converter of claim 3, wherein, When the pulse control circuit determines that the driving signal is at a non-active voltage level at a rising edge of the frequency signal, the pulse control circuit extends a turn-on time of the driving signal used to drive the switch circuit by increasing a pulse skip modulation voltage.

5. The voltage converter of claim 1, wherein, The pulse control circuit comprises: a turn-on time modulator comprising: a plurality of current sources coupled in parallel between a voltage source and the ground voltage, and configured to output a PSM voltage; a PSM adjustment circuit receiving the frequency signal and the driving signal, and outputting an up-down signal based on a voltage level of the driving signal relative to the frequency signal; and a counter coupled between the PSM adjustment circuit and the plurality of current sources, and configured to enable a number of the plurality of current sources based on the up-down signal; a comparator coupled to the plurality of current sources to receive the PSM voltage, and configured to generate the skip signal based on the feedback voltage and the PSM voltage.

6. The voltage converter of claim 5, wherein, The comparator compares the PSM voltage with a control voltage corresponding to the feedback voltage, wherein the control voltage is generated by comparing the feedback voltage with a predetermined reference voltage.

7. The voltage converter of claim 6, wherein, The pulse control circuit starts outputting the skip signal when the PSM voltage is greater than the control voltage.

8. The voltage converter of claim 5, wherein, The pulse control circuit further comprises: a noise margin generator coupled between the turn-on time modulator and the comparator, and comprising: an amplifier having a first interface, a second interface and an output interface coupled to the first interface; a voltage source having a predetermined boundary voltage, coupled between the second interface of the amplifier and the current sources of the turn-on time modulator; a first switch coupled between the output interface of the amplifier and the second interface of the comparator, and having a control interface coupled to the driving signal or the duty cycle signal; and a second switch coupled between the first interface of the amplifier and the second interface of the comparator, and having a control interface coupled to the frequency signal. a second switch coupled between the current source of the on-time modulator and the second interface of the comparator and having a control interface coupled to an inverted drive signal or an inverted duty cycle signal.

9. A voltage converter receiving an input voltage and generating an output voltage, characterized in that comprising: an output inductor having a first interface and a second interface and being charged and discharged according to the input voltage; a switching circuit coupled to the input voltage, the first interface of the output inductor, and a ground voltage and configured to switch between a first state and a second state, wherein the switching circuit couples the input voltage to the output inductor to charge the output inductor in the first state and couples the output inductor to the ground voltage to discharge the output inductor in the second state; a switch drive circuit configured to output a drive signal to control the switching circuit to switch between the first state and the second state according to a duty cycle signal and a skip signal; and a pulse skip mode control circuit coupled to the second interface of the output inductor and configured to dynamically generate the skip signal according to a feedback voltage corresponding to the output voltage and a frequency signal.

10. The voltage converter of claim 9, wherein, The PSM control circuit includes a comparator having a first interface coupled to the feedback voltage corresponding to the output voltage, a second interface coupled to an error amplifier, and an output interface coupled to the switch drive circuit.

11. The voltage converter of claim 10, wherein, The PSM control circuit further includes: a PSM adjustment circuit receiving the frequency signal and the drive signal and outputting an up-down signal according to the frequency signal and the drive signal; a plurality of current sources coupled in parallel to each other between a first source voltage and a second source voltage and outputting a PSM voltage according to a number of the current sources enabled; an up-down counter coupled to the PSM adjustment circuit and the plurality of current sources and configured to enable the number of the current sources according to the up-down signal received from the PSM adjustment circuit, wherein the PSM voltage is coupled to the second interface of the comparator.

12. The voltage converter of claim 10, wherein, The PSM control circuit further includes: a PSM adjustment circuit coupled to the frequency signal and a switch drive circuit to receive the drive signal and output an enable signal based on the frequency signal and the drive signal; a current source outputting a PSM voltage according to the enable signal; an amplifier having a first interface, a second interface, and an output interface coupled to the first interface; a voltage source having a predetermined voltage coupled between the second interface of the amplifier and the PSM voltage; a first switch coupled between the output interface of the amplifier and the second interface of the comparator and having a control interface coupled to a duty cycle signal; and a second switch coupled between the current source and the second interface of the comparator and having a control interface coupled to an inverted duty cycle signal.

13. The voltage converter of claim 9, wherein, Further comprising: a duty cycle generator coupled to the frequency signal and the second terminal of the output inductor to receive the feedback voltage and generate the duty cycle signal from the frequency signal and the feedback voltage, the duty cycle signal being output to the switch drive circuit.

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