Simulation battery power supply device for mainboard module power supply and test method

Abstract

The invention aims to provide a simulation battery power supply device for mainboard module power supply and a test method. The system comprises an MCU controller and a system power supply circuit, the MCU controller is connected with a signal transfer soft board through a signal processing board, the signal transfer soft board is connected with a product to be tested through a mainboard, and the signal processing board comprises a voltage reduction circuit, a voltage stabilizing circuit, an instrument amplification circuit, a comparator circuit and an NAND gate comparison circuit. The system power supply circuit is connected with the voltage stabilizing circuit through the step-down circuit, the voltage stabilizing circuit is connected with the instrument amplifying circuit and the signal switching soft board, and the NAND gate comparison circuit is connected with the instrument amplifying circuit through the comparator circuit. The NAND gate comparison circuit and the step-down circuit are both connected with the MCU controller. The invention is applied to the technical field of mainboard power supply.

Description

Technical Field

[0001] This invention relates to the technical field of motherboard power supply, and particularly to a simulated battery power supply device and testing method for motherboard module power supply. Background Technology

[0002] MLB refers to the motherboard. Currently, in the testing industry, MLB modules are typically powered directly by batteries. However, for mass production workstations, using batteries presents several challenges. First, a fully charged battery operates at 4.2V, and its voltage drops as the charge decreases. Under heavy loads, this voltage drop can lead to instability in testing. Second, powering the motherboard can cause surges during startup, potentially resulting in motherboard failure. Furthermore, under heavy loads, continuous high-current discharge from the battery can cause overheating, swelling, and even fire. Since current testing solutions typically use batteries to power the MLB motherboard, and mobile phone motherboards often use high-density lithium-ion batteries (as disclosed in Chinese patent CN208141328U, which describes a motherboard battery charging and power supply circuit and motherboard), using batteries to power the MLB during mass production can lead to overheating and overload under prolonged operation. Additionally, continuous charging and discharging of the battery over extended periods can cause battery lifespan degradation. Furthermore, under continuous overload conditions, improper handling can easily lead to overheating, explosion, and fire hazards. Therefore, in large-scale production processes, seeking new alternatives to battery power supply solutions is particularly important for ensuring safety and quality. Thus, it is necessary to provide a simulated battery power supply device and testing method for motherboard module power supply. This device features a simple circuit, adjustable power supply, long-term power supply with low heat generation, compatibility with various motherboards, more flexible application scenarios, and high testing efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a simulated battery power supply device and test method for power supply of motherboard modules. The circuit is simple, the power supply is adjustable, it can provide power for a long time with low heat generation, it is compatible with a variety of motherboards, the application scenarios are more flexible, and the test efficiency is high.

[0004] The technical solution adopted in this invention is as follows: This invention includes an MCU controller and a system power supply circuit. The MCU controller is connected to a signal adapter flexible board via a signal processing board. The signal adapter flexible board is connected to the product under test via a motherboard. The signal processing board includes a step-down circuit, a voltage regulator circuit, an instrumentation amplifier circuit, a comparator circuit, and a NAND gate comparison circuit. The system power supply circuit is connected to the voltage regulator circuit via the step-down circuit. The voltage regulator circuit is connected to the instrumentation amplifier circuit and the signal adapter flexible board. The NAND gate comparison circuit is connected to the instrumentation amplifier circuit via the comparator circuit. Both the NAND gate comparison circuit and the step-down circuit are connected to the MCU controller. As can be seen from the above solutions, the hardware circuit power supply solution for motherboard power supply in this application has an adjustable power supply, can power various MLB models, has good compatibility, is simple to maintain and upgrade, can reduce customer costs, a single power supply board can be reused, can provide power for a long time with low heat generation; it is compatible with a variety of MLB motherboards, making the application scenarios more flexible, and for large-scale production, it is more convenient to test multiple modules and multiple channels on integrated lines, which also improves testing efficiency.

[0005] In a preferred embodiment, the system power supply circuit includes a relay switch and a first MOSFET, the relay switch is connected to the drain of the first MOSFET, the source of the first MOSFET is grounded, and the gate of the first MOSFET is connected to the buck circuit.

[0006] In a preferred embodiment, the buck circuit includes a DC-DC synchronous buck converter, the IN pin of which is connected to the gate of the first MOSFET, the NAND gate comparator circuit is connected to the EN pin of the DC-DC synchronous buck converter, and the SW pin of the DC-DC synchronous buck converter is connected to the voltage regulator circuit via an inductor.

[0007] In a preferred embodiment, the voltage regulator circuit includes a first LDO linear regulator and a second LDO linear regulator, wherein the IN pins of both the first and second LDO linear regulators are connected to the SW pin of the DC-DC synchronous buck converter, and the OUT pins of both the first and second LDO linear regulators are connected to the instrumentation amplifier circuit.

[0008] In a preferred embodiment, the instrumentation amplifier circuit includes an instrumentation amplifier, wherein the OUT pins of the first LDO linear regulator and the second LDO linear regulator are both connected to the sampling resistor via the input terminal of the instrumentation amplifier.

[0009] In a preferred embodiment, the comparator circuit includes a first comparator and a second comparator. The NAND gate comparator circuits are both connected to the output terminals of the first comparator and the second comparator. The input terminal of the first comparator is connected to a first buffer, and the input terminal of the second comparator is connected to a second buffer. Both the first buffer and the second buffer are connected to the instrumentation amplifier circuit.

[0010] In a preferred embodiment, the NAND gate comparison circuit includes a first NAND gate flip-flop and a second NAND gate flip-flop, wherein the first NAND gate flip-flop is connected to the second NAND gate flip-flop, and the second NAND gate flip-flop is connected to a second MOS transistor.

[0011] A preferred embodiment is that the testing method includes the following steps: Step 1: Input a voltage of 3.3V to the gate (G) of the first MOSFET. According to the switching characteristics of the MOSFET, when the gate voltage is greater than the source voltage by 0.7V, The first MOSFET will be turned on, and at this time the drain (D) is connected to GND, causing the relay switch to close, thereby inputting 12V DC power to the IN input terminal of the DC-DC synchronous buck converter; Step 2: After the DC 12V power supply is input to the DC-DC synchronous buck converter, the upper end of the EN enable pin of the DC-DC synchronous buck converter is connected to DC 12V through a 3.3K pull-up resistor, and the lower end is connected to the drain of the second MOSFET. According to the power-on state, no load is connected at this time, and the second MOSFET is not triggered to conduct. As long as the EN enable pin meets the drive voltage greater than 1.2V, the DC-DC synchronous buck converter can be enabled to work normally. Step 3: When the input 12V passes through the DC-DC synchronous buck converter, the voltage at the output of the DC-DC synchronous buck converter is 4.5V. Calculate based on the formula. The theoretical output voltage of the SW pin of the DC-DC synchronous buck converter is 4.53V. Step 4: The inductor passes through the DC-DC synchronous buck converter; Step 5: After the voltage stabilizes initially through the inductor, it will be input to the IN input terminals of the first LDO linear regulator and the second LDO linear regulator. The voltage after passing through the first LDO linear regulator and the second LDO linear regulator is 4.2V, which will be used as the power supply voltage for the motherboard module. Step 6: Based on the 4.2V voltage obtained in Step 5, in order to prevent overcurrent and overvoltage at the product end, it is necessary to add overcurrent protection and overvoltage protection capabilities to the circuit design. Step 7: Based on the analysis in Step 6, the circuit for adding current detection will add the sampling resistor with Rsense = 0.01R to the 4.2V voltage supply loop, and connect the instrumentation amplifier across the sampling resistor. The instrumentation amplifier has a high common-mode rejection capability of 120dB, a low low input bias current of only 500pA, and a fixed amplification factor of 100. The detected current will be converted into voltage and input to the back end, passing through the first buffer, acting as a voltage follower. Step 8: Begin analyzing the overcurrent protection detection circuit's operating status. Based on step 7, the voltage after passing through the first buffer is divided using two 1K resistors. This voltage then enters the inverting input of the first comparator. At this time, a fixed comparison bias voltage of 2V is input to the non-inverting input. The unknown voltage at the inverting input will be compared with the 2V voltage at the non-inverting input. If the voltage at the inverting input is less than that at the non-inverting input, a high level of 3.3V is output, which is the pull-up voltage of 3.3V at the back end of the first comparator. If the voltage at the inverting input is greater than that at the non-inverting input, a low level of 0V is output. Finally, the level signal output from the first comparator is input to the A pin of the first NAND gate flip-flop. Step 9: Continue analyzing the overvoltage protection detection circuit's operating state. The output at point TP201 is PP_VBATT_VCC=4.2V. PP_VBATT_VC will first be connected to the second buffer, and then this voltage will enter the inverting input of the first buffer. At this time, a fixed comparison bias voltage of 2.25V is input to the non-inverting input. The unknown voltage at the inverting input will be compared with the voltage of 2.25V at the non-inverting input. If the voltage at the inverting input is less than that at the non-inverting input, a high level of 3.3V will be output, which is the pull-up voltage of 3.3V at the back end of the first comparator. If the voltage at the inverting input is greater than that at the non-inverting input, a low level of 0V will be output. Finally, the level signal output from the first comparator will be input to the B pin of the first NAND gate flip-flop. Step 10: After the overcurrent detection level and the overvoltage detection level are respectively entered into the first NAND gate flip-flop, according to the logic working principle of the first NAND gate flip-flop, as long as either input A or B is in a low level state, the output state of the first NAND gate flip-flop is low level, otherwise it is high level. The output state of the first NAND gate flip-flop will enter the B terminal pin of the second NAND gate flip-flop. Step 11: Control the PB1 pin of the MCU controller to set it to push-pull output a high level of 3.3V and input it to the A terminal pin of the second NAND gate flip-flop. According to the logic working principle of the second NAND gate flip-flop, the second NAND gate flip-flop will output a low level as long as both A and B inputs are in a high level state, otherwise it will output a high level. When the output of the second NAND gate flip-flop is low, the second MOSFET will not be turned on. At this time, the voltage of the EN enable pin of the DC-DC synchronous buck converter is greater than 1.2V. At this time, the DC-DC synchronous buck converter can work normally and continuously provide voltage output. When the second NAND gate flip-flop outputs a high level, the second MOS transistor will be turned on. At this time, the voltage of the EN enable pin of the DC-DC synchronous buck converter is less than 1.2V. At this time, the DC-DC synchronous buck chip U301 cannot work normally, and the voltage output is turned off. Step 12: According to the overcurrent detection in step 7, the voltage at the upper end of the first resistor is connected to the PA4_IN4 input pin of the internal ADC of the MCU controller. According to the overvoltage detection in step 9, the voltage at the upper end of the second resistor is connected to the PA5_IN5 input pin of the internal ADC of the MCU controller, thereby realizing the real-time software detection of voltage and current status by the MCU controller. Step 13: The circuit implements hardware and software protection, and the load capacity of the circuit board is tested through adjustable load, which meets the design objectives and requirements. Attached Figure Description

[0012] Figure 1 This is a structural diagram of the present invention; Figure 2 This is a system block diagram of the present invention; Figure 3 This is a test block diagram of the signal processing board; Figure 4 This is a flowchart of the test signal process of the present invention; Figure 5 This is the circuit diagram of the power supply circuit for the system. Figure 6 This is the circuit diagram of the instrument amplifier circuit; Figure 7 This is the circuit diagram of the aforementioned step-down circuit; Figure 8 This is the circuit diagram of the voltage regulator circuit. Figure 9 This is the circuit schematic of the comparator circuit; Figure 10This is the circuit diagram of the NAND gate comparison circuit. Detailed Implementation

[0013] like Figures 1 to 4 As shown, in this embodiment, the present invention includes an MCU controller 1 and a system power supply circuit 2. The MCU controller 1 is connected to a signal adapter flexible board 4 via a signal processing board 3. The signal adapter flexible board 4 is connected to the product under test 6 via a main board 5. The signal processing board 3 includes a step-down circuit 7, a voltage regulator circuit 8, an instrumentation amplifier circuit 9, a comparator circuit 10, and a NAND gate comparison circuit 11. The system power supply circuit 2 is connected to the voltage regulator circuit 8 via the step-down circuit 7. The voltage regulator circuit 8 is connected to the instrumentation amplifier circuit 9 and the signal adapter flexible board 4. The NAND gate comparison circuit 11 is connected to the instrumentation amplifier circuit 9 via the comparator circuit 10. Both the NAND gate comparison circuit 11 and the step-down circuit 7 are connected to the MCU controller 1. The MCU controller 1 is an STM32F030C8T6.

[0014] The step-down circuit 7 converts the input high DC voltage into a low DC voltage of 4.5V. Considering the high conversion efficiency and low heat generation of DC-DC converters, the resulting low DC voltage will have significant switching noise. This 4.5V low DC voltage is then used as the input voltage of the voltage regulator circuit 8. After linear regulation, a 4.2V voltage is output for powering the MLB motherboard. On one hand, the low input-output voltage difference of the linear regulator chip also ensures reduced heat generation from the LDO chip, thus guaranteeing high conversion efficiency. On the other hand, the voltage regulator circuit 8 can support a high current output of 3A and a low output noise of 40uV RMS. Simultaneously, this power supply needs to implement overcurrent and overvoltage protection functions to ensure that the product is not damaged due to abnormalities in the power supply itself. Therefore, both hardware and software trigger protection were considered in the initial design. When overcurrent or overvoltage occurs in the product's power supply, hardware protection is triggered first, pulling the EN enable pin of the buck circuit 7 low to GND. The buck circuit 7 then stops working, resulting in no voltage output on its SW pin, thus reducing the risk of product burnout and increasing test safety and reliability. This achieves synchronous buck conversion followed by linear regulation via an LDO. An Rsens current sampling resistor is added to the power supply circuit for real-time sampling, and the current magnitude is constantly monitored by the microcontroller's integrated ADC. Simultaneously, hardware protection is implemented using a NAND gate trigger to achieve the hardware protection function. This application is applicable to applications requiring low-noise power supply, applications requiring readback of operating current and voltage, and other specified application scenarios such as 5V / 4A product power supply applications.

[0015] like Figure 5 As shown, in this embodiment, the system power supply circuit 2 includes a relay switch K101 and a first MOSFET Q101. The relay switch K101 is connected to the drain of the first MOSFET Q101, the source of the first MOSFET Q101 is grounded, and the gate of the first MOSFET Q101 is connected to the step-down circuit 7.

[0016] like Figure 7 As shown, in this embodiment, the step-down circuit 7 includes a DC-DC synchronous step-down converter U301. The IN pin of the DC-DC synchronous step-down converter U301 is connected to the gate of the first MOSFET Q101. The NAND gate comparator circuit 11 is connected to the EN pin of the DC-DC synchronous step-down converter U301. The SW pin of the DC-DC synchronous step-down converter U301 is connected to the voltage regulator circuit 8 via inductor L301. The DC-DC synchronous step-down converter U301 is model MP2491NGQB-P. Using the MP2491N synchronous step-down converter chip, it features high conversion efficiency and high output current, ensuring that the load requirements can be met.

[0017] like Figure 8 As shown, in this embodiment, the voltage regulator circuit 8 includes a first LDO linear regulator U401 and a second LDO linear regulator U402. The IN pins of both the first LDO linear regulator U401 and the second LDO linear regulator U402 are connected to the SW pin of the DC-DC synchronous buck converter U301. The OUT pins of both the first LDO linear regulator U401 and the second LDO linear regulator U402 are connected to the instrumentation amplifier circuit 9. Both the first LDO linear regulator U401 and the second LDO linear regulator U402 are model LT3083EDF#PBF. Using two linear regulator chips LT3083EDF#PBF serves to combine them into one unit, increasing the output current to a maximum of 6A.

[0018] like Figure 6 As shown, in this embodiment, the instrumentation amplifier circuit 9 includes an instrumentation amplifier U201. The OUT pins of the first LDO linear regulator U401 and the second LDO linear regulator U402 are both connected to the sampling resistor R201 via the input terminal of the instrumentation amplifier U201. The instrumentation amplifier U201 is an INA186 model. The instrumentation amplifier U201 amplifies the test signal, with a fixed amplification factor of gain=100 times. The purpose of this circuit is to amplify the weak signal to be measured by 100 times before sending it to the analog-to-digital converter (ADC) for voltage measurement.

[0019] likeFigure 9 As shown, in this embodiment, the comparator circuit 10 includes a first comparator U501B and a second comparator U501A. The NAND gate comparator circuit 11 is connected to the output terminals of both the first comparator U501B and the second comparator U501A. A first buffer U502A is connected to the input terminal of the first comparator U501B, and a second buffer U502B is connected to the input terminal of the second comparator U501A. Both the first buffer U502A and the second buffer U502B are connected to the instrumentation amplifier circuit 9. The first comparator U501B and the second comparator U501A are model LM393DR. When an overcurrent occurs at the product load terminal, the comparator circuit 10 converts the overcurrent into a voltage and compares it with a set voltage, thereby controlling the LM393DR to output a toggling level to trigger the NAND gate chip's protection shutdown. When an overvoltage occurs at the product terminal, it compares the voltage with a set voltage, thereby controlling the LM393DR to output a toggling level to trigger the NAND gate chip's protection shutdown.

[0020] like Figure 10 As shown, in this embodiment, the NAND gate comparator circuit 11 includes a first NAND gate flip-flop U601 and a second NAND gate flip-flop U602. The first NAND gate flip-flop U601 is connected to the second NAND gate flip-flop U602, and the second NAND gate flip-flop U602 is connected to a second MOS transistor Q601. The NAND gate comparator circuit 11 detects the input signal and then outputs a toggling level. When an overcurrent or overvoltage occurs in the circuit, the power supply is turned off to provide protection.

[0021] like Figures 1 to 2 As shown, in this embodiment, the testing method includes the following steps: Step 1: Input a voltage of 3.3V to the gate (G) of the first MOSFET Q101. According to the switching characteristics of the MOSFET, when the gate voltage is greater than the source voltage by 0.7V, The first MOSFET Q101 will be turned on, and at this time the drain (D) is connected to GND, causing the relay switch K101 to close, thereby inputting 12V DC power to the IN input terminal of the DC-DC synchronous buck converter U301; Step 2: After the DC12V power supply is input to the DC-DC synchronous buck converter U301, the upper end of the EN enable pin of the DC-DC synchronous buck converter U301 is connected to DC12V through a pull-up resistor of 3.3K, and the lower end is connected to the drain of the second MOSFET Q601. According to the power-on state, no load is connected at this time, and the second MOSFET Q601 is not triggered to conduct. As long as the EN enable pin meets the drive voltage greater than 1.2V, the DC-DC synchronous buck converter U301 can be enabled to work normally. Step 3: When the input 12V passes through the DC-DC synchronous buck converter U301, the voltage at the output of the DC-DC synchronous buck converter U301 is 4.5V. Based on the formula... The theoretical output voltage of the SW pin of the DC-DC synchronous buck converter U301 is 4.53V. Step 4: The DC-DC synchronous buck converter U301 passes through the inductor L301; Step 5: After the voltage is initially stabilized by the inductor L301, the voltage will be input to the IN input terminals of the first LDO linear regulator U401 and the second LDO linear regulator U402. The voltage after passing through the first LDO linear regulator U401 and the second LDO linear regulator U402 is 4.2V, which will be used as the power supply voltage for the motherboard 5 module. Step 6: Based on the 4.2V voltage obtained in Step 5, in order to prevent overcurrent and overvoltage at the product end, it is necessary to add overcurrent protection and overvoltage protection capabilities to the circuit design. Step 7: Based on the analysis in Step 6, the circuit for adding current detection will add the sampling resistor R201 with Rsense = 0.01R to the 4.2V voltage supply circuit, and connect the instrumentation amplifier U201 across the sampling resistor R201. The instrumentation amplifier U201 has a high common-mode rejection capability of 120dB, a low low input bias current of only 500pA, and a fixed amplification factor of 100. After the detected current is converted into voltage, it is input to the back end and first passes through the first buffer U502A, which acts as a voltage follower. Step 8: Begin analyzing the working state of the overcurrent protection detection circuit. According to step 7, the voltage after passing through the first buffer U502A is divided by two 1K resistors. Then, this voltage enters the inverting input of the first comparator U501B. At this time, a fixed comparison bias voltage of 2V is input at the non-inverting input. The unknown voltage at the inverting input will be compared with the voltage of 2V at the non-inverting input. If the voltage at the inverting input is less than that at the non-inverting input, a high level of 3.3V is output, which is the pull-up voltage of 3.3V at the back end of the first comparator U501B. If the voltage at the inverting input is greater than that at the non-inverting input, a low level of 0V is output. Finally, the level signal output from the first comparator U501B will be input to the A pin of the first NAND gate flip-flop U601. Step 9: Continue analyzing the overvoltage protection detection circuit's operating state. The output at point TP201 is PP_VBATT_VCC=4.2V. PP_VBATT_VC will first be connected to the second buffer U502B. Then, this voltage enters the inverting input of the first buffer U502A. At this time, a fixed comparison bias voltage of 2.25V is input at the non-inverting input. The unknown voltage at the inverting input will be compared with the voltage of 2.25V at the non-inverting input. If the voltage at the inverting input is less than that at the non-inverting input, a high level of 3.3V will be output, which is the pull-up voltage of 3.3V at the back end of the first comparator U501B. If the voltage at the inverting input is greater than that at the non-inverting input, a low level of 0V will be output. Finally, the level signal output from the first comparator U501B will be input to the B pin of the first NAND gate flip-flop U601. Step 10: After the overcurrent detection level and the overvoltage detection level are respectively entered into the first NAND gate flip-flop U601, according to the logic working principle of the first NAND gate flip-flop U601, as long as either input A or B is in a low level state, the output state of the first NAND gate flip-flop U601 is low level, otherwise it is high level. The output state of the first NAND gate flip-flop U601 will enter the B terminal pin of the second NAND gate flip-flop U602. Step 11: Control the PB1 pin of the MCU controller 1 to set it to push-pull output of 3.3V high level input to the A terminal pin of the second NAND gate flip-flop U602. According to the logic working principle of the second NAND gate flip-flop U602, the second NAND gate flip-flop U602 will output a low level as long as both A and B inputs are in a high level state, otherwise it will output a high level. When the second NAND gate flip-flop U602 outputs a low level, the second MOS transistor Q601 will not be turned on. At this time, the voltage of the EN enable pin of the DC-DC synchronous buck converter U301 is greater than 1.2V. At this time, the DC-DC synchronous buck converter U301 can work normally and continuously provide voltage output. When the second NAND gate flip-flop U602 outputs a high level, the second MOS transistor Q601 will be turned on. At this time, the voltage of the EN enable pin of the DC-DC synchronous buck converter U301 is less than 1.2V. At this time, the DC-DC synchronous buck chip U301 cannot work normally, and the voltage output is turned off. Step 12: According to the overcurrent detection in step 7, the voltage at the upper end of the first resistor R508 is connected to the PA4_IN4 input pin of the internal ADC of the MCU controller 1. According to the overvoltage detection in step 9, the voltage at the upper end of the second resistor R516 is connected to the PA5_IN5 input pin of the internal ADC of the MCU controller 1, thereby realizing the real-time software detection of voltage and current status by the MCU controller 1. Step 13: The circuit implements hardware and software protection, and the load capacity of the circuit board is tested through adjustable load, which meets the design objectives and requirements.

[0022] In this embodiment, the inductor L301 is also commonly referred to as a power inductor or energy storage inductor. Connecting the SW output terminal of U301 can serve the following three purposes: Energy storage: Converts stored magnetic energy into electrical energy and releases it to the output terminal to maintain the load current; Smoothing current: Making the current smoother utilizes the characteristic that current cannot change abruptly, converting pulsed current into a relatively smooth DC output current, thereby reducing ripple in the output signal. Voltage regulation: According to the volt-second balance principle, when the DC-DC circuit is in steady state, the integral of the voltage across the inductor in one cycle is zero. The inductor efficiently reduces the output voltage by storing or releasing energy.

[0023] In this embodiment, Table 1.1 below shows the VBATT output voltage measurement values ​​of the 10 groups of programmable DC electronic loads (IT8511) under no load, load of 1A, load of 2A, load of 2.5A, and load of 3A.

[0024] Table 1.2 below shows the VBATT output power measurement values ​​for 10 groups of programmable DC electronic loads (IT8511) under no load, 1A load, 2A load, 2.5A load, and 3A load.

[0025] Test configuration parameters: Table 1.1 Comparison of voltage measured by multimeter 34401A and voltage readback from electronic load (IT8511) Table 1.2 Comparison of current measured by multimeter 34401A and current readback from electronic load (IT8511) During the test, the voltage value measured by the multimeter (34465A) was set as the measured value of the standard instrument, and the electronic load (IT8511) was used as the load terminal readback voltage measurement value.

[0026] Electronic load (IT8511) voltage measurement accuracy = |(Multimeter voltage test average - Electronic load (IT8511) voltage test average)| / Multimeter voltage test average During the test, the current value measured by the multimeter (34465A) was set as the standard instrument measurement value, and the electronic load (IT8511) was used as the load terminal readback current measurement value.

[0027] Electronic load (IT8511) current measurement accuracy = |(Multimeter current test average - Electronic load (IT8511) current test average)| / Multimeter voltage test average In summary, the conclusions drawn from the measured data are as follows: By comparing the voltage measured with the voltage test value read back from the electronic load (IT8511) using a multimeter 34401A, as well as the current test value, the data shows that the power supply board's testing capability and accuracy meet the testing requirements.

[0028] On the one hand, there is a comparison of current test values. The test accuracy is 0.001% under the condition of Load 2A where the difference is the smallest, and less than 0.823% under the condition of Load 0.1A where the difference is the smallest.

[0029] On the one hand, there is a comparison of voltage test values. Under the condition of Load 0.1A, the test accuracy is 0.054%, and under the condition of Load 0.1A, the test accuracy is less than 2.274%.

[0030] For the testing industry, the required accuracy of the power supply is within 5%. Therefore, the MLB power supply integrated circuit board developed in this application can replace the battery as a simulated battery for power supply.

[0031] Although the embodiments of the present invention are described with reference to actual solutions, they do not constitute a limitation on the meaning of the present invention. Modifications to the embodiments and combinations with other solutions based on this specification will be obvious to those skilled in the art.

Claims

1. A kind of analog battery-powered device for mainboard module power supply, including MCU controller (1) and system power supply circuit (2), the MCU controller (1) is connected with signal switching soft board (4) by signal processing board (3), the signal switching soft board (4) is connected with product (6) to be measured by mainboard (5), it is characterized by: The signal processing board (3) includes a voltage reduction circuit (7), a voltage stabilization circuit (8), an instrument amplification circuit (9), a comparator circuit (10), a NAND gate comparison circuit (11), the system power supply circuit (2) is connected with the voltage stabilization circuit (8) through the voltage reduction circuit (7), the voltage stabilization circuit (8) is connected with the instrument amplification circuit (9) and the signal switching soft board (4), the NAND gate comparison circuit (11) is connected with the instrument amplification circuit (9) through the comparator circuit (10), and the NAND gate comparison circuit (11) and the voltage reduction circuit (7) are connected with the MCU controller (1).

2. The simulated battery power supply device for power supply of a motherboard module according to claim 1, wherein, The system power supply circuit (2) includes a relay switch (K101) and a first MOS tube (Q101), the drain electrode of the relay switch (K101) is connected with the first MOS tube (Q101), the source electrode of the first MOS tube (Q101) is grounded, and the gate electrode of the first MOS tube (Q101) is connected with the voltage reduction circuit (7).

3. The simulated battery power supply device for power supply of a motherboard module according to claim 2, wherein, The voltage reduction circuit (7) includes a DCDC synchronous voltage reduction converter (U301), the IN pin of the DCDC synchronous voltage reduction converter (U301) is connected with the gate electrode of the first MOS tube (Q101), the NAND gate comparison circuit (11) is connected with the EN pin of the DCDC synchronous voltage reduction converter (U301), and the SW pin of the DCDC synchronous voltage reduction converter (U301) is connected with the voltage stabilization circuit (8) through an inductor (L301).

4. The simulated battery power supply device for power supply of a motherboard module according to claim 3, wherein, The voltage stabilization circuit (8) includes a first LDO linear voltage stabilizer (U401) and a second LDO linear voltage stabilizer (U402), the IN pin of the first LDO linear voltage stabilizer (U401) and the IN pin of the second LDO linear voltage stabilizer (U402) are connected with the SW pin of the DCDC synchronous voltage reduction converter (U301), and the OUT pin of the first LDO linear voltage stabilizer (U401) and the OUT pin of the second LDO linear voltage stabilizer (U402) are connected with the instrument amplification circuit (9).

5. The simulated battery power supply device for power supply of a motherboard module according to claim 4, wherein, The instrument amplification circuit (9) includes an instrument amplifier (U201), the OUT pin of the first LDO linear voltage stabilizer (U401) and the OUT pin of the second LDO linear voltage stabilizer (U402) are connected with a sampling resistor (R201) through the input end of the instrument amplifier (U201).

6. The simulated battery power supply device for power supply of a motherboard module according to claim 5, wherein, The comparator circuit (10) includes a first comparator (U501B) and a second comparator (U501A), the NAND gate comparison circuit (11) is connected with the output end of the first comparator (U501B) and the output end of the second comparator (U501A), the input end of the first comparator (U501B) is connected with a first buffer (U502A), the input end of the second comparator (U501A) is connected with a second buffer (U502B), and the first buffer (U502A) and the second buffer (U502B) are connected with the instrument amplification circuit (9).

7. The simulated battery power supply device for power supply of a motherboard module according to claim 6, wherein, The NAND gate comparison circuit (11) comprises a first NAND gate flip-flop (U601) and a second NAND gate flip-flop (U602), the first NAND gate flip-flop (U601) is connected with the second NAND gate flip-flop (U602), and the second NAND gate flip-flop (U602) is connected with a second MOS tube (Q601).

8. A method for testing the simulated battery power supply device for power supply of the motherboard module as claimed in claim 7, wherein: The test method comprises the following steps: Step 1, input 3V3 voltage at the gate G of the first MOS tube (Q101), according to the switching characteristics of the MOS tube, when the gate voltage is greater than the source voltage 0.7V, The first MOS tube (Q101) will be turned on, at this time the drain D is connected to GND, so that the relay switch (K101) is closed, thereby inputting 12V DC power supply to the IN input end of the DCDC synchronous step-down converter (U301); Step 2, after the DC12V DC power supply is input into the DCDC synchronous step-down converter (U301), the upper end of the EN enabling pin of the DCDC synchronous step-down converter (U301) is connected to DC12V through a pull-up 3.3K resistor, and the lower end is connected to the drain D of the second MOS tube (Q601), according to the power-on state, at this time no load is connected, the second MOS tube (Q601) is not triggered to be turned on, and the DCDC synchronous step-down converter (U301) can work normally when the EN enabling pin meets the driving voltage greater than 1.2V; Step 3, when inputting 12V through the DCDC synchronous step-down converter (U301), the voltage at the back end of the DCDC synchronous step-down converter (U301) is 4.5V, and the output voltage of the DCDC synchronous step-down converter (U301) is designed according to the formula The output of the DCDC synchronous step-down converter (U301) is 4.53V; Step 4, through the inductor (L301) in the DCDC synchronous step-down converter (U301); Step 5, after the voltage is preliminarily stabilized through the inductor (L301), the voltage at this time is input into the IN input end of the first LDO linear voltage stabilizer (U401) and the second LDO linear voltage stabilizer (U402), and the voltage through the first LDO linear voltage stabilizer (U401) and the second LDO linear voltage stabilizer (U402) is 4.2V, which will be used as the power supply point voltage of the mainboard (5) module; Step 6, according to the 4.2V voltage obtained in step 5, in order to prevent overcurrent and overvoltage at the product end, it is necessary to add the ability of overcurrent protection and overvoltage protection in the circuit. Step 7, according to the analysis of step 6, the circuit of increasing current detection will increase the sampling resistance (R201) of Rsense = 0.01R in the voltage supply circuit of 4.2V, and connect the instrument amplifier (U201) at both ends of the sampling resistance (R201), the instrument amplifier (U201) has a high common mode rejection capability of 120dB and a low input bias current of only 500pA and a fixed amplification of 100 times, and after the detected current is converted into voltage, it is input to the first buffer (U502A) for voltage follower; Step 8, start analyzing the working state of the overcurrent protection detection circuit, according to step 7, then the voltage after the first buffer (U502A) is divided by two 1K resistors, and then the voltage enters the inverting input terminal of the first comparator (U501B), at this time the fixed comparison bias voltage of 2V is input to the same phase input terminal, and the unknown voltage of the inverting input terminal will be compared with the voltage of 2V of the same phase input terminal, if the voltage of the inverting input terminal is less than that of the same phase input terminal, the output high level is 3.3V, that is, the pull-up voltage 3.3V at the back end of the first comparator (U501B), if the voltage of the inverting input terminal is greater than that of the same phase input terminal, the output low level is 0V, and finally the level signal output from the first comparator (U501B) is input to the A pin of the first NAND gate trigger (U601); Step 9, continue to analyze the working state of the overvoltage protection detection circuit, the output at TP201 point network is PP_VBATT_VCC = 4.2V, which will first connect PP_VBATT_VC to the second buffer (U502B), and then the voltage enters the inverting input terminal of the first buffer (U502A), at this time the fixed comparison bias voltage of 2.25V is input to the same phase input terminal, and the unknown voltage of the inverting input terminal will be compared with the voltage of 2.25V of the same phase input terminal, if the voltage of the inverting input terminal is less than that of the same phase input terminal, the output high level is 3.3V, that is, the pull-up voltage 3.3V at the back end of the first comparator (U501B), if the voltage of the inverting input terminal is greater than that of the same phase input terminal, the output low level is 0V, and finally the level signal output from the first comparator (U501B) is input to the B pin of the first NAND gate trigger (U601); Step 10, after the level state of overcurrent detection and the level state of overvoltage detection are input into the first NAND gate trigger (U601) respectively, according to the logic working principle of the first NAND gate trigger (U601), as long as any one of A or B input is low level state, the output state of the first NAND gate trigger (U601) is low level, otherwise it is output high level, the output state of the first NAND gate trigger (U601) will enter the B pin of the second NAND gate trigger (U602). Step 11, control the PB1 pin of the MCU controller (1) to set a high level input of 3.3V push-pull output to the A end pin of the second NAND gate trigger (U602), according to the logic working principle of the second NAND gate trigger (U602), as long as A and B any input is high level state, the second NAND gate trigger (U602) will output low level, otherwise it will output high level; when the second NAND gate trigger (U602) outputs low level, the second MOS tube (Q601) will not conduct, at this time the voltage of the EN enable pin of the DCDC synchronous buck converter (U301) is greater than 1.2V, at this time the DCDC synchronous buck converter (U301) can work normally and continuously provide voltage output; when the second NAND gate trigger (U602) outputs high level, the second MOS tube (Q601) will conduct, at this time the voltage of the EN enable pin of the DCDC synchronous buck converter (U301) is less than 1.2V, at this time the DCDC synchronous buck chip U301 cannot work normally and the voltage output is off; Step 12, according to the overcurrent detection of step 7, the voltage at the upper end of the first resistor (R508) is connected to the corresponding PA4_IN4 input pin of the internal ADC of the MCU controller (1), and according to the overvoltage detection of step 9, the voltage at the upper end of the second resistor (R516) is connected to the corresponding PA5_IN5 input pin of the internal ADC of the MCU controller (1), so as to realize real-time software detection of voltage and current state by the MCU controller (1); Step 13, the circuit realizes hardware and software protection, and tests the load capacity of the circuit board through adjustable load, which achieves the design purpose and requirement.

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