Fir filter design method based on real-time calculation of loop resistance

Abstract

The application relates to the technical field of power equipment state monitoring, and discloses a FIR filter design method based on real-time calculation of loop resistance, which comprises the following steps: firstly, a mapping rule of prototype coefficients to multiphase sub-filter banks is established, and a linear control condition for strictly aligning branch energy barycenters with a nominal group time delay is constructed; subsequently, a coefficient correction operator containing the control condition is used to perform optimal approximation correction on initial coefficients generated according to frequency domain indexes, so that target filter coefficients are obtained. By configuring a digital signal processor according to the application, periodic interference introduced by channel switching can be eliminated from the source while high-frequency response details are reserved, and the accuracy and reliability of loop resistance online monitoring data can be greatly improved.

Description

Technical Field

[0001] This invention relates to the field of power equipment condition monitoring technology, and more specifically, to a design method for FIR filters based on real-time calculation of loop resistance. Background Technology

[0002] In the operation and maintenance system of smart grids, loop resistance is a key indicator for assessing the connection status of current-carrying circuits in power equipment, the degree of contact wear, and oxidation. With the evolution of monitoring technology, the traditional offline periodic maintenance mode is gradually shifting to online monitoring and dynamic resistance measurement mode. Such applications typically employ the millivolt drop method principle, which involves simultaneously acquiring the loop current signal and the voltage drop signal across the contacts, and then calculating the ratio of the two through numerical calculations to obtain the real-time resistance value.

[0003] Due to the complex environment at power plant sites, the acquired raw signals often contain strong power frequency interference, high-frequency transient noise from switching operations, and various electromagnetic interferences. Therefore, before calculating the resistance ratio, a finite impulse response (FIR) filter is typically configured in the digital signal processing link for anti-aliasing, combined with downsampling techniques to reduce the data throughput pressure of subsequent processing units. In engineering implementation, to save hardware logic resources and reduce power consumption, a polyphase decomposition structure is widely used to achieve synchronous operation of filtering and downsampling. This structure uses a commutator to split the input data into multiple parallel sub-filter branches for processing.

[0004] However, existing FIR filter designs typically focus only on frequency domain response metrics, such as passband ripple, stopband attenuation, and overall linear phase properties. In multiphase downsampling architectures, this traditional design approach has a significant, often overlooked, flaw: after the coefficients of the prototype filter are mapped to multiple sub-filter branches, the energy centroids (i.e., weighted delay centers) of each branch in the time domain are often not consistent.

[0005] In actual operation of online loop resistance monitoring, the inconsistency between the centers of gravity of the branches due to the periodic channel switching mechanism exhibited by the multiphase structure during operation can lead to periodic deviations in the effective sampling time of the input signal. When the actual loop resistance shows a smooth trend due to equipment temperature rise or contact movement, this periodic deviation will incorrectly convert the rate of resistance change (i.e., the slope of the trend) into pseudo-periodic fluctuations synchronized with the downsampling factor.

[0006] Such spurious fluctuations can severely interfere with the operation and maintenance system's assessment of equipment health. For example, it may mask subtle signs of early contact degradation or be misinterpreted as oscillations caused by poor equipment contact. Traditional solutions typically involve adding a smoothing filter at the back end, but this significantly introduces additional measurement delays, preventing the system from capturing the rapid changes in detail during circuit breaker operation and failing to meet the timeliness requirements of dynamic measurements. Summary of the Invention

[0007] This invention provides a design method for FIR filters based on real-time calculation of loop resistance, which solves the technical problems mentioned in the background art.

[0008] This invention provides a method for designing FIR filters based on real-time calculation of loop resistance, including:

[0009] A digital signal processing link including anti-aliasing filtering and downsampling processing is established, and the coefficient allocation rules from prototype filter coefficients to multi-rate signal decimation structure are established, wherein the multi-rate signal decimation structure includes multiple parallel processing branches corresponding to different sampling times.

[0010] Branch delay consistency control conditions are set to ensure that the center of the impulse response weighted delay of each parallel processing branch is consistent with the nominal group delay of the prototype filter, so as to eliminate the spurious fluctuations in the resistance change rate caused by multi-phase switching.

[0011] Initial filter coefficients are generated based on preset frequency domain response indicators. Then, using a coefficient correction operator that includes the branch delay consistency control condition, the initial filter coefficients are subjected to optimal approximation correction operation to obtain the target filter coefficients.

[0012] Based on the target filter coefficients, the downsampling module of the digital signal processor is configured to synchronously process the voltage and current signals to output a real-time loop resistance value that eliminates sampling phase correlation interference.

[0013] The beneficial effects of this invention include: by introducing a multi-phase branch delay consistency control mechanism during the generation of finite impulse response filter coefficients, the problem of periodic drift in sampling time caused by the energy centroid deviation of each parallel processing branch in the multi-rate signal extraction structure is fundamentally solved, thereby eliminating the phenomenon that the rate of change of loop resistance trend is incorrectly modulated into pseudo-periodic fluctuations; without increasing the back-end smoothing processing delay, this invention significantly improves the ability of dynamic resistance measurement to capture weak degradation trends and the signal fidelity, effectively avoids the risk of false alarms caused by algorithm defects, and ensures the authenticity and timeliness of status monitoring data of power equipment such as circuit breakers. Attached Figure Description

[0014] Figure 1This is a flowchart of the FIR filter design method based on real-time calculation of loop resistance according to the present invention;

[0015] Figure 2 This is a schematic diagram illustrating a specific implementation scenario of the present invention;

[0016] Figure 3 This is a schematic diagram of the synchronization processing mechanism of the present invention. Detailed Implementation

[0017] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and implement the subject matter described herein, and changes may be made to the function and arrangement of the elements discussed without departing from the scope of this specification. Various processes or components may be omitted, substituted, or added as needed in the examples. Furthermore, features described in some examples may be combined in other examples.

[0018] like Figure 1 As shown, the FIR filter design method based on real-time calculation of loop resistance includes:

[0019] A digital signal processing link including anti-aliasing filtering and downsampling processing is established, and the coefficient allocation rules from prototype filter coefficients to multi-rate signal decimation structure are established, wherein the multi-rate signal decimation structure includes multiple parallel processing branches corresponding to different sampling times.

[0020] Branch delay consistency control conditions are set to ensure that the center of the impulse response weighted delay of each parallel processing branch is consistent with the nominal group delay of the prototype filter, so as to eliminate the spurious fluctuations in the resistance change rate caused by multi-phase switching.

[0021] Initial filter coefficients are generated based on preset frequency domain response indicators. Then, using a coefficient correction operator that includes the branch delay consistency control condition, the initial filter coefficients are subjected to optimal approximation correction operation to obtain the target filter coefficients.

[0022] Based on the target filter coefficients, the downsampling module of the digital signal processor is configured to synchronously process the voltage and current signals to output a real-time loop resistance value that eliminates sampling phase correlation interference.

[0023] Preferably, a digital signal processing link including anti-aliasing filtering and downsampling processing is established, including:

[0024] Real-time collected voltage digital sequence With current digital sequence Using the same set of target filter coefficients as input signals respectively The input signal is subjected to convolution filtering and then downsampled according to a preset factor. Perform equal-interval decimation operations to generate downsampled voltage sequences. With downsampled current sequence The calculation formulas are as follows:

[0025]

[0026]

[0027] in, The total length of the target filter coefficients. For coefficient index, This is the index of the downsampled output sequence;

[0028] The real-time loop resistance sequence is calculated by dividing the downsampled voltage sequence value at each sampling time by the corresponding downsampled current sequence value. The calculation formula is as follows:

[0029]

[0030] A voltage digital sequence is a discrete numerical sequence obtained by converting the voltage signal of a power equipment circuit acquired in real time into an analog-to-digital converter. It can be acquired using a high-precision analog-to-digital converter (with a sampling rate no less than twice the highest frequency of the signal) combined with a voltage sensor. The voltage sensor must be electrically isolated from the power equipment circuit to ensure safety.

[0031] Digital current sequence is a discrete numerical sequence obtained by converting real-time power equipment circuit current signals into digital signals using analog-to-digital conversion. It can be acquired using Rogowski coil current sensors or Hall effect current sensors in conjunction with a high-precision analog-to-digital converter. The sensor must be matched to the circuit current rating to ensure the measurement range.

[0032] The target filter coefficients are a set of fixed discrete values ​​used for convolution filtering of the voltage and current digital sequences after branch delay consistency correction.

[0033] The downsampling factor is a preset factor used to reduce the amount of data extracted. It is preferably between 2 and 16, taking into account the power frequency and harmonic frequency characteristics of the power system. It is necessary to meet the anti-aliasing filtering requirements while controlling the data throughput pressure and avoiding excessive downsampling that could lead to loss of signal details.

[0034] Downsampled voltage sequences are low-rate discrete numerical sequences obtained by convolution filtering and equal-interval decimation of voltage digital sequences.

[0035] Downsampled current sequences are low-rate discrete numerical sequences obtained by convolution filtering and equal-interval decimation of current digital sequences.

[0036] The total length of the target filter coefficients is the number of coefficients contained in the target filter. It is preferably an odd number between 33 and 129 to ensure filtering effect while controlling computational complexity. An odd length facilitates the realization of linear phase characteristics.

[0037] The coefficient index is a sequential identifier used to traverse the coefficients of the target filter, and its value ranges from 0 to the total length of the target filter coefficients minus one.

[0038] The downsampled output sequence index is a sequential identifier used to traverse the downsampled voltage sequence and the downsampled current sequence, and its value is a non-negative integer.

[0039] The real-time loop resistance sequence is a discrete numerical sequence composed of the ratio of the downsampled voltage sequence value to the corresponding downsampled current sequence value at each sampling time.

[0040] The core principle of synchronously processing voltage and current digital sequences using the same set of target filter coefficients is to ensure that the filtering delay and amplitude-frequency characteristics of the two signals are completely consistent. If two independent filters are used, even if the parameters are nominally identical, slight differences in the actual hardware implementation will cause phase and amplitude deviations between the two signals, thus introducing additional resistance calculation errors. For example, in a 100 Hz signal processing scenario, a 1-microsecond delay difference between the two filters will cause voltage and current phase misalignment, resulting in significant deviations in the calculated resistance values.

[0041] The link order in which the filtering downsampling ratio is calculated is fixed because downsampling before filtering can lead to aliasing distortion, while calculating the ratio before filtering can amplify noise and interference. For example, in the case of 50 Hz power frequency interference in a power field, if downsampling is performed before filtering, the interference signal may be folded into the effective signal frequency band and cannot be effectively filtered out. Filtering before downsampling can suppress interference in advance and ensure the accuracy of subsequent ratio calculations.

[0042] The specific implementation of convolution filtering can use the multiplication and accumulation unit of a digital signal processor. It sequentially multiplies each input signal value with its corresponding filter coefficient and then sums the results. The processing order is from the beginning to the end of the input sequence, performing the convolution operation point by point. For example, for a filter of length 33, each output point requires 33 multiplications and 32 additions.

[0043] The timing control for equally spaced decimations must be synchronized with the original sampling clock. The decimation trigger signal is generated by a timer of the digital signal processor, and the timer frequency is set to the original sampling frequency divided by the downsampling factor. For example, if the original sampling frequency is 10 kHz and the downsampling factor is 5, the timer frequency is set to 2 kHz, and each trigger decimates one filtered signal value.

[0044] The sampling rate of the voltage and current digital sequences must be adapted to the downsampling factor. The sampling rate should be no less than the product of the downsampling factor and the highest frequency of the signal, and no less than 20 kHz, to cover the power system's power frequency and common harmonic frequencies. For example, when the downsampling factor is 4 and the highest frequency of the signal is 5 kHz, the sampling rate should be no less than 20 kHz.

[0045] The numerical accuracy of the loop resistance sequence calculation can be guaranteed by using 32-bit floating-point arithmetic. The division operation uses the hardware division unit of the digital signal processor. At the same time, a numerical range threshold is set. When the downsampled current sequence value is lower than 0.01 amperes, the previous resistance calculation result is temporarily stored to avoid numerical overflow or abnormal fluctuations caused by small currents.

[0046] Preferably, a coefficient allocation rule for the prototype filter coefficients to the multi-rate signal decimation structure is established, wherein the multi-rate signal decimation structure includes multiple parallel processing branches corresponding to different sampling times, including:

[0047] Obtain the prototype filter coefficient sequence Set downsampling factor As the modulus of multiphase decomposition;

[0048] According to the index order of the prototype filter coefficient sequence, the index values ​​are paired with the downsampling factor. Perform modulo operations, and group prototype filter coefficients with the same modulo operation result into the same parallel processing branch. In the process, the sub-filter coefficient sequence serves as the branch of parallel processing. Its mapping rule formula is:

[0049]

[0050] in, The index for the parallel processing branch, with a value range of 1. to ; This is the internal index of the sub-filter coefficient sequence; Indicates the index of the prototype filter coefficient sequence. The coefficient value.

[0051] The prototype filter coefficient sequence is an initial discrete numerical sequence that has not undergone branch delay consistency correction and is used to map to the multiphase parallel processing branches.

[0052] The downsampling factor is a preset multiphase decomposition modulus, which is also the multiple of subsequent equal-interval decimations. It is preferably between 2 and 16 to balance data compression efficiency and signal detail preservation, adapt to the frequency range of power equipment circuit signals, and avoid excessive branches after decomposition leading to wasted hardware resources or insufficient branches affecting the downsampling effect.

[0053] The parallel processing branch index is used to distinguish the order of different parallel processing channels after multiphase decomposition, and its value ranges from 0 to the downsampling factor minus one.

[0054] The sub-filter coefficient sequence is a discrete numerical sequence of prototype filter coefficients that, after modulo distribution, belong to the same parallel processing branch.

[0055] The sub-filter internal index is a sequential identifier used to traverse the sub-filter coefficients in each parallel processing branch, and its value is a non-negative integer.

[0056] Using the downsampling factor as the modulus of polyphase decomposition, and allocating coefficients through modulo indexing, ensures that the coefficients of each parallel processing branch correspond to a specific phase position of the prototype filter. This allocation method directly matches the linear-periodic time-varying characteristics of the multi-rate signal decimation structure, allowing for precise implementation of subsequent branch delay consistency control. For example, when the downsampling factor is 4, the modulo result of prototype filter coefficient indices 0, 4, 8, etc., is 0, and they are assigned to branch 0; the modulo result of indices 1, 5, 9, etc., is 1, and they are assigned to branch 1, and so on. The coefficients of each branch correspond to coefficients with a fixed phase interval in the prototype filter, providing a structural basis for aligning the time centroids of each branch, which differs from the allocation method in general polyphase decomposition that lacks explicit phase binding.

[0057] The rule for calculating the length of the sub-filter coefficient sequence is as follows: when the total length of the prototype filter coefficients is divisible by the downsampling factor, the lengths of all sub-filter coefficient sequences are equal, which is the total length of the prototype filter coefficients divided by the downsampling factor; when it is not divisible, the length of the sub-filter coefficient sequence of the first few branches is the quotient plus one, and the length of the remaining branches is the quotient. For example, if the total length of the prototype filter coefficients is 33 and the downsampling factor is 4, 33 divided by 4 has a quotient of 8 and a remainder of 1, then the length of branch 0 is 9, and the lengths of branches 1, 2, and 3 are 8.

[0058] The specific implementation of the modulo operation can be achieved in software by directly calculating using the modulo operator built into the programming language, or in hardware by using a circuit composed of adders and comparators to cyclically compare the index value with the downsampling factor to obtain the remainder.

[0059] The hardware implementation of the parallel processing branch can be a multi-channel processing unit of a digital signal processor or a distributed logic resource of a field-programmable gate array. Each branch corresponds to an independent multiplication and accumulation unit to ensure parallel processing efficiency.

[0060] Preferably, a branch delay consistency control condition is set to ensure that the center of the impulse response weighted delay of each parallel processing branch is consistent with the nominal group delay of the prototype filter, so as to eliminate spurious fluctuations in the resistance change rate caused by multi-phase switching, including:

[0061] Calculate each of the parallel processing branches separately. Time-indexed weighted first-order moments of the sub-filter coefficient sequence and the sum of coefficient values The calculation formulas are as follows:

[0062]

[0063]

[0064] in, The sub-filter coefficient sequence, This is the internal index of the sub-filter. To reduce the sampling factor, For parallel processing of branch indexes;

[0065] Calculate the prototype filter coefficients nominal group latency The calculation formula is as follows:

[0066]

[0067] in, The total length of the prototype filter coefficients. For coefficient index;

[0068] Construct linear constraint equations to limit the time index-weighted first moment of each of the parallel processing branches. Subtract the nominal group delay The sum of the coefficients of this branch The product of and is strictly equal to zero, and its formula is:

[0069]

[0070] The parallel processing branch index is used to distinguish the order of different parallel processing channels after multiphase decomposition, and its value ranges from 0 to the downsampling factor minus one.

[0071] The sub-filter coefficient sequence is a discrete numerical sequence of prototype filter coefficients that, after modulo distribution, belong to the same parallel processing branch.

[0072] The sub-filter time index weighted first moment is the sum of the values ​​obtained by multiplying each coefficient of the sub-filter by its corresponding time index, and is used to quantize the delay center of the branch.

[0073] The sum of sub-filter coefficients is the cumulative value of all sub-filter coefficients within the same parallel processing branch, used to characterize the energy intensity of the branch.

[0074] The prototype filter coefficients are the initial discrete numerical sequences used to map to the multiphase parallel processing branches without branch delay consistency correction.

[0075] The nominal group delay is the value obtained by dividing the weighted sum of all coefficients of the prototype filter with their corresponding indices by the total sum of the coefficients, and it represents the overall average delay of the prototype filter.

[0076] The total length of the prototype filter coefficients is the number of coefficients contained in the prototype filter. It is preferably an odd number between 33 and 129. An odd length makes it easier to calculate the center of symmetry, ensures linear phase characteristics, and avoids inaccurate time delay quantization due to an excessively short total length of coefficients, while an excessively long total length increases the computational burden.

[0077] The coefficient index is a sequential identifier used to traverse the coefficients of the prototype filter, and its value ranges from 0 to the total length of the prototype filter coefficients minus one.

[0078] Defining the weighted first-order moments and coefficient sum of the sub-filter time indices as a quantitative indicator of branch delay transforms the abstract branch time centroid into a calculable and constrainable mathematical quantity. Traditional polyphase filter design only focuses on the overall group delay of the prototype filter, ignoring the delay differences between branches. This design, however, accurately captures the actual delay center of each branch through these two indicators. For example, with a downsampling factor of 4 and a total prototype filter coefficient length of 33, the sub-filter coefficients of branch 0 correspond to prototype indices 0, 4, 8, etc. Calculating the weighted first-order moments and coefficient sum of these coefficients clearly reveals the delay characteristics of that branch.

[0079] Constructing linear constraint equations to force the time delay center of each branch to align with the nominal group time delay is a dedicated design for loop resistance calculation scenarios. This equation structurally eliminates time delay deviations between branches, preventing periodic drift in sampling timing during multi-phase switching. For example, when the nominal group time delay is 16, the weighted first moment of the time index of the four branches must be equal to the product of 16 and the sum of the coefficients of each branch, ensuring that the effective sampling time of the signal is consistent for all branches, thus avoiding spurious fluctuations in the rate of resistance change from the source.

[0080] The calculation precision of the sub-filter time-indexed weighted first moment and the sum of coefficient values ​​requires 32-bit floating-point arithmetic. In hardware implementation, this can be accomplished through the multiplication and accumulation unit of a digital signal processor. In software implementation, high-precision mathematical library functions can be called to ensure that the calculation error is less than 0.001, thus avoiding the impact of quantization error on the time delay judgment.

[0081] The linear constraint equations can be solved using Gaussian elimination. When the number of branches is M, a system of M linear equations is formed, and the coefficient corrections are solved using elementary matrix transformations. If the system of equations is overdetermined, the least squares method can be used to obtain the optimal approximate solution, ensuring that the overall constraint conditions are satisfied.

[0082] The reasonable range for the nominal group delay is half of the total length of the prototype filter coefficients minus one. For example, when the total length of the coefficients is 33, the nominal group delay is 16. This range ensures that the delay center falls in the middle region of the filter coefficients, which conforms to the delay characteristics of a linear phase filter.

[0083] When the sum of the coefficients of some branches is 0, it indicates that the branch has no valid coefficients. The prototype filter coefficient allocation rules need to be re-examined, invalid branches removed, or the downsampling factor adjusted to ensure that each branch has non-zero coefficients, thus avoiding meaningless division operations. For example, if the downsampling factor is 4 and the sum of the coefficients of branch 1 is 0, the downsampling factor can be adjusted to 3, or the prototype coefficients can be reallocated to ensure that the coefficients of each branch are non-zero.

[0084] Preferably, the initial filter coefficients are generated based on a preset frequency domain response index, including:

[0085] Determine the passband cutoff frequency for anti-aliasing filtering Stopband start frequency and the weighted error coefficients for each frequency band ;

[0086] Using the Chebyshev optimal uniform approximation algorithm, a set of passband cutoff frequencies is calculated to satisfy the given conditions. With stopband start frequency The requirement is to find a finite-length sequence that minimizes the maximum weighted error in the frequency domain, and use it as the initial filter coefficients. :

[0087]

[0088] in, The length of the initial filter coefficients, The value must meet the anti-aliasing requirements. , here This is a downsampling factor.

[0089] The passband cutoff frequency is the highest frequency at which a signal can pass through without attenuation in anti-aliasing filtering. It is preferably between 1 kHz and 5 kHz to adapt to the power system's mains frequency and common harmonic frequencies, thus preserving the effective frequency components of the loop resistance signal while preventing low-frequency interference from entering subsequent processing.

[0090] The stopband start frequency is the lowest frequency at which the signal begins to attenuate significantly during anti-aliasing filtering. It is preferably half to two-thirds of the Nyquist frequency corresponding to the downsampling factor, that is, the stopband start frequency does not exceed the converted frequency of π divided by the downsampling factor, so as to ensure that there is no aliasing distortion during the downsampling process. For example, when the downsampling factor is 4, the stopband start frequency does not exceed 12.5 kHz.

[0091] The passband weighted error coefficient is a weight value used to adjust the allowable error of the passband ripple. It is preferably 1 to 2, so that the passband signal needs to maintain a high fidelity. Setting the weight lower than that of the stopband can prioritize ensuring the amplitude accuracy of the effective signal.

[0092] The stopband weighted error coefficient is a weight value used to adjust the allowable error of stopband attenuation. It is preferably between 10 and 100. To significantly suppress interference signals, a higher weight can force the algorithm to improve the stopband attenuation effect and reduce interference residue.

[0093] The initial filter coefficients are calculated using the Chebyshev optimal uniform approximation algorithm and are finite-length discrete numerical sequences that satisfy preset frequency domain specifications.

[0094] The initial filter coefficient length is the number of coefficients included in the initial filter. It is preferably an odd number between 33 and 129. An odd length facilitates the subsequent implementation of linear phase characteristics, while balancing the filtering effect and computational complexity. This avoids the problem of the frequency domain performance not meeting the requirements if the length is too short, and the computational burden increasing if the length is too long.

[0095] The downsampling factor is a preset multiphase decomposition modulus and an equal-interval decimation factor. It is preferably between 2 and 16 to match the data flow requirements of power equipment signal processing, while taking into account both data compression efficiency and signal detail preservation.

[0096] A clear and strong binding relationship is established between the stopband start frequency and the downsampling factor; that is, the stopband start frequency should not exceed the frequency calculated by dividing π by the downsampling factor. This is a specific anti-aliasing design for multiphase downsampling structures. Traditional FIR filter designs may only generalize the frequency domain specifications without clearly defining their relationship with the downsampling factor, which can easily lead to aliasing of interference signals during downsampling. For example, if the downsampling factor is 5, the corresponding Nyquist frequency is 25 kHz, and the stopband start frequency should be set to no more than 15.7 kHz to ensure that interference signals above this frequency are sufficiently attenuated and prevent aliasing into the effective signal frequency band.

[0097] The initial coefficients are generated using the Chebyshev optimal uniform approximation algorithm, with the core objective of minimizing the maximum weighted error in the frequency domain to achieve more uniform passband ripple and stopband attenuation. For example, with a passband weighted error coefficient of 1 and a stopband weighted error coefficient of 50, the algorithm prioritizes ensuring the uniformity of stopband attenuation, significantly suppressing power frequency harmonic interference, while controlling the passband ripple within acceptable limits to ensure that the amplitude of the loop resistance signal is not distorted. Unlike filters designed with ordinary window functions, this approach offers superior frequency domain performance and greater specificity.

[0098] The selection of the passband cutoff frequency and stopband start frequency should be combined with the power field interference. If the field power frequency interference is strong, the passband cutoff frequency can be 1 kHz to 3 kHz, and the stopband start frequency can be 1.5 to 2 times the passband cutoff frequency. For example, when the passband cutoff frequency is 2 kHz, the stopband start frequency can be 3 kHz to 4 kHz.

[0099] The standard for setting the passband weighted error coefficient and the stopband weighted error coefficient is as follows: adjust according to the interference intensity. When the high-frequency interference is severe, the stopband weighted error coefficient can be increased to 80 to 100. When the signal amplitude stability requirement is high, the passband weighted error coefficient can be set to 1 and the stopband weighted error coefficient can be set to 50 to 80.

[0100] The implementation details of Chebyshev's best uniform approximation algorithm are as follows: At the software level, dedicated functions from a digital signal processing library can be called, with the number of iterations set to 100 to 500. The convergence condition is that the maximum deviation of the coefficients between two adjacent iterations is less than 0.0001. At the hardware level, it can be implemented through a dedicated algorithm module, employing a pipelined architecture to improve computational speed. The initial filter coefficients are floating-point numbers ranging from -1 to 1, stored with 32-bit floating-point precision to avoid numerical overflow and ensure sufficient accuracy margin for subsequent coefficient correction.

[0101] Preferably, the initial filter coefficients are subjected to optimal approximation correction operation using a coefficient correction operator that includes the branch delay consistency control condition to obtain the target filter coefficients, including:

[0102] Construct a linear phase-symmetric constraint matrix This is used to constrain the filter coefficients to satisfy the centrosymmetry property, for a length of... The filter has the following constraints: ;

[0103] The linear phase symmetric constraint matrix The matrix constructed based on the aforementioned branch delay consistency control conditions Perform row merging to form a comprehensive linear constraint matrix. It is represented as:

[0104]

[0105] A least-squares orthogonal projection operator based on the comprehensive linear constraint matrix is ​​constructed, and the initial filter coefficients are calculated using this operator. The optimal approximation solution is obtained to obtain the target filter coefficients. The formula for calculating its closed-form solution is:

[0106]

[0107] in, To be the transpose of the composite linear constraint matrix, It is the inverse matrix of the matrix product.

[0108] The linear phase symmetry constraint matrix is ​​a matrix used to constrain the filter coefficients to satisfy the centrosymmetry characteristic. Its function is to ensure that the filter as a whole exhibits linear phase characteristics.

[0109] The branch delay consistency constraint matrix is ​​a matrix constructed based on the branch delay alignment requirements. It is used to force the time centroid of each parallel processing branch to be consistent with the nominal group delay.

[0110] The integrated linear constraint matrix is ​​a matrix obtained by row merging of the linear phase symmetric constraint matrix and the branch delay consistency constraint matrix, thus integrating the two types of constraints.

[0111] The initial filter coefficients are generated by the Chebyshev optimal uniform approximation algorithm and are a finite-length discrete numerical sequence that satisfies the preset frequency domain response index.

[0112] The target filter coefficients are discrete numerical sequences that, after being corrected by the correction operator corresponding to the integrated linear constraint matrix, simultaneously satisfy the frequency domain index and the branch delay consistency requirements.

[0113] The filter length is the number of coefficients contained in the filter. It is preferably an odd number between 33 and 129. An odd length makes it easier to construct a centrally symmetric linear phase constraint, while balancing the feasibility of constraint solving with computational complexity. It avoids constraint conflicts caused by too short a length, and increases the burden of matrix operations by too long a length.

[0114] The coefficient index is a sequential identifier used to traverse the filter coefficients, and its value ranges from 0 to the filter length minus one.

[0115] Simultaneously applying linear phase symmetry constraints and branch delay consistency constraints, and constructing a comprehensive constraint matrix through matrix row merging, is a dedicated optimization design for loop resistance calculation scenarios. Traditional filter designs typically only consider frequency domain indicators or linear phase, failing to incorporate branch delay consistency into the joint constraints, leading to a mismatch between performance and structural requirements in multiphase structures. For example, when the filter length is 33, the linear phase constraint requires that the coefficients of indices 0 and 32, and 1 and 31, be equal, while the branch delay constraint requires that the time centroids of each branch be aligned. The comprehensive matrix can simultaneously guarantee both of these requirements, avoiding conflicts caused by individual constraints.

[0116] The coefficient correction is performed using the least squares orthogonal projection operator. The core principle is to minimize changes to the initial filter coefficients while preserving the original frequency domain performance, all while satisfying the constraints. For example, if the initial coefficients already meet the requirements for passband ripple and stopband attenuation, the correction process only adjusts the coefficient components that affect the consistency of branch delays through projection operations, ensuring that the corrected coefficients still meet the frequency domain specifications. This approach differs from the traditional method of redesigning coefficients, balancing efficiency and performance.

[0117] The specific construction details of the linear phase symmetric constraint matrix are as follows: the matrix dimension is half the filter length multiplied by the filter length. For a filter of length N, the matrix contains N / 2 rows (rounded down). Each row has 1 and -1 only at the coefficient indices ℓ and N-1-ℓ, and 0 at the other positions. For example, when N=33, the matrix has 16 rows. The first row has 1 and -1 at indices 0 and 32, the second row has 1 and -1 at indices 1 and 31, and so on.

[0118] The elements of the branch delay consistency constraint matrix are defined as follows: the matrix dimension is the downsampling factor multiplied by the filter length, each row corresponds to a parallel branch, and only the coefficient index position corresponding to that branch is ℓ minus the nominal group delay, the other positions are 0. For example, when the downsampling factor is 4 and N=33, the matrix has 4 rows, and the row corresponding to branch 0 is filled with the corresponding ℓ minus the nominal group delay value at index positions 0, 4, 8, etc.

[0119] The condition for the linear constraint matrix to be invertible is that the filter length is greater than the number of constraint equations, i.e., N>M+N / 2 (rounded down). For example, when M=4 and N=33, the number of constraint equations is 4+16=20, and 33>20 satisfies the invertibility condition.

[0120] The stability measures for numerical computation are as follows: before matrix inversion, singular value decomposition is performed on the matrix to remove singular values ​​less than 1e-6 to avoid numerical ill-conditioning; 64-bit floating-point arithmetic is used for matrix operations to reduce accumulated errors.

[0121] The allowable range of frequency domain index deviations after correction is: passband ripple deviation not exceeding 20% ​​of the initial value, and stopband attenuation deviation not exceeding 10% of the initial value, to ensure that the anti-aliasing requirements are still met after correction.

[0122] Preferably, the downsampling module of the digital signal processor is configured based on the target filter coefficients to synchronously process the voltage and current signals, so as to output a real-time loop resistance value that eliminates sampling phase correlation interference, including:

[0123] According to the established coefficient allocation rules, the target filter coefficients are... Reorganized into Sub-filter coefficient sequences of the parallel processing branch Its mapping formula is:

[0124]

[0125] Multiple sets of the sub-filter coefficient sequences They are respectively loaded into the corresponding registers of the multi-rate signal decimation structure of the digital signal processor;

[0126] Controlling the multi-rate signal extraction structure utilizes For real-time input voltage signals With current signal Perform multiphase filtering and downsampling to output a downsampled voltage sequence. With downsampled current sequence The ratio of the two is calculated to obtain the real-time loop resistance value after eliminating the trend differential term periodic modulation caused by the branch time centroid deviation. :

[0127]

[0128] The target filter coefficients are discrete numerical sequences that simultaneously meet the frequency domain specifications and structural requirements after being corrected for both branch delay consistency and linear phase constraints.

[0129] The corrected sub-filter coefficient sequence is a discrete numerical sequence that is reorganized according to a preset allocation rule and assigned to each parallel processing branch.

[0130] The parallel processing branch index is used to distinguish the order of different parallel processing channels after multiphase decomposition, and its value ranges from 0 to the downsampling factor minus one.

[0131] The sub-filter internal index is a sequential identifier used to traverse the sub-filter coefficients in each parallel processing branch, and its value is a non-negative integer.

[0132] Voltage signals are discrete numerical sequences of circuit voltages from power equipment acquired in real time and converted from analog to digital. They can be acquired using high-precision voltage sensors in conjunction with analog-to-digital converters. The sensors must have electrical isolation capabilities to adapt to the power field environment.

[0133] The current signal is a discrete numerical sequence of circuit currents in power equipment acquired in real time and converted from analog to digital. It can be acquired using a Hall current sensor or a Rogowski coil sensor paired with an analog-to-digital converter. The sensor range must match the rated current of the circuit.

[0134] Downsampled voltage sequences are low-rate discrete numerical sequences obtained by multiphase filtering and equal-interval decimation of voltage signals.

[0135] Downsampled current sequences are low-rate discrete numerical sequences obtained by multiphase filtering and equal-interval decimation of current signals.

[0136] The real-time loop resistance value is the ratio of the downsampled voltage sequence value to the corresponding downsampled current sequence value at each sampling time, and is the final measurement result after eliminating phase correlation interference.

[0137] The downsampling factor is a preset polyphase decomposition modulus and an equal-interval decimation factor. It is preferably between 2 and 16 to balance data processing efficiency and signal detail preservation, and to adapt to the computing power of digital signal processors.

[0138] Reorganizing the target filter coefficients into a sequence of corrected sub-filter coefficients according to the allocation rules is a key design feature to ensure that the branch delay consistency constraints are implemented at the hardware level. Traditional polyphase filter deployments only focus on coefficient loading and do not emphasize the strong binding between the corrected coefficients and the allocation rules, which may cause the constraints of the software design to fail in the hardware implementation. For example, when the downsampling factor is 4, the target filter coefficients indices 0, 4, 8, etc. are reorganized into branch 0, and indices 1, 5, 9, etc. are reorganized into branch 1, ensuring that the coefficients of each branch still maintain the corrected delay characteristics, so that the hardware processing is consistent with the software design goals.

[0139] The multi-rate signal decimation structure of the control digital signal processor synchronously performs polyphase filtering and downsampling, directly outputting the resistor value to eliminate periodic modulation. This is a proprietary solution that deeply couples algorithm design with hardware implementation. For example, the processor switches parallel branches in a fixed timing sequence through an internal commutator. Each branch filters the input signal with corrected coefficients, and the ratio is directly calculated after decimation, avoiding the introduction of additional deviations in intermediate stages. This differs from the method of separating filtering, decimation, and ratio calculation in general signal processing.

[0140] The specific model of the digital signal processor can be Texas Instruments' TMS320 series or ADI's Blackfin series. It must support multi-rate signal decimation structure and hardware multiply-accumulate unit, and have an operation rate of not less than 100 MHz to meet real-time processing requirements.

[0141] The timing control for loading the sub-filter coefficient sequence into the register is as follows: the loading trigger signal is synchronized with the sampling clock of the analog-to-digital converter. A set of coefficients is loaded in each sampling cycle, and the loading order is from branch 0 to the branch corresponding to the downsampling factor minus one, ensuring that the coefficients match the timing of the signal input. For example, when the sampling clock is 10 kHz, a loading operation is triggered every 100 microseconds.

[0142] The hardware coordination logic for multiphase filtering and downsampling is as follows: the commutator is switched by a timer, with the switching frequency equal to the downsampled output frequency. The multiplication and accumulation operations of each branch are synchronized with the commutator switching. The filtered signal is buffered in a register and then extracted by the decimation module at intervals. For example, when the downsampling factor is 5, the commutator switches branches every 5 sampling periods, and the decimation module extracts the filtering results synchronously.

[0143] The output interface protocol for real-time loop resistance values ​​can use CAN bus or Ethernet, with a data transmission format of 32-bit floating point and a transmission rate of no less than 1 kHz, to ensure that the back-end monitoring system receives data in a timely manner.

[0144] The anti-interference design of the digital signal processor includes: using a shielded enclosure to reduce electromagnetic interference, adding decoupling capacitors to the power supply to stabilize power supply, adding TVS diodes to the signal input channel for overvoltage protection, and adapting to the complex electromagnetic environment of the power field.

[0145] like Figure 2 As shown, Figure 2 The hardware architecture and signal processing link of the online monitoring system for loop resistance of a typical power equipment (taking a circuit breaker as an example) to which this invention is applied are demonstrated. Figure 2 This demonstrates how analog signals are acquired through current source injection and Kelvin four-wire voltage sampling, and then converted to digital signals via analog-to-digital converter (ADC). The location of the multiphase FIR decimation module within the system is indicated; this module is the key processing unit for configuring the filter coefficients designed in this invention, responsible for synchronously processing voltage and current data and ultimately outputting high-precision real-time loop resistance values.

[0146] like Figure 3 As shown, Figure 3 This paper reveals the technical challenges faced by existing standard multiphase downsampling structures when processing dynamic trend signals. The left-hand structural diagram shows the input signal being distributed to different parallel branch sub-filters for alternating processing via a commutator; the middle timing diagram clearly indicates that, due to the lack of constraints in traditional designs, there is an inherent deviation in the time centroid of each branch filter; the trend comparison diagram on the right visually reflects the result of this centroid deviation: the originally smooth true resistance trend is superimposed with periodic spurious fluctuations synchronized with the switching frequency at the output.

[0147] The embodiments of this example have been described above. However, this example is not limited to the specific implementation methods described above. The specific implementation methods described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms based on the guidance of this example, and all of them are within the protection scope of this example.

Claims

1. A method for designing FIR filters based on real-time calculation of loop resistance, characterized in that, include: A digital signal processing link including anti-aliasing filtering and downsampling processing is established, and the coefficient allocation rules from the prototype filter coefficients to the multi-rate signal decimation structure are defined. The multi-rate signal decimation structure includes multiple parallel processing branches corresponding to different sampling times, including: Obtain the prototype filter coefficient sequence and set the downsampling factor as the modulus of the polyphase decomposition; According to the index order of the prototype filter coefficient sequence, the index value is modulo the downsampling factor; The prototype filter coefficients with the same modulo operation result are divided into the same parallel processing branch and used as the sub-filter coefficient sequence of the parallel processing branch, thereby mapping a single set of prototype filter coefficients into multiple sets of sub-filter coefficient sequences of parallel processing branches. A branch delay consistency control condition is set to ensure that the center of the impulse response weighted delay of each parallel processing branch is consistent with the nominal group delay of the prototype filter, thereby eliminating spurious fluctuations in the resistance change rate caused by multiphase switching, including: Calculate the time index weighted first moment and the sum of coefficient values ​​for the sub-filter coefficient sequence of each of the parallel processing branches; The ratio of the overall time-indexed weighted first moment of the prototype filter coefficients to the sum of the overall coefficient values ​​is calculated and used as the nominal group delay. A linear constraint equation is constructed to ensure that the product of the time index weighted first moment of each parallel processing branch minus the sum of the nominal group delay and the coefficient values ​​of that branch is equal to zero, thereby ensuring that the time centroids of all parallel processing branches remain aligned from the perspective of the downsampled output. Initial filter coefficients are generated based on preset frequency domain response indicators. Then, using a coefficient correction operator that includes the branch delay consistency control condition, optimal approximation correction operations are performed on the initial filter coefficients to obtain the target filter coefficients, including: Construct a linear phase symmetric constraint matrix to constrain the filter coefficients to satisfy the central symmetry property in order to ensure the overall linear phase; The linear phase symmetric constraint matrix is ​​row-merged with the matrix constructed based on the branch delay consistency control condition to form a comprehensive linear constraint matrix; Construct a least-squares orthogonal projection operator based on the comprehensive linear constraint matrix, use the least-squares orthogonal projection operator to calculate the projection vector of the initial filter coefficients under all constraint conditions, and superimpose the projection vector onto the initial filter coefficients or directly use it as the correction result, thereby obtaining the target filter coefficients that satisfy both the frequency domain response index and the branch delay consistency. Based on the target filter coefficients, the downsampling module of the digital signal processor is configured to synchronously process the voltage and current signals to output a real-time loop resistance value that eliminates sampling phase correlation interference.

2. The FIR filter design method based on real-time calculation of loop resistance according to claim 1, characterized in that, Establish a digital signal processing link that includes anti-aliasing filtering and downsampling processing, including: The real-time acquired voltage and current digital sequences are used as input signals, and the input signals are subjected to convolution filtering processing using the same set of target filter coefficients. The filtered voltage and current signals are sampled at equal intervals according to the preset downsampling factor to generate downsampled voltage and current sequences respectively. The real-time loop resistance sequence is calculated by dividing the downsampled voltage sequence value at each sampling time by the corresponding downsampled current sequence value.

3. The FIR filter design method based on real-time calculation of loop resistance according to claim 1, characterized in that, The initial filter coefficients are generated based on the preset frequency domain response specifications, including: Determine the passband cutoff frequency, stopband start frequency, and weighted error coefficients for each frequency band used for anti-aliasing filtering; The Chebyshev optimal uniform approximation algorithm is used to calculate a set of finite-length sequences that satisfy the requirements of the passband cutoff frequency and the stopband start frequency and minimize the maximum weighted error in the frequency domain, and these sequences are used as the initial filter coefficients.

4. The FIR filter design method based on real-time calculation of loop resistance according to claim 1, characterized in that, Based on the target filter coefficients, the downsampling module of the digital signal processor is configured to synchronously process voltage and current signals to output a real-time loop resistance value that eliminates sampling phase correlation interference, including: According to the coefficient allocation rules, the target filter coefficients are reorganized into a sequence of sub-filter coefficients for multiple parallel processing branches; The multiple sets of sub-filter coefficient sequences are respectively loaded into the corresponding registers of the multi-rate signal decimation structure of the digital signal processor; The multi-rate signal extraction structure is controlled to perform multiphase filtering and downsampling on the real-time input voltage and current signals, output downsampled voltage and current sequences, and calculate the ratio of the downsampled voltage and current sequences to obtain the real-time loop resistance value that eliminates the trend differential term periodic modulation caused by the branch time centroid deviation.

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