Signal processing chip, electronic equipment and signal processing method

Abstract

The invention provides a chip processing chip, electronic equipment and a chip processing method. Wherein the signal processing chip comprises a low-pass filter, a comparator and a first hysteresis voltage generating circuit, the input end of the low-pass filter is connected with the input end of the signal processing chip, the output end of the low-pass filter is connected with the first input end of the comparator, and the output end of the first hysteresis voltage generating circuit is connected with the second input end of the comparator; the output end of the comparator is connected with the input end of the first hysteresis voltage generation circuit, and the output end of the comparator is connected with the output end of the signal processing chip. According to the invention, large-swing noise can be suppressed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of clock signal processing, and in particular to a signal processing chip, an electronic device and a signal processing method. BACKGROUND

[0002] As a feedback system that can keep the phase synchronization between the output signal and the input signal, the phase-locked loop needs to receive a reference clock signal from a reference clock source. When the phase-locked loop is applied in an electronic device, the radio frequency antenna in the electronic device will cause interference to the reference clock signal, thereby causing the reference clock signal to generate glitches and other noises. When the reference clock signal with glitches is input into the phase-locked loop, the phase-locked loop will lose lock and other conditions. In order to eliminate the glitches on the reference clock signal, a clock signal processing module can be arranged between the reference clock source and the phase-locked loop.

[0003] In the related art, the clock signal processing module can include a plurality of transistors, and the plurality of transistors in combination can generate a hysteresis voltage, and the hysteresis voltage can be changed by adjusting the size ratio between the transistors. However, generating a larger hysteresis voltage will cause the size of some transistors to be too large, thereby causing the parasitic capacitance to increase and other adverse effects. Therefore, the hysteresis voltage generated by this scheme is usually small, and thus it cannot suppress large swing noise. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a signal processing chip, an electronic device and a signal processing method, which can suppress large swing noise.

[0005] In a first aspect of the present application, a signal processing chip is provided, comprising: a low-pass filter, a comparator and a first hysteresis voltage generating circuit. Wherein the input end of the low-pass filter is connected with the input end of the signal processing chip, the output end of the low-pass filter is connected with the input end of the comparator, the output end of the first hysteresis voltage generating circuit is connected with the second input end of the comparator, the output end of the comparator is connected with the input end of the first hysteresis voltage generating circuit, and the output end of the comparator is connected with the output end of the signal processing chip.

[0006] The signal processing chip can receive the to-be-processed signal input by the input end of the signal processing chip, and perform low-pass filtering on the to-be-processed signal, so as to reduce the noise higher than the cut-off frequency of the low-pass filter in the to-be-processed signal, for example, the noise higher than 1 GHz can be reduced to within 50 mV, and a low-pass filtered signal is obtained. The low-pass filter can send the low-pass filtered signal to the first input end of the comparator. The comparator can compare the low-pass filtered signal with the reference signal, obtain a comparison result signal, and send the comparison result signal to the first hysteresis voltage generating circuit. The first hysteresis voltage generating circuit can generate a first hysteresis voltage according to the comparison result signal, and send the first hysteresis voltage to the second input end of the comparator. After receiving the first hysteresis voltage, the comparator can compare the low-pass filtered signal sent by the low-pass filter with the first hysteresis voltage, or can obtain an operated hysteresis voltage after performing relevant operation on the first hysteresis voltage, and compare the low-pass filtered signal with the operated hysteresis voltage to obtain a comparison result signal. The comparator can output the comparison result signal as an output signal.

[0007] In the present application, the to-be-processed signal is first subjected to low-pass filtering, so that the noise with a higher frequency in the to-be-processed signal is greatly reduced. Then, the first hysteresis voltage generating circuit generates a first hysteresis voltage, and the low-pass filtered signal is compared with the first hysteresis voltage or an operated hysteresis voltage of the first hysteresis voltage, so that the noise with a reduced swing can be suppressed. Therefore, the present application can suppress the noise with a large swing.

[0008] Based on this, the signal processing chip can further include a second hysteresis voltage generating circuit and an adder. The output end of the comparator is further connected to the input end of the second hysteresis voltage generating circuit, so that the comparator can further send the comparison result signal to the second hysteresis voltage generating circuit. After receiving the comparison result signal, the second hysteresis voltage generating circuit can generate a second hysteresis voltage.

[0009] The output end of the second hysteresis voltage generating circuit is connected to the first input end of the adder, the output end of the first hysteresis voltage generating circuit is connected to the second input end of the adder, and the output end of the adder is connected to the second input end of the comparator. In this way, the first hysteresis voltage generating circuit can send the first hysteresis voltage to the adder, the second hysteresis voltage generating circuit can send the second hysteresis voltage to the adder, and the adder can perform addition operation on the first hysteresis voltage and the second hysteresis voltage to obtain a combined hysteresis voltage, and send the combined hysteresis voltage to the comparator for comparison.

[0010] Further, the frequency of the second hysteresis voltage outputted by the second hysteresis voltage generating circuit is lower than the frequency of the first hysteresis voltage outputted by the first hysteresis voltage generating circuit. That is, the second hysteresis voltage generating circuit can generate a second hysteresis voltage with a lower frequency, thereby suppressing the noise with a lower frequency in the low-pass filtered signal outputted by the low-pass filter. The first hysteresis voltage generating circuit can generate a first hysteresis voltage with a higher frequency, thereby suppressing the noise with a higher frequency in the low-pass filtered signal outputted by the low-pass filter. Therefore, the present application can suppress the noise with a higher frequency and the noise with a lower frequency simultaneously, that is, the present application can suppress the noise in a wide frequency domain.

[0011] Further, the comparator comprises a first-stage comparator and a second-stage comparator connected in series, the input terminal of the first-stage comparator is the input terminal of the comparator, the output terminal of the first-stage comparator is connected to the input terminal of the second-stage comparator, and the output terminal of the second-stage comparator is the output terminal of the comparator. The output terminal of the first-stage comparator is connected to the input terminal of the first hysteresis voltage generating circuit, and the output terminal of the second-stage comparator is connected to the input terminal of the second hysteresis voltage generating circuit. That is, the comparison result signal received by the first hysteresis voltage generating circuit is the comparison result signal obtained after one-stage comparison, and the comparison result signal received by the second hysteresis voltage generating circuit is the comparison result signal obtained after two-stage comparison. Therefore, compared with the second hysteresis voltage generating circuit, the speed of the comparison result signal received by the first hysteresis voltage generating circuit is faster, and the frequency of the comparison result signal received by the first hysteresis voltage generating circuit is higher. Thus, the frequency of the first hysteresis voltage generated by the first hysteresis voltage generating circuit is higher than the frequency of the second hysteresis voltage generated by the second hysteresis voltage generating circuit.

[0012] In some embodiments of the present application, the first-stage comparator comprises a first transistor and a second transistor, the first pole of the first transistor and the first pole of the second transistor are both connected to a power supply terminal, the second pole of the first transistor is connected to a control pole, and the second pole of the second transistor is connected to a control pole.

[0013] For the first hysteresis voltage generating circuit, in a possible embodiment, the first hysteresis voltage generating circuit comprises a third transistor and a fourth transistor, the first pole of the third transistor and the first pole of the fourth transistor are both connected to a power supply terminal, the control pole of the third transistor is connected to the second pole of the fourth transistor and to the second pole of the first transistor, and the control pole of the fourth transistor is connected to the second pole of the third transistor and to the second pole of the second transistor. In this way, a first hysteresis voltage of about 50mV can be generated, and the first hysteresis voltage is generated at a faster speed to filter out high-frequency glitches.

[0014] In another possible implementation, the first hysteresis voltage generating circuit includes a first current source and a second current source, an input terminal of the first current source and an input terminal of the second current source are connected to the power terminal, an output terminal of the first current source is connected to the second electrode of the first transistor, an output terminal of the second current source is connected to the second electrode of the second transistor, and a control terminal of the first current source and a control terminal of the second current source are connected to the output terminal of the comparator. In this way, the comparator can send a comparison result signal to the first current source and the second current source respectively, and the control terminal of the first current source can adjust the current of the first current source according to the comparison result signal after receiving the comparison result signal, so as to adjust the voltage at the output terminal of the first current source. Similarly, the voltage at the output terminal of the second current source can also be adjusted. The first hysteresis voltage generated by the first hysteresis voltage generating circuit is related to the voltage at the output terminal of the first current source and the voltage at the output terminal of the second current source, so the first hysteresis voltage can also be adjusted. In this way, the present application also provides another way to implement the first hysteresis voltage generating circuit, and the implementation structure is also relatively simple.

[0015] For the second hysteresis voltage generating circuit, in one possible implementation, the second hysteresis voltage generating circuit includes a first resistor and a second resistor, at least one of the first resistor and the second resistor is an adjustable resistor, a first terminal of the first resistor is connected to the power terminal, a second terminal of the first resistor is connected to a first terminal of the second resistor and connected to a first input terminal of the adder, and a second terminal of the second resistor is grounded, that is, the first resistor and the second resistor are connected in series. The output terminal of the second comparator is connected to the control terminal of the adjustable resistor, so that the second comparator can send a comparison result signal to the adjustable resistor, and the adjustable resistor can adjust the resistance value according to the received comparison result signal, so as to adjust the voltage at the second terminal of the first resistor and the first terminal of the second resistor, which is the second hysteresis voltage. By using the scheme of the first resistor and the second resistor connected in series, the implementation scheme can be relatively simple, the materials are easy to obtain, the implementation is easy, and the cost is relatively low.

[0016] Further, in one example, one of the first resistor and the second resistor is an adjustable resistor, for example, the first resistor is an adjustable resistor and the second resistor is a constant resistor; or, the second resistor is an adjustable resistor and the first resistor is a constant resistor. In another example, both the first resistor and the second resistor are adjustable resistors. In this way, the adjustment of the second hysteresis voltage can be more flexible.

[0017] In another possible implementation, the second hysteresis voltage generating circuit includes a voltage-controlled current source and a third resistor. The control terminal of the voltage-controlled current source is connected to the output terminal of the second comparator, so that the voltage-controlled current source can receive a comparison result signal from the output terminal of the second comparator and adjust the current according to the comparison result signal.

[0018] The input end of the voltage-controlled current source is connected to a power supply end, and the output end of the voltage-controlled current source is also connected to the first end of the third resistor, and the second end of the third resistor is grounded. In this way, the voltage-controlled current source is connected in series with the third resistor. The output end of the voltage-controlled current source is connected to the first input end of the adder. When the current of the voltage-controlled current source is adjusted, the voltage of the output end of the voltage-controlled current source will also be adjusted, and this voltage is the second hysteresis voltage. Thus, the application also provides another way to realize the second hysteresis voltage generation circuit, and the implementation structure is also relatively simple.

[0019] In some embodiments of the application, since the comparison result signal output by the comparator also contains a small amount of glitches with small amplitude, in order to eliminate these glitches and improve the noise suppression effect of the signal processing chip on the signal to be processed, the signal processing chip further comprises a glitch elimination circuit, the input end of the glitch elimination circuit is connected to the output end of the comparator, and the output end of the glitch elimination circuit is connected to the output end of the signal processing chip. Thus, the glitch elimination circuit can receive the comparison result signal output by the comparator and perform glitch elimination processing on the comparison result signal to eliminate the remaining glitches.

[0020] Further, the glitch elimination circuit comprises a first delay circuit, an AND gate, a second delay circuit and an OR gate, the input end of the first delay circuit and the first input end of the AND gate are both connected to the output end of the comparator, and the output end of the first delay circuit is connected to the second input end of the AND gate. In this way, the comparator can send the comparison result signal to the first delay circuit and the AND gate respectively, the first delay circuit can delay the comparison result signal to obtain a delayed comparison result signal and send it to the AND gate. The AND gate can receive the delayed comparison result signal and the comparison result signal directly sent by the comparator without delay, and perform AND operation on the two comparison result signals to retain the signals common to the two comparison result signals and remove the glitches outside the common signals to obtain the signal after AND operation.

[0021] The input end of the second delay circuit and the first input end of the OR gate are both connected to the output end of the AND gate, the output end of the second delay circuit is connected to the second input end of the OR gate, and the output end of the OR gate is connected to the output end of the signal processing chip. In this way, the AND gate can send the signal after AND operation to the second delay circuit and the OR gate respectively, the second delay circuit can delay the signal after AND operation to obtain a delayed signal and send it to the OR gate. The OR gate can receive the delayed signal and the signal after AND operation directly sent by the AND gate without delay, and perform OR operation on the two signals to retain any signal existing in the two comparison result signals to obtain the signal after AND operation. Thus, the glitches are eliminated without losing the comparison result signal output by the comparator.

[0022] In a second aspect, the present application provides an electronic device comprising a circuit board and the signal processing chip of any of the above embodiments, wherein the circuit board is electrically connected with the signal processing chip. The electronic device can achieve all the effects of the signal processing chip.

[0023] In a third aspect, the present application provides a signal processing method applied to a signal processing chip, wherein the chip comprises a low-pass filter, a comparator and a first hysteresis voltage generating circuit. The method comprises: receiving a to-be-processed signal by the low-pass filter, and performing low-pass filtering on the to-be-processed signal, and sending the low-pass filtered signal to the comparator; comparing, by the comparator, the low-pass filtered signal with a reference signal, obtaining a comparison result signal and outputting; receiving, by the first hysteresis voltage generating circuit, the comparison result signal and generating a first hysteresis voltage, and outputting the first hysteresis voltage, wherein the first hysteresis voltage is used to update the reference signal.

[0024] In the present application, the to-be-processed signal is first subjected to low-pass filtering, thereby reducing the large amplitude of the high-frequency noise in the to-be-processed signal; then the first hysteresis voltage generating circuit generates the first hysteresis voltage, and the low-pass filtered signal is compared with the first hysteresis voltage or the hysteresis voltage obtained by operation, thereby the noise with reduced amplitude can be suppressed. Therefore, the present application can suppress large-amplitude noise.

[0025] Based on this, the signal processing chip further comprises a second hysteresis voltage generating circuit and an adder, and after the step of comparing, by the comparator, the low-pass filtered signal with the reference signal, obtaining a comparison result signal and outputting, the signal processing method further comprises: receiving, by the second hysteresis voltage generating circuit, the comparison result signal and generating a second hysteresis voltage, and outputting the second hysteresis voltage to the adder; receiving, by the adder, the first hysteresis voltage and the second hysteresis voltage, and outputting a combined hysteresis voltage to the comparator, wherein the combined hysteresis voltage is related to the first hysteresis voltage and the second hysteresis voltage, and the combined hysteresis voltage is used to update the reference signal.

[0026] Moreover, the frequency of the second hysteresis voltage is lower than the frequency of the first hysteresis voltage. That is, the second hysteresis voltage generating circuit can generate a second hysteresis voltage with a lower frequency, thereby the noise with a lower frequency in the low-pass filtered signal output by the low-pass filter can be suppressed. The first hysteresis voltage generating circuit can generate a first hysteresis voltage with a higher frequency, thereby the noise with a higher frequency in the low-pass filtered signal output by the low-pass filter can be suppressed. Therefore, the present application can simultaneously suppress the noise with a higher frequency and the noise with a lower frequency.

[0027] Further, since the comparison result signal outputted by the comparator also contains a small amount of glitches with small amplitude, in order to eliminate the glitches and improve the noise suppression effect of the signal processing chip on the signal to be processed, the signal processing chip further comprises a glitch elimination circuit, after the step of comparing the low-pass filtered signal with the reference signal by the comparator to obtain the comparison result signal and outputting, the method further comprises: the glitch elimination circuit receives the comparison result signal outputted by the comparator, eliminates the glitches in the comparison result signal and then outputs, so that the remaining glitches in the comparison result signal can be eliminated. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative labor on the basis of these drawings.

[0029] Figure 1 The connection relationship between the reference clock source, the PLL and the radio frequency antenna is shown in the figure;

[0030] Figure 2 The structure schematic diagram of the clock signal processing module is shown in the figure; Figure 1

[0031] Figure 3 The circuit structure diagram of the clock signal processing module is shown in the figure; Figure 2

[0032] Figure 4 The output signal of the clock signal processing module is shown in the figure; Figure 3

[0033] Figure 5 The comparison of the output signals of the ordinary comparator and the comparator with hysteresis effect is shown in the figure;

[0034] Figure 6 The circuit structure diagram of the clock signal processing module is shown in the figure; Figure 2

[0035] Figure 7 The structure principle schematic diagram of the signal processing chip in the first embodiment of the present application is shown in the figure;

[0036] Figure 8 The structure principle schematic diagram of the signal processing chip in the second embodiment of the present application is shown in the figure;

[0037] Figure 9 The circuit structure diagram of the signal processing chip is shown in the figure; Figure 8 ​​​​​

[0038] Figure 10 For Figure 9 Port schematic diagram of any transistor in the application;

[0039] Figure 11 For Figure 9 Process schematic diagram of the comparison result signal sent by the spur elimination circuit to the comparator;

[0040] Figure 12 For Figure 8 Circuit structure diagram of the signal processing chip shown in Figure 2;

[0041] Figure 13 For Figure 8 Circuit structure diagram of the signal processing chip shown in Figure 3;

[0042] Figure 14 For Figure 8 Circuit structure diagram of the signal processing chip shown in Figure 4;

[0043] Figure 15 For Figure 8 Flowchart of signal processing amplification of the signal processing chip shown in Figure 5;

[0044] Figure 16 For Figure 9 Flowchart of signal processing amplification of the signal processing chip shown in Figure 6.

[0045] Icon: 10-reference clock source; 20-PLL; 30-clock signal processing module; 301-inverter; 302-hysteresis voltage generating circuit; 31-low pass filter; 32-comparator; 321-first stage comparator; 322-second stage comparator; 33-first hysteresis voltage generating circuit; 34-second hysteresis voltage generating circuit; 35-adder; 36-spur elimination circuit; 361-first delay circuit; 362-AND gate; 363-second delay circuit; 364-OR gate; 2-radio frequency antenna; 3-reference clock line. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0047] The term "and / or", merely used to describe associated objects, means that there can be three relationships, for example, A and / or B, can mean: A alone, A and B exist at the same time, B alone, three cases, where A, B can be singular or plural. The character " / " generally represents the "or" relationship between the associated objects before and after. "At least one" means one or more, and "multiple" means two or more. "At least one" or the like means any combination of these items, including single or multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0048] The terms "first" and "second" and the like in the description and claims of the present application are used to distinguish different objects, not to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, not to describe the specific order of the target objects.

[0049] The terms "connection", "connected", and the like are used to express the intercommunication or interaction between different components, which can include direct connection or indirect connection through other components. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, including a series of steps or units. The method, system, product or device does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", and the like are only used to describe the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, which can change accordingly according to the orientation of the components placed in the drawings.

[0050] In the embodiments of the present application, the words "exemplary" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" and the like is intended to present the relevant concept in a specific manner.

[0051] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. For example, multiple processing units mean two or more processing units; multiple systems mean two or more systems.

[0052] To facilitate understanding, the terms used in this application will be explained first.

[0053] Phase-locked loop (PLL): A feedback system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a target frequency, which can maintain the phase synchronization between the output signal and the input signal.

[0054] Reference clock: The reference clock provided to the PLL, which can be used by the PLL to perform operations such as frequency multiplication and phase alignment.

[0055] Wideband large swing noise: Due to external interference, the PLL's reference clock signal carries noise with complex frequency components and large amplitude. The frequency range of wideband large swing noise is 0.5MHz to 5GHz, and the amplitude reaches 500mV.

[0056] Hysteresis comparator: A comparator with hysteresis lap-loop propagation characteristics, which can also be understood as a single-limit comparator with positive feedback.

[0057] Digital-to-analog converter (DAC): Converts digital signals into analog signals.

[0058] Electronic devices such as mobile phones usually have features such as Figure 1 The reference clock source 10, PLL 20, and RF antenna 2 are shown. The reference clock source 10 can send a reference clock signal to the PLL 20, which can receive the reference clock signal and other data signals, and forward the data signals to the RF antenna 2. During the forwarding of data signals, the PLL 20 can maintain phase synchronization between the output data signal and the input data signal.

[0059] The port physical layer (PHY) internet protocol (IP) applied to the intelligent home open interconnection platform is used as a high-speed low-power interface (Serdes) IP, which effectively solves the bottleneck of data bandwidth demand of the camera and board-level signal integrity (SI). However, with the diversification of the layout of the mobile phone motherboard, especially the widespread popularity of folding screen mobile phones, the distance between the camera and the motherboard increases, and the length of the reference clock line 3 of the reference clock signal provided by the PLL 20 also increases, which causes the reference clock signal to be easily disturbed by the radio frequency antenna 2. That is, when the radio frequency antenna 2 transmits and receives signals, it will bring large amplitude and wide frequency domain interference noise to the reference clock signal, which can also be called a glitch. For example, the amplitude VPP of the interference noise is approximately 500 mV, and the frequency range is 0.7 GHz-5.5 GHz. After the reference clock signal with the glitch is transmitted to the PLL 20, the PLL 20 will lose lock. That is, the output signal of the PLL 20 cannot keep synchronization with the frequency and phase of the input signal. This situation can cause communication interruption, signal quality degradation, and other problems.

[0060] In order to eliminate the glitch brought by the radio frequency antenna 2 to the reference clock signal, as shown in Figure 2 , a clock signal processing module 30 can be arranged between the reference clock source 10 and the PLL 20. The clock signal processing module 30 can receive the reference clock signal sent by the reference clock source 10, and perform filtering and other processing on the reference clock signal, and send the filtered reference clock signal to the PLL 20, thereby ensuring the normal work of the PLL 20.

[0061] In a related technology, as shown in Figure 3 , the clock signal processing module 30 can include a capacitor C, a resistor R, and an inverter 301, wherein the first end of the capacitor C is used as the input end of the clock signal processing module 30, the second end of the capacitor C is connected with the input end of the inverter 301, and the output end of the inverter 301 is used as the output end of the clock signal processing module 30. The first end of the resistor R is connected with the input end of the inverter 301, and the second end of the resistor R is connected with the output end of the inverter 301. The capacitor C can be used to isolate the direct current component, and the resistor R can provide a common mode bias point when it is negatively fed back to the inverter 301.

[0062] The capacitor C can generally be used as a high-pass filter, that is, noise with a frequency lower than the cutoff frequency can be filtered out or reduced in amplitude. If the noise occurs at the flip side of the input signal, after being amplified by the inverter 301, a glitch as shown in Figure 4 will still be generated, and the reference clock signal with the glitch will cause the PLL 20 to lose lock when input to the PLL 20.

[0063] In another related art, the clock signal processing module 30 includes a plurality of transistors, which are combined to generate a hysteresis voltage, and the hysteresis voltage can be changed by adjusting the size ratio between the transistors. The larger the size ratio is, the larger the hysteresis voltage is. The larger the hysteresis voltage is, the larger the swing of the noise that can be filtered out is. However, when the size ratio is too large, the size of some transistors will be too large, which will cause adverse effects such as an increase in parasitic capacitance. Therefore, the hysteresis voltage generated by this scheme is usually small, and thus cannot suppress large-swing noise.

[0064] Based on this, an embodiment of the present application provides a signal processing chip. In one application scenario, the signal processing chip can be applied to processing of a clock signal. In one example, the signal processing chip can only include the clock signal processing module 30. That is, the clock signal processing module 30 can be installed as a separate chip with a circuit board, or packaged with other chips. In another example, in addition to the clock signal processing module 30 as shown in Figure 2 , the signal processing chip can also include the reference clock source 10 and the PLL 20 as shown in Figure 2 .

[0065] In another application scenario, the signal processing chip can be applied to a scenario of processing other types of signals in addition to the clock signal. For example, a data signal, etc.

[0066] In any of the above application scenarios, signal processing chips can be used in electronic devices. Besides the signal processing chip, the electronic device may also include a circuit board, and the signal processing chip is electrically connected to the circuit board. In this embodiment, the electronic device can be, for example, a server, consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronic products, etc., and this application embodiment does not impose any limitations on this. Illustrated, the aforementioned consumer electronics can be mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics can be smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. Automotive electronics can be in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can be automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can include servers, memory, radar, base stations, and other communication equipment.

[0067] Hysteresis can be suppressed by setting a hysteresis comparator with hysteresis effect in the clock signal processing module 30. Figure 2 The noise in the reference clock signal sent by the reference clock source 10 is shown. Here, a general-purpose comparator and a hysteresis comparator are respectively set in the clock signal processing module 30, and the signals output by the general-purpose comparator and the hysteresis comparator are compared. The comparison result is as follows. Figure 5 As shown. From Figure 5 As can be seen, when there is a lot of noise in the input signal (i.e., the reference clock signal), for example, when the voltage Vin curve of the input signal is not a smooth transition curve, a conventional comparator will respond to the input signal multiple times on the voltage flip edge, thus generating glitches. When these glitches are input to... Figure 2 Following the PLL20 shown will cause it to lose lock. A comparator with hysteresis dynamically adjusts the threshold voltage based on the output signal voltage Vout. For example, when the output signal voltage Vout changes from 1 to 0, the threshold voltage changes from VL to VH; when the output signal voltage Vout changes from 0 to 1, the threshold voltage changes from VH to VL, thus preventing glitches. Figure 5 As can be seen, the output signal of a conventional comparator has more glitches, while the output signal of a hysteresis comparator has almost no glitches. This demonstrates that the hysteresis comparator can eliminate glitches (i.e., noise) in the input signal.

[0068] Furthermore, based on the working principle of the hysteresis comparator, the following can be derived: Figure 6 The clock signal processing module 30 shown is... Figure 6 In the clock signal processing module 30, a comparator 32 and a hysteresis voltage generation circuit 302 are included. The hysteresis voltage generation circuit 302 generates a hysteresis voltage and sends it to the comparator 32. The hysteresis voltage generation circuit 302 and the comparator 32 are used together, and their function is equivalent to that of a hysteresis comparator. Therefore, Figure 6 The output signal of the clock signal processing module 30 shown is... Figure 5 The output signals of the hysteresis comparators shown are the same. Figure 6 The clock signal processing module 30 shown also has the function of eliminating glitches, that is, it has the function of suppressing noise.

[0069] Based on this, in this embodiment, as Figure 7 As shown, the clock signal processing module 30 may include a low-pass filter 31, a comparator 32, and a first hysteresis voltage generation circuit 33. The input terminal of the low-pass filter 31 is connected to the input terminal of the signal processing chip 1, the output terminal of the low-pass filter 31 is connected to the first input terminal of the comparator 32, the output terminal of the first hysteresis voltage generation circuit 33 is connected to the second input terminal of the comparator 32, the output terminal of the comparator 32 is connected to the input terminal of the first hysteresis voltage generation circuit 33, and the output terminal of the comparator 32 is connected to the output terminal of the signal processing chip 1.

[0070] Clock signal processing module 30 can process clock signals. Figure 2 The reference clock signal sent by the reference clock source 10 shown is processed by the waiting signal. During the processing, such as Figure 7 As shown, the low-pass filter 31 can receive the signal to be processed input from the input terminal of the signal processing chip 1, and perform low-pass filtering on the signal to be processed to reduce the noise swing in the signal to be processed that is higher than the cutoff frequency of the low-pass filter 31. For example, the noise swing higher than 1 GHz can be reduced to less than 50 mV to obtain the low-pass filtered signal, and send the low-pass filtered signal to the first input terminal of the comparator 32.

[0071] Comparator 32 receives the low-pass filtered signal from low-pass filter 31, compares the low-pass filtered signal with a reference signal to obtain a comparison result signal, and sends the comparison result signal to the first hysteresis voltage generation circuit 33. Simultaneously, it outputs the comparison result signal as an output signal from clock signal processing module 30. When processing the signal to be processed for the first time, the voltage of the reference signal can be a preset value.

[0072] The first hysteresis voltage generation circuit 33 generates a first hysteresis voltage based on the comparison result signal and sends the first hysteresis voltage to the second input terminal of the comparator 32. The comparison result signal contains a comparison result of 1 or 0. When the comparison result is 1, the first hysteresis voltage can be Vref1 + ΔV1; when the comparison result is 0, the first hysteresis voltage can be Vref1 - ΔV1. Here, Vref1 can be a preset reference voltage value, and ΔV1 can be a preset voltage change.

[0073] After receiving the first hysteresis voltage, comparator 32 can compare the voltage of the low-pass filtered signal sent by low-pass filter 31 with the first hysteresis voltage. Alternatively, it can perform correlation operations on the first hysteresis voltage to obtain the calculated hysteresis voltage, and then compare the voltage of the low-pass filtered signal with the calculated hysteresis voltage to obtain a comparison result signal. Comparator 32 can continue to send the comparison result signal to the first hysteresis voltage generation circuit 33, and can also output the comparison result signal as an output signal from the clock signal processing module 30.

[0074] In this embodiment, the signal to be processed is first subjected to low-pass filtering, which significantly reduces higher-frequency noise in the signal. Then, a first hysteresis voltage is generated by the first hysteresis voltage generation circuit 33, and the low-pass filtered signal is compared with the first hysteresis voltage or its calculated hysteresis voltage. Since the first hysteresis voltage generation circuit 33 and the comparator 32 function similarly to a hysteresis comparator, the reduced-swing noise output from the low-pass filter 31 can be suppressed. Therefore, this embodiment can suppress large-swing noise.

[0075] To further improve the noise suppression effect on the signal being processed, such as Figure 8 As shown, the clock signal processing module 30 may further include a second hysteresis voltage generation circuit 34 and an adder 35. The output of the comparator 32 is also connected to the input of the second hysteresis voltage generation circuit 34. Thus, the comparator 32 can send a comparison result signal to the second hysteresis voltage generation circuit 34, which generates a second hysteresis voltage upon receiving the comparison result signal. For example, the comparison result signal may contain a comparison result of 1 or 0. When the comparison result is 1, the second hysteresis voltage may be Vref2 + ΔV2; when the comparison result is 0, the second hysteresis voltage may be Vref2 - ΔV2. Vref2 may be a preset reference voltage value, and ΔV2 may be a preset voltage change. It is understood that Vref1 in the first hysteresis voltage and Vref2 in the second hysteresis voltage may be the same or different. Similarly, ΔV1 in the first hysteresis voltage and ΔV2 in the second hysteresis voltage may be the same or different.

[0076] like Figure 8As shown, the output of the second hysteresis voltage generation circuit 34 is connected to the first input of the adder 35, the output of the first hysteresis voltage generation circuit 33 is connected to the second input of the adder 35, and the output of the adder 35 is connected to the second input of the comparator 32. Thus, the first hysteresis voltage generation circuit 33 can send the first hysteresis voltage to the adder 35, and the second hysteresis voltage generation circuit 34 can send the second hysteresis voltage to the adder 35. The adder 35 can perform an addition operation on the first and second hysteresis voltages to obtain a combined hysteresis voltage, and then send the combined hysteresis voltage to the comparator 32 for comparison.

[0077] and, Figure 8 The frequency of the second hysteresis voltage output by the second hysteresis voltage generating circuit 34 is lower than the frequency of the first hysteresis voltage output by the first hysteresis voltage generating circuit 33. That is, the second hysteresis voltage generating circuit 34 can generate a lower frequency second hysteresis voltage, thereby suppressing lower frequency noise in the low-pass filtered signal output by the low-pass filter 31. The first hysteresis voltage generating circuit 33 can generate a higher frequency first hysteresis voltage, thereby suppressing higher frequency noise in the low-pass filtered signal output by the low-pass filter 31. Therefore, the combination of the low-pass filter 31 and the first hysteresis voltage generating circuit 33 can suppress higher frequency noise, for example, noise with a frequency higher than 1 GHz. The second hysteresis voltage generating circuit 34 can suppress lower frequency noise, for example, noise with a frequency between 100 MHz and 1 GHz. In other words, this embodiment can suppress both higher and lower frequency noise simultaneously, i.e., it can suppress wideband noise, thereby reducing noise. Figure 1 The interference caused by the radio frequency antenna 2 to the clock signal trace 3 is shown.

[0078] Furthermore, in this embodiment, comparator 32 can be a two-stage comparator, specifically, as follows: Figure 9As shown, comparator 32 may include a cascaded first-stage comparator 321 and a second-stage comparator 322. The input terminal of the first-stage comparator 321 serves as the input terminal of comparator 32, and the output terminal of the first-stage comparator 321 is connected to the input terminal of the second-stage comparator 322. The output terminal of the second-stage comparator 322 serves as the output terminal of comparator 32. The output terminal of the first-stage comparator 321 is connected to the input terminal of the first hysteresis voltage generation circuit 33, and the output terminal of the second-stage comparator 322 is connected to the input terminal of the second hysteresis voltage generation circuit 34. The output terminal of the first hysteresis voltage generation circuit 33 is connected to the input terminal of the second-stage comparator 322. In other words, the comparison result signal received by the first hysteresis voltage generation circuit 33 is the result signal obtained after one stage of comparison; while the comparison result signal received by the second hysteresis voltage generation circuit 34 is the result signal obtained after two stages of comparison. Therefore, compared to the second hysteresis voltage generation circuit 34, the comparison result signal received by the first hysteresis voltage generation circuit 33 is faster and has a higher frequency. This results in the generation frequency of the first hysteresis voltage being higher than that of the second hysteresis voltage.

[0079] Specifically, such as Figure 9 As shown, comparator 32 may include transistor M1 (first transistor), transistor M2 (second transistor), transistor M5, transistor M6, transistor M7, transistor M8, transistor M9, transistor M10, transistor M1, resistor R2, and resistor R3.

[0080] In this configuration, the first terminals of transistors M1, M2, M5, and M6, and the first terminal of resistor R2 are all connected to the power supply terminal VDD1. The second terminal of transistor M1 is connected to its control terminal and also to the control terminal of transistor M5. The second terminal of transistor M2 is connected to its control terminal and also to the control terminal of transistor M6. The second terminal of transistor M5 is connected to the first terminal of transistor M8 and also to its control terminal; the second terminal of transistor M8 is grounded. The second terminal of transistor M6 is connected to the first terminal of transistor M11 and also to the control terminal of transistor M8; the second terminal of transistor M11 is grounded. The second terminal of resistor R2 is connected to the first terminal of resistor R3 and also to the control terminal of transistor M7. The second terminal of transistor M7 is grounded. The second terminal of transistor M3 is connected to the first terminal of transistor M10. The second terminal of transistor M10 is connected to the first terminal of transistor M9. The control terminal of transistor M9 is connected to the control terminal of transistor M7; the second terminal of transistor M9 is grounded. Transistors M7, M8, M9, and M11 are all used for starting current.

[0081] like Figure 9As shown, the control terminal of transistor M10 can be used as the first input terminal a1 of comparator 32, the control terminal of transistor M2 can be used as the second input terminal a2 of comparator 32, and the second terminal of transistor M6 can be used as the output terminal b of comparator 32.

[0082] like Figure 9 As shown, transistors M1 and M2 can form a first-stage comparator 321, and transistors M5 and M6 can form a second-stage comparator 322.

[0083] It is understood that, for any transistor M in the embodiments of this application, the first terminal can be either the source (S) or the drain (D), and the second terminal can be either the source (S) or the drain (D). For example, the first terminal is the source (S) and the second terminal is the drain (D), or the first terminal is the drain (D) and the second terminal is the source (S). The control terminal can be the gate (G). The positional relationship of the three terminals of transistor M can be referred to... Figure 10 .

[0084] like Figure 9 As shown, in this embodiment, the low-pass filter 31 can be a resistor-capacitor (RC) filter. For example, the low-pass filter 31 may include a resistor R1 and a capacitor C1. The first terminal of resistor R1 serves as the input terminal IN of the clock signal processing module 30, and... Figure 2 The reference clock source 10 shown is electrically connected. The second terminal of resistor R1 is connected to the first terminal of capacitor C1, and the second terminal of capacitor C1 is grounded. In other embodiments, the low-pass filter 31 may also be a resistor-inductor-capacitor (RLC) filter, etc.

[0085] like Figure 9 As shown, the clock signal processing module 30 may further include capacitor C2, resistor R4, and resistor R5. The second terminal of resistor R1 in the low-pass filter 31 is connected to the first terminal of capacitor C2. The first terminal of resistor R4 is connected to the power supply terminal VDD2. The second terminals of resistor R4 and the first terminals of resistor R5 are both connected to the second terminal of capacitor C2 and to the control electrode of transistor M10, i.e., connected to the first input terminal of comparator 32. The second terminal of resistor R5 is grounded. Capacitor C2 can be a DC blocking capacitor. The function of resistors R4 and R5 is to provide a voltage bias point for the control electrode of transistor M10.

[0086] like Figure 9As shown, the first hysteresis voltage generating circuit 33 includes transistor M3 (the third transistor) and transistor M4 (the fourth transistor). The first terminals of transistors M3 and M4 are both connected to the power supply terminal VDD1. The control terminal of transistor M3 is connected to the second terminal of transistor M4 and also connected to the second terminal of transistor M1. The control terminal of transistor M4 is connected to the second terminal of transistor M3 and also connected to the second terminal of transistor M2. This generates a first hysteresis voltage of approximately 50mV, and the generation speed of the first hysteresis voltage is relatively fast, thus filtering out high-frequency glitches.

[0087] like Figure 9 As shown, the second hysteresis voltage generating circuit 34 may include resistor R6 (first resistor) and resistor R7 (second resistor), at least one of resistors R6 and R7 being an adjustable resistor. In one example, one of the first and second resistors is an adjustable resistor; for example, the first resistor is an adjustable resistor and the second resistor is a constant resistor; or, the second resistor is an adjustable resistor and the first resistor is a constant resistor. In another example, such as... Figure 9 As shown, both the first and second resistors are adjustable resistors.

[0088] like Figure 9 As shown, the first end of resistor R6 is connected to the power supply terminal VDD3, and the second end of resistor R6 is connected to the first end of resistor R7 and also to the first input terminal of adder 35. The second end of resistor R7 is grounded, meaning that resistors R6 and R7 are connected in series. The output terminal b of the second-stage comparator 322 is connected to the control terminal of the adjustable resistor. Figure 9 In this circuit, resistors R6 and R7 are both adjustable resistors. The output terminal b of the second-stage comparator 322 is connected to the control terminal of resistor R6 and also to the control terminal of resistor R7. Thus, the second-stage comparator 322 can send the comparison result signal to resistors R6 and R7. Resistors R6 and R7 can adjust their respective resistance values ​​according to the received comparison result signal, thereby adjusting the voltage at the connection point between the second terminal of resistor R6 and the first terminal of resistor R7. This connection point is the output terminal of the second hysteresis voltage generation circuit 34, and the voltage at this point is the second hysteresis voltage. Using resistors R6 and R7 in series makes the implementation simpler, more readily available, easier to implement, and lower in cost. Furthermore, when both resistors R6 and R7 are adjustable, the adjustment of the second hysteresis voltage becomes more flexible. Furthermore, since the resistance values ​​of resistors R6 and R7 need to be adjusted after receiving the comparison result signal sent by comparator 32, the response speed of the second hysteresis voltage generation circuit 34 is slower, and the frequency of the generated second hysteresis voltage is lower.

[0089] like Figure 9As shown, adder 35 may include transistor M12. The control terminal of transistor M12 can serve as the first input terminal of adder 35, connected to the output terminal of second hysteresis voltage generation circuit 34, i.e., connected to the second terminal of resistor R6 and the first terminal of resistor R7. The first terminal of transistor M12 can serve as the second input terminal of adder 35, connected to the output terminal of first hysteresis voltage generation circuit 33, i.e., connected to the second terminal of transistor M4. The second terminal of transistor M12 can serve as the output terminal of adder 35, connected to the input terminal of comparator 32. Second hysteresis voltage generation circuit 34 can control the voltage of control terminal of transistor M12, and first hysteresis voltage generation circuit 33 can control the voltage of first terminal of transistor M12. Transistor M12 can calculate the voltage of first terminal by the voltage of control terminal and the voltage of second terminal, thereby realizing the addition operation of first hysteresis voltage and second hysteresis voltage.

[0090] Since the comparison result signal output by comparator 32 still contains a small amount of small spikes, in order to eliminate these spikes and improve the noise suppression effect of the clock signal processing module 30 on the signal to be processed, such as... Figure 9 As shown, the clock signal processing module 30 also includes a glitch elimination circuit 36. The input terminal of the glitch elimination circuit 36 ​​is connected to the output terminal b of the comparator 32, and the output terminal of the glitch elimination circuit 36 ​​is connected to the output terminal OUT of the clock signal processing module 30. Therefore, the glitch elimination circuit 36 ​​can receive the comparison result signal output by the comparator 32 and perform glitch elimination processing on the comparison result signal to eliminate remaining glitches.

[0091] Furthermore, such as Figure 9 As shown, the glitch elimination circuit 36 ​​includes a first delay circuit 361, an AND gate 362, a second delay circuit 363, and an OR gate 364. The input terminals of the first delay circuit 361 and the first input terminal of the AND gate 362 are both connected to the output terminal of the comparator 32, and the output terminal of the first delay circuit 361 is connected to the second input terminal of the AND gate 362. Thus, as... Figure 11 As shown, comparator 32 can send the comparison result signal to the first delay circuit 361 and AND gate 362 respectively. The first delay circuit 361 can delay the comparison result signal to obtain a delayed comparison result signal, which is then sent to AND gate 362. AND gate 362 can receive the delayed comparison result signal and the undelayed comparison result signal directly sent by comparator 32, and perform an AND operation on these two comparison result signals. This retains the common signal between the two comparison result signals and removes glitches other than the common signal, obtaining the signal after the AND operation.

[0092] like Figure 9As shown, the input terminal of the second delay circuit 363 and the first input terminal of the OR gate 364 are both connected to the output terminal of the AND gate 362, the output terminal of the second delay circuit 363 is connected to the second input terminal of the OR gate 364, and the output terminal of the OR gate 364 is connected to the output terminal OUT of the clock signal processing module 30. Thus, as... Figure 11 As shown, AND gate 362 can send the AND-operated signal to the second delay circuit 363 and OR gate 364 respectively. The second delay circuit 363 can delay the AND-operated signal to obtain a delayed signal, and then send the delayed signal to OR gate 364. OR gate 364 can receive the delayed signal and the undelayed AND-operated signal directly sent by AND gate 362, perform an OR operation on these two signals, and retain either of the two comparison result signals to obtain the OR-operated signal. This ensures that the comparison result signal output by comparator 32 is not lost, thus eliminating glitches.

[0093] In addition, such as Figure 9 As shown, the clock signal processing module 30 may further include an inverter 301, which is connected between the comparator 32 and the glitch elimination circuit 36. Specifically, the input terminal of the inverter 301 is connected to the output terminal b of the comparator 32, and the output terminal of the inverter 301 is connected to the input terminal of the glitch elimination circuit 36.

[0094] In other embodiments of this application, such as Figure 12 As shown, with Figure 9 The difference between the embodiments shown lies in the structure of the first hysteresis voltage generating circuit 33 and the second hysteresis voltage generating circuit 34.

[0095] Specifically, such as Figure 12As shown, the first hysteresis voltage generating circuit 33 includes a first current source A1 and a second current source A2. The input terminals of both current source A1 and A2 are connected to a power supply. The output terminal of the first current source A1 is connected to the second terminal of transistor M1, and the output terminal of the second current source A2 is connected to the second terminal of transistor M2. The control terminals of the first and second current sources A1 and A2 are respectively connected to the output terminals of comparator 32. Therefore, comparator 32 can send comparison result signals to the first current source A1 and A2 respectively. After receiving the comparison result signal, the control terminal of the first current source A1 can adjust its current according to the comparison result signal, thereby adjusting the voltage at the output terminal of the first current source A1. Similarly, it can also adjust the voltage at the output terminal of the second current source A2. The first hysteresis voltage generated by the first hysteresis voltage generating circuit 33 is related to the voltage at the output terminals of the first current source A1 and A2, thus the first hysteresis voltage can also be adjusted. Therefore, this application embodiment also provides another way to implement the first hysteresis voltage generating circuit 33, and the structure of this implementation is also relatively simple.

[0096] like Figure 12 As shown, the second hysteresis voltage generating circuit 34 includes a voltage-controlled current source A3 and a resistor R7 (the third resistor). The control terminal of the voltage-controlled current source A3 is connected to the output terminal b of the second-stage comparator 322. Thus, the voltage-controlled current source A3 can receive the comparison result signal from the output terminal b of the second-stage comparator 322 and adjust its own current according to the comparison result signal.

[0097] like Figure 12 As shown, the input terminal of the voltage-controlled current source A3 is connected to the power supply terminal VDD3, and the output terminal of the voltage-controlled current source A3 is also connected to the first terminal of the resistor R7, while the second terminal of the resistor R7 is grounded. Thus, the voltage-controlled current source A3 and the resistor R7 are connected in series. The output terminal of the voltage-controlled current source A3 is connected to the first input terminal of the adder 35 (i.e., the control electrode of the transistor M12). When the current of the voltage-controlled current source A3 is adjusted, the voltage at the output terminal of the voltage-controlled current source A3 will also be adjusted accordingly. The output terminal of the voltage-controlled current source A3 is the output terminal of the second hysteresis voltage generating circuit 34, and therefore, the voltage at the output terminal of the voltage-controlled current source A3 is the second hysteresis voltage. Therefore, this embodiment of the application also provides another way to implement the second hysteresis voltage generating circuit 34, and this implementation method has a relatively simple structure.

[0098] In other embodiments of this application, such as Figure 13 As shown, with Figure 9 The difference between the illustrated embodiments lies in the structure of the first hysteresis voltage generating circuit 33. Specifically, in this embodiment, the first hysteresis voltage generating circuit 33 employs... Figure 12 The structure shown.

[0099] In other embodiments of this application, such as Figure 14 As shown, with Figure 9 The difference between the illustrated embodiments lies in the structure of the second hysteresis voltage generating circuit 34. Specifically, in this embodiment, the second hysteresis voltage generating circuit 34 employs... Figure 12 The structure shown.

[0100] This application also provides a signal processing method that can be applied to... Figure 7 The signal processing chip 1 shown is described. Figure 7 In the chip processing chip, there are a low-pass filter 31, a comparator 32 and a first hysteresis voltage generation circuit 33.

[0101] like Figure 15 As shown, signal processing methods may include:

[0102] S151, the low-pass filter receives the signal to be processed, performs low-pass filtering on the signal to be processed, and sends the low-pass filtered signal to the comparator.

[0103] like Figure 7 As shown, the low-pass filter 31 can receive the signal to be processed input from the input terminal of the clock signal processing module 30, and perform low-pass filtering on the signal to be processed to reduce the signal swing of the signal to be processed that is higher than the cutoff frequency of the low-pass filter 31. For example, the noise swing higher than 1 GHz can be reduced to less than 50 mV to obtain the low-pass filtered signal, and the low-pass filtered signal can be sent to the first input terminal of the comparator 32.

[0104] S152, the comparator compares the low-pass filtered signal with the reference signal to obtain the comparison result signal.

[0105] Comparator 32 compares the low-pass filtered signal with the reference signal to obtain a comparison result signal, and sends the comparison result signal to the first hysteresis voltage generation circuit 33. When the signal to be processed is processed for the first time, the voltage of the reference signal can be a preset value.

[0106] S153, the first hysteresis voltage generation circuit receives the comparison result signal and generates the first hysteresis voltage, and outputs the first hysteresis voltage.

[0107] In this embodiment, the first hysteresis voltage generation circuit 33 can output a first hysteresis voltage to the comparator 32, and the first hysteresis voltage is used to update the reference signal. That is, the voltage of the reference signal can be the first hysteresis voltage, or a hysteresis voltage obtained by performing calculations on the first hysteresis voltage. After receiving the first hysteresis voltage, the comparator 32 can compare the low-pass filtered signal sent by the low-pass filter 31 with the first hysteresis voltage, or it can perform correlation operations on the first hysteresis voltage to obtain the calculated hysteresis voltage, and compare the low-pass filtered signal with the calculated hysteresis voltage to obtain a comparison result signal.

[0108] S154, the comparator outputs the comparison result signal.

[0109] In this embodiment, the signal to be processed is first subjected to low-pass filtering to reduce the large swing of higher frequency noise in the signal; then, a first hysteresis voltage is generated by the first hysteresis voltage generation circuit 33, and the low-pass filtered signal is compared with the first hysteresis voltage or its calculated hysteresis voltage, thereby suppressing the noise after the swing is reduced. Therefore, this embodiment can suppress large swing noise.

[0110] Other embodiments of this application also provide a signal processing method that can be applied to... Figure 8 The clock signal processing module 30 is shown. Figure 8 In the clock signal processing module 30, there are a low-pass filter 31, a comparator 32, a first hysteresis voltage generation circuit 33, a second hysteresis voltage generation circuit 34, an adder 35, and a glitch elimination circuit 36.

[0111] like Figure 16 As shown, signal processing methods may include:

[0112] S161, the low-pass filter receives the signal to be processed, performs low-pass filtering on the signal to be processed, and sends the low-pass filtered signal to the comparator.

[0113] Reference Figure 15 The steps shown in step S151 are executed and will not be repeated here.

[0114] S162, the comparator compares the low-pass filtered signal with the reference signal, obtains the comparison result signal and outputs it.

[0115] Comparator 32 can send the comparison result signal to the first hysteresis voltage generation circuit 33 and the second hysteresis voltage generation circuit 34.

[0116] S163, the first hysteresis voltage generating circuit receives the comparison result signal and generates the first hysteresis voltage, and outputs the first hysteresis voltage.

[0117] ReferenceFigure 15 The step S153 shown is executed.

[0118] S164, the second hysteresis voltage generation circuit receives the comparison result signal and generates the second hysteresis voltage, and outputs the second hysteresis voltage to the adder.

[0119] The second hysteresis voltage generating circuit 34 can generate a second hysteresis voltage after receiving the comparison result signal. For example, the comparison result signal contains a comparison result of 1 or 0. When the comparison result is 1, the first hysteresis voltage can be Vref + ΔV; when the comparison result is 0, the first hysteresis voltage can be Vref - ΔV.

[0120] S165, the adder receives the first hysteresis voltage and the second hysteresis voltage, and outputs the combined hysteresis voltage to the comparator.

[0121] In this embodiment, the combined hysteresis voltage is related to the first hysteresis voltage and the second hysteresis voltage. For example, the combined hysteresis voltage can be obtained by adding the first hysteresis voltage and the second hysteresis voltage. The combined hysteresis voltage is used to update the reference signal, that is, the voltage of the reference signal is set to the combined hysteresis voltage.

[0122] Furthermore, the frequency of the second hysteresis voltage is lower than the frequency of the first hysteresis voltage. That is, the second hysteresis voltage generating circuit 34 can generate a lower frequency second hysteresis voltage, thereby suppressing lower frequency noise in the low-pass filtered signal output by the low-pass filter 31. The first hysteresis voltage generating circuit 33 can generate a higher frequency first hysteresis voltage, thereby suppressing higher frequency noise in the low-pass filtered signal output by the low-pass filter 31. Therefore, the embodiments of this application can suppress both higher and lower frequency noise simultaneously.

[0123] S166, the glitch elimination circuit receives the comparison result signal output by the comparator, and outputs the comparison result signal after glitch elimination.

[0124] The glitch elimination circuit 36 ​​can receive the comparison result signal output by the comparator 32 and perform glitch elimination processing on the comparison result signal to eliminate the remaining glitch.

[0125] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A signal processing chip, characterized by, The signal processing chip comprises a low-pass filter, a comparator and a first hysteresis voltage generating circuit, an input end of the low-pass filter is connected with an input end of the signal processing chip, an output end of the low-pass filter is connected with a first input end of the comparator, an output end of the first hysteresis voltage generating circuit is connected with a second input end of the comparator, an output end of the comparator is connected with an input end of the first hysteresis voltage generating circuit, and an output end of the comparator is connected with an output end of the signal processing chip. The signal processing chip further comprises a second hysteresis voltage generating circuit and an adder, an output end of the second hysteresis voltage generating circuit is connected with a first input end of the adder, an output end of the first hysteresis voltage generating circuit is connected with a second input end of the adder, an output end of the adder is connected with a second input end of the comparator, and an output end of the comparator is further connected with an input end of the second hysteresis voltage generating circuit.

2. The signal processing chip of claim 1, wherein, The frequency of the hysteresis voltage output by the second hysteresis voltage generating circuit is lower than the frequency of the hysteresis voltage output by the first hysteresis voltage generating circuit. The comparator comprises a first-stage comparator and a second-stage comparator connected in cascade, an input end of the first-stage comparator serves as an input end of the comparator, an output end of the first-stage comparator is connected with an input end of the second-stage comparator, and an output end of the second-stage comparator serves as an output end of the comparator.

3. The signal processing chip of claim 2, wherein, An output end of the first-stage comparator is connected with an input end of the first hysteresis voltage generating circuit, and an output end of the second-stage comparator is connected with an input end of the second hysteresis voltage generating circuit. The first-stage comparator comprises a first transistor and a second transistor, a first pole of the first transistor and a first pole of the second transistor are both connected with a power supply end, a second pole of the first transistor is connected with a control pole, and a second pole of the second transistor is connected with a control pole.

4. The signal processing chip of claim 3, wherein, The first hysteresis voltage generating circuit comprises a third transistor and a fourth transistor, a first pole of the third transistor and a first pole of the fourth transistor are both connected with a power supply end, a control pole of the third transistor is connected with a second pole of the fourth transistor and connected with a second pole of the first transistor, and a control pole of the fourth transistor is connected with a second pole of the third transistor and connected with a second pole of the second transistor. The comparator comprises a first-stage comparator and a second-stage comparator connected in cascade, the first-stage comparator comprises a first transistor and a second transistor, a first pole of the first transistor and a first pole of the second transistor are both connected with a power supply end, a second pole of the first transistor is connected with a control pole, and a second pole of the second transistor is connected with a control pole.

5. The signal processing chip of claim 2, wherein, ​ The first hysteresis voltage generating circuit comprises a first current source and a second current source, an input end of the first current source and an input end of the second current source are connected to a power supply end, an output end of the first current source is connected to a second electrode of the first transistor, an output end of the second current source is connected to a second electrode of the second transistor, and a control end of the first current source and a control end of the second current source are connected to an output end of the comparator.

6. The signal processing chip according to any one of claims 3-5, characterized in that, The second hysteresis voltage generating circuit comprises a first resistor and a second resistor, at least one of the first resistor and the second resistor is an adjustable resistor, a first end of the first resistor is connected to a power supply end, a second end of the first resistor is connected to a first end of the second resistor and connected to a first input end of the adder, and a second end of the second resistor is grounded, and an output end of the second-stage comparator is connected to a control end of the adjustable resistor.

7. The signal processing chip of claim 6, wherein, The first resistor and the second resistor are both adjustable resistors.

8. The signal processing chip according to any one of claims 3-5, characterized in that, The second hysteresis voltage generating circuit comprises a voltage-controlled current source and a third resistor, an input end of the voltage-controlled current source is connected to a power supply end, a control end of the voltage-controlled current source is connected to an output end of the second-stage comparator, an output end of the voltage-controlled current source is connected to a first input end of the adder, and the output end of the voltage-controlled current source is also connected to a first end of the third resistor, and a second end of the third resistor is grounded.

9. The signal processing chip according to any one of claims 1 to 8, characterized in that, The signal processing chip further comprises a glitch elimination circuit, an input end of the glitch elimination circuit is connected to an output end of the comparator, and an output end of the glitch elimination circuit is connected to an output end of the signal processing chip.

10. The signal processing chip of claim 9, wherein, The glitch elimination circuit comprises a first delay circuit, an AND gate, a second delay circuit and an OR gate, an input end of the first delay circuit and a first input end of the AND gate are both connected to an output end of the comparator, an output end of the first delay circuit is connected to a second input end of the AND gate; an input end of the second delay circuit and a first input end of the OR gate are both connected to an output end of the AND gate, an output end of the second delay circuit is connected to a second input end of the OR gate, and an output end of the OR gate is connected to an output end of the signal processing chip.

11. An electronic device, comprising: The circuit board is electrically connected with the signal processing chip.

12. A signal processing method, characterized by, The method is applied to a signal processing chip, and the chip processing chip comprises a low-pass filter, a comparator and a first hysteresis voltage generating circuit, and the method comprises: The low-pass filter receives a signal to be processed and performs low-pass filtering on the signal to be processed, and sends a signal filtered by low-pass filtering to the comparator; The comparator compares the signal filtered by low-pass filtering with a reference signal, obtains a comparison result signal and outputs the comparison result signal; The first hysteresis voltage generating circuit receives the comparison result signal and generates a first hysteresis voltage, and outputs the first hysteresis voltage, and the first hysteresis voltage is used to update the reference signal.

13. The signal processing method of claim 12, wherein, The signal processing chip further comprises a second hysteresis voltage generating circuit and an adder, after the step of the comparator comparing the low-pass filtered signal with a reference signal, obtaining a comparison result signal and outputting, the method further comprises: The second hysteresis voltage generating circuit receives the comparison result signal and generates a second hysteresis voltage, and outputs the second hysteresis voltage to the adder, the frequency of the second hysteresis voltage is lower than the frequency of the first hysteresis voltage; The adder receives the first hysteresis voltage and the second hysteresis voltage, and outputs a combined hysteresis voltage to the comparator, the combined hysteresis voltage is related to the first hysteresis voltage and the second hysteresis voltage, and the combined hysteresis voltage is used to update the reference signal.

14. The signal processing method of claim 12 or 13, characterized by, The signal processing chip further comprises a glitch elimination circuit, after the step of the comparator comparing the low-pass filtered signal with a reference signal, obtaining a comparison result signal and outputting, the method further comprises: The glitch elimination circuit receives the comparison result signal output by the comparator and outputs after glitch elimination.

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