Clock-free self-tuning RFID tag

Abstract

A self-tuning apparatus and related methods include: a self-tuning device; a first voltage indicative of a first amplitude of an input signal to an antenna stored in a first capacitor when a variable capacitor bank coupled to the antenna is in a first configuration and a second voltage indicative of a second amplitude of the input signal when the variable capacitor bank is in a second configuration are compared. A first output signal based on the comparison is used to determine that the first configuration of the variable capacitor bank is an optimized configuration of the variable capacitor bank. The variable capacitor bank is configured in the first configuration.

Description

Technical Field

[0001] The present invention generally relates to radio frequency identification (RFID) tag devices, and more specifically, to systems and methods for tuning the antenna of an RFID tag to optimize the power signal generated by the RFID tag. Background Technology

[0002] Radio Frequency Identification (RFID) is a wireless system consisting of two components: a tag and a reader. The reader is a device with one or more antennas that transmit radio waves and receive signals returned from the RFID tag. Tags that use radio waves to transmit their identity and other information to a nearby reader can be passive or active. Passive RFID tags can be powered by the reader and do not have batteries. Active RFID tags can be battery-powered. Near Field Communication (NFC) is a wireless communication technology that enables bidirectional communication over short distances. NFC tags are increasingly used in multiple markets, including medical, consumer, retail, industrial, automotive, and smart grid markets. NFC is a type of RFID technology. Due to internal or external factors, such as distance from another device or tag, nearby objects, etc., the tag antenna needs to be tuned to balance antenna impedance before a data reading cycle begins, thereby optimizing the received signal strength. Summary of the Invention

[0003] According to a first aspect of the present invention, a radio frequency identification (RFID) tag is provided, comprising:

[0004] An antenna configured to receive input signals;

[0005] A variable capacitor bank electrically coupled to the antenna; and

[0006] A self-tuning circuit coupled to the antenna, wherein the self-tuning circuit is configured to modify the capacitance of the variable capacitor bank according to a self-tuning algorithm to optimize the signal strength of the input signal, wherein the self-tuning circuit does not include a clock source, and the self-tuning circuit includes:

[0007] The first comparator includes:

[0008] A first capacitor, configured to store a first voltage indicating a first amplitude of the input signal when the variable capacitor bank is in a first configuration, and

[0009] A first comparator device has a first input terminal and a second input terminal, wherein the first input terminal is configured to receive a second voltage indicating a second amplitude of the input signal when the variable capacitor bank is in a second configuration, and the second input terminal is configured to receive the first voltage from the first capacitor, wherein the first comparator device is configured to generate a first output signal based on the difference between the first voltage and the second voltage; and

[0010] A controller is configured to use the first output signal of the first comparator device to determine that the first configuration of the variable capacitor bank is an optimal configuration of the variable capacitor bank compared to the second configuration, and to configure the variable capacitor bank with the first configuration.

[0011] In one or more embodiments, the RFID tag further includes:

[0012] The second comparator includes:

[0013] The second capacitor, and

[0014] A second comparator device has a first input terminal and a second input terminal, wherein the first input terminal is configured to receive an input signal and the second input terminal is configured to be connected to the second capacitor.

[0015] In one or more embodiments, the controller is configured to:

[0016] When the variable capacitor bank is in the first configuration, the second capacitor stores the first voltage indicating the first amplitude of the input signal;

[0017] A threshold voltage is applied to the first input terminal of the second comparator device, wherein the threshold voltage is the minimum voltage value of the self-tuning circuit; and

[0018] The second capacitor is connected to a ground node to discharge the second capacitor, wherein the second comparator device generates a low output value when the voltage of the second capacitor is greater than the threshold voltage, and generates a high output value when the voltage of the second capacitor is less than the threshold voltage.

[0019] In one or more embodiments, the controller is configured to:

[0020] The output of the second comparator device has changed from the low output value to the high output value; and

[0021] The self-tuning circuit terminates the execution of the self-tuning algorithm.

[0022] In one or more embodiments, the controller is configured to reset the self-tuning circuit by discharging the first capacitor to the ground node and the second capacitor to the ground node before executing the self-tuning algorithm.

[0023] In one or more embodiments, the first voltage indicating the first amplitude of the input signal and the threshold voltage are generated by a voltage divider electrically connected to the antenna.

[0024] In one or more embodiments, a rectifier is connected between the voltage divider and the antenna.

[0025] In one or more embodiments, the first comparator is configured to generate the first output signal without receiving or using an oscillating clock signal.

[0026] According to a second aspect of the present invention, an apparatus is provided, comprising:

[0027] The first comparator includes:

[0028] A first capacitor, configured to store a first voltage indicating a first amplitude of an input signal when a variable capacitor bank coupled to the antenna is in a first configuration, and

[0029] A first comparator device has a first input terminal and a second input terminal, wherein the first input terminal is configured to receive a second voltage indicating a second amplitude of the input signal when the variable capacitor bank is in a second configuration, and the second input terminal is configured to receive the first voltage from the first capacitor, wherein the first comparator device is configured to generate a first output signal based on the difference between the first voltage and the second voltage; and

[0030] A controller configured to determine the configuration of the variable capacitor bank using the first output signal of the first comparator device.

[0031] In one or more embodiments, the device further includes:

[0032] The second comparator includes:

[0033] The second capacitor, and

[0034] A second comparator device has a first input terminal and a second input terminal, wherein the first input terminal is configured to receive an input signal and the second input terminal is configured to be connected to the second capacitor.

[0035] In one or more embodiments, the controller is configured to:

[0036] When the variable capacitor bank is in the first configuration, the second capacitor stores the first voltage indicating the first amplitude of the input signal;

[0037] A threshold voltage is applied to the first input terminal of the second comparator device, wherein the threshold voltage is a minimum voltage value of the device; and

[0038] The second capacitor is connected to a ground node to discharge the second capacitor, wherein the second comparator device generates a low output value when the voltage of the second capacitor is greater than the threshold voltage, and generates a high output value when the voltage of the second capacitor is less than the threshold voltage.

[0039] In one or more embodiments, the first voltage indicating the first amplitude of the input signal and the threshold voltage are generated by a voltage divider electrically connected to the antenna.

[0040] In one or more embodiments, a rectifier is connected between the voltage divider and the antenna.

[0041] In one or more embodiments, the first comparator is configured to generate the first output signal without receiving or using an oscillating clock signal.

[0042] According to a third aspect of the present invention, a method for performing a self-tuning algorithm on a radio frequency identification tag is provided, comprising:

[0043] When the variable capacitor bank of the antenna coupled to the first capacitor is in the first configuration, a first voltage indicating the first amplitude of the input signal is stored in the antenna;

[0044] When the variable capacitor bank is in the second configuration, a second voltage indicating the second amplitude of the input signal is provided to the first input terminal of the first comparator device;

[0045] The first voltage is provided from the first capacitor to the second input of the first comparator device, wherein the first comparator device is configured to generate a first output signal based on the difference between the first voltage and the second voltage;

[0046] Using the first output signal of the first comparator device, it is determined that the first configuration of the variable capacitor bank is an optimal configuration of the variable capacitor bank compared to the second configuration; and

[0047] Configure the variable capacitor bank according to the first configuration.

[0048] In one or more embodiments, the method further includes providing a second comparator having a first input configured to receive an input signal, wherein a second input of the second comparator is connected to a second capacitor.

[0049] In one or more embodiments, the method further includes:

[0050] When the variable capacitor bank is in the first configuration, the second capacitor stores the first voltage indicating the first amplitude of the input signal;

[0051] A threshold voltage is applied to the first input terminal of the second comparator device, wherein the threshold voltage is a minimum voltage value; and

[0052] The second capacitor is connected to a ground node to discharge the second capacitor, wherein the second comparator device generates a low output value when the voltage of the second capacitor is greater than the threshold voltage, and generates a high output value when the voltage of the second capacitor is less than the threshold voltage.

[0053] In one or more embodiments, the method further includes:

[0054] The output of the second comparator device has changed from the low output value to the high output value; and

[0055] The self-tuning algorithm is terminated.

[0056] In one or more embodiments, the method further includes using a voltage divider to generate a first voltage and a threshold voltage that indicate the first amplitude of the input signal.

[0057] In one or more embodiments, the method additionally generates the first output signal without receiving or using an oscillating clock signal.

[0058] These and other aspects of the invention will become apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description

[0059] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0060] In the attached diagram:

[0061] Figure 1 A schematic diagram of an embodiment of an RFID tag including an antenna is shown.

[0062] Figure 2 This is a block diagram depicting the functional components of the RFID tag self-tuning system disclosed herein.

[0063] Figure 3 This is a flowchart depicting a method that can be implemented by an RFID tag controller, the method being designed to optimize the configuration of a capacitor bank coupled to the tag antenna to optimize power coupling from the ambient electric field to the antenna.

[0064] Figure 4 This is a circuit diagram depicting an example RFID tag self-tuning circuit configured according to this disclosure.

[0065] Figure 5 It is a description that can be made by Figure 4 The flowchart illustrates a method for implementing a controller for a self-tuning circuit of an RFID tag, the method being designed to implement a self-tuning algorithm to determine the optimal configuration of the RFID tag's antenna.

[0066] Figure 6 This is a flowchart depicting an example method implemented by an RFID tag controller to perform the tag initiation process.

[0067] Figure 7 This is a flowchart depicting an example method implemented by an RFID controller to perform this signal acquisition.

[0068] Figure 8 This is a flowchart depicting an example method implemented by the controller of an RFID tag to perform a signal comparison step. Detailed Implementation

[0069] The present invention generally relates to radio frequency identification (RFID) tag devices, and more specifically, to systems and methods for tuning the antenna of an RFID tag to optimize the power signal generated by the RFID tag.

[0070] It is readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of various embodiments as illustrated in the accompanying drawings is not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. Although various aspects of the embodiments are presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0071] The invention may be implemented in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments should be considered in all respects as illustrative rather than restrictive. Therefore, the scope of the invention is indicated by the appended claims, not by a detailed description thereof. All modifications falling within the equivalent meaning and scope of the claims should be included within their scope.

[0072] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable with the invention should be included in or in any single embodiment of the invention. In fact, language relating to features and advantages should be understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, discussions of features and advantages throughout this specification, as well as similar language, may (but not necessarily) refer to the same embodiment.

[0073] Furthermore, the features, advantages, and characteristics described in this invention may be combined in any suitable manner in one or more embodiments. Those skilled in the art will recognize that, in view of the description herein, this invention may be practiced without one or more of a particular feature or advantage in a specific embodiment. In other instances, additional features and advantages that may not be present in all embodiments of the invention may be recognized in certain embodiments.

[0074] Throughout this specification, references to "an embodiment," "an embodiment," "an example," or similar language mean that a particular feature, structure, or characteristic described in connection with a specified embodiment is included in at least one embodiment of the invention. Therefore, throughout this specification, the phrases "in one embodiment," "in an embodiment," and similar language may (but not necessarily) all refer to the same embodiment.

[0075] Radio frequency identification (RFID) tags can store a wide range of information, from a single serial number to several pages of data. For example, near field communication (NFC) is a technology based on RFID.

[0076] In active peer-to-peer (P2P) operation mode, two active RFID tag devices can establish a wireless communication channel between them. In this mode, the active device, powered by an external power source, can power the passive device, which emits an electromagnetic field. In typical applications, passive NFC devices are used because a passive NFC device can be a simple tag whose electronic circuitry can be powered by the electromagnetic field emitted by the active device.

[0077] As observed with passive devices, the strength of the received electromagnetic field (and therefore the ability of that field to power the passive device) can depend on the distance between the passive and active devices, as well as external factors such as nearby objects, other ambient electric fields, etc. Therefore, in some cases, a passive device may be able to tune its antenna to improve its ability to absorb energy from the electric field emitted by the active device, thereby improving power delivery to the passive device. In various approaches, this may involve configuring the passive device to include a switchable capacitor bank coupled to its antenna. By adjusting the capacitance value of the switchable capacitor bank, the passive device can “tune” its antenna to improve power delivery. Specifically, the input impedance of the passive device’s receiver antenna can be adjusted or tuned by changing the capacitance value of the capacitor bank to optimize the signal strength of the input signal destined for the passive device.

[0078] Figure 1 A schematic diagram of an embodiment of an RFID tag 100 including an antenna 102 is shown. The antenna 102 may be a coil antenna. The antenna 102 absorbs energy from the ambient electromagnetic field and provides the energy as an input AC signal to a charge pump (e.g., an AC-to-DC converter) 104, which accumulates the electrical energy received from the antenna 102 to ultimately generate a usable output DC voltage.

[0079] Typically, the energy absorbed by antenna 102 is in the form of a continuous wave with a predefined frequency (e.g., 13.56 MHz). Charge pump 104 receives the AC signal and converts it into a DC voltage. Charge pump 104 can use a diode and a charge / discharge capacitor to convert the input AC signal into a higher voltage DC signal. When the input AC signal is positive, current flows through the diode and charges the capacitor, and during the negative cycle, no current flows through the diode and the capacitor discharges.

[0080] The charge pump 104 may include or be coupled to a limiter circuit 110. The limiter circuit 110 limits the output of the charge pump 104 to a predefined voltage. The limiter circuit 110 can be used to protect components of the RFID tag 100 from electrical spikes that may be caused by electrostatic events or excessively high received signal strength for the safe operation of the RFID tag 100.

[0081] The RFID tag 100 includes an envelope detector 116 for receiving the envelope of the input signal from the antenna 102 to provide a DC output. An envelope detector (or peak detector) is an electronic circuit that takes a (relatively) high-frequency amplitude-modulated signal as input and provides the envelope of the original signal as output.

[0082] The RFID tag 100 includes a processing system 114 configured to optimize the input signal strength based on a signal from a detector 108. The signal from the detector 108 may include information about changes in the signal strength of the input AC signal received via the antenna 102, enabling the processing system 114 to optimize the input signal strength, in one example by changing the input impedance of the antenna 102 of the RFID tag 100. In this case, the processing system 114 may be configured to modify the configuration of an adjustable capacitor bank coupled to the antenna 102 to optimize power delivery to the antenna 102.

[0083] In RFID tag 100, processing system 114 is responsible for configuring antenna 102 and any connected adjustable capacitor bank to optimize power delivery from any ambient electromagnetic field entering antenna 102 for use by RFID tag 100. In conventional RFID tags, any such processing system 114 can be used as a time-controlled finite state machine (FSM) to control the overall operation of RFID tag 100.

[0084] The routine operation of the processing system 114 in controlling the configuration of antenna 102 typically requires implementing an FSM (Functional Simulation) to enable the RFID tag 100 component to detect the power level of the signal currently received at antenna 102 of the RFID tag 100, and then, based on the analysis of the signal amplitude, configure a tunable input impedance and a circuit that adjusts the input impedance of antenna 102 based on the signal amplitude measurement. These functions are typically provided by standard synchronous digital logic circuitry in the processing system 114. Such circuitry requires an oscillator operating at a specific frequency as a system clock to control and enable the operation of the digital logic system. The power required to operate such an oscillator and circuitry is not negligible, thus significantly consuming the power of a conventional RFID tag 100, which may negatively impact the performance of such systems.

[0085] To address the problems associated with traditional tuning methods (i.e., implemented with digital logic), this disclosure provides an alternative method for antenna tuning in RFID tags, which utilizes analog logic circuitry to execute the tuning algorithm. In embodiments, this disclosure provides a clockless self-tuning circuit for antenna tuning in RFID devices, offering a non-clock-driven antenna tuning method that optimizes power usage within the RFID tag device. Specifically, this method reduces power consumption of components required to provide clock signals and other digital logic control circuitry, and mitigates the risk that such oscillators may fail to power on in environments with relatively low amplitude electromagnetic fields.

[0086] This disclosure presents a system in which a self-tuning algorithm and components are operated using an asynchronous signal derived from a signal received at the antenna of an RFID tag. Specifically, without using an input clock signal, aspects of the self-tuning system are configured to detect changes in the amplitude of the signal received by the antenna of the RFID tag, caused by changes in antenna impedance, as a mechanism to optimize the antenna configuration and reduce power consumption compared to conventional methods.

[0087] Figure 2 This is a block diagram depicting the functional components of the RFID tag self-tuning system 200 of this disclosure. The RFID tag self-tuning system 200 includes an antenna 202 located within an ambient electric field 204. The antenna 202 is connected to a capacitor bank 206. The tuning capacitor bank 206 is a component whose capacitance value can be adjusted by electrically connecting or disconnecting different combinations of individual capacitors within the capacitor bank 206. Typically, the capacitor bank 206 is implemented by a collection of capacitors and switches, such that different capacitor combinations (each capacitor combination may have the same capacitance value or different capacitance values) can be electrically connected within the capacitor bank 206 to adjust their inductance and the impedance of the connected antenna 202.

[0088] A power supply and detector 208 is coupled to antenna 202 and configured to receive an electrical signal generated by ambient electric field 204 from antenna 202. The power supply and detector 208 is configured to use the electrical signal to provide electrical power to other components of the self-tuning system 200 (e.g., by using a charge pump), as described herein, and to output a measurement indicating the amplitude of the electrical signal received from antenna 202.

[0089] The power management unit (PMU) 210 is configured to control the operability of the RFID tag self-tuning system 200 based on the amplitude of the power supply signal received from the power supply and detector 208. In an example operating mode, the PMU 210 is a control system configured to maintain various components of the self-tuning system (e.g., in both the analog and digital domains) in a reset state (i.e., state "0") until signals received from the power supply and detector 208 indicate that the power supply signal is sufficient, meeting all power-on conditions of the self-tuning system 200. Once those conditions are met, the PMU 210 is configured to leave the reset conditions and assert the SA_start_ok signal, enabling the self-tuning system 200 to transition to its first operating state (i.e., state "1"), as detailed below.

[0090] The self-tuning system 200 includes two signal sampling circuits, namely sampler 212 and sampler 214. The operation of these sampling circuits is described in more detail below; however, generally speaking, sampler 212 and sampler 214 are configured to acquire proportional samples of the power supply signal generated by the power supply and detector 208. The output of sampler 212, equal to the amplitude of the power supply signal received from the power supply and detector 208, is provided as input to the input power enhancement detector 216. The input power enhancement detector 216 is configured to determine whether the current amplitude of the sampled signal acquired by the capacitor bank 206 in its current configuration is greater than the amplitude of the sampled signal acquired by the capacitor bank 206 in a different configuration. Therefore, this comparison enables the self-tuning circuit 200 to identify in which configuration of the capacitor bank 206 the power signal generated by the power supply and detector 208 has a larger amplitude. By iteratively testing different capacitor bank 206 configurations in this manner, the self-tuning system 200 can determine the capacitor bank 206 configuration that optimizes the ability of the antenna 202 to absorb electrical energy from the ambient electric field 204.

[0091] Sampler 214 is configured similarly to sampler 212, as it is also configured to measure the amplitude of the power supply signal received from the power supply and detector 208. The output of sampler 214 is provided to input power reduction detector 218. Input power reduction detector 218 is configured to determine whether the current amplitude of the sampled signal acquired by capacitor bank 206 in its current configuration is less than or equal to the amplitude of the sampled signal acquired by capacitor bank 206 in a different configuration. When the output of input power reduction detector 218 becomes high, it indicates that the coupling between antenna 202 and ambient electric field 204 has become less effective. This high value (as described herein) can be used to terminate self-tuning operation because further modifications to capacitor bank 206 could further reduce the efficiency of antenna 202, indicating that an optimal configuration has been determined.

[0092] As described below, samplers 212 and 214 can operate in two different modes depending on the operating state of the self-tuning system 200. When the self-tuning system 200 is in state 1 (e.g., when first enabled after a reset), samplers 212 and 214 are configured to fully reset within a “discharge time” (described below). Once samplers 212 and 214 are reset (ensuring their respective measurements are accurate in the future), the self-tuning system 200 enters state “2”, where both samplers 212 and 214 accumulate the signal from the power supply and detector 208 output within a “charging time” (described below) until sampling of the output signal is complete (the amount of time required is at least partially determined by the amplitude of the power supply signal). At that point, as described below, the self-tuning circuit 200 moves to the next state “4”.

[0093] The input power reduction detector 218 is also configured to implement a "timeout" function of the self-tuning circuit 200. In this case, the input power reduction detector 218 is configured to determine a timeout window, the duration of which is proportional to the input power, for waiting for the output of the input power increase detector 216. As described herein, the duration of the timeout window is selected to be greater than the time required for the input power increase detector 216 to generate its output signal. If the input power increase detector 216 fails to generate an output within the timeout window, the input power reduction detector 218 will generate a timeout indication.

[0094] To control the overall operation of the self-tuning system 200, the controller 220 includes an asynchronous digital circuitry configured to determine the operation of samplers 212 and 214. As described herein, this circuitry is not clock-driven digital logic (and is therefore asynchronous digital logic), but rather based on timing events generated by input power boost detector 216 and input power debuff detector 218. Based on the outputs of input power boost detector 216 and input power debuff detector 218, the digital portion of the controller 220 is configured to implement a capacitor tuning algorithm to determine the configuration of capacitor bank 206.

[0095] The operation of the self-tuning system 200 is summarized by monitoring the power level of the signal received from detector 208 over time to determine whether the current configuration of capacitor bank 206 improves antenna coupling. This process is performed in the analog domain of the self-tuning system 200 and does not rely on a digital controller driven by a digital clock signal. Based on the analog monitoring operation, digital controller 220 is configured to transmit signals to adjust the configuration of capacitor bank 206, optimizing the configuration of antenna 202 to improve power coupling.

[0096] Figure 3 This is a flowchart depicting a method 300 that can be implemented by controller 220, the method being designed to optimize the configuration of capacitor bank 206 and antenna 202 to optimize the power coupling from ambient electric field 204 to antenna 202. See also... Figure 2 This allows for the best understanding. Figure 3 .

[0097] At block 302, controller 220 determines (e.g., using PMU 210) whether self-tuning circuit 200 is powered on. This determination is based on the amplitude of the power supply signal received from power supply and detector 208, as described above. If a sufficient power supply signal is not received from power supply and detector 208, this method will loop and wait until a sufficient power supply required for operation of self-tuning system 200 is detected.

[0098] If a sufficient power supply signal required for the operation of the self-tuning system 200 is detected, then at block 304, the self-tuning system 200 enters a first state, in which the signal sampling components of the self-tuning system 200 (i.e., samplers 212 and 214) are reset. According to method 300, this may involve the controller 220 waiting for a period of time (t). delay1 This ensures that the sampling block is completely reset before the self-tuning system 200 can exit the state.

[0099] In reset delay (t delay1 Upon expiration, at block 306, controller 220 configures samplers 212 and 214 to measure the amplitude of the signal received from the power supply and detector 208, the signal being directly derived from the electrical energy coupled from the ambient electric field 204 to antenna 202. This process may take some time due to the charging of various sensing capacitors (described below), therefore block 306 executes a time period (t). delay2 This time period is chosen to ensure that both sampler 212 and sampler 214 have measured the full amplitude of the signal received from the power supply and detector 208. After the sampling period has elapsed, the method moves to block 308, where the self-tuning system 200 enters a new state (i.e., state 4), in which controller 220 reconfigures capacitor bank 206 based on a predetermined capacitor bank modification algorithm according to the measurement generated at block 306.

[0100] Next, method 300 branches into two parallel paths, performing a comparison to determine whether the sample generated by sampler 212 and sampler 214 at block 306 in the first capacitor bank 206 configuration (i.e., the configuration at block 308) is greater than or less than the current power supply signal generated by the new (second) capacitor bank 206 using the configuration implemented at block 308.

[0101] Specifically, at block 310, controller 220 uses a first comparator (e.g., input power boost detector 216) to determine whether the power supply and the output signal of detector 208 have increased due to the configuration of the new capacitor bank 206. Simultaneously, at block 312, controller 220 uses a second comparator (e.g., input power decrease detector 218) to determine whether the power supply and the output signal of detector 208 have decreased due to the configuration of the new capacitor bank 206, or whether a specific timeout condition has been met, wherein, as described herein, the timeout duration may depend on the amplitude of the input signal received from antenna 402.

[0102] As described below, using the outputs of the two comparators, at block 314, controller 220 determines whether the configuration of capacitor bank 206 has been optimized such that antenna 202 is absorbing the maximum possible amount of energy from ambient electric field 204, and therefore the power supply signal generated by power supply and detector 208 is at its maximum available value.

[0103] In this case, method 300 moves to box 316, where controller 220 sets a system marker indicating that the self-tuning algorithm has completed, and then method 300 ends at box 318, where the RFID tag enters normal data transmission operation.

[0104] However, if at block 314 the controller 220 determines that the self-tuning algorithm has not been completed, then method 300 moves to block 320, where the self-tuning system 200 enters a new state (i.e., state 4), in which the configuration of capacitor bank 206 is modified (by increasing or decreasing its capacitance). Specifically, if the outputs of blocks 310 and 312 indicate that a recent modification of capacitor bank 206 has increased the amplitude of the power supply signal, then block 320 involves further modifying the configuration of capacitor bank 206 in the same manner (i.e., by further increasing or decreasing the capacitance of capacitor bank 206) to potentially further increase the amplitude of the power supply signal. However, if the outputs of blocks 310 and 312 indicate that a recent modification of capacitor bank 206 has decreased the amplitude of the power supply signal, then block 320 involves further modifying the configuration of capacitor bank 206 in the opposite manner to potentially increase the amplitude of the power supply signal by tuning antenna 202 in the opposite direction. With capacitor bank 206 configured in this way, method 300 returns to block 304 and is re-executed to evaluate the new capacitor bank 206 configuration.

[0105] In various embodiments, method 300 may include a "catch-all" timeout 322, such that if the control algorithm of method 300 fails (e.g., due to a jammed digital logic section or other aspects of the control loop stalling), the catch-all timeout 322 can detect the failure and force the system to reset.

[0106] To further illustrate the operation of the self-tuning system 200 Figure 4 This is a circuit diagram depicting an RFID tag self-tuning circuit 400 configured according to this disclosure. The RFID tag self-tuning circuit 400 can implement the functions of the self-tuning system 200. In the RFID tag self-tuning circuit 400, the antenna 402 is represented by an inductor. Adjustable capacitors form a variable capacitor bank 404 that can be configured with different capacitances to achieve tuning of the antenna 402.

[0107] A charge pump 406 is connected across antenna 402 and is configured to accumulate charge based on an output signal generated by antenna 402. The accumulated charge is expressed as a voltage (V). CP The output voltage V is supplied to a start sensor 412 (POR) and a PMU (408), the PMU generating a supply voltage for the controller (480). The controller's supply voltage has its own start sensor (POR) 410. Additionally, VCP supplies voltage to comparators 430 and 450. Sensor 410 is configured to determine the output voltage V. CP (It is similar to that of) Figure 2 The power supply signal (output of detector 208) is used to monitor whether it is sufficient to enable proper operation of the RFID tag self-tuning circuit 400. A power-on reset module 410 is configured to monitor the overall supply signal V supplied to comparators 430 and 450. CP Furthermore, a power-on reset module 412 is configured to monitor the supply signal generated from PMU 208 supplied to controller 480.

[0108] If V CP If the signal amplitude exceeds a threshold (set as the minimum voltage required for proper operation of the RFID tag self-tuning circuit 400), then the two power-on reset modules 410 and 412 generate certain power-on reset signals to bring the RFID tag self-tuning circuit 400 into an initial reset state before implementing its self-tuning function. Specifically, the power-on reset values ​​generated by the power-on reset modules 410 and 412 are provided as inputs to the controller 480, enabling the controller 480 to control the operation of the RFID tag self-tuning circuit 400, as detailed below.

[0109] The RFID tag self-tuning circuit 400 also includes a peak detector circuit 414, which is configured to determine the envelope signal V of the signal originating from the output of the antenna 402. ENV The amplitude. In some embodiments, the signal V output by the peak detector circuit 414 is not utilized. ENV Instead, the signal output by charge pump 406 (VCP) can be used instead of the envelope signal V. ENV Because V CP It is related to the envelope signal V ENVA signal proportional to the signal received from antenna 402. Peak detector circuit 414 includes diodes 416 and 418 connected across antenna 402. Diodes 416 and 418 act as rectifiers for the AC signal received from antenna 402 to generate a rectified output signal, which is supplied to the first input of operational amplifier 420. The second input of operational amplifier 420 is connected to the first terminal of capacitor 422. The second terminal of capacitor 422 is connected to a ground node, and therefore, the second input of operational amplifier 420 receives the voltage of capacitor 422 as an input signal. The output of operational amplifier 420 is supplied to diode 424. Therefore, in this configuration, the output of diode 424 is a signal equal to the amplitude of the envelope of the signal received from antenna 402.

[0110] The output of diode 424 is distributed across voltage divider 426, which includes a plurality of resistors (e.g., provided by resistors, diodes, or resistor-voltage-drop components) connected in series between the output of diode 424 and ground node to generate an output voltage V. ENV,HIGH1 V ENV,MED and V ENV,LOW Generally speaking, V ENV,HIGH With envelope signal V ENV Proportional and with a small voltage drop, so that the comparator device 432 of comparator 430 can be biased. V ENV,MED With envelope signal V ENV Proportional and having a voltage drop, it can be used to define the initial voltage of capacitor 456 (which in turn determines the discharge time). V ENV,LOW It is also proportional to the envelope, but has a higher voltage drop and is used to limit the threshold voltage of capacitor 456, which determines when the capacitor discharges.

[0111] When using these voltages, comparator 430 is configured to first use V ENV,HIGH1 The current peak voltage is sampled (i.e., capacitor 436 is charged to V). ENV,HIGH1 In the comparison phase, V ENV,HIGH1 The subsequent value is compared with the current voltage of capacitor 436, and the current voltage of capacitor 436 is still V. ENV,HIGH1 The previous value of V. ENV,HIGH1 The new value is greater than the earlier value, indicating that the configuration change of the variable capacitor bank 404 has improved power coupling. Conversely, within comparator 430, V ENV,LOW This is used to discharge capacitor 436, allowing capacitor 436 to enter a known initialization state (e.g., in the state of V) before a new sampling operation is performed. ENV,LOW Equal voltages.

[0112] Within the RFID tag self-tuning circuit 400, the comparator 450 uses V ENV_MED and VENV_LOW A timeout is generated, which depends on the voltage of the signal received from antenna 402. Specifically, as described herein, capacitor 456 is charged to V. ENV_MED And then discharge to V ENV_LOW This requires a certain amount of time. If the output of comparator 430 does not switch within this time period, then the output of comparator 450 will switch its output, as described herein, and the output is detected and acted upon by controller 480.

[0113] The RFID tag self-tuning circuit 400 includes a comparator 430 (e.g., Figure 2 The sampler 212). The comparator includes a comparator device 432. The comparator device 432 includes a first input terminal connected to a switch 434. The switch 434 is configured to selectively connect to receive different voltage values ​​V output by the peak detector circuit 414. ENV,HIGH1 V ENV,MED and V ENV,LOW The second input terminal of comparator device 432 receives the voltage of capacitor 436 as input. Switch 438 is connected across capacitor 436. During normal operation, switch 438 remains in the open position, such that the voltage of capacitor 436 is provided as input to the second terminal of comparator device 432. However, if switch 438 is closed, capacitor 436 discharges its stored voltage to ground node 440. Current source 435 is connected to capacitor 436 via switch 437. When switch 437 is closed, current source 435 charges capacitor 436.

[0114] In this configuration, comparator device 432 is configured to output a high value at output terminal 442 when the input received from capacitor 436 at the first input terminal is greater than the input received at the second input terminal, and to output a low value when the input received at the first input terminal is less than the input received at the second input terminal. Comparator device 432

[0115] The RFID tag self-tuning circuit 400 includes a comparator 450 (e.g., Figure 2 The sampler 214). Comparator 450 includes comparator device 452. Comparator device 452 includes a first input terminal connected to switch 454. Switch 454 is configured to selectively connect to receive different voltage values ​​V output by peak detector circuit 414. ENV,MED and V ENV,LOWThe second input terminal of comparator device 452 receives the voltage of capacitor 456 as input. Switch 458 is connected across capacitor 456. During normal operation, switch 458 remains in the open position, such that the voltage of capacitor 456 is provided as input to the second terminal of comparator device 452. However, if switch 458 is closed, capacitor 456 discharges its stored voltage to ground node 460. Current source 455 is connected to capacitor 456 via switch 457. When switch 457 is closed, current source 455 charges capacitor 456.

[0116] In this configuration, comparator device 452 is configured to output a high value at output terminal 462 when the input received from capacitor 456 at the first input terminal is greater than the input received at the second input terminal, and to output a low value when the input received at the first input terminal is less than the input received at the second input terminal.

[0117] The controller 480 includes inputs configured to receive various signals from other components in the RFID tag self-tuning circuit 400. Specifically, the controller 480 includes input 482 configured to receive each of the power-on reset signals generated by power-on reset modules 410 and 412, and two output signals output by each of comparator devices 432 and 452. Using those input signals, the controller 480 is configured to implement a method for controlling the operation of the RFID tag self-tuning circuit 400. The controller 480 controls the operation of the RFID tag self-tuning circuit 400 by generating an output signal at output 484 to control the configuration of the various components of the RFID tag self-tuning circuit 400. Specifically, output terminal 484 outputs control signals to control the operation of switches 434 (i.e., SW11), 437 (i.e., SW12), 438 (i.e., SW13), 454 (i.e., SW21), 455 (i.e., SW22), and 458 (i.e., SW23) and the variable capacitor bank 404 (i.e., SW11). CAP Configuration of ).

[0118] Figure 5 This is a flowchart depicting a method 500 that can be implemented by a controller 480 of an RFID tag self-tuning circuit 400, the method being designed to implement a self-tuning algorithm to determine the optimal configuration of the antenna 402 and the variable capacitor bank 404 of the RFID tag self-tuning circuit 400. See also... Figure 4 This allows for the best understanding. Figures 5 to 8 .

[0119] At blocks 502 and 504, controller 480 monitors power-on reset signals from power-on reset modules 410 and 412 at input 482. If both reset signals indicate that the energy supplied from antenna 402 is sufficient to enable operation of RFID tag self-tuning circuit 400, then the self-tuning algorithm can be executed.

[0120] Next, method 500 moves to box 506, causing the RFID tag self-tuning circuit 400 to enter state 1, as described above, to initiate the reset of the signal sampling capacitors (i.e., capacitors 436 and 456) of the RFID tag self-tuning circuit 400. For illustration, Figure 6 This is a flowchart depicting an example method 600 implemented by controller 480 to perform this initiation process. At block 602, controller 480 configures the components of 400 via its various output signals 484 in the following manner. In comparator 430, controller 480 operates switch 434 such that voltage V ENV,LOW Connected to the first input terminal of comparator device 432. Controller 480 opens switch 437 (disconnecting capacitor 436 from current source 435). Controller 480 closes switch 438, thereby discharging capacitor 436 to ground node 440. In comparator 450, controller 480 operates switch 454 in a similar manner, causing voltage V... ENV,LOW Connected to the first input terminal of comparator device 452. Controller 480 opens switch 457 (disconnecting capacitor 456 from current source 455). Controller 480 closes switch 458, thereby discharging capacitor 456 to ground node 460. At block 604, a control loop is implemented to maintain switches 438, 437, 458, and 457 in this condition until the outputs of both comparator device 432 and output terminal 462 become high, indicating that the two sensing capacitors 436 and 456 have been fully discharged.

[0121] Once capacitors 436 and 456 are discharged (and the outputs of comparators 430 and 450 have gone high), indicating that the voltage across each capacitor 436, 456 is less than V, this indicates that the voltage across each capacitor 436, 456 is less than V. ENV,LOW Comparator 430 and comparator 450 are then reset, and method 600 ends.

[0122] Return to Figure 5 When comparators 430 and 450 are reset, at block 508, controller 480 causes RFID tag self-tuning circuit 400 to enter state 2, measuring the amplitude of the signal received from antenna 402 in its current configuration (i.e., where variable capacitor bank 404 is set to a specific capacitor value). Figure 7This is a flowchart depicting an example method 700 implemented by controller 480 to execute this signal process. At block 702, controller 480 configures the components of 400 via its various output signals 484 in the following manner. In comparator 430, switch 434 is configured to connect to voltage V. ENV,HIGH1 The input terminal is configured such that voltage is provided at the first input of comparator device 432. Switch 437 closes, causing current source 435 to begin charging capacitor 436. The output of comparator device 432 will be high until the voltage stored by capacitor 436 is charged to equal voltage V. ENV,HIGH1 When the quantity is high, the output of comparator 432 will become low. When switch 437 is closed, switch 438 is open to prevent capacitor 436 from discharging to ground node 440.

[0123] In comparator 450, switch 454 is configured to be connected to voltage V. ENV,MED The input terminal is configured such that voltage is provided at the first input of comparator device 452. Switch 457 is closed, causing current source 455 to begin charging capacitor 456. The output of comparator device 452 will be high until the voltage stored by capacitor 456 equals voltage V. ENV,MED At this time, the output of comparator device 452 will become low. When switch 457 is closed, switch 458 is open to prevent capacitor 456 from discharging to ground node 460.

[0124] In this configuration, capacitor 436 is charged to voltage V. ENV,HIGH1 Alternatively, its sample can be used, at which point the output of comparator device 432 becomes low. Simultaneously, capacitor 456 is charged to voltage V. ENV,MED Alternatively, its sample can be used, at which point the output of comparator device 452 becomes low.

[0125] In method 700, at block 704, controller 480 monitors the output of comparator 430 (i.e., the output of comparator device 432 at output terminal 442) to detect when its output switches to a low value (indicating that capacitor 436 has been charged to voltage V). ENV,HIGH1 At that time, at box 706, switch 437 is turned off to prevent further changes in capacitor 436, thus maintaining the voltage of capacitor 436 at V. ENV,HIGH1 .

[0126] In a separate method flow, at block 708, controller 480 monitors the output of comparator 450 (i.e., the output of comparator device 452 at output 462) to detect when its output switches to a low value (indicating that capacitor 456 has been charged to the desired voltage V). ENV,MEDAt that time, at box 710, switch 457 is turned off to prevent further changes in capacitor 456, so that the voltage of capacitor 456 remains at V. ENV,MED .

[0127] Method 700 ends after the outputs of both comparators 430 and 450 switch to low values ​​(confirmed by controller 480 at step 712).

[0128] Return to Figure 5 After completing sampling frame 508 to capture V in capacitor 436 ENV,HIGH1 The current voltage and capacitor 456 V ENV,MED After the voltage is applied, controller 480 at block 510 uses the control signal generated at output 484 to modify the configuration of variable capacitor bank 404 (e.g., by removing a capacitor from the bank, thereby reducing the capacitance of variable capacitor bank 404 by a discrete amount, but other modification algorithms can also be used, such as the algorithm that initially added the capacitor to the bank). Upon first execution of block 510, the configuration of variable capacitor bank 404 is determined according to system variables. <sign>Increase or decrease the capacitance of the variable capacitor bank 404. If <sign>If it's positive, then the capacitance increases by one step. If... <sign>If the value is negative, then the capacitance decreases. (Variable) <sign>The initial value can be determined according to a predetermined process. As discussed below, as the self-tuning algorithm proceeds, <sign>The value can be modified for future execution of box 510 to optimize the configuration of the variable capacitor bank 404.

[0129] At block 512, a comparison step is performed, wherein controller 480 determines whether the new configuration of the variable capacitor bank 404 generated by block 510 improves the tuning of antenna 402, thereby increasing the amount of energy coupled to antenna 402. Figure 8 This is a flowchart depicting an example method 800 implemented by controller 480 to perform this comparison step. At block 802, controller 480 configures the components of 400 via its various output signals 484 in the following manner. In comparator 430, switch 434 is configured to operate at voltage V. ENV,HIGH1 The lower connection is to the end. V ENV,HIGH1 The voltage is determined by the envelope of the signal received from the antenna 402 when the variable capacitor bank 404 is in its new configuration (as described above), and therefore if the new configuration of the variable capacitor bank 404 improves the coupling of the antenna 402, then V will be higher than the previous value sampled during execution block 508 described above. ENV,HIGH1 It can be increased. In comparator 450, switch 454 is at voltage V ENV,LOW The lower connection is at the end. Switch 458 closes, causing capacitor 456 to begin discharging (this operation can be controlled by the current trap) to ground node 460, and switch 457 opens (at the same time that switch 458 closes).

[0130] In this configuration, if the new configuration of the variable capacitor bank 404 improves the coupling of the antenna 402, making V ENV,HIGH1 The current value is greater than the sampling step ( Figure 5 During the period of frame 508) V ENV,HIGH1 If the value of 430 is high, then the output of comparator device 432 will become high, indicating that the new configuration of variable capacitor bank 404 is an improvement. If so, then at block 804, controller 480 determines that the output of 430 (i.e., at the output terminal 442 of comparator device 432) has become high, and then method 800 ends. In this state, <sign>The value remains unchanged because the previous modification to the configuration of the variable capacitor bank 404 improved the coupling, and further changes to the configuration of the variable capacitor bank 404 in the same "direction" can further improve the coupling. Therefore, any changes to the configuration of the variable capacitor bank 404 in future iterations will modify the capacitance of the variable capacitor bank 404 in the same direction as the changes made before executing method 800. In short, the previous changes to the configuration of the variable capacitor bank 404 improved the coupling of the antenna 402, so further changes in the same direction can further improve said coupling.

[0131] However, if the new configuration of the variable capacitor bank 404 does not improve the coupling of the antenna 402, making V ENV,HIGH1 The current value is less than the sampling step ( Figure 5 During the period of frame 508) V ENV,HIGH1 If the value stored on capacitor 436 is low, then the output of comparator 430 will remain low, and block 804 will not complete. In this case, comparator 450 acts as an analog timeout detector. In the configuration of 450, capacitor 456 will gradually discharge to ground node 460 until the voltage stored on capacitor 456 drops below the minimum value V. ENV,LOW Once the discharge is complete, the output of comparator 450 switches to a high value, which is detected at block 806. This condition indicates that the recent configuration change of the variable capacitor bank 404 has not improved the coupling of antenna 402. Therefore, at block 808, <sign>The value is reversed so that any further changes to the configuration of the variable capacitor bank 404 occur in the opposite direction, and then the method ends.

[0132] Return to Figure 5 At block 516, the controller determines whether the conditions for exiting the self-tuning operation have been met. This may involve determining whether block 510 has been executed a threshold number of times, whether the capacitor bank has reached a configuration equal to the minimum or maximum capacitance, or whether the self-tuning algorithm has timed out (e.g., timed out more than once consecutively or sequentially).

[0133] When the end-of-tuning condition is met at box 516, the variable sa_finished is set to a high value '1' at box 518 to indicate that self-tuning is complete, then the method ends, and the current configuration of the variable capacitor bank 404 is used for other RF tag operations.

[0134] Despite Figure 5 Not shown, but additional stop criteria may exist. For example, if a system failure occurs, or any system voltage (e.g., V) CP Or derived from V ENV If the voltage drops below a certain threshold, the method can exit early, even if the self-tuning process has not been completed.

[0135] However, if it is determined at block 516 that the conditions for exiting the self-tuning operation have not been met, the method returns to block 506 and re-executes the reset, sampling, and variable capacitor bank 404 adjustments in blocks 506, 508, and 510. In these future iterations, the capacitance of the variable capacitor bank 404 is adjusted according to the values ​​set in method 800. <sign>The values are adjusted.

[0136] In some aspects, the technology described herein relates to a radio frequency identification (RFID) tag comprising: an antenna configured to receive an input signal; a variable capacitor bank electrically coupled to the antenna; and a self-tuning circuit coupled with the antenna, wherein the self-tuning circuit is configured to modify a capacitance of the variable capacitor bank according to a self-tuning algorithm to optimize a signal strength of the input signal, wherein the self-tuning circuit does not include a clock source, and the self-tuning circuit comprises: a first comparator comprising: a first capacitor configured to store a first voltage indicative of a first magnitude of the input signal when the variable capacitor bank is in a first configuration, and a first comparator device having a first input and a second input, wherein the first input is configured to receive a second voltage indicative of a second magnitude of the input signal when the variable capacitor bank is in a second configuration, and the second input is configured to receive the first voltage from the first capacitor, wherein the first comparator device is configured to generate a first output signal based on a difference between the first voltage and the second voltage; and a controller configured to determine, using the first output signal of the first comparator device, that the first configuration of the variable capacitor bank is an optimized configuration of the variable capacitor bank compared to the second configuration, and to configure the variable capacitor bank in the first configuration.

[0137] In some aspects, the technology described herein relates to an RFID tag, further comprising: a second comparator comprising: a second capacitor, and a second comparator device having a first input and a second input, wherein the first input is configured to receive an input signal, and the second input is configured to be connected to the second capacitor.

[0138] In some aspects, the technology described herein relates to an RFID tag, wherein the controller is configured to: cause the second capacitor to store the first voltage indicative of the first magnitude of the input signal when the variable capacitor bank is in the first configuration; apply a threshold voltage to the first input of the second comparator device, wherein the threshold voltage is a minimum voltage value of the self-tuning circuit; and connect the second capacitor to a ground node to discharge the second capacitor, wherein the second comparator device generates a low output value when a voltage of the second capacitor is greater than the threshold voltage, and the second comparator device generates a high output value when the voltage of the second capacitor is less than the threshold voltage.

[0139] In some aspects, the technology described herein relates to an RFID tag, wherein the controller is configured to: detect that an output of the second comparator device has transitioned from the low output value to the high output value; and cause the self-tuning circuit to terminate execution of the self-tuning algorithm.

[0140] In some aspects, the technology described herein relates to an RFID tag, wherein the controller is configured to, prior to executing the self-tuning algorithm, reset the self-tuning circuit by discharging the first capacitor to the ground node and discharging the second capacitor to the ground node.

[0141] In some aspects, the technology described herein relates to an RFID tag, wherein the first voltage is indicative of the first magnitude of the input signal, and the threshold voltage is generated by a voltage divider electrically connected to the antenna.

[0142] In some aspects, the technology described herein relates to an RFID tag, wherein a rectifier is connected between the voltage divider and the antenna.

[0143] In some aspects, the technology described herein relates to an RFID tag, wherein the first comparator is configured to generate the first output signal without receiving or using an oscillating clock signal.

[0144] In some aspects, the technology described herein relates to an apparatus comprising: a first comparator comprising: a first capacitor configured to store a first voltage indicative of a first magnitude of an input signal when a variable capacitor bank coupled to an antenna is in a first configuration, and a first comparator device having a first input and a second input, wherein the first input is configured to receive a second voltage indicative of a second magnitude of the input signal when the variable capacitor bank is in a second configuration, and the second input is configured to receive the first voltage from the first capacitor, wherein the first comparator device is configured to generate a first output signal based on a difference between the first voltage and the second voltage; and a controller configured to determine a configuration of a variable capacitor bank using the first output signal of the first comparator device.

[0145] In some aspects, the technology described herein relates to an apparatus, additionally comprising: a second comparator comprising: a second capacitor, and a second comparator device having a first input and a second input, wherein the first input is configured to receive an input signal, and the second input is configured to be connected to the second capacitor.

[0146] In some aspects, the technology described herein relates to an apparatus, wherein the controller is configured to: cause the second capacitor to store the first voltage indicative of the first amplitude of the input signal when the variable capacitor bank is in the first configuration; apply a threshold voltage to the first input of the second comparator apparatus, wherein the threshold voltage is a minimum voltage value of the apparatus; and connect the second capacitor to a ground node to discharge the second capacitor, wherein the second comparator apparatus generates a low output value when a voltage of the second capacitor is greater than the threshold voltage and generates a high output value when the voltage of the second capacitor is less than the threshold voltage.

[0147] In some aspects, the technology described herein relates to an apparatus, wherein the first voltage is indicative of the first amplitude of the input signal and the threshold voltage is generated by a voltage divider electrically connected to the antenna.

[0148] In some aspects, the technology described herein relates to an apparatus, wherein a rectifier is connected between the voltage divider and the antenna.

[0149] In some aspects, the technology described herein relates to an apparatus, wherein the first comparator is configured to generate the first output signal without receiving or using an oscillating clock signal.

[0150] In some aspects, the technology described herein relates to a method of performing a self-tuning algorithm for a radio frequency identification tag, comprising: storing a first voltage indicative of a first amplitude of an input signal to an antenna when a variable capacitor bank coupled to the antenna in a first capacitor; providing a second voltage indicative of a second amplitude of the input signal to a first input of a first comparator apparatus when the variable capacitor bank is in a second configuration; providing the first voltage from the first capacitor to a second input of the first comparator apparatus, wherein the first comparator apparatus is configured to generate a first output signal based on a difference between the first voltage and the second voltage; determining, using the first output signal of the first comparator apparatus, that the first configuration of the variable capacitor bank is an optimized configuration of the variable capacitor bank compared to the second configuration; and configuring the variable capacitor bank in the first configuration.

[0151] In some aspects, the technology described herein relates to a method, further comprising providing a second comparator having a first input configured to receive an input signal, wherein a second input of the second comparator is connected to a second capacitor.

[0152] In some aspects, the technology described herein relates to a method, further comprising: when the variable capacitor bank is in the first configuration, causing the second capacitor to store a first voltage indicating the first amplitude of the input signal; applying a threshold voltage to the first input of the second comparator device, wherein the threshold voltage is a minimum voltage value; and connecting the second capacitor to a ground node to discharge the second capacitor, wherein the second comparator device generates a low output value when the voltage of the second capacitor is greater than the threshold voltage, and generates a high output value when the voltage of the second capacitor is less than the threshold voltage.

[0153] In some aspects, the techniques described herein relate to a method that further includes: detecting that the output of the second comparator device has changed from the low output value to the high output value; and terminating the self-tuning algorithm.

[0154] In some aspects, the techniques described herein relate to a method that further includes using a voltage divider to generate a first voltage and a threshold voltage that indicate the first amplitude of the input signal.

[0155] In some respects, the techniques described herein relate to a method for additionally generating the first output signal without receiving or using an oscillating clock signal.

[0156] As those skilled in the art will understand, aspects of this disclosure can be embodied as systems, processes, methods, and / or program products. Therefore, aspects of this disclosure can take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware aspects (which may be generally referred to herein as "circuit," "circuit system," "module," or "system"). Furthermore, aspects of this disclosure can take the form of program products embodied in one or more computer-readable storage media on which computer-readable program code is embodied. (However, any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.)

[0157] Computer-readable storage media can be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, biological, atomic, or semiconductor systems, devices, controllers, or apparatuses, or any suitable combination thereof, wherein the computer-readable storage medium itself is not a transient signal.

[0158] Computer-readable signal media may include propagated data signals embodying computer-readable program code therein, for example, in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. Computer-readable signal media may be any computer-readable medium that is not a computer-readable storage medium but can transmit, propagate, or transfer programs for use by or in connection with an instruction execution system, device, controller, or apparatus.

[0159] The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of circuit systems, systems, methods, processes, and program products according to various embodiments of the present disclosure. In this regard, certain blocks in the block diagrams may represent modules, segments, or portions of code, which include one or more executable program instructions for implementing specified logical functions. It should also be noted that in some embodiments, the functions mentioned in the various blocks may occur in a different order than that shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order.

[0160] These program instructions may be provided to one or more processors and / or controllers of a general-purpose computer, a special-purpose computer, or other programmable data processing equipment (e.g., a controller) to produce a machine such that the instructions, which are executed via the processor of the computer or other programmable data processing equipment, create a circuit system or component for implementing the functions / actions specified in the block diagram.

[0161] The foregoing detailed description is illustrative in nature only and is not intended to limit the subject matter or the use of embodiments of this application and such embodiments.

[0162] As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, one is not to be bound by any express or implied theory presented in prior art, background art, or detailed description.

[0163] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter. Furthermore, certain terms may be used herein for reference only, and therefore such terms are not intended to be limiting, and unless the context clearly indicates otherwise, the terms "first," "second," and other such numerical terms referring to structures do not imply order or sequence.

[0164] As used herein, a "node" means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity exists. Furthermore, two or more nodes can be implemented with a single physical element (and although receiving or outputting at a common node, two or more signals can still be multiplexed, modulated, or otherwise distinguished).

[0165] The above description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly communicates with) another element, and not necessarily mechanically. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly communicates with) another element electrically or otherwise, and not necessarily mechanically. Therefore, the schematic diagrams shown in the figures depict an exemplary arrangement of elements, but additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0166] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the above detailed description will provide those skilled in the art with convenient guidance for implementing the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.< / sign> < / sign> < / sign> < / sign> < / sign> < / sign> < / sign> < / sign>

Claims

1. A radio frequency identification (RFID) tag, characterized by comprises: an antenna configured to receive an input signal; a variable capacitor bank electrically coupled to the antenna; and a self-tuning circuit coupled with the antenna, wherein the self-tuning circuit is configured to modify a capacitance of the variable capacitor bank according to a self-tuning algorithm to optimize a signal strength of the input signal, wherein the self-tuning circuit does not include a clock source, and the self-tuning circuit comprises: a first comparator comprising: a first capacitor configured to store a first voltage indicative of a first magnitude of the input signal when the variable capacitor bank is in a first configuration, and a first comparator device having a first input and a second input, wherein the first input is configured to receive a second voltage indicative of a second magnitude of the input signal when the variable capacitor bank is in a second configuration, and the second input is configured to receive the first voltage from the first capacitor, wherein the first comparator device is configured to generate a first output signal based on a difference between the first voltage and the second voltage; and a controller configured to determine, using the first output signal of the first comparator device, that the first configuration of the variable capacitor bank is an optimized configuration of the variable capacitor bank compared to the second configuration, and to configure the variable capacitor bank in the first configuration. further comprising:

2. The RFID tag of claim 1, wherein, a second comparator comprising: a second capacitor, and a second comparator device having a first input and a second input, wherein the first input is configured to receive an input signal, and the second input is configured to be connected to the second capacitor. the controller is configured to:

3. The RFID tag of claim 2, wherein, cause the second capacitor to store the first voltage indicative of the first magnitude of the input signal when the variable capacitor bank is in the first configuration; apply a threshold voltage to the first input of the second comparator device, wherein the threshold voltage is a minimum voltage value of the self-tuning circuit; and connect the second capacitor to a ground node to discharge the second capacitor, wherein the second comparator device generates a low output value when a voltage of the second capacitor is greater than the threshold voltage, and the second comparator device generates a high output value when the voltage of the second capacitor is less than the threshold voltage. the controller is configured to:

4. The RFID tag of claim 3, wherein, detect that an output of the second comparator device has transitioned from the low output value to the high output value; and cause the self-tuning circuit to terminate execution of the self-tuning algorithm. the controller is configured to reset the self-tuning circuit, prior to execution of the self-tuning algorithm, by discharging the first capacitor to the ground node and discharging the second capacitor to the ground node.

5. The RFID tag of claim 4, wherein, the first voltage indicative of the first magnitude of the input signal and the threshold voltage are generated by a voltage divider electrically connected to the antenna.

6. The RFID tag of claim 3, wherein, a rectifier is connected between the voltage divider and the antenna.

7. The RFID tag of claim 6, wherein, the first comparator is configured to generate the first output signal without receiving or using an oscillating clock signal.

8. The RFID tag of claim 1, wherein, comprises:

9. An apparatus, comprising: a first comparator comprising: ​ a first capacitor configured to store a first voltage indicative of a first magnitude of an input signal when a variable capacitor bank coupled to an antenna is in a first configuration, and a first comparator device having a first input and a second input, wherein the first input is configured to receive a second voltage indicative of a second magnitude of the input signal when the variable capacitor bank is in a second configuration, and the second input is configured to receive the first voltage from the first capacitor, wherein the first comparator device is configured to generate a first output signal based on a difference between the first voltage and the second voltage; and a controller configured to determine a configuration of a variable capacitor bank using the first output signal of the first comparator device.

10. A method of performing a self-tuning algorithm for a radio frequency identification tag, characterized by, comprises: storing a first voltage indicative of a first magnitude of an input signal to an antenna when a variable capacitor bank coupled to the antenna is in a first configuration; providing a second voltage indicative of a second magnitude of the input signal to a first input of a first comparator device when the variable capacitor bank is in a second configuration; providing the first voltage from the first capacitor to a second input of the first comparator device, wherein the first comparator device is configured to generate a first output signal based on a difference between the first voltage and the second voltage; determining that the first configuration of the variable capacitor bank is an optimized configuration of the variable capacitor bank compared to the second configuration using the first output signal of the first comparator device; and configuring the variable capacitor bank in the first configuration. comprises: storing a first voltage indicative of a first magnitude of an input signal to an antenna when a variable capacitor bank coupled to the antenna is in a first configuration; providing a second voltage indicative of a second magnitude of the input signal to a first input of a first comparator device when the variable capacitor bank is in a second configuration; providing the first voltage from the first capacitor to a second input of the first comparator device, wherein the first comparator device is configured to generate a first output signal based on a difference between the first voltage and the second voltage; determining that the first configuration of the variable capacitor bank is an optimized configuration of the variable capacitor bank compared to the second configuration using the first output signal of the first comparator device; and configuring the variable capacitor bank in the first configuration.

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