Computing system and calibration method of modulator thereof
By setting up registers in the optoelectronic computing system to store the occupancy status information of the optical transmission channel, the conflict between modulator calibration and computing tasks is resolved, achieving efficient modulator calibration and stable system operation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2026-03-10
AI Technical Summary
In optoelectronic computing systems, the calibration task of the modulator and the computing task may conflict due to the occupation of the optical transmission channel, resulting in a decrease in system performance.
By setting registers in the computing system to store the occupancy status information of the optical transmission channel, and controlling the calibration process of the modulator based on this information, conflicts between calibration tasks and computing tasks on the optical transmission channel can be avoided.
This effectively avoids conflicts in the optical transmission channel between calibration and computation tasks, ensuring that the modulator operates under appropriate conditions and improving the system's computational efficiency and stability.
Smart Images
Figure CN121643889A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of photonic computing, and more specifically, to a calibration method for a computing system and its modulator. Background Technology
[0002] Optoelectronic computing systems are hybrid optoelectronic systems. Because they include a large number of optical devices, such as modulators, optical power beamsplitters, and photodetectors, they are quite sensitive to ambient temperature. Some modulators can be used to modulate optical signals based on electrical signals, thereby enabling information to be transmitted as optical signals.
[0003] When a photoelectric computing system performs computing tasks, the modulator may be affected by temperature or other factors. Sometimes it is necessary to calibrate the modulator. Calibration can make a certain optical path have a desired specific phase change, so that the modulator can work in a suitable state.
[0004] When running an optoelectronic computing system to perform computational tasks, calibration tasks and computational tasks may conflict because they both need to occupy the optical transmission channel. Summary of the Invention
[0005] This invention provides a computing system and a calibration method for related modulators that can resolve the aforementioned optical transmission channel occupancy conflicts.
[0006] According to one embodiment of the present invention, the computing system includes:
[0007] A photonic integrated circuit chip, comprising an optical transmission channel, wherein the optical transmission channel includes a modulator;
[0008] The control unit includes a register storing information indicating the occupancy status of the optical transmission channel; and
[0009] A calibration module is used to calibrate the modulator;
[0010] The calibration module determines whether to calibrate the modulator based on information in the register of the control unit.
[0011] In some implementations, the calibration module is configured to send a first control command to the photonic integrated circuit chip based on information in the register of the control unit, the first control command including a command instructing the photonic integrated circuit chip to perform the calibration.
[0012] In some embodiments, the computing system further includes a computing task management module, which sends a second control command to the photonic integrated circuit chip based on information in the registers of the control unit.
[0013] In some embodiments, the control unit is configured to receive the first control command or the second control command and send the received first control command or the second control command to the photonic integrated circuit chip.
[0014] In some implementations, the control unit includes a buffer for temporarily storing the first control command or the second control command.
[0015] In some embodiments, the modulator includes a calibration section. The first control command being executed to calibrate the modulator includes applying an input electrical signal to the calibration section to control the phase of the optical path corresponding to the calibration section.
[0016] In some embodiments, the modulator includes an MZI (Mach-Zehnder interferometer) modulator comprising a first arm and a second arm. The first arm includes a first calibration segment, and the second arm includes a second calibration segment; the calibration segment includes both the first and second calibration segments. In some embodiments, applying an input electrical signal to the calibration segment includes applying an electrical signal to at least one of the first and second calibration segments.
[0017] In some implementations, the control unit is also configured to forward information read from the photonic integrated circuit chip.
[0018] In some implementations, the control unit includes an FPGA (Field Programmable Gate Array) chip.
[0019] Embodiments of the present invention also provide a calibration method for a modulator in a computing system, the computing system including an optical transmission channel, the optical transmission channel including a modulator. The calibration method includes:
[0020] Read the information from the register, which indicates the occupancy status of the optical transmission channel;
[0021] The modulator is calibrated based on the information in the register.
[0022] In some embodiments, the computing system includes a photonic integrated circuit chip, which includes the optical transmission channel.
[0023] The step of performing calibration of the modulator based on the information in the register includes:
[0024] When the information indicates that the optical transmission channel is not occupied, a first control command is sent to the photonic integrated circuit chip; the first control command is executed to calibrate the modulator.
[0025] In some embodiments, the modulator includes a calibration section. The first control command being executed to calibrate the modulator includes applying an input electrical signal to the calibration section to control the phase of the optical path corresponding to the calibration section.
[0026] In some embodiments, the modulator includes an MZI modulator comprising a first arm and a second arm. The first arm includes a first calibration segment, and the second arm includes a second calibration segment; the calibration segment includes both the first and second calibration segments. In some embodiments, applying an input electrical signal to the calibration segment includes applying an electrical signal to at least one of the first and second calibration segments.
[0027] In some implementations, the computing system includes an FPGA chip that includes the registers.
[0028] In some implementations, the FPGA chip is configured to receive the first control command and send the received first control command to the photonic integrated circuit chip.
[0029] In some implementations, the FPGA chip includes a buffer for temporarily storing the first control command.
[0030] According to an embodiment of the present invention, by setting a register that stores information indicating the occupancy status of the optical transmission channel and performing calibration of the modulator in the optical transmission channel based on this information, the conflict between calibration tasks and other tasks in occupying the optical transmission channel can be effectively avoided.
[0031] Various aspects, features, and advantages of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Attached Figure Description
[0032] Figure 1 This is a block diagram illustrating an example architecture of a computing system according to an embodiment of the present invention.
[0033] Figure 2 This is a block diagram illustrating an example architecture of a computing system according to another embodiment of the present invention.
[0034] Figure 3 This is a schematic diagram of the modulator according to an embodiment of the present invention. Detailed Implementation
[0035] In the following description, exemplary embodiments of the invention will be described in more detail with reference to the accompanying drawings. However, it should be understood that the invention may be embodied in various different forms and should not be construed as limited to the embodiments shown herein. Rather, these embodiments are provided by way of example so that the description of the invention will be thorough and complete, and will fully convey to those skilled in the art various aspects and features of the invention.
[0036] It should be understood that this document may not describe processes, elements, and techniques that are not necessary for those skilled in the art to fully understand the various aspects and features of the invention. The terms “comprising,” “including,” and “having” as used herein specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when preceding it, rather than individual elements of that list.
[0037] Furthermore, the terms “first,” “second,” and other similar terms are intended to distinguish different objects and do not imply priority, order, or sequence unless explicitly stated herein.
[0038] Figure 1 An exemplary embodiment of the computing system of the present invention is shown. For example... Figure 1As shown, according to one embodiment of the present invention, the computing system 10 includes a photonic integrated circuit chip 100, a control unit 200, and a calibration module 300. The photonic integrated circuit chip 100 includes an optical transmission channel 105, which includes a modulator 101 and an optical waveguide 104. The modulator 101 can be used to modulate the optical signal transmitted in the optical waveguide 104 according to an electrical signal, thereby enabling information to be transmitted as an optical signal. During system operation, the modulator 101 may be affected by temperature or other factors, and sometimes it is necessary to calibrate the modulator 101. Calibration can cause a desired specific phase change in a certain optical path, etc., so that the modulator 101 operates in a suitable state. In some embodiments, the calibration module 300 is used to calibrate the modulator. In some implementations, the calibration task and the system's computational task are executed independently. However, they may conflict because both require the simultaneous use of the optical transmission channel. Therefore, the control unit 200 of this invention includes a register 201 that stores information indicating the occupancy status of the optical transmission channel 105 of the photonic integrated circuit chip 100. The calibration module 300 determines whether to calibrate the modulator 101 based on the information in the register 201 of the control unit 200. Exemplarily, the calibration module 300 sends a first control command to the photonic integrated circuit chip 100 based on the information in the register 201 of the control unit 200. The photonic integrated circuit chip 100 executes the first control command, thereby performing the calibration of the modulator 101. In an exemplary implementation, the calibration module 300 reads the information in the register 201. When the information indicates that the optical transmission channel 105 of the photonic integrated circuit chip 100 is not occupied, it sends the first control command, thereby avoiding calibration when the optical transmission channel 105 is occupied, which could lead to a conflict. In some implementations, register 201 stores a value of "0" to indicate that the optical transmission channel 105 is occupied, and stores a non-zero value to indicate that the optical transmission channel is not occupied.
[0039] In some embodiments, the modulator 101 includes a calibration section. The photonic integrated circuit chip 100 executing a first control command to calibrate the modulator 101 includes applying an input electrical signal to the calibration section to control the phase of the optical path corresponding to the calibration section, so that the modulator 101 operates in a suitable state.
[0040] In some embodiments of the present invention, such as Figure 3As shown, the modulator 101 includes an MZI modulator, which includes a first arm (upper arm) 110 and a second arm (lower arm) 120. Each arm has a data segment 102 and a calibration segment 103. The calibration segment 103 of the first arm 110 is described as a first calibration segment, and the calibration segment 103 of the second arm 120 is described as a second calibration segment. The data segment 102 is used to convert electrical signals carrying information into optical signals for data transmission. The calibration segment 103 can be used to calibrate the phase of a certain optical path in the modulator. For example, if the modulator has an unwanted inherent phase difference in this arm due to manufacturing process, ambient temperature, etc., the calibration segment 103 can be adjusted to make the phase difference zero. The calibration segment 103 can also be used to make a certain arm have a desired specific phase, etc. In some embodiments, applying an input electrical signal to the calibration segment 103 includes applying an electrical signal to at least one of the first calibration segment of the first arm 110 and the second calibration segment of the second arm 120.
[0041] It should be understood that, in addition to the modulator 101, the optical transmission channel of the photonic integrated circuit chip 100 may also include optical devices such as optical power beam splitters and photodetectors.
[0042] It should also be understood that, in addition to the calibration module 300, the computing system 10 may also have modules that perform other tasks. The calibration task may conflict with other tasks that simultaneously require the optical transmission channel. This invention effectively avoids this conflict through the settings of register 201.
[0043] Figure 2 Another exemplary embodiment of the computing system of the present invention is shown. Figure 1 Compared to the computing system 10 shown, the computing system 20 in this embodiment further includes a computing task management module 400. The computing task management module 400 sends a second control command to the photonic integrated circuit chip 100 based on information in the register 201 of the control unit 200. The photonic integrated circuit chip 100 executes the second control command, for example, by enabling data transmission through the optical transmission channel 105. Exemplarily, in some embodiments, the computing task management module 400 can manage electronic computing units (...). Figure 2 (Not shown) The calculation is performed using electrical signals, while the optical transmission channel 105 can transmit data using optical signals. Thus, the computing system 20 constitutes an optoelectronic computing system. For example, the electronic computing unit can be integrated into an electronic integrated circuit chip, which constitutes part of the computing system 20.
[0044] In some embodiments, the photonic integrated circuit chip 100 can use optical signals for calculation and convert the calculation results into electrical signals through photoelectric conversion. The computing system 20 may include an electronic integrated circuit chip. Figure 2 (Not shown), the electrical signal after photoelectric conversion is transmitted to an electronic integrated circuit chip for further processing.
[0045] In some implementations, at least one of the computing task management module and the calibration module can be integrated into an electronic integrated circuit chip. Exemplarily, at least one of the computing task management module and the calibration module can be manufactured using semiconductor processes, thus serving as part of the electronic integrated circuit chip.
[0046] When the computing system 20 executes a computing task, the optical transmission channel 105 can be used to transmit certain data related to the computing task. The execution of the calibration task and the computing task may conflict because both require the optical transmission channel to be used simultaneously. Therefore, the computing task management module 400 sends a second control command to the photonic integrated circuit chip 100 based on information in the register 201 of the control unit 200. In an exemplary embodiment, the computing task management module 400 reads information from the register 201. When this information indicates that the photonic integrated circuit chip 100 is not in a calibration state (e.g., when the optical transmission channel 105 is not occupied by a calibration task), it sends a second control command to enable data transmission through the optical transmission channel, thereby avoiding conflict with the calibration process.
[0047] In some embodiments, the control unit 200 is configured to receive the first control command or the second control command and send the received first control command or the second control command to the photonic integrated circuit chip.
[0048] In some embodiments, the control unit 200 includes a buffer 202 for temporarily storing the first control command or the second control command.
[0049] In some embodiments, the control unit 200 is also configured to forward information read from the photonic integrated circuit chip 100.
[0050] In one exemplary embodiment, the control unit 200 includes an FPGA chip. This FPGA chip has a parallel processing command mechanism. As a relay station for signal transmission and processing, the FPGA chip can receive control commands to the photonic integrated circuit chip 100 from the calibration module 300 and the computing task management module 400, or return information read from the photonic integrated circuit chip 100 to the corresponding modules. In some embodiments, the calibration module 300 and the computing task management module 400 can be program modules or software running on a host computer (e.g., a computer). Conflicts may occur when the FPGA chip receives multiple tasks or commands simultaneously. For example, the execution of calibration tasks and computing tasks are independent, and they may conflict because they both need to occupy the optical transmission channel simultaneously. Therefore, the FPGA chip (i.e., the control unit 200) is equipped with a register 201 and a buffer 202 to facilitate the serialization of multiple command processing. Exemplarily, the buffer 202 adopts a FIFO (First-In-First-Out) mechanism.
[0051] For example, when the value of register 201 is 0, that is, register 201 is in an unlocked state, the host computer can write any value. When the value of register 201 is 0, that is, register 201 is in a locked state, the host computer cannot write any non-zero value, only writing 0 can initialize register 201 back to 0.
[0052] When the host computer needs to send or receive control commands, such as when the calibration module 300 needs to send a first control command or the computing task management module 400 needs to send a first control command, it first reads the value of register 201. Specifically, when the value of register 201 is not equal to 0, register 201 is in a locked state, and the host computer program (e.g., calibration module 300 or computing task management module 400) must wait until the value read from register 201 is 0; when the value of register 201 is 0, register 201 is in an unlocked state, and the host computer program (e.g., calibration module 300 or computing task management module 400) can set the value of register 201 to any non-zero value, and then send the control command to the FPGA chip. In some embodiments, the host computer control command is transmitted to the FPGA chip (i.e., control unit 200) through the PCIe interface.
[0053] According to the above exemplary implementation, through the processing mechanism of the FPGA chip, when multiple control commands (which may come from different programs of the same device, such as from the calibration module or the computing task management module, or from multiple different devices) are passed in, the FPGA chip can serialize these commands and forward them to the photonic integrated circuit chip in an orderly manner, thereby avoiding conflicts in the occupancy of the optical transmission channel of the photonic integrated circuit chip by different control commands.
[0054] Furthermore, embodiments of the present invention also provide a calibration method for a modulator of a computing system, the method comprising at least a portion of the processing or operation involved in the computing system of any embodiment.
[0055] In one exemplary embodiment, the calibration method includes the following processes:
[0056] S100, Read the information from the register, which indicates the occupancy status of the optical transmission channel;
[0057] S200, calibrating the modulator is performed based on the information in the register, the modulator being contained in the optical transmission channel of the photonic integrated circuit chip.
[0058] In some implementations, in processing S200, performing calibration of the modulator based on the information in the register includes: sending a first control command to the photonic integrated circuit chip when the information indicates that the optical transmission channel is not occupied; the first control command is executed to calibrate the modulator.
[0059] In some embodiments, the modulator includes a calibration section. The first control command being executed to calibrate the modulator includes applying an input electrical signal to the calibration section to control the phase of the optical path corresponding to the calibration section.
[0060] In some implementations, such as Figure 3 As shown, the modulator includes an MZI modulator, which comprises a first arm 110 and a second arm 120. Each arm has a data segment 102 and a calibration segment 103. The calibration segment 103 of the first arm 110 is described as a first calibration segment, and the calibration segment 103 of the second arm 120 is described as a second calibration segment. Applying an input electrical signal to the calibration segment 103 includes applying an electrical signal to at least one of the first calibration segment of the first arm 110 and the second calibration segment of the second arm 120.
[0061] In some embodiments, the register is configured in an FPGA chip. The FPGA chip is configured to receive the first control command and send the received first control command to the photonic integrated circuit chip. In some embodiments, the FPGA chip includes a buffer for temporarily storing the first control command. The FPGA chip serializes multi-command processing by setting the register and the buffer. In an exemplary embodiment, the buffer employs a FIFO mechanism. In processing S200, performing the calibration of the modulator based on the information in the register includes: reading a value from the register, wherein when the value of the register is != 0 (i.e., not equal to 0), the register is in a locked state, indicating that the optical transmission channel of the photonic integrated circuit chip is occupied by other tasks, and the sending of the first control command to the FPGA chip is suspended until the read register value is 0; when the register is 0, the register is in an unlocked state, indicating that the optical transmission channel of the photonic integrated circuit chip is not occupied by other tasks, and control commands regarding the calibration of the modulator can be sent to the FPGA chip, and the register is set to any non-zero value to indicate that the optical transmission channel of the photonic integrated circuit chip is currently occupied, and other tasks should not send control commands temporarily.
[0062] The calibration method according to embodiments of the present invention avoids conflicts between calibration tasks and other tasks, and can perform reliable and effective calibration of the modulator of a photonic integrated circuit chip.
[0063] Those skilled in the art should understand that the embodiments disclosed above are intended to fully explain the technical solution of the present invention and are not intended to limit the scope of the claimed patent protection. Various modifications, alterations, or variations can be made to the embodiments without departing from the spirit or essence of the present invention. These modifications, alterations, or variations still fall within the scope covered by the claims of the present invention.
Claims
1. A computing system comprising: a photonic integrated circuit chip comprising an optical transmission channel, the optical transmission channel comprising a modulator; a control unit comprising a register storing information indicative of an occupancy state of the optical transmission channel; and a calibration module configured to calibrate the modulator; wherein the calibration module determines whether to calibrate the modulator according to the information in the register of the control unit.
2. The computing system of claim 1, wherein, The calibration module is configured to send a first control command to the photonic integrated circuit chip according to the information in the register of the control unit, the first control command comprising a command instructing the photonic integrated circuit chip to perform the calibration.
3. The computing system of claim 2, wherein, The computing system further comprises a computing task management module configured to send a second control command to the photonic integrated circuit chip according to the information in the register of the control unit.
4. The computing system of claim 3, wherein, The control unit is configured to receive the first control command or the second control command and send the received first control command or second control command to the photonic integrated circuit chip.
5. The computing system of claim 4, wherein, The control unit comprises a buffer configured to temporarily store the first control command or the second control command.
6. The computing system of claim 2, wherein, The modulator comprises a calibration section, The first control command is executed to calibrate the modulator by applying an input electrical signal to the calibration section to control a phase of a corresponding optical path of the calibration section.
7. The computing system of claim 6, wherein, The modulator comprises a MZI modulator comprising a first arm and a second arm, the first arm comprising a first calibration section and the second arm comprising a second calibration section;The calibration section comprises the first calibration section and the second calibration section.
8. The computing system of claim 7, wherein, The applying of the input electrical signal to the calibration section comprises applying an electrical signal to at least one of the first calibration section and the second calibration section.
9. The computing system of claim 4, wherein, The control unit is further configured to forward information read from the photonic integrated circuit chip.
10. The computing system of any of claims 1 to 9, wherein, The control unit comprises an FPGA chip. 11.A calibration method for a modulator of a computing system, the computing system comprising an optical transmission channel, the optical transmission channel comprising a modulator, wherein the calibration method comprises: reading information of a register, the information being indicative of an occupancy state of the optical transmission channel; performing calibration of the modulator according to the information of the register.
12. The calibration method of claim 11, wherein, The computing system comprises a photonic integrated circuit chip, the photonic integrated circuit chip comprising the optical transmission channel; The performing of the calibration of the modulator according to the information of the register comprises: when the information is indicative of the optical transmission channel being unoccupied, sending a first control command to the photonic integrated circuit chip; The first control command is executed to calibrate the modulator.
13. The calibration method of claim 12, wherein, The modulator comprises a calibration section, The first control command is executed to calibrate the modulator by applying an input electrical signal to the calibration section to control a phase of a corresponding optical path of the calibration section.
14. The calibration method of claim 13, wherein, The modulator comprises a MZI modulator comprising a first arm and a second arm, the first arm comprising a first calibration section and the second arm comprising a second calibration section;The calibration section comprises the first calibration section and the second calibration section.
15. The method of calibration of claim 14, wherein, The applying an input electrical signal to the calibration segment includes applying an electrical signal to at least one of the first calibration segment and the second calibration segment.
16. The method of calibration of claim 12, wherein, The computing system includes an FPGA chip that includes the register.
17. The method of calibration of claim 16, wherein, The FPGA chip is configured to receive the first control command and send the received first control command to the photonic integrated circuit chip.
18. The method of calibration of claim 17, wherein, The FPGA chip includes a buffer to temporarily store the first control command.