Performance analysis method and device for source address verification, equipment and storage medium

Abstract

The invention provides a performance analysis method and device for source address verification, equipment and a storage medium, and relates to the technical field of network security. The method comprises the following steps: receiving a source address verification processing program written through a description language; loading an algorithm configuration file; wherein the algorithm configuration file at least comprises a performance model configured for a plurality of preset algorithms, and the performance model is used for calculating the consumed time length of the operation statement based on the operand length of each operation statement; based on the source address verification processing program and the performance model, calculating the consumed time length of each operation statement; and generating a performance analysis report of the source address verification processing program according to the time-consuming duration of all the operation statements in the source address verification processing program. According to the embodiment of the invention, automatic and theoretical performance analysis can be carried out on the source address verification processing flow based on the formalized description language and the predefined algorithm configuration file under the condition of separating from the dependence of specific hardware.

Description

Technical Field

[0001] This invention relates to the field of network security technology, and in particular to a performance analysis method, apparatus, device, and storage medium for source address verification. Background Technology

[0002] With the increasing frequency of cross-domain source address spoofing attacks, distributed denial-of-service (DDoS) attacks, and reflection attacks, Source Address Validation (SAV) mechanisms have become a key foundational technology for system-level security protection within Internet autonomous systems (AAS). The core of the SAV mechanism lies in the fact that the data plane needs to perform a series of complex verification operations for each network packet, such as hash calculations, table lookups, tag generation and verification, etc. Therefore, accurately assessing the performance overhead introduced by different SAV schemes in the data plane is crucial for scheme selection, standardization, and deployment in actual high-speed network equipment.

[0003] Currently, industry evaluation of SAV solutions primarily relies on real-world testing on actual or dedicated programmable hardware platforms (such as specific switch or router models). This method first requires fully implementing the target SAV solution as an executable data plane program (e.g., using P4 language), then deploying it to hardware, and measuring performance metrics such as processing latency and throughput by sending test traffic. However, this hardware-based testing method suffers from significant drawbacks, including high testing costs and strong platform dependence. Because different hardware platforms have varying architectures, resources, and performance baselines, it is difficult to conduct fair and unified comparisons of performance data between different SAV solutions, and it also hinders rapid and low-cost performance iteration and exploration in the early stages of solution design.

[0004] Therefore, there is currently a lack of an effective means to formally describe the data plane processing logic of the SAV scheme and automatically derive its theoretical performance overhead without being dependent on specific hardware. Summary of the Invention

[0005] This invention provides a performance analysis method, apparatus, device, and storage medium for source address verification, which can automate and theoretically analyze the source address verification process based on a formal description language and predefined algorithm configuration files without being dependent on specific hardware.

[0006] In a first aspect, the present invention provides a performance analysis method for source address verification, comprising the following steps: Receive a source address verification handler written in a description language; wherein the source address verification handler includes at least a plurality of operation statements; Load the algorithm configuration file; wherein the algorithm configuration file includes at least a performance model configured for multiple preset algorithms, and the performance model is used to calculate the time consumption of the operation statement based on the operand length of each operation statement; Based on the source address verification process and the performance model, calculate the time consumption of each operation statement; Based on the time taken by all operation statements in the source address verification process, a performance analysis report of the source address verification process is generated.

[0007] Preferably, according to the performance analysis method for source address verification provided by the present invention, before the step of calculating the time consumption of each operation statement based on the source address verification processing program and the performance model, the method includes: The source address verification process is parsed to obtain data definition statements and operation statements; A symbol table is constructed based on the data definition statement; wherein, the symbol table is used to record variable identifiers and the lengths of operands corresponding to the variable identifiers; Based on the operation statement and the symbol table, the time consumption function corresponding to the algorithm for the operand is obtained from the algorithm configuration file.

[0008] Preferably, in the performance analysis method for source address verification provided by the present invention, the data definition statement is used to declare variable identifiers and associated operand lengths; The operation statements are used to invoke the algorithm in the algorithm configuration file to operate on the declared variables; The performance model includes at least a time consumption function, which is used to calculate the time consumption of the operation statement based on the operand length of each operation statement. Each algorithm is configured with at least one time consumption function.

[0009] Preferably, according to the performance analysis method for source address verification provided by the present invention, before the step of obtaining the time-consuming function of the algorithm corresponding to the operands from the algorithm configuration file based on the operation statement and the symbol table, the method includes: Check if the algorithm to be invoked for each of the aforementioned operation statements exists in the algorithm configuration file; Check whether the number of operands provided by the operation statement is consistent with the number of operands required for the algorithm configured in the algorithm configuration file; Check whether each operand in the operation statement has been recorded in the symbol table.

[0010] Preferably, in the performance analysis method for source address verification provided by the present invention, the performance model includes at least an output length function; After the step of parsing the source address verification process to obtain the data definition statement and operation statement, the method includes: When the operation statement indicates an assignment result, the assignment result length is calculated based on the operand length in the operation statement and the output length function of the corresponding algorithm. Update the symbol table with the variable identifier of the assignment result and the corresponding length of the assignment result.

[0011] Preferably, according to the performance analysis method for source address verification provided by the present invention, the step of calculating the time consumption of each operation statement based on the source address verification processing program and the performance model includes: The operand length of the operand is obtained from the symbol table according to the operation statement, and the time consumption function of the algorithm corresponding to the operand is obtained from the algorithm configuration file; The operand length is substituted into the time consumption function to calculate the time consumption of the operation statement.

[0012] Preferably, according to the performance analysis method for source address verification provided by the present invention, the step of substituting the operand length of the operand into the time consumption function to calculate the time consumption of the operation statement includes: When the operand length in the symbol table is a symbolic variable, the symbolic variable is substituted into the time-consuming function to generate the performance overhead of the operation statement; wherein, the performance overhead is an expression containing the symbolic variable.

[0013] Secondly, the present invention also provides a performance analysis device for source address verification, comprising the following modules: A receiving module is used to receive a source address verification processing program written in a description language; wherein the source address verification processing program includes at least a plurality of operation statements; A loading module is used to load algorithm configuration files; wherein the algorithm configuration files include at least performance models configured for multiple preset algorithms, and the performance models are used to calculate the time consumption of the operation statement based on the operand length of each operation statement; The calculation module is used to calculate the time consumption of each operation statement based on the source address verification process and the performance model. The generation module is used to generate a performance analysis report of the source address verification process based on the time consumption of all operation statements in the source address verification process.

[0014] Thirdly, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the performance analysis method for source address verification as described above.

[0015] Fourthly, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the performance analysis method for source address verification as described above.

[0016] Fifthly, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the performance analysis method for source address verification as described above.

[0017] This invention provides a performance analysis method, apparatus, device, and storage medium for source address verification. The method involves receiving a source address verification processing program written in a formal description language, wherein the source address verification processing program includes at least multiple operation statements; loading an algorithm configuration file, wherein the algorithm configuration file includes at least performance models configured for multiple preset algorithms, the performance models being used to calculate the execution time of each operation statement based on the operand length of each operation statement; calculating the execution time of each operation statement based on the source address verification processing program and the performance models; and generating a performance analysis report for the source address verification processing program based on the execution time of all operation statements in the source address verification processing program. This method enables automated and theoretical performance analysis of the source address verification process based on a formal description language and predefined algorithm configuration files, independent of specific hardware dependencies. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the performance analysis method for source address verification provided by the present invention.

[0020] Figure 2 This is a schematic diagram of the performance analysis device for source address verification provided by the present invention.

[0021] Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] First, it should be noted that all actions involving the acquisition of signal information or data in this invention are carried out in compliance with the relevant data protection laws and policies of the country where the invention is located, and with the authorization granted by the owner of the relevant device.

[0024] The following is combined with Figures 1-3 This invention describes a performance analysis method, apparatus, device, and storage medium for source address verification, which enables automated and theoretical performance analysis of the source address verification process based on a formal description language and predefined algorithm configuration files, independent of specific hardware dependencies.

[0025] Figure 1 This is a flowchart illustrating a performance analysis method for source address verification provided by the present invention, as shown below. Figure 1 As shown, the method may include, but is not limited to, steps S100 to S400: S100, receive a source address verification processing program written in a description language; wherein, the source address verification processing program includes at least a plurality of operation statements; S200, Load algorithm configuration file; wherein, the algorithm configuration file includes at least a performance model configured for multiple preset algorithms, and the performance model is used to calculate the time consumption of the operation statement based on the operand length of each operation statement; S300, based on the source address verification process and the performance model, calculate the time consumption of each operation statement; S400: Generate a performance analysis report for the source address verification process based on the time consumption of all operation statements in the source address verification process.

[0026] The performance analysis method for source address verification proposed in this invention will be described in detail and completely below with reference to the accompanying drawings and specific embodiments. The core of the performance analysis method for source address verification (SAV) proposed in this invention lies in abstracting the SAV processing logic through a formal description language (hereinafter referred to as the "modeling language") and automatically deriving the theoretical performance overhead of the logic using a predefined algorithm performance model.

[0027] One embodiment of the present invention automatically completes the entire process of parsing, verification, calculation and result generation by receiving a formalized processing description and a scalable algorithm performance model, and finally outputs quantifiable performance analysis conclusions.

[0028] The execution entity of this method is a performance modeling engine deployed on a computing device. This engine requires no manual intervention in the computation process; its automated workflow begins by simultaneously reading two input files: the SAV processing program file (e.g., program.dpdl) and the algorithm configuration file (e.g., algo_models.csv). Subsequently, the engine sequentially launches modules such as lexical analysis, syntax analysis, semantic analysis, performance calculation, and result synthesis, ultimately outputting a performance analysis report to a file or visualization interface. The entire process is program-scheduled, triggering each functional module in turn.

[0029] In some embodiments, the Network Packet Processing Description Language (DPDL-SAV) for source address verification performance modeling is used to formally describe the data plane verification process and automatically calculate the overall processing time function.

[0030] This description language enables those skilled in the art to quickly estimate the performance of different SAV schemes in the data plane without the need for real equipment by abstracting operational semantics, algorithm parameterization, and symbolic performance derivation.

[0031] In step S100 of some embodiments, a source address verification process written in a description language is received; wherein the source address verification process includes at least a plurality of operation statements.

[0032] The system provides a file upload interface or text editor, allowing users to submit or write modeling language code. This language is a domain-specific language (DSL) whose syntax is designed to concisely describe the processing steps of the data plane.

[0033] The modeling engine's file monitoring module or API interface detects new input events. This occurs when a file conforming to the naming conventions appears in the system path. When a .dpdl file is loaded, the file loading subroutine is automatically triggered. This subroutine reads the entire file content, converts it from a byte stream stored on disk to a string buffer in memory, and passes it to the downstream parsing module. This process is entirely program-controlled and does not rely on interactive commands.

[0034] The SAV (Source Address Verification) handler is, in this context, a text file conforming to a predefined syntax, containing a serialized description of the data plane verification logic. This enables automatic capture and preparation of input for the modeling task.

[0035] DPDL-SAV (Data Plane Description Language for Source AddressValidation) is a domain-specific language used to describe the processing flow of network data plane.

[0036] Unlike traditional P4, DPDL-SAV does not involve hardware implementation logic, but focuses on theoretically time-consuming computation and modeling.

[0037] This language uses algorithms as its basic unit and can formally define things like hash calculations. It performs algorithms such as encryption / decryption (AES, HMAC), table lookup (Search), tag generation (TagGen), and verification code comparison (Verify), and automatically derives the theoretical time consumption of each operation based on the length of the input operands, the algorithm complexity, and the parameters defined in the configuration file.

[0038] In SAV applications, DPDL-SAV can be used to: model verification paths with different mechanisms (such as Ingress / Egress verification); calculate the cumulative time consumption of different algorithm combinations (HMAC, AES, lookup table); and compare the performance differences of schemes under different message sizes and verification complexities.

[0039] In step S200 of some embodiments, an algorithm configuration file is loaded; wherein the algorithm configuration file includes at least a performance model configured for multiple preset algorithms, and the performance model is used to calculate the time consumption of the operation statement based on the operand length of each operation statement.

[0040] Understandably, the system reads the algorithm configuration file from a preset path or a user-specified location. This configuration file uses a structured format (such as CSV, JSON, or YAML), where each line or entry defines a performance model for the algorithm, mapping the algorithm identifier to its performance mathematical model. The core of the performance model is the time consumption function, a mathematical expression that defines the functional relationship between the time required to execute the algorithm and the length of its input data (i.e., operands).

[0041] In some embodiments, the configuration management module loads the algorithm configuration file (algo_models.csv file) according to a preset path. The CSV parser automatically splits each row, identifying columns such as "algorithm name," "number of operands," "time-consuming function expression," and "output length function expression." The program then converts each row of data into an internal structure object and stores it in a hash table (i.e., an algorithm dictionary) with the algorithm name as the key. The time-consuming function expression is parsed into a evaluateable syntax tree form for subsequent computation.

[0042] This embodiment establishes a globally queryable algorithm performance knowledge base, providing a basis for subsequent automatic calculations.

[0043] In step S300 of some embodiments, the time consumption of each operation statement is calculated based on the source address verification process and the performance model.

[0044] This embodiment represents the core work of the compilation analysis engine. The engine parses the source address verification process line by line to identify the operation statements. For each operation statement, it first determines the algorithm called (such as extract), then finds the corresponding time-consuming function from the algorithm dictionary of the performance model, then obtains the operand length of the actual operands of the statement, and finally substitutes the operand length into the time-consuming function to calculate the time consumption of each operation statement.

[0045] In this embodiment, the computer execution program receives the Abstract Syntax Tree (AST) from the parsing module. It automatically identifies all nodes of type "operation statement" by traversing the AST. For each such node, it extracts the "algorithm identifier" and "operand list" of the operation statement from the source address verification handler. Then, it queries the algorithm dictionary to obtain the corresponding time-consuming function and queries the symbol table to obtain the operand length for each operand. Finally, it calls the time-consuming function from the algorithm dictionary, substitutes the operand length into the time-consuming function, and automatically calculates the time-consuming value or symbolic expression for the operation statement. This process is repeated until all operation statements have been processed.

[0046] In this embodiment, the operation statement is a node in the AST, representing an indivisible data processing action. The evaluator is a subroutine of the system, responsible for interpreting and executing mathematical expressions.

[0047] This embodiment achieves fully automatic conversion from syntax elements to performance data without the need for manual intervention in intermediate calculations.

[0048] In step S400 of some embodiments, a performance analysis report of the source address verification process is generated based on the time taken by all operation statements in the source address verification process.

[0049] In some embodiments of the present invention, the engine sums up the time consumed by all operation statements in the source address verification process (or calculates the worst-case or specified path if branches exist) to form the total overhead. The result can be a specific numerical value (when the length of all operands is constant) or a symbolic expression (when the length of operands is variable). The result output module presents this result in a formatted format, generating a performance analysis report of the source address verification process.

[0050] It should be noted that the time calculation results for all statements are temporarily stored in a list. The result synthesis module automatically iterates through this list and performs an accumulation operation for linear processes. If there are branches in the process, the time items to be accumulated are selected according to a preset strategy (such as calculating the worst path). After accumulation, a final expression or value representing the total cost is generated. The report generation subroutine formats this result into a text report (e.g., "Total Delay = 315 + 1.5"). N”, or pass it as a parameter to the visualization module.

[0051] This embodiment automatically integrates scattered performance data to form a final conclusive output.

[0052] In some embodiments of the present invention, before the step of calculating the time consumption of each operation statement based on the source address verification process and the performance model, the method includes: The source address verification process is parsed to obtain data definition statements and operation statements; A symbol table is constructed based on the data definition statement; wherein, the symbol table is used to record variable identifiers and the lengths of operands corresponding to the variable identifiers; Based on the operation statement and the symbol table, the time consumption function corresponding to the algorithm for the operand is obtained from the algorithm configuration file.

[0053] In some embodiments of the present invention, the data definition statement is used to declare variable identifiers and associated operand lengths; The operation statements are used to invoke the algorithm in the algorithm configuration file to operate on the declared variables; The performance model includes at least a time consumption function, which is used to calculate the time consumption of the operation statement based on the operand length of each operation statement. Each algorithm is configured with at least one time consumption function.

[0054] Understandably, the lexical analyzer scans the program string and automatically segments it into a stream of lexical units (tokens), such as identifiers, colons, and numbers. The parser, based on predefined grammar rules, drives a state machine to automatically process the token stream, identifying the boundaries and structure of "data definition statements" and "operation statements," and generating an abstract syntax tree (AST). During AST construction, whenever a complete data definition statement (such as `packet: L`) is identified, the parser automatically calls the symbol table management routine to insert a record into the symbol table. This record uses the variable name `packet` as the key, and its value is a property object where the `length` property is set to `L`.

[0055] The symbol table is a key data structure maintained internally by the compiler / interpreter, typically a hash table or dictionary, used to store attribute information of various identifiers (such as variable names) in the program. An Abstract Syntax Tree (AST) is a tree-like representation of the source code's syntactic structure, facilitating automated program analysis.

[0056] This embodiment uses automated syntax analysis to transform text programs into a traversable tree structure and simultaneously establishes an attribute database of program variables, providing context for semantic analysis and performance calculation.

[0057] When the performance calculation module encounters an operation statement node while traversing the AST, the program automatically extracts the algorithm name (e.g., SHA256) from that node. Subsequently, the program uses this algorithm name as the key to automatically look up the previously constructed algorithm dictionary. This is a simple hash lookup process. If the lookup is successful, the performance model object bound to that algorithm (containing time-consuming functions, etc.) is retrieved; if it fails, an error handling process is triggered.

[0058] This embodiment automatically establishes a link between operation calls in the program and the background mathematical model through efficient dictionary lookup.

[0059] In some embodiments, DPDL-SAV (a source address verification handler written in a description language) contains two types of statements: data definition statements: .

[0060] Here, data_name is a variable identifier representing the variable name; length is a number, constant, or symbolic variable.

[0061] Note that this language does not care about the specific value of the data, but only the length of the data that is directly related to the computation time. Therefore, the data definition only defines the length of the data and not its specific value. If the data length given here is an identifier indicating that the data length is variable, then if this data is used in the computation, the time result obtained will be a function that takes that identifier as an input parameter.

[0062] Operation statements: .

[0063] Here, algorithm is the algorithm name, which corresponds to the number of operands, execution time, and result function; res and opr are both identifiers, opr must be defined, and res can be undefined; opr_times indicates the number of times the operation is repeated, which is 1 if it does not exist; the initial "res =" can be omitted, indicating that the calculation result is not saved (only the execution time of this statement is calculated).

[0064] The language allows the combination of operations to form hierarchical structures, such as: , , , , This allows for an abstract representation of the tag generation process in a certain SAV scheme.

[0065] In some embodiments of the present invention, before the step of obtaining the time-consuming function of the algorithm corresponding to the operands from the algorithm configuration file according to the operation statement and the symbol table, the method includes: Check if the algorithm to be invoked for each of the aforementioned operation statements exists in the algorithm configuration file; Check whether the number of operands provided by the operation statement is consistent with the number of operands required for the algorithm configured in the algorithm configuration file; Check whether each operand in the operation statement has been recorded in the symbol table.

[0066] Understandably, the semantic analyzer is automatically invoked before the performance calculation module begins computation. This analyzer performs the following automatic checks for each operation statement node: Algorithm Existence Check: Automatically checks if the algorithm name extracted from the node exists in the key set of the algorithm dictionary. If it does not exist, an "Undefined Algorithm Error" object containing the error location and description is automatically generated, and the current compilation process is interrupted.

[0067] Operand count check: Automatically reads the standard number of operands required by the algorithm from the algorithm dictionary and compares it with the actual number of operand child nodes contained in the AST node. If the counts do not match, an "Operation count mismatch error" is automatically generated.

[0068] Operand definition check: Automatically traverses all operand identifier child nodes of this node. For each identifier, the program automatically queries the symbol table to check if a record exists with that identifier as the key. If any identifier is undefined, an "undefined variable error" is automatically generated.

[0069] Only after all these checks pass will the program allow the performance calculations described above to be performed.

[0070] Strict pre-validation is automatically performed before the calculation begins to ensure the logical validity of the input program, prevent "garbage in, garbage out", and ensure the reliability of the analysis results.

[0071] In some embodiments of the present invention, the performance model includes at least an output length function; After the step of parsing the source address verification process to obtain the data definition statement and operation statement, the method includes: When the operation statement indicates an assignment result, the assignment result length is calculated based on the operand length in the operation statement and the output length function of the corresponding algorithm. Update the symbol table with the variable identifier of the assignment result and the corresponding length of the assignment result.

[0072] Understandably, when processing an operation statement with an assignment result (such as `hash = sha256(packet)`), the program, after calculating the execution time, automatically obtains the output length function from the algorithm's performance model. The program substitutes the actual length values ​​of the operands into this function to calculate the theoretical length of the result variable (hash). Subsequently, the program automatically calls the symbol table management routine to insert or update the symbol table with `hash` and its calculated theoretical length as new entries. This process ensures that the newly generated variable attributes can be automatically recognized and used by subsequent statements.

[0073] The output length function in this embodiment is part of the performance model, defining the functional relationship between the size of the algorithm's output data and the size of its input data.

[0074] This embodiment realizes the automatic propagation of node attributes in the data flow graph, enabling the program to automatically handle multi-level serial operation processes.

[0075] In some embodiments of the present invention, calculating the time consumption of each operation statement based on the source address verification process and the performance model includes: The operand length of the operand is obtained from the symbol table according to the operation statement, and the time consumption function of the algorithm corresponding to the operand is obtained from the algorithm configuration file; The operand length is substituted into the time consumption function to calculate the time consumption of the operation statement.

[0076] Understandably, for each operation statement, the computation subroutine automatically performs the following operations: First, based on the operand identifier list, it initiates a series of query requests to the symbol table to automatically obtain the length attribute value corresponding to each operand, forming a "length parameter list." Simultaneously, it automatically retrieves the parsed time-consuming function syntax tree from the algorithm dictionary. Then, the computation subroutine binds the values ​​in the "length parameter list" sequentially to the corresponding variables in the time-consuming function syntax tree and automatically calls the mathematical engine to perform the evaluation. The evaluation result is the execution time of that statement.

[0077] This embodiment combines dynamic table lookup with static function evaluation to achieve accurate performance calculation in a specific context.

[0078] In some embodiments of the present invention, substituting the operand length of the operand into the time-consuming function to calculate the time consumption of the operation statement includes: When the operand length in the symbol table is a symbolic variable, the symbolic variable is substituted into the time-consuming function to generate the performance overhead of the operation statement; wherein, the performance overhead is an expression containing the symbolic variable.

[0079] Understandably, when the operand length retrieved from the symbol table is not a specific numerical value but a symbolic variable (such as L or N), the mathematical evaluator automatically switches to symbolic computation mode. In this mode, the mathematical evaluator does not attempt to calculate the specific value of log2(N), but instead applies the operation log2 to the symbol N, generating a new symbolic expression log2(N). Ultimately, the performance result of the entire statement and even the entire program will be expressed as a composite mathematical expression containing these symbolic variables (such as T_total = a...). L + b log2(N) + c). Subsequently, the visualization module can accept the range of symbolic variable values ​​specified by the user (or the upper-level script), automatically perform intensive sampling and numerical calculation on the expression, and drive the plotting library to generate performance trend curves. The entire process does not require modification of the original processing program or restarting the complete analysis process.

[0080] It should be noted that a symbolic variable represents an unknown or variable quantity, and retains its symbolic form during computation. Symbolic computation refers to the calculation of mathematical expressions using symbolic rather than numerical forms.

[0081] This embodiment achieves "modeling once, analysis multiple times," which can automatically generate analytical expressions that reveal the essential relationship between performance and key design parameters, and automatically perform parameter scanning and visualization based on the expressions, greatly improving the automation and efficiency of design space exploration.

[0082] In some embodiments, the system master controller automatically follows a predefined compilation pipeline. This pipeline sequentially activates components such as the lexical analyzer, syntax analyzer, semantic analyzer, performance calculator, and result synthesizer, and automatically passes data structures (such as token streams, ASTs, and symbol tables) between components. This pipelined automatic scheduling ensures the sequentiality and consistency of processing.

[0083] In some embodiments, when the final performance result is a symbolic expression, the system's visualization interface can receive instructions from an automation script, such as {"variable": "L", "range": [64, 1500], "steps": 100}. The program automatically takes 100 values ​​at equal intervals within the range of 64 to 1500, substitutes them into the expression sequentially to obtain 100 data points, and automatically calls a graphics library to draw a delay-message length curve. Finally, the image is saved or displayed.

[0084] In some embodiments, the function expressions in the algorithm configuration file can be generated through an automated process. For example, the system can integrate a micro-benchmarking framework that automatically compiles the algorithm kernel, runs it in a simulation environment or isolated hardware, collects time-consuming data under different input scales, then automatically calls a curve fitting program, selects the best-fit function (such as linear or logarithmic), generates coefficients, and finally automatically writes them into the algorithm configuration file. This constitutes an automated closed loop from measurement to modeling.

[0085] In some embodiments, a range of parameter values ​​for at least one symbolic variable is received, sampling is performed within the range of parameter values, the numerical calculation is performed on each sampled value to obtain a series of performance data points, and a performance change curve is generated based on the performance data points.

[0086] The method of this invention was used to model a source address verification (SAV) scheme, and a symbolic total delay formula was obtained, for example, T(L, N) = 2.1 L + 20 log2(N) + 100 (in nanoseconds), where L represents the variable message length and N represents the variable routing prefix table size. Researchers wanted to visually understand how latency changes as the message length L varies within a typical range (e.g., 64 to 1500 bytes).

[0087] Input analysis commands through the system's graphical user interface (GUI) or script interface. These commands specify the target symbolic variable, its value range, and sampling precision. For example, submitting via a GUI form: Analysis variable: L, Starting value: 64, Ending value: 1500, Number of sampling points: 100.

[0088] The system instruction parsing module automatically receives and parses this instruction, extracting key parameters: symbolic variable identifier L, value range [64, 1500], and sampling quantity 100.

[0089] The system's parameter sampling module executes automatically based on the parsed instructions. It adopts an equal-interval sampling strategy, and the calculated sampling step size is (1500 - 64) / (100 - 1) ≈ 14.55.

[0090] The module automatically generates a sampling sequence containing 100 values: L1=64, L2≈78.55, L3≈93.10, …, L 100 =1500. This sequence is stored in a memory array for use in the next calculation.

[0091] The system performance calculation engine is automatically invoked and enters the numerical calculation loop. The engine sequentially reads each value L from the sample array. i .

[0092] For each L i The engine replaces the symbolic variable L in the performance model T(L, N) with the specific numerical value L. i (Meanwhile, other variables such as N need to be assigned a fixed value, for example, N=100000, which can be preset or specified by the user.) The engine then automatically calculates the numerical result T of the expression. i .

[0093] After the loop ends, the engine outputs a value consisting of (L) i , T i A set of performance data points composed of data pairs, for example: [(64,423.8), (78.55, 457.2), …, (1500, 3250.5)].

[0094] The system's visualization module automatically receives the above set of performance data points.

[0095] The module calls a built-in plotting library (such as Matplotlib or Plotly) to automatically create a two-dimensional coordinate plot. The horizontal axis is labeled "Message Length (Bytes)" and the vertical axis is labeled "Verification Delay (nanoseconds)".

[0096] The module will include all (L) i , T i The data points are plotted on the graph and automatically connected with smooth line segments to form a continuous trend curve.

[0097] Ultimately, the performance change curve is automatically rendered in the analysis results area of ​​the system interface, or saved as an image file (such as PNG format) for output.

[0098] In some embodiments of the present invention, the compilation process of DPDL-SAV adopts a line-by-line linear compilation strategy, which is jointly implemented through a symbol table, an operation table, and a time-consuming function parsing module. The overall process is as follows: First, statement parsing and classification are performed; that is, the compiler first parses the input DPDL-SAV program line by line, distinguishing it into data definition statements and operation statements.

[0099] For data definition statements The system registers the variable name and length information in the variable table and marks the variable as "defined".

[0100] like If it is a symbolic variable, then the variable is marked as a dynamic length variable, and a symbolic function expression will be generated in the subsequent time-consuming calculation.

[0101] Algorithm validity checking and parameter validation, i.e., when parsing operation statements... At that time, the compiler will perform multiple layers of verification: examine Check if it's defined in the configuration file; if not, report an error. Check if the number of input operands matches the algorithm definition. Check if each operand is defined in the variable table and has a valid length. After the evaluation of the time-consuming function and the return value derivation pass verification, the compiler reads the corresponding algorithm's time-consuming function and return value length function from the configuration file. Substitute the operand length into the time consumption function to calculate the theoretical time consumption of a single operation; If there exists " If the total time is calculated by multiplication and summation, then the total time will be calculated. If the assignment statement "res =" exists, then the operand length is substituted into the return value length function to derive the result. The length information is updated, and the variable table is updated.

[0102] After compilation, the system sums the time-consuming functions of all statements to obtain the complete total time-consuming expression: in, A time-consuming function for each statement. The length of its corresponding operand.

[0103] DPDL-SAV supports symbolic compilation. When the input contains variable-length data (such as message size and AS_PATH length), the system will generate corresponding symbolic expressions to automatically plot performance trend curves under different input parameters.

[0104] In Source Address Verification (SAV) scenarios, this symbolic analysis can help researchers quickly assess the impact of changes in message length or path complexity on verification latency and throughput performance.

[0105] A core feature of DPDL-SAV is the extensibility and customization capabilities of its algorithm configuration files. The configuration files define the basic properties of the algorithm in a declarative format, including: algorithm name; number of operands; time function; and output length function.

[0106] Users can flexibly define algorithm configuration files according to different application scenarios. The algorithm configuration files adopt a CSV structure, for example: , The system automatically loads these definitions during compilation and calls them in operation statements.

[0107] This embodiment provides a default configuration file containing common operations (hashing, encryption, table lookup, message verification codes, etc.). Users can also extend this file by adding algorithms and their parameter counts and execution times directly into the configuration CSV file. Users need to define the corresponding time functions through experimental measurements (micro-benchmarking) or theoretical analysis. DPDL-SAV automatically parses these expressions during execution to generate a complete performance model.

[0108] The method provided by this invention can be used not only for performance modeling of network data plane operations, but also for any sequential processing task (such as signal processing, data encryption, message filtering, etc.), provided that the operation time mainly depends on the input length.

[0109] In SAV scenarios, configuration files allow users to define time models for various message verification algorithms, such as hash-based tag generation (HMAC-SHA256), key table-based fast lookup (Binary Search over ASTable), and cryptographic signature-based identity verification (AES or ECC Verify). Through the combined definitions in configuration files, researchers can quickly simulate the performance differences of different implementation schemes, providing a basis for optimizing the high-performance data plane of SAV.

[0110] To facilitate user-defined algorithms, this embodiment also provides a conversion function from algorithm function to time consumption function. The input is the algorithm provided by the user; we perform a black-box time consumption test on the algorithm and output its time consumption function.

[0111] This abstract transformation from algorithm to time consumption gives the language a certain degree of versatility. This language can fit hashing, encryption / decryption, table lookup, and other operations with time consumption in the form of linear or simple piecewise functions, thus directly transforming the operation flow of source address verification mechanisms into computable performance metrics.

[0112] The performance analysis apparatus for source address verification provided by the present invention is described below. The performance analysis apparatus for source address verification described below and the performance analysis method for source address verification described above can be referred to in correspondence.

[0113] like Figure 2 The diagram shows a structural schematic of a performance analysis device for source address verification provided by the present invention. The performance analysis device for source address verification includes the following modules: The receiving module 210 is used to receive a source address verification processing program written in a description language; wherein the source address verification processing program includes at least a plurality of operation statements; The loading module 220 is used to load the algorithm configuration file; wherein the algorithm configuration file includes at least a performance model configured for multiple preset algorithms, and the performance model is used to calculate the time consumption of the operation statement based on the operand length of each operation statement; The calculation module 230 is used to calculate the time consumption of each operation statement based on the source address verification process and the performance model. The generation module 240 is used to generate a performance analysis report of the source address verification process based on the time consumption of all operation statements in the source address verification process.

[0114] Preferably, the performance analysis device for source address verification provided by the present invention is specifically used to parse the source address verification processing program to obtain data definition statements and operation statements; A symbol table is constructed based on the data definition statement; wherein, the symbol table is used to record variable identifiers and the lengths of operands corresponding to the variable identifiers; Based on the operation statement and the symbol table, the time consumption function corresponding to the algorithm for the operand is obtained from the algorithm configuration file.

[0115] Preferably, the performance analysis device for source address verification provided by the present invention is specifically used in the data definition statement to declare variable identifiers and associated operand lengths; The operation statements are used to invoke the algorithm in the algorithm configuration file to operate on the declared variables; The performance model includes at least a time consumption function, which is used to calculate the time consumption of the operation statement based on the operand length of each operation statement. Each algorithm is configured with at least one time consumption function.

[0116] Preferably, the performance analysis device for source address verification provided by the present invention is specifically used to check whether the algorithm to be called for each operation statement exists in the algorithm configuration file; Check whether the number of operands provided by the operation statement is consistent with the number of operands required for the algorithm configured in the algorithm configuration file; Check whether each operand in the operation statement has been recorded in the symbol table.

[0117] Preferably, the performance analysis device for source address verification provided by the present invention is specifically used to calculate the assignment result length of the assignment result based on the operand length in the operation statement and the output length function of the corresponding algorithm when the operation statement indicates an assignment result; Update the symbol table with the variable identifier of the assignment result and the corresponding length of the assignment result.

[0118] Preferably, the performance analysis device for source address verification provided by the present invention is specifically used to obtain the operand length of the operand from the symbol table according to the operation statement, and to obtain the time consumption function of the algorithm corresponding to the operand from the algorithm configuration file; The operand length is substituted into the time consumption function to calculate the time consumption of the operation statement.

[0119] Preferably, the performance analysis device for source address verification provided by the present invention is specifically used to, when the operand length in the symbol table is a symbol variable, substitute the symbol variable into the time-consuming function to generate the performance overhead of the operation statement; wherein, the performance overhead is an expression containing the symbol variable.

[0120] Figure 3 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 3As shown, the electronic device may include: a processor 310, a communications interface 320, a memory 330, and a communication bus 340, wherein the processor 310, the communications interface 320, and the memory 330 communicate with each other via the communication bus 340. The processor 310 can call logical instructions in the memory 330 to execute a performance analysis method for source address verification. This method includes: receiving a source address verification handler written in a description language; wherein the source address verification handler includes at least multiple operation statements; loading an algorithm configuration file; wherein the algorithm configuration file includes at least a performance model configured for multiple preset algorithms, the performance model being used to calculate the execution time of each operation statement based on the operand length of each operation statement; calculating the execution time of each operation statement based on the source address verification handler and the performance model; and generating a performance analysis report for the source address verification handler based on the execution time of all operation statements in the source address verification handler.

[0121] Furthermore, the logical instructions in the aforementioned memory 330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the performance analysis method for source address verification provided by the above methods. The method includes: receiving a source address verification processing program written in a description language; wherein the source address verification processing program includes at least a plurality of operation statements; loading an algorithm configuration file; wherein the algorithm configuration file includes at least a performance model configured for a plurality of preset algorithms, the performance model being used to calculate the time consumption of the operation statement based on the operand length of each operation statement; calculating the time consumption of each operation statement based on the source address verification processing program and the performance model; and generating a performance analysis report of the source address verification processing program based on the time consumption of all operation statements in the source address verification processing program.

[0123] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the performance analysis method for source address verification provided by the methods described above. The method includes: receiving a source address verification processing program written in a description language; wherein the source address verification processing program includes at least a plurality of operation statements; loading an algorithm configuration file; wherein the algorithm configuration file includes at least a performance model configured for a plurality of preset algorithms, the performance model being used to calculate the time consumption of the operation statement based on the operand length of each operation statement; calculating the time consumption of each operation statement based on the source address verification processing program and the performance model; and generating a performance analysis report of the source address verification processing program based on the time consumption of all operation statements in the source address verification processing program.

[0124] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0125] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A performance analysis method for source address verification, characterized by, The method comprises: receiving a source address verification program written in a description language; wherein the source address verification program comprises at least a plurality of operation statements; loading an algorithm configuration file; wherein the algorithm configuration file comprises at least a performance model configured for a plurality of preset algorithms, and the performance model is used to calculate a time consumption length of each operation statement based on an operand length of each operation statement; calculating a time consumption length of each operation statement based on the source address verification program and the performance model; generating a performance analysis report of the source address verification program according to the time consumption lengths of all operation statements in the source address verification program.

2. The performance analysis method for source address verification according to claim 1, wherein, before the step of calculating a time consumption length of each operation statement based on the source address verification program and the performance model, the method comprises: parsing the source address verification program to obtain a data definition statement and an operation statement; constructing a symbol table according to the data definition statement; wherein the symbol table is used to record a variable identifier and an operand length corresponding to the variable identifier; obtaining a time consumption function of an algorithm corresponding to an operand from the algorithm configuration file according to the operation statement and the symbol table. The method comprises:

3. The performance analysis method for source address verification according to claim 2, wherein, the data definition statement is used to declare a variable identifier and an associated operand length; the operation statement is used to call an algorithm in the algorithm configuration file to operate on the declared variable; the performance model comprises at least a time consumption function, and the time consumption function is used to calculate a time consumption length of each operation statement based on an operand length of each operation statement, and each algorithm configuration comprises at least one time consumption function.

4. The performance analysis method for source address verification according to claim 2, wherein, before the step of obtaining a time consumption function of an algorithm corresponding to an operand from the algorithm configuration file according to the operation statement and the symbol table, the method comprises: checking whether an algorithm to be called by each operation statement exists in the algorithm configuration file; checking whether a number of operands provided by the operation statement is consistent with a number of required operands configured for the algorithm in the algorithm configuration file; checking whether each operand in the operation statement has been recorded in the symbol table. The performance model comprises at least an output length function; after the step of parsing the source address verification program to obtain a data definition statement and an operation statement, the method comprises:

5. The performance analysis method for source address verification according to claim 2, wherein, in a case where the operation statement indicates an assignment result, calculating an assignment result length of the assignment result according to an operand length in the operation statement and an output length function of the corresponding algorithm; updating a variable identifier of the assignment result and the corresponding assignment result length to the symbol table.

6. The performance analysis method for source address verification according to claim 5, wherein, the step of calculating a time consumption length of each operation statement based on the source address verification program and the performance model comprises: ​ ​ ​ According to the operation statement, an operation number length of the operation number is obtained from the symbol table, and the time-consuming function of the algorithm corresponding to the operation number is obtained from the algorithm configuration file; The operation number length of the operation number is substituted into the time-consuming function for calculation to obtain a time-consuming duration of the operation statement.

7. The performance analysis method for source address verification according to claim 6, wherein, The operation number length of the operation number is substituted into the time-consuming function for calculation to obtain a time-consuming duration of the operation statement, comprising: In the case that the operation number length in the symbol table is a symbol variable, the symbol variable is substituted into the time-consuming function to generate a performance overhead of the operation statement; wherein the performance overhead is an expression containing the symbol variable.

8. A performance analysis apparatus for source address verification, characterized by, Comprising: A receiving module configured to receive a source address verification processing program written in a description language; wherein the source address verification processing program comprises at least a plurality of operation statements; A loading module configured to load an algorithm configuration file; wherein the algorithm configuration file comprises at least a performance model configured for a plurality of preset algorithms, and the performance model is used to calculate a time-consuming duration of each operation statement based on an operation number length of the operation statement; A calculating module configured to calculate a time-consuming duration of each operation statement based on the source address verification processing program and the performance model; A generating module configured to generate a performance analysis report of the source address verification processing program according to the time-consuming duration of all operation statements in the source address verification processing program.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The processor implements the performance analysis method for source address verification according to any one of claims 1 to 7 when executing the program. 10.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the performance analysis method for source address verification according to any one of claims 1 to 7 when executed by the processor.

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