Bus error frame identification method and device and readable storage medium

Abstract

The invention discloses a bus error frame identification method and device and a readable storage medium. The method comprises the following steps: acquiring a differential voltage signal and a corresponding current signal of a CAN bus node; performing continuous dominant bit signal extraction on the differential voltage signal based on a dynamic analysis window to obtain an abnormal frame differential voltage signal and a corresponding abnormal frame current signal; determining a voltage change sequence according to the abnormal frame differential voltage signal, and determining a current direction mark according to the abnormal frame current signal; and determining node driving characteristics according to the voltage change sequence, determining a node driving state according to the current direction mark, and determining an error frame identification result according to the node driving characteristics and the node driving state. Through cross validation of the node driving characteristics determined by the voltage change sequence and the node driving state determined by the current direction mark, node-level bus error frame positioning can be realized, and the bus error diagnosis precision is improved.

Description

Technical Field

[0001] This application relates to the field of automotive network technology, specifically to a bus error frame identification method, apparatus, and readable storage medium. Background Technology

[0002] As one of the most widely used communication protocols in automotive electronics, industrial control, and the Internet of Things (IoT), the reliability of CAN bus communication directly affects system security and operational stability. With the increasing electrification of vehicles and the growing complexity of industrial automation systems, the scale of CAN bus networks is expanding, leading to a significant increase in the frequency of errors. Accurate and efficient error diagnosis technology has become a core requirement for ensuring real-time system operation and reducing maintenance costs. Especially in scenarios with extremely high requirements for communication reliability, such as autonomous driving and intelligent connected vehicles, rapid and accurate diagnosis of bus errors has become a key bottleneck in the industry's technological development.

[0003] Currently, CAN bus error diagnosis mainly relies on two technical approaches: The first is error counter-based diagnostics, which diagnoses faults by monitoring the transmit and receive error counters of CAN nodes. When a node detects a bus error, its internal error counter automatically increments; when the count exceeds a preset threshold (typically 127 / 255), the node enters a Bus-Off state. Diagnostic tools read the error counter values ​​of each node and identify the node with the highest count as a suspected fault source. The second approach is logic analyzer-based decoding diagnosis. This involves capturing the bus waveform using a logic analyzer or a professional decoding oscilloscope and identifying the location of error frames using protocol decoding software. The decoded message sequence is then manually analyzed, combined with the context in which the error frame occurred, to determine the possible faulty node.

[0004] However, existing bus error diagnosis methods, particularly those based on error counters, can only identify nodes entering the Bus-Off state and cannot pinpoint the specific error source. Furthermore, misinterpretations of legitimate messages by receiving nodes also increase the counter. Decoding-based diagnosis using logic analyzers relies on professional analysis of the decoding results and cannot identify overlapping errors caused by multiple nodes simultaneously. Therefore, existing diagnostic methods have low accuracy and struggle to achieve precise node-level location. Summary of the Invention

[0005] This application provides a bus error frame identification method, apparatus, and readable storage medium, which can solve the problems of low diagnostic accuracy and difficulty in achieving precise node-level positioning technology in the prior art.

[0006] In a first aspect, embodiments of this application provide a bus error frame identification method, including: Obtain the differential voltage signal and corresponding current signal of the CAN bus node; Based on the dynamic analysis window, continuous dominant bit signals are extracted from the differential voltage signal to obtain the abnormal frame differential voltage signal and the corresponding abnormal frame current signal. The voltage change sequence is determined based on the differential voltage signal of the abnormal frame, and the current direction marker is determined based on the current signal of the abnormal frame. The node driving characteristics are determined based on the voltage change sequence, the node driving state is determined based on the current direction mark, and the error frame identification result is determined based on the node driving characteristics and the node driving state.

[0007] In conjunction with the first aspect, in one implementation, determining a voltage change sequence based on anomaly frame differential voltage signals includes: The differential voltage change of adjacent abnormal frames is calculated sequentially to obtain the voltage change sequence.

[0008] In conjunction with the first aspect, in one implementation, determining a current direction marker based on an abnormal frame current signal includes: The current polarity is statistically analyzed on the abnormal frame current signal to obtain the current direction mark.

[0009] In conjunction with the first aspect, in one implementation, determining node driving characteristics based on a voltage change sequence includes: Node driving characteristics are determined based on voltage change sequences and voltage change thresholds; The voltage change threshold is determined based on the difference in drive voltage between the CAN bus node and its neighboring nodes.

[0010] In conjunction with the first aspect, in one implementation, acquiring the differential voltage signal and the corresponding current signal of the CAN bus node includes: Acquire the raw differential voltage signal and bus current signal of the CAN bus node; The amplitude of the original differential voltage signal is normalized to obtain the differential voltage signal. The differential voltage signal and the bus current signal are aligned on the time axis to obtain the current signal corresponding to the differential voltage signal.

[0011] In conjunction with the first aspect, in one implementation, time-axis alignment of the differential voltage signal and the bus current signal is performed to obtain the current signal corresponding to the differential voltage signal, including: The signal acquisition delay is determined based on the dominant transition edge of the differential voltage signal. Based on the signal acquisition delay, the bus current signal is compensated for the delay and aligned with the time axis to obtain the current signal corresponding to the differential voltage signal.

[0012] In conjunction with the first aspect, in one implementation, the window size of the dynamic analysis window is within the range of a baseline window size and a maximum window size; The reference window size is determined based on the bus protocol type.

[0013] In conjunction with the first aspect, in one implementation, the bus error frame identification method further includes: The location of the error frame and the actual pulse width are determined based on the error frame identification results; The error type is determined based on the location of the error frame and the actual pulse width.

[0014] Secondly, embodiments of this application provide a bus error frame identification device, comprising: The signal acquisition unit is used to acquire the differential voltage signal and the corresponding current signal of the CAN bus node; An abnormal frame identification unit is used to extract continuous dominant bit signals from the differential voltage signal based on a dynamic analysis window, so as to obtain the abnormal frame differential voltage signal and the corresponding abnormal frame current signal. The feature extraction unit is used to determine the voltage change sequence based on the differential voltage signal of the abnormal frame and to determine the current direction marker based on the current signal of the abnormal frame. The error frame identification unit is used to determine the node driving characteristics based on the voltage change sequence, determine the node driving state based on the current direction mark, and determine the error frame identification result based on the node driving characteristics and the node driving state.

[0015] Thirdly, embodiments of this application provide a computer-readable storage medium storing a bus error frame identification program, wherein when the bus error frame identification program is executed by a processor, it implements the steps of the bus error frame identification method as described above.

[0016] The beneficial effects of the technical solutions provided in this application include: By determining the node driving characteristics through voltage change sequences, the voltage step difference information in the voltage change sequences can be used to identify whether the node participates in driving. By determining the node driving state through current direction marking, it is possible to verify whether the node is in an active or passive state. Through cross-verification of node driving characteristics and node driving state, node-level bus error frame localization can be achieved, improving the accuracy of bus error diagnosis. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating an embodiment of the bus error frame identification method of this application; Figure 2 This is a schematic diagram of the data acquisition process in an embodiment of this application; Figure 3 This is a detailed flowchart illustrating step S203 of this application; Figure 4 This is a logic diagram for determining node errors in an embodiment of this application; Figure 5This is a schematic diagram of the functional modules of an embodiment of the bus error frame identification device of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0020] In a first aspect, embodiments of this application provide a method for identifying bus error frames.

[0021] In one embodiment, reference is made to Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the bus error frame identification method of this application. Figure 1 As shown, the bus error frame identification method includes: S101. Obtain the differential voltage signal and corresponding current signal of the CAN bus node; S102. Based on the dynamic analysis window, the differential voltage signal is continuously extracted to obtain the abnormal frame differential voltage signal and the corresponding abnormal frame current signal. S103. Determine the voltage change sequence based on the abnormal frame differential voltage signal, and determine the current direction mark based on the abnormal frame current signal; S104. Determine the node driving characteristics based on the voltage change sequence, determine the node driving state based on the current direction mark, and determine the error frame identification result based on the node driving characteristics and the node driving state.

[0022] Specifically, the embodiment first acquires the differential voltage signal and current signal of the CAN bus node, performs timing alignment on the differential voltage signal and current signal, and performs amplitude standardization processing on the differential voltage signal to ensure the consistency of feature extraction.

[0023] Then, based on the principle of six consecutive dominant bits in an error frame, a dynamic analysis window is set up to detect consecutive dominant bits in real time. The dynamic analysis window initializes a reference window according to the bus protocol type, and the length of the reference window corresponds to the length of six consecutive dominant bits under the current bus protocol. Simultaneously, the analysis window can dynamically expand within a calibrated upper limit to ensure complete capture of the error frame content. Then, the differential voltage signal with consecutive dominant bits extracted by the dynamic analysis window is used as the differential voltage signal of the abnormal frame, and combined with the corresponding current signal for further judgment.

[0024] Then, for voltage signals, due to differences in the driver chip and node hardware and software design, each node has a different driving capability. When two nodes with different driving capabilities drive simultaneously, an observable voltage step difference will occur. Therefore, this embodiment calculates the differential voltage change of adjacent dominant bits to generate a voltage change sequence, and combines this with a set voltage change threshold to identify whether a node participates in driving.

[0025] For current signals, the implementation example verifies whether a node is in an active or passive state by detecting the polarity of the node current. When current is measured to flow out of the node (positive current), it indicates that the node is actively driving the bus. When current flows into the node (negative current), it indicates that the node is in a passive receiving state, and the bus driving is dominated by other nodes.

[0026] The final embodiment uses the node driving characteristics identified by the voltage signal and the current direction mark identified by the current signal to perform cross-validation to determine the error frame identification result, thus completing the node-level CAN bus error frame identification.

[0027] In this embodiment, node driving characteristics are determined by voltage change sequence. The voltage step difference information in the voltage change sequence can be used to identify whether a node participates in driving. The node driving state is determined by current direction marking, which can verify whether the node is in an active or passive state. By cross-verifying the node driving characteristics and the node driving state, node-level bus error frame localization can be achieved, improving the accuracy of bus error diagnosis.

[0028] Furthermore, in one embodiment, Figure 2 This is a schematic diagram of the data acquisition process in an embodiment of this application, as shown below. Figure 2 As shown, the differential voltage signal and corresponding current signal of the CAN bus node are obtained, including: S201. Acquire the raw differential voltage signal and bus current signal of the CAN bus node; S202. Normalize the amplitude of the original differential voltage signal to obtain the differential voltage signal; S203. Align the differential voltage signal and the bus current signal on the time axis to obtain the current signal corresponding to the differential voltage signal.

[0029] Furthermore, in one embodiment, Figure 3 This is a detailed flowchart of step S203 of this application, as shown below. Figure 3 As shown, the differential voltage signal and the bus current signal are time-axis aligned to obtain the current signal corresponding to the differential voltage signal, including: S301. The signal acquisition delay is determined based on the dominant transition edge of the differential voltage signal. S302. Based on the signal acquisition delay, the bus current signal is compensated for the delay and the time axis is aligned to obtain the current signal corresponding to the differential voltage signal.

[0030] Specifically, during the signal synchronization acquisition process, this embodiment uses a high-precision differential probe to synchronously capture the CAN_H and CAN_L signals of the CAN bus, while simultaneously using a current probe to measure the bus drive current of the node under test. The three signals are synchronized via hardware triggering to ensure timing consistency.

[0031] For CAN_H and CAN_L signals, the differential voltage can be obtained by calculating the difference. The acquisition system collects and records the continuous waveform of the differential voltage changing over time to obtain the original differential voltage signal. For the bus drive current, the polarity (inflow / outflow) and timing of the node drive current are collected and recorded as the bus current signal.

[0032] In addition to acquiring differential voltage signals and bus current signals during signal synchronous acquisition, the embodiment can optionally also acquire logic measurement TX / RX signals for auxiliary verification. The logic measurement TX / RX signals can be obtained by measuring the numerical pin signals between the CAN node controller and the CAN transceiver chip using a logic analyzer or oscilloscope.

[0033] To further align the time axis, the embodiment uses the dominant transition edge of the differential voltage as a reference point to calculate the inherent delay between each channel. Based on the calculated inherent delay, digital delay compensation is applied to the current and logic signals to eliminate timing deviations between the probe and the acquisition channels. The processed data ensures that the voltage transition and current change are synchronized, establishing an accurate time reference for subsequent pulse width measurements and achieving time synchronization of the voltage, current, and logic signals.

[0034] Furthermore, considering data acquisition errors, voltage amplitude normalization is also required. The example calculates the gain compensation coefficient for each acquisition device by measuring the differential voltage reference value under standard dominant conditions. Then, amplitude normalization is performed on all voltage sampling points based on the gain compensation coefficient to eliminate sensitivity differences between different probes and acquisition devices. The normalized voltage data can be directly compared with waveform characteristics under different test environments, ensuring consistency in feature extraction.

[0035] In this embodiment, by corresponding the time axis, an accurate time reference can be established for subsequent steps, and by normalizing the voltage amplitude, data acquisition errors can be eliminated, ensuring the consistency of feature extraction.

[0036] Furthermore, in one embodiment, the window size of the dynamic analysis window is within the range of a baseline window size and a maximum window size; The reference window size is determined based on the bus protocol type.

[0037] Specifically, in signal analysis, the implementation example initializes the analysis window based on the bus protocol type, that is, based on the principle of 6 dominant bits of the error frame, the network reference window is set.

[0038] For example, for a traditional CAN network, setting The baseline window corresponds to 6 consecutive dominant bits at 500kbps.

[0039] For CANFD networks, the reference window at the arbitration end is the same as that of traditional CAN. In the data segment, the length of the 6 dominant bits is set according to the actual baud rate of the CANFD data field. For example, for a baud rate of 2 Mbps, it is set to... .

[0040] Then, the number of dominant bits is detected in real time using an analysis window, and the window size is dynamically expanded to fully capture the error frame content. Window expansion takes into account the overlapping of several nodes or bit padding. An upper limit is set for the window size, for example, the maximum length cannot exceed... (Can be calibrated) to avoid capturing excessively long content.

[0041] The number of consecutive dominant sites detected can be expressed as , and the dynamic analysis window can be expressed as: For traditional CAN: T_win = max(12μs, N×2μs); For the CANFD data segment: T_win = max(3μs, N×0.5μs).

[0042] That is, the window size is greater than or equal to the baseline window size.

[0043] In this embodiment, setting the network reference window according to the bus protocol type can ensure that the reference window can adapt to the data format of the differential voltage signal, and the integrity of the captured error frames can be guaranteed by the dynamically adjustable window size.

[0044] Further, in one embodiment, determining the voltage change sequence based on the abnormal frame differential voltage signal includes: The differential voltage change of adjacent abnormal frames is calculated sequentially to obtain the voltage change sequence.

[0045] Further, in one embodiment, determining the current direction marker based on the abnormal frame current signal includes: The current polarity is statistically analyzed on the abnormal frame current signal to obtain the current direction mark.

[0046] Specifically, during the feature parameter extraction process, the embodiment extracts and generates three types of features from the processed waveform data: voltage change sequence, current direction identifier, and pulse width mode.

[0047] The voltage change sequence is generated by calculating the differential voltage change between adjacent dominant sites. Timing curve. In the specific calculation steps, for the normalized differential voltage waveform, the voltage difference between adjacent dominant potentials can be calculated using the following formula:

[0048] in, Indicates the first Individual time.

[0049] The generated result is calculated using the above formula. The sequence can reflect changes in the driving node.

[0050] Pulse width mode (PWM) detects standard error flag patterns and abnormal pulse widths by identifying the duration characteristics of consecutive dominant bits identified through a continuous dynamic analysis window. Based on the principle that an error frame lasts for six dominant bits, the standard error flag pattern consists of six consecutive dominant bits, as shown in the example for CAN. A 2Mbps baud rate CANFD data segment corresponds to An abnormal pulse width is defined as a number of consecutive dominant bits exceeding the standard error mode.

[0051] The current direction indicator is generated by statistically analyzing the current polarity (positive direction for outflow and negative direction for inflow) during the error period and generating a direction marker sequence.

[0052] The extracted features are then packaged into a standard data result, including time-aligned voltage change sequences, pulse width feature vectors, and current direction markers. The feature dataset preserves the temporal correlation of the original waveforms, providing complete physical layer feature information for subsequent fault diagnosis.

[0053] In this embodiment, preserving the temporal correlation of the original waveform during data processing can provide complete and accurate physical layer feature information for fault diagnosis.

[0054] Further, in one embodiment, determining node driving characteristics based on a voltage change sequence includes: Node driving characteristics are determined based on voltage change sequences and voltage change thresholds; The voltage change threshold is determined based on the difference in drive voltage between the CAN bus node and its neighboring nodes.

[0055] Specifically, the embodiment extracts node driving features through voltage change sequences, determines node driving states through current direction markings, and achieves node-level bus error frame localization through cross-verification of node driving features and node driving states, thereby improving the accuracy of bus error diagnosis.

[0056] For the specific diagnostic process described in the examples, please refer to [link / reference]. Figure 4 , Figure 4 This is a logic diagram for node error judgment in an embodiment of this application, such as... Figure 4 As shown in the example, based on voltage amplitude analysis and current direction analysis, it can determine whether there is an active driving error or a passive reception error at this node. The specific process is as follows: In voltage amplitude analysis, the amplitude jumps of the differential voltage between consecutive dominant potentials are considered voltage steps, reflecting the differences in driving capability between different nodes. A sliding window detection method is used to identify voltage difference abrupt changes and calculate the voltage difference between adjacent dominant potentials. A dynamic threshold is used to determine significant changes. The threshold value can be adjusted based on the network size to ensure that effective differences are captured while avoiding noise interference. When the set threshold is exceeded, it can be determined that different nodes are switching (at this time, the current node may be in control of the drive, or it may be another node, which needs to be combined with the current direction below).

[0057] During the threshold determination process, due to differences in the driver chip and node hardware and software design, the driving capability of each node will vary. When two nodes with different driving capabilities are driven simultaneously, an observable voltage step difference will occur. Therefore, the threshold is taken as a safety factor percentage of the voltage difference between the two closest nodes in the network when driven individually, such as 60%, or adaptively adjusted.

[0058] Example: If node A drives 2.1V and node B drives 1.9V, then the threshold can be set at 60% of the voltage difference, i.e., 0.12V.

[0059] In current direction analysis, the bus driving relationship is verified by detecting the polarity of the node current, providing crucial status information for fault diagnosis. When current is measured flowing out of a node (positive current), it indicates that the node is actively driving the bus; while when current flows into a node (negative current), it indicates that the node is in a passive receiving state, in which case the bus driving is dominated by other nodes. That is: positive current marks active driving, and negative current marks passive receiving.

[0060] The implementation then combines voltage and current characteristics for cross-validation. When a significant voltage change exceeds a threshold while the current direction is negative, it indicates potential bus contention or multi-node conflict; conversely, if a voltage change is accompanied by a positive current, the active driving behavior of the node is confirmed. This bidirectional validation mechanism significantly improves the reliability of node state judgment, especially in identifying hidden faults in complex network environments. The implementation uses this to set feature association rules: the node driving state is obtained by adding the voltage ΔV sequence to the current direction. Then, a current-voltage timing correlation model is established to accurately match the driving behavior. The matching method is shown in the table below. Table 1: Temporal Association Matching Table

[0061] The current direction I_dir is always measured relative to the current node being measured. When I_dir is positive, current flows out of the node being measured; when I_dir is negative, current flows into the node being measured.

[0062] Furthermore, it should be noted that the above method is only for single-node measurement, enabling node-level error identification for a single tested node. However, in some other embodiments, data can be collected from multiple nodes and this method can be used for identification. Moreover, during the identification of multiple tested nodes, the identification results can be mutually verified. For example, if one node's identification result indicates a bus conflict, i.e., multi-node contention, then the reliability of identifying another node as having an active error is higher. Or, if the identification results of two nodes contradict each other, it is necessary to check and verify whether there is a threshold setting problem or a data acquisition device malfunction.

[0063] In this embodiment, cross-verification of current and voltage can be used to locate bus error frames at the node level, thereby improving the accuracy of bus error diagnosis.

[0064] Furthermore, in one embodiment, the bus error frame identification method further includes: The location of the error frame and the actual pulse width are determined based on the error frame identification results; The error type is determined based on the location of the error frame and the actual pulse width.

[0065] Specifically, in addition to cross-validation of voltage and current, the features generated by the implementation also include pulse width features. Combined with the actual network protocol, further error type analysis can be performed based on the pulse width features. For example, for the CANFD protocol, baud rate switching bit (BRS) verification is additionally performed. By measuring the actual pulse width of the key bits in the control segment and comparing it with the theoretical value, sampling point mismatch problems can be diagnosed.

[0066] Error types include the following: Bit stuffing error: Violation of the "padding every five bits" rule, meaning there are more than 5 consecutive bits of the same polarity before the error frame. Pulse width characteristic analysis: Fixed at more than 5 bit times (for CAN, this means more than...). For example, in If it is found that there is no opposite polarity bit filled, then 6 consecutive dominant bits are output as an active error.

[0067] CRC checksum error: The receiving node calculates a CRC mismatch. Pulse width characteristic analysis: It also outputs 6 consecutive dominant bits as an active error flag. Differentiation method: Combined with determining the location of the error, it occurs in the CRC segment rather than the data segment.

[0068] CANFD sampling point error: Characterized by an abnormal BRS bit width. Error flag: 6 consecutive bits at high speeds (e.g., 2Mbps). Dominant bit. Differentiation method: Combined with determining the location of occurrence, if it occurs in the BRS bit, it can be determined as a CANFD sampling point error.

[0069] During diagnosis, by combining the current data protocol, error types can be further subdivided according to the different manifestations of various types of errors.

[0070] In this embodiment, by further subdividing and judging the error type, more valuable diagnostic information can be provided for bus error diagnosis and subsequent maintenance and debugging.

[0071] Secondly, embodiments of this application also provide a bus error frame identification device.

[0072] In one embodiment, reference is made to Figure 5 , Figure 5 This is a functional module diagram of an embodiment of the bus error frame identification device of this application. Figure 5 As shown, the bus error frame identification device includes: The signal acquisition unit 501 is used to acquire the differential voltage signal and the corresponding current signal of the CAN bus node; The abnormal frame identification unit 502 is used to extract the continuous dominant bit signal from the differential voltage signal based on the dynamic analysis window, so as to obtain the abnormal frame differential voltage signal and the corresponding abnormal frame current signal. Feature extraction unit 503 is used to determine the voltage change sequence based on the abnormal frame differential voltage signal and to determine the current direction mark based on the abnormal frame current signal; Error frame identification unit 504 is used to determine node driving characteristics based on voltage change sequence, determine node driving state based on current direction mark, and determine error frame identification result based on node driving characteristics and node driving state.

[0073] The functions of each module in the above-mentioned bus error frame identification device correspond to the steps in the above-mentioned bus error frame identification method embodiment, and their functions and implementation processes will not be described in detail here.

[0074] Thirdly, embodiments of this application also provide a computer-readable storage medium.

[0075] This application provides a computer-readable storage medium storing a bus error frame identification program, wherein when the bus error frame identification program is executed by a processor, it implements the following bus error frame identification method: Obtain the differential voltage signal and corresponding current signal of the CAN bus node; Based on the dynamic analysis window, continuous dominant bit signals are extracted from the differential voltage signal to obtain the abnormal frame differential voltage signal and the corresponding abnormal frame current signal. The voltage change sequence is determined based on the differential voltage signal of the abnormal frame, and the current direction marker is determined based on the current signal of the abnormal frame. The node driving characteristics are determined based on the voltage change sequence, the node driving state is determined based on the current direction mark, and the error frame identification result is determined based on the node driving characteristics and the node driving state.

[0076] The method implemented when the bus error frame identification program is executed can be referred to in various embodiments of the bus error frame identification method of this application, and will not be repeated here.

[0077] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0078] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0079] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0080] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0081] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0082] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods of the various embodiments of this application.

[0083] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for identifying a bus error frame, characterized by, The method comprises: acquiring a differential voltage signal and a corresponding current signal of a CAN bus node; performing continuous dominant bit signal extraction on the differential voltage signal based on a dynamic analysis window to obtain an abnormal frame differential voltage signal and a corresponding abnormal frame current signal; determining a voltage change sequence according to the abnormal frame differential voltage signal and determining a current direction marker according to the abnormal frame current signal; determining a node driving feature according to the voltage change sequence, determining a node driving state according to the current direction marker, and determining an error frame identification result according to the node driving feature and the node driving state.

2. The bus error frame identification method of claim 1, wherein, The method further comprises: determining an error frame position and an actual pulse width according to the error frame identification result; and determining an error type according to the error frame position and the actual pulse width.

3. The bus error frame identification method of claim 1, wherein, The method comprises: a signal acquisition unit configured to acquire a differential voltage signal and a corresponding current signal of a CAN bus node; 4. The bus error frame identification method of claim 1, wherein, an abnormal frame identification unit configured to perform continuous dominant bit signal extraction on the differential voltage signal based on a dynamic analysis window to obtain an abnormal frame differential voltage signal and a corresponding abnormal frame current signal; a feature extraction unit configured to determine a voltage change sequence according to the abnormal frame differential voltage signal and determine a current direction marker according to the abnormal frame current signal; an error frame identification unit configured to determine a node driving feature according to the voltage change sequence, determine a node driving state according to the current direction marker, and determine an error frame identification result according to the node driving feature and the node driving state.

5. The bus error frame identification method of claim 1, wherein, ​ ​ ​ ​ 6. The bus error frame identification method of claim 5, wherein, ​ ​ ​ 7. The bus error frame identification method of claim 1, wherein, ​ ​ 8. The bus error frame identification method of claim 1, wherein, ​ ​ ​ 9. A bus error frame identification apparatus characterized by comprising: ​ ​ ​ ​ ​ 10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a bus error frame identification program, and when the bus error frame identification program is executed by the processor, the steps of the bus error frame identification method according to any one of claims 1 to 8 are implemented.

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