High-speed low-power-consumption two-step echo cancellation circuit based on shared delay chain

Abstract

The invention discloses a high-speed low-power-consumption two-step echo cancellation circuit based on a shared delay chain, and belongs to the technical field of high-speed serial interfaces. The circuit comprises a central shared coarse tuning delay chain, a plurality of tap modules sharing the delay chain, a weighting unit and a summing unit, the tap module comprises a fine adjustment delay stage, and multiplexes a transmitter side multiphase clock signal to perform phase fine adjustment; the weighting unit weighs the delay signal replica, and the summing unit subtracts the delay signal replica from the received signal after superposition so as to eliminate the echo. The receiver system adopts a separated subtraction architecture, near-end echoes are eliminated in front of the input end of a continuous time linear equalizer, far-end echoes are eliminated behind the output end of the continuous time linear equalizer, and a digital control logic module is additionally arranged to realize closed-loop adaptive control. Through resource sharing and architecture optimization, the power consumption and the chip area are greatly reduced, wide-range and high-precision echo cancellation is realized, and the method is suitable for a data communication system with 112Gb / s and higher rate.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-speed serial interface (SerDes), and particularly relates to a high-speed low-power two-step echo cancellation circuit based on a shared delay chain. BACKGROUND

[0002] In high-speed data links such as short-reach backplane (SBD) and direct-attach-cable, impedance discontinuities (such as connectors, vias, package transitions, etc.) existing on the signal path will cause signal reflection, resulting in echoes mixed with the main signal. These echoes will seriously deteriorate the integrity of the received signal, increase the bit error rate (BER), and are one of the key bottlenecks limiting the rate and performance improvement of the link.

[0003] In order to solve the echo problem, the industry usually adopts echo cancellation (EC) technology. However, the traditional echo canceller scheme has significant limitations. For example, some echo cancellers that use mixed-signal delay modules have a power consumption as high as 0.38pJ / b; while digital solutions based on ADCs (analog-to-digital converters) have higher precision, but their power consumption and circuit complexity also increase accordingly, and the power consumption may even reach 2pJ / b. In the context of continuously rising data rates to 112Gb / s or even higher, such high power consumption has become an unacceptable burden.

[0004] In addition, linear equalization circuits commonly used in receivers, such as feed-forward equalizers (FFE) and continuous-time linear equalizers (CTLE), have high-pass filtering characteristics as their design goal is to compensate for high-frequency losses in the channel. This characteristic not only cannot eliminate echoes caused by reflections, but may also amplify echo signals, further deteriorating signal quality. At the same time, the differences in characteristics of near-end echoes (NE) and far-end echoes (FE) (near-end echoes have small delays and large amplitudes; far-end echoes have large delays and small amplitudes and are more dispersed) and their complexity in changing with package solutions and channel lengths all pose higher requirements on echo cancellation technology.

[0005] Therefore, there is an urgent need for an echo cancellation scheme that can effectively eliminate echoes at ultra-high rates while having low power consumption, low complexity, and high integration, to meet the stringent requirements of the next generation of data communication systems. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a high-speed low-power two-step echo cancellation circuit based on a shared delay chain to solve the technical problem of high power consumption, complex circuit, and difficulty in integration of the echo canceller in the prior art at high rates.

[0007] The application adopts the following technical solutions: A high-speed low-power two-step echo cancellation circuit based on a shared delay chain, comprising: A central shared coarse delay chain composed of a plurality of cascaded delay units, used to provide common delay resources for a plurality of echo cancellation taps; A plurality of taps, each including a fine delay stage, the fine delay stage being connected to an output node of the coarse delay chain, used to make fine phase adjustments on the basis of the delay provided by the coarse delay chain, wherein the fine delay stage multiplexes a multi-phase clock signal on the transmitter side for phase selection; A weighting unit connected to the output of each tap, used to weight the delay signal copies output by each tap; A summing unit connected to the weighting unit, used to superimpose the weighted signal copies to generate an analog echo signal and subtract it from the input signal of the receiver.

[0008] Preferably, the delay units in the coarse delay chain are D flip-flops, which are driven by a low-frequency reference clock.

[0009] Preferably, the coarse delay chain includes 31 cascaded D flip-flops, providing programmable delay with a step of 4UI and a total coverage of 128UI.

[0010] Preferably, the fine delay stage includes a multiplexer that selects signals from the outputs of the selected node and its adjacent nodes of the coarse delay chain to achieve phase adjustment.

[0011] Preferably, the multiplexer is a 4:1 multiplexer, and the input signals are taken from the outputs of the selected node and adjacent D flip-flops with a time step of 1UI.

[0012] Preferably, the taps are 4, including 1 near-end echo tap and 3 far-end echo taps.

[0013] Preferably, the weighting coefficients of the weighting unit are trained and converged by an adaptive algorithm.

[0014] Another technical solution of the application is a high-speed receiver front-end system integrated with an echo cancellation function, comprising: The high-speed low-power two-step echo cancellation circuit based on a shared delay chain; A continuous-time linear equalizer; A first subtractor arranged before the input end of the continuous-time linear equalizer, used to subtract the analog echo signal generated by the near-end tap in the echo cancellation circuit from the received signal; A second subtractor, located after the output of the continuous-time linear equalizer, is used to subtract the analog echo signal generated by the far-end tap of the echo cancellation circuit from the signal output by the continuous-time linear equalizer.

[0015] Preferably, it further includes a digital control logic module, which receives the post-decision data and error signal output by the data decision unit, and performs adaptive control on all tap modules of the echo cancellation circuit based on the post-decision data and error signal.

[0016] Preferably, the control signals output by the digital control logic module include: The coarse adjustment selection signal for the central shared coarse adjustment delay chain, the fine adjustment selection signal for the fine adjustment delay stage within each tap module, and the coefficient adjustment signal for the corresponding weighting unit of each tap module.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects: A high-speed, low-power two-step echo cancellation circuit based on a shared delay chain is disclosed. The central shared coarse-tuning delay chain provides common delay resources for all taps, avoiding redundant deployment of delay units and significantly reducing hardware resource consumption. The fine-tuning delay stage multiplexes existing multi-phase clock signals from the transmitter side, eliminating the need for additional high-power delay-locked loops (DLLs) or phase interpolators, thus simplifying the circuit structure. The cooperation between the weighting unit and the summing unit enables unified processing of multiple echo components, ensuring the integrity of echo cancellation while improving system scalability through modular design. This invention achieves low power consumption, low complexity, and high integration while retaining the core echo cancellation function, fully adapting to the stringent hardware resource requirements of 112Gb / s and higher data communication scenarios.

[0018] Furthermore, as a small-size, low-power unit in the standard library, the D-type flip-flop reduces power consumption by more than 50% compared to the high-speed, high-drive-capability delay units in traditional solutions, while maintaining the same delay performance. The low-frequency reference clock further reduces dynamic power consumption, avoiding the additional power loss caused by high-frequency clocks. Simultaneously, the cascaded structure of the D-type flip-flop offers high stability and controllable timing characteristics, maintaining delay accuracy over a wide temperature and voltage range. Combined with a shared architecture, this ensures consistency of multi-tap delay resources and reduces placement and routing complexity, laying a stable foundation for high-precision phase adjustment in subsequent fine-tuning stages, achieving a balance between low power consumption and high reliability.

[0019] Furthermore, the cascaded design of 31 DFFs, after precise calculations, satisfies the wide-range delay coverage of 128UI, enabling the capture of long-distance propagation delays of far-end echoes, while avoiding resource waste caused by redundant units. The 4UI time step strikes a balance between wide coverage and initial accuracy, avoiding excessive pursuit of fine steps that would increase hardware complexity, while providing a suitable adjustment base for the fine-tuning stage. This design allows the coarse-tuning delay chain to adapt to echo delay differences under different channel lengths and encapsulation schemes. Combined with the 1UI step accuracy of the fine-tuning stage, it forms a wide-range + high-precision delay adjustment capability, providing core support for the comprehensive elimination of multiple types of echoes at ultra-high speeds.

[0020] Furthermore, the multiplexer has a simple structure and fast response speed. Compared with complex phase adjustment modules, it has lower power consumption and less delay, making it suitable for high-speed signal processing requirements. The input signal is taken from the coarse adjustment point and the adjacent output, eliminating the need to generate an additional phase signal, reducing interference in the signal path and ensuring the accuracy of phase adjustment. This design enables the fine adjustment stage to perform precise fine-tuning within the delay range locked by the coarse adjustment, effectively compensating for the insufficient accuracy caused by the coarse adjustment step. It achieves a collaborative working mode of coarse adjustment setting the range and fine adjustment setting the accuracy, ensuring that the delay signal copy generated by each tap can accurately match the propagation delay of the corresponding echo, improving the targeting of echo cancellation.

[0021] Furthermore, the 1UI step accuracy meets the phase matching requirements of high speeds of 112Gb / s and above, accurately offsetting minute phase deviations in high-speed signals and ensuring thorough echo cancellation. The selection of a 4:1 MUX is well-suited to the coarse adjustment of the 4UI step. By selecting the coarse adjustment point and the outputs of the three adjacent nodes, the coarse adjustment range of the 4UI is precisely covered, achieving phase adjustment without dead zones. This design requires no additional signal source or complex control logic; high-precision fine-tuning can be achieved simply through MUX selection. This reduces circuit complexity and power consumption while improving adjustment efficiency, fully leveraging the advantages of the two-step delay architecture and ensuring accurate adaptation of the multi-tap system to echoes with different characteristics.

[0022] Furthermore, considering the differences in characteristics between near-end and far-end echoes, a single near-end tap is sufficient to meet the cancellation requirements of large-amplitude echoes, avoiding resource waste; three far-end taps can respectively match far-end echoes with different propagation paths, ensuring comprehensive coverage of dispersed echoes. This number and ratio of taps has been verified through actual channel testing, demonstrating its ability to handle common echo distributions in scenarios such as short-distance backplanes and direct cable connections, without causing hardware resource redundancy or increased power consumption due to excessive taps. This balances cancellation effectiveness with system cost, improving the practicality and versatility of the solution.

[0023] Furthermore, the amplitude and polarity of the echo dynamically change with factors such as channel length, encapsulation scheme, and temperature variations, making it difficult to maintain optimal cancellation performance with fixed coefficients. Adaptive algorithms can automatically adjust the weighting coefficients based on the real-time state of the received signal, ensuring that the delayed signal replica accurately replicates the amplitude and polarity characteristics of the actual echo. This design achieves dynamic optimization without manual intervention, improving system robustness and enabling the echo cancellation circuit to adapt to different application scenarios and environmental changes. It avoids a decrease in cancellation performance due to channel fluctuations, ensuring stable improvement in signal integrity at high speeds.

[0024] A high-speed receiver front-end system integrating echo cancellation functionality is disclosed. The high-pass filtering characteristic of the CTLE (Channel-to-Echo Array) amplifies near-end echoes. Subtracting the near-end echoes before their input prevents amplification and distortion, ensuring accurate cancellation of large near-end echoes. Far-end echoes, after channel filtering, have spectral characteristics that better match the CTLE-equalized main signal. Subtraction at the CTLE output further improves cancellation accuracy. This architecture achieves coordinated operation of echo cancellation and channel equalization, resolving the mutual interference problem in traditional solutions. This significantly improves overall signal recovery performance, enabling the receiver system to maintain excellent signal integrity at ultra-high speeds, meeting the stringent requirements of next-generation data communication systems. The differentiated processing strategy based on echo characteristics represents a deep system-level optimization, significantly improving the overall receiver's signal recovery capability and bit error rate performance, which is another outstanding inventive aspect of this invention.

[0025] Furthermore, the digital control logic module receives the decision data and error signal from the data decision unit, enabling real-time monitoring of the echo cancellation effect and thus providing closed-loop feedback control for all taps. Compared to open-loop systems, this design eliminates the need for manual parameter adjustments, automatically adapting to the reflection characteristics of different channels and improving system usability. Simultaneously, closed-loop control rapidly responds to channel changes, promptly correcting delay selection and weighting coefficients to ensure optimal echo cancellation performance. This avoids performance degradation due to environmental fluctuations or channel aging, providing a reliable guarantee for stable communication at ultra-high speeds.

[0026] Furthermore, the coarse adjustment selection signal, fine adjustment selection signal, and coefficient adjustment signal correspond to the core links of delay chain adjustment and weighted optimization, respectively, forming a comprehensive control dimension. By precisely controlling the delay range of the central shared coarse adjustment delay chain, the fine adjustment phase of each tap, and the weighting coefficients, fine-grained control of the entire echo cancellation process can be achieved, ensuring that each technical link can be dynamically optimized according to actual needs. This design fully leverages the advantages of closed-loop control, avoids control blind spots, further improves the system's adjustment accuracy and response speed, ensures coordinated optimization between the echo cancellation circuit and the receiver system, and adapts to dynamic communication scenarios with speeds of 112Gb / s and higher.

[0027] In summary, this invention achieves breakthroughs in power consumption, area, and performance for high-speed echo cancellation through innovative circuit architecture combining resource sharing and two-step delay. Furthermore, through innovative system architecture combining discrete subtraction and adaptive control, it achieves coordinated optimization and intelligent operation and maintenance with channel equalization. The entire solution combines the advantages of simplified structure, superior performance, and strong adaptability, providing key technical support for SerDes speeds of 112Gbps and above.

[0028] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the following description of the relative embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This invention provides a high-speed, low-power echo cancellation circuit for data generation. Figure 2 A high-speed 4:1 Mux circuit is provided as an example of the present invention; Figure 3 According to Figure 1 A timing diagram of the circuit shown; Figure 4 An adder circuit provided in an embodiment of the present invention; Figure 5 The simulation comparison chart shows the echo cancellation performance before and after using the circuit of this invention.

[0031] Figure 6 This invention provides a high-speed, low-power echo cancellation circuit data connection architecture for Embodiment 2 of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0036] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0037] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0038] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0039] This invention provides a high-speed, low-power two-step echo cancellation circuit based on a shared delay chain. By sharing the coarse-tuning delay resources and multiplexing the clock in the fine-tuning stage, it can significantly reduce the power consumption and chip area of ​​the multi-tap echo canceller while ensuring high-precision and wide-range cancellation of multiple echoes, and improve the design flexibility and scalability. It is suitable for data communication systems with speeds of 112Gb / s and higher.

[0040] Please see Figure 1 This invention discloses a high-speed, low-power two-step echo cancellation circuit based on a shared delay chain, comprising: a two-step delay chain architecture that divides the total echo delay path into coarse and fine adjustment stages; the two-step delay chain architecture includes a coarse adjustment delay stage and a fine adjustment delay stage; the coarse adjustment delay stage is used to provide a wide range of programmable delays (e.g., 128 UI) with a large time step (e.g., 4 UI), and is composed of multiple cascaded low-speed, small-size delay units (e.g., D-type flip-flops, DFF), thereby significantly reducing the power consumption and area of ​​this part while achieving a wide range of delay coverage; The fine-tuning delay stage is connected to the output node of the coarse-tuning delay stage and is used to perform phase fine-tuning with fine time steps (e.g., 1UI) based on the selected coarse-tuning delay. Its core is a multiplexer (e.g., 4:1MUX), which multiplexes the existing multiphase clock signals on the transmitter (TX) side for phase selection, avoiding the introduction of additional high-power fine delay-locked loop (DLL) or phase interpolator.

[0041] As a further improvement of the present invention, the echo cancellation circuit adopts a multi-tap architecture, such as a 4-tap echo cancellation scheme containing one near-end (NE) tap and three far-end (FE) taps; wherein each tap independently generates a delay-adjustable signal copy using the above-described two-step delay chain architecture.

[0042] As a further improvement of the present invention, the circuit further includes a weighted summation unit; the signal copies generated by the two-step delay chain of each tap are weighted by their respective corresponding coefficients (N1-N4) to simulate the amplitude and polarity of the actual echo; the weighted signal copies are superimposed in the summation unit and subtracted from the input signal of the receiver (RX), thereby achieving accurate elimination of multiple echo components in the original signal.

[0043] Example 1 The core innovation of this invention lies in a resource-sharing design: by constructing a centrally shared coarse-tuning delay chain, common delay resources are provided for multiple echo cancellation taps. This architecture decouples the echo delay generation process into two stages: a large-range, large-step coarse-tuning stage and a high-precision, small-step fine-tuning stage. The system integrates only a single common coarse-tuning delay chain consisting of 31 cascaded D-flip-flops (DFFs). This common coarse-tuning delay chain allows the DFFs in the chain to use small-size, low-power-consumption units from the standard library, offering a significant advantage in power consumption and layout area compared to the high-speed, large-drive delay units required in traditional solutions. The input signal passes sequentially through these DFFs, generating a series of delay signals with 4UI steps, achieving a total coverage of 128UI, sufficient to effectively capture long-delayed far-end echoes. The core idea of ​​this circuit is to decouple the echo delay generation process, dividing it into a large-range, large-step coarse-tuning stage and a small-range, high-precision fine-tuning stage. This innovative architecture aims to achieve extreme optimization of circuit power consumption and area while ensuring echo cancellation functionality. The coarse-tuning delay stage, serving as the foundation for wide-range delay coverage, consists of a shift register chain of 31 cascaded D-type flip-flops (DFFs). Input signals pass sequentially through these DFFs driven by a low-frequency reference clock (e.g., 7GHz), enabling the use of small-size, low-power cells from the standard library, offering significant advantages in power consumption and layout compared to traditional solutions. A 16-to-1 selector allows selection of output nodes spaced at specific UI intervals (e.g., 4 UIs) on the chain, achieving coarse locking of a total delay range of up to 128 UIs, crucial for compensating for long-delay far-end echoes.

[0044] Please see Figure 2 Following the coarse adjustment stage is the fine adjustment delay stage, which is responsible for precise phase fine-tuning near the delay point selected by the coarse adjustment. At the core of this stage is a 4:1 multiplexer (MUX), whose input signals come from the selected node of the coarse adjustment and the output of the DFF in its vicinity.

[0045] Please see Figure 3By digitally controlling the MUX, one of the signals can be selected as the fine-tuned output, thus achieving fine-grained phase adjustment with a resolution of 1 UI. The ingenuity of this scheme lies in the fact that the multiphase signals required for fine-tuning can be directly reused from the clock generation module resources already present in the high-speed transceiver transmitter (TX), avoiding the need for additional integration of complex delay-locked loops (DLLs) or phase interpolators (PIs). This clock multiplexing strategy is one of the key technical means for achieving low power consumption and low complexity in this scheme, enabling high-precision phase alignment through simple MUX selection.

[0046] To address the potential presence of multiple echoes with varying characteristics in real-world channels, this invention designs the aforementioned two-step delay chain, integrating coarse and fine adjustment functions, into a standardized, reusable modular unit. A complete echo cancellation system comprises multiple such modular units, such as a four-tap system containing one near-end (NE) tap and three far-end (FE) taps. Each tap module can independently adjust its delay time to precisely match the propagation delay of a specific echo component in the channel. This modular design provides the system with exceptional flexibility and scalability. The echo cancellation capability can be configured by simply adding or removing tap modules based on the complexity of channel reflections in different application scenarios. Each additional tap module eliminates one more major echo component, thus adapting to diverse channel environments in a highly cost-effective manner.

[0047] In the system, each tap module generates a delayed signal copy representing a simulation of a given echo in the time dimension. To fully replicate the real echo, a set of programmable weighting coefficients is needed to simulate its amplitude and polarity. The output signal of each tap is multiplied by its corresponding coefficients, which are typically trained and converged using an adaptive algorithm. Finally, all weighted delayed signal copies are fed into a summing circuit for linear superposition, generating a simulated total echo signal. This simulated echo signal is then subtracted from the receiver's input signal, with the specific adder circuitry as shown below. Figure 4 As shown, this effectively eliminates the aliased real echoes in the original signal, recovering a clean data signal. Through this structure, the present invention not only achieves high-precision, full-range echo cancellation, but also fundamentally solves the contradiction between high power consumption, high complexity, and low flexibility in traditional echo cancellers through a two-step delay architecture and modular expansion design concept.

[0048] The result of the cancellation is as follows Figure 5 As shown, for a 112Gbps PAM4 transceiver, when 4-tap echo cancellation is adopted, the residual voltage decreases from 49.2mV to 29.4mV compared to not adopting echo cancellation, and the self-crosstalk is optimized from 26.2dB to 31.3dB.

[0049] Example 2 A high-speed receiver front-end system integrating echo cancellation function is disclosed. The system adopts the high-speed, low-power two-step echo cancellation circuit based on the shared delay chain and achieves optimal synergy between echo cancellation and channel equalization through an innovative split subtraction architecture, thereby further improving the overall signal recovery performance.

[0050] In this receiver front-end system, in addition to the echo cancellation circuit described in Example 1, a continuous-time linear equalizer (CTLE), a main signal path subtractor (main Schermmer), and a data decision unit (Slicer) are also included in sequence. The CTLE is used to compensate for the high-frequency signal components that have been attenuated by the channel, and it itself has high-pass filtering characteristics.

[0051] The core innovation of this embodiment lies in the fact that it does not subtract all analog echo signals from the main signal at the same point. Instead, it employs a separate subtraction architecture that processes the near-end echo (NE) and far-end echo (FE) differently based on their different physical characteristics. Specifically, the analog echo signals generated by one or more taps used to eliminate NE are sent to a first subtractor located before the CTLE input for subtraction. Meanwhile, the analog echo signals generated by multiple taps used to eliminate FE are combined and sent to a second subtractor located after the CTLE output and before the main decision unit input for subtraction.

[0052] The advantage of this split-subtraction architecture is that near-end echoes (NEs) typically have large amplitudes and wide frequencies. If they enter the CTLE (Continuous Transmission Equalization) channel without processing, their signal components will be undesirably amplified and distorted by the high-pass characteristics of the CTLE, increasing the difficulty of subsequent cancellation. By subtracting the NE components before the CTLE, this problem can be effectively avoided, ensuring accurate cancellation of the large NE signal. On the other hand, far-end echoes (FEs) have undergone long-distance round-trip transmission through the channel, and their spectral characteristics have been filtered and shaped by the channel itself, making them more similar to the spectrum of the main signal after CTLE equalization. Therefore, canceling FEs after the CTLE can achieve better spectrum matching, thereby achieving a more accurate far-end echo cancellation effect.

[0053] In addition, the system includes a digital control logic module. This module receives the decision data and error signal from the final-stage data decision unit and, based on this feedback information, adaptively controls all taps in the echo cancellation circuit. The control signals include: a coarse-tuning selection signal for the central shared coarse-tuning delay chain, a fine-tuning selection signal for the fine-tuning MUX within each tap, and a coefficient adjustment signal for the weighting unit of each tap. Through this closed-loop feedback control, the entire receiver front-end system can automatically adapt to the reflection characteristics of different channels and dynamically adjust to achieve optimal echo cancellation and signal decision performance.

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0055] 1. Simulation / Experimental Data (1) Core performance test data

[0056] (2) Environmental adaptability test data Operating temperature range: -40℃~85℃. Within this range, the delay accuracy fluctuation is ≤±0.05UI, and the weighted coefficient adaptive convergence time is ≤10μs, ensuring stable operation in extreme environments. Channel length adaptation: Supports short-distance backplanes and direct connection cables (DAC) from 0.5 to 10m, with a bit error rate ≤1×10⁻⁶ for different channel lengths. -12 It has excellent adaptability.

[0057] In summary, this invention provides a high-speed, low-power two-step echo cancellation circuit based on a shared delay chain, effectively solving the technical challenges of high power consumption, circuit complexity, and difficulty in integration associated with traditional solutions at ultra-high speeds. Its core advantages are reflected in: 1. Significantly low power consumption and low cost: By sharing the coarse tuning chain and reusing the TX clock, the use of a large number of high-speed delay units and dedicated DLL / PI is avoided. Simulations show that power consumption can be reduced to below 0.15pJ / b, and the chip area is significantly reduced.

[0058] 2. High precision and high performance: It adopts a two-step delay method that combines coarse and fine delays, achieving a delay coverage of 1UI accuracy and 128UI range. It can accurately match and eliminate multiple echoes. Experimental data shows that it can reduce the residual voltage of echoes by about 40% and optimize self-crosstalk by more than 5dB.

[0059] 3. Excellent flexibility and scalability: The modular tap design allows for flexible configuration of the number of taps according to the complexity of channel reflection, giving the system strong environmental adaptability.

[0060] 4. System-level performance improvement: The innovative split subtraction architecture enables echo cancellation and linear equalizer to work together without interference, thereby improving the overall signal integrity and bit error rate performance of the receiver.

[0061] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A high speed low power two-step echo cancellation circuit based on a shared delay chain, characterized by, The application relates to a shared delay chain based high-speed low-power two-step echo cancellation circuit. The application comprises: a central shared coarse delay chain composed of multiple cascaded delay units, which is used to provide common delay resources for multiple echo cancellation taps; multiple taps, each of which comprises a fine delay stage connected with an output node of the coarse delay chain, which is used to make fine phase adjustment on the basis of the delay provided by the coarse delay chain, wherein the fine delay stage multiplexes multiple-phase clock signals on the transmitter side for phase selection; a weighting unit connected with the output of each tap, which is used to weight the delay signal copies output by each tap; 2. The shared delay line based high speed low power two-step echo cancellation circuit of claim 1, wherein, a summing unit connected with the weighting unit, which is used to superimpose the weighted multiple signal copies to generate an analog echo signal and subtract the analog echo signal from the input signal of the receiver.

3. The shared delay line based high speed low power two-step echo cancellation circuit of claim 2, wherein, The delay units in the coarse delay chain are D-type flip-flops driven by a low-frequency reference clock.

4. The shared delay line based high speed low power two-step echo cancellation circuit of claim 1, wherein, The coarse delay chain comprises 31 cascaded D-type flip-flops, which provide programmable delay with 4UI steps and a total coverage of 128UI.

5. The shared delay line based high speed low power two-step echo cancellation circuit of claim 4, wherein, The fine delay stage comprises a multiplexer which selects signals from the outputs of the selected node and its adjacent nodes of the coarse delay chain to realize phase adjustment.

6. The shared delay line based high speed low power two-step echo cancellation circuit of claim 1, wherein, The multiplexer is a 4:1 multiplexer, and the input signals are obtained from the outputs of the selected node and its adjacent D-type flip-flops of the coarse delay chain with 1UI time steps.

7. The shared delay line based high speed low power two step echo cancellation circuit of claim 1, wherein, The taps are 4, including one near-end echo tap and three far-end echo taps.

8. A high speed receiver front end system integrated with echo cancellation functionality, characterized by The weighting coefficients of the weighting unit are trained and converged by an adaptive algorithm. The application relates to a shared delay chain based high-speed low-power two-step echo cancellation circuit. The application comprises: a shared delay chain based high-speed low-power two-step echo cancellation circuit according to any one of claims 1 to 7; a continuous-time linear equalizer; 9. The high speed receiver front end system integrated with echo cancellation functionality of claim 8, wherein, a first subtractor arranged before the input end of the continuous-time linear equalizer, which is used to subtract an analog echo signal generated by a near-end tap in the echo cancellation circuit from a received signal; 10. The high speed receiver front end system integrated with echo cancellation functionality of claim 8, wherein, a second subtractor arranged after the output end of the continuous-time linear equalizer, which is used to subtract an analog echo signal generated by a far-end tap in the echo cancellation circuit from the signal output by the continuous-time linear equalizer. The application further comprises a digital control logic module which receives decision data output by a data decision device and an error signal, and performs adaptive control on all tap modules of the echo cancellation circuit based on the decision data and the error signal. The control signals output by the digital control logic module comprise: coarse selection signals for the central shared coarse delay chain, fine selection signals for the fine delay stages in each tap module, and coefficient adjustment signals for the weighting units corresponding to each tap module. The application relates to a shared delay chain based high-speed low-power two-step echo cancellation circuit.

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