Semiconductor device and forming method thereof

Abstract

Semiconductor devices and methods of forming are provided. An exemplary method includes receiving a transistor including a gate structure over a channel region, first and second source / drain features coupled to the channel region, and a dielectric structure over the first and second source / drain features; forming a first trench extending through the dielectric structure to expose the first source / drain feature, forming a second trench extending through the dielectric structure to expose the second source / drain feature; forming a mask layer to cover the first groove, wherein an opening of the mask layer exposes a part of the second groove; after forming the mask layer, performing an ion implantation process to form a doped region in the second source / drain feature; and forming a first source / drain contact in the first trench and a second source / drain contact in the second trench after performing the ion implantation process.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods of forming the same, and particularly to static random access memory devices and methods of forming the same. Background Technology

[0002] In deep sub-micron integrated circuit technology, embedded static random access memory (SRAM) devices have become popular memory cells in high-speed communications, image processing, and system-on-chip (SoC) products. The amount of embedded SRAM in microprocessors and SoCs is constantly increasing to meet the performance requirements of each new technology generation. The performance of transistors in an SRAM cell can affect the minimum operating voltage (Vmin) of the SRAM cell. This can lead to SRAM performance falling below standard or even device failure. Therefore, although existing memory devices generally meet their intended purpose, they are not entirely satisfactory in every aspect. Summary of the Invention

[0003] This invention provides a semiconductor device comprising a memory cell including a write end portion and a read end portion electrically coupled to the write end portion and including a p-type transistor, the p-type transistor including a first source / drain component having one or more epitaxial layers including p-type dopant; a second source / drain component substantially the same as the first source / drain component; and a p-type doped region extending into the one or more epitaxial layers of the first source / drain component.

[0004] This invention provides a semiconductor device comprising a first p-type transistor having a first gate structure disposed above a first portion of an active region; and a second p-type transistor having a second gate structure disposed above a second portion of the active region, wherein the second p-type transistor includes a first source / drain component having a first dopant concentration and a second source / drain component having a second dopant concentration greater than the first dopant concentration.

[0005] This invention provides a method for forming a semiconductor device, including a receiving transistor with a gate structure above a channel region; a first source / drain component and a second source / drain component coupled to the channel region; and a dielectric structure above the first source / drain component and the second source / drain component; forming a first trench extending through the dielectric structure to expose the first source / drain component, and forming a second trench extending through the dielectric structure to expose the second source / drain component; forming a mask layer covering the first trench, wherein an opening in the mask layer exposes a portion of the second trench; after forming the mask layer, performing an ion implantation process to form a doped region in the second source / drain component; and after performing the ion implantation process, forming a first source / drain contact in the first trench, and forming a second source / drain contact in the second trench. Attached Figure Description

[0006] The embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0007] Figure 1A It is a planar schematic diagram illustrating a portion or the entirety of an integrated circuit chip according to various aspects of this disclosure.

[0008] Figure 1B Based on various aspects of this disclosure, a plan view illustrating part or all of a memory cell such as a static random access memory cell is provided.

[0009] Figure 2 Based on various aspects of this disclosure, circuit diagrams are drawn illustrating memory cells such as static random access memory cells that can be implemented in the integrated circuit chip of FIG1.

[0010] Figure 3 This is a partial layout schematic diagram of a memory device including static random access memory cells, based on various aspects of this disclosure.

[0011] Figure 4 This is a schematic flowchart illustrating a method for forming a memory device including static random access memory cells, based on one or more aspects of this disclosure.

[0012] Figure 5 , Figure 6 , Figure 11 , Figure 12 , Figure 13 It is illustrated in accordance with one or more aspects of this disclosure. Figure 4 A partial top view of the memory device during various manufacturing stages in the process.

[0013] Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 17 as well as Figure 18 It is illustrated in accordance with one or more aspects of this disclosure. Figure 4 During the various manufacturing stages of the method, along Figure 3 The section line AA shown is Figure 6 A partial cross-sectional view of the memory device captured by the section line A'-A' shown.

[0014] Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B as well as Figure 15B It is illustrated in accordance with one or more aspects of this disclosure. Figure 4 During the various manufacturing stages of the method, along Figure 6 The illustrated section BB captures a partial layout schematic diagram and / or cross-sectional schematic diagram of the memory device.

[0015] Figure 11C , Figure 12C , Figure 13C , Figure 14C as well as Figure 15C It is illustrated in accordance with one or more aspects of this disclosure. Figure 4 During the various manufacturing stages of the method, along Figure 6 The diagram shows a partial layout of the memory device captured by the section CC and / or a cross-sectional view.

[0016] Figure 16 Based on one or more aspects of this disclosure, a dopant concentration curve is plotted for a doped region within a certain depth range in the source / drain component.

[0017] Figure 19 This is a flowchart illustrating a method for forming a first alternative memory device including a static random access memory cell, according to one or more aspects of this disclosure.

[0018] Figure 20A partial layout schematic diagram of the first alternative memory device is shown in accordance with various aspects of this disclosure.

[0019] Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 as well as Figure 26 It is illustrated in accordance with one or more aspects of this disclosure. Figure 19 During the various manufacturing stages of the method, along Figure 20 A partial cross-sectional schematic diagram of the first alternative memory device captured by section AA and / or section DD.

[0020] Figure 27 This is a partial cross-sectional schematic diagram of a second memory device taken along section line AA, according to one or more aspects of this disclosure.

[0021] Figure 28 Based on one or more aspects of this disclosure, dopant concentration curves of a first doped region and a second doped region within a certain depth range in the source / drain component are plotted.

[0022] Figure 29 A partial layout schematic diagram of a third alternative memory device is shown in accordance with various aspects of this disclosure.

[0023] Figure 30 This is a partial cross-sectional schematic diagram of a third memory device taken along section line EE, according to one or more aspects of this disclosure.

[0024] Figure 31 This is a partial cross-sectional schematic diagram of a third memory device taken along section line FF, according to one or more aspects of this disclosure.

[0025] Figure 32 as well as Figure 33 Partial top views of the fourth alternative memory device and the fifth alternative memory device are shown in accordance with various aspects of this disclosure.

[0026] Figure 34 This is a schematic diagram illustrating a partial layout of an integrated circuit chip, based on one or more aspects of this disclosure.

[0027] Figure 35 Based on various aspects of this disclosure, circuit diagrams are drawn illustrating different memory cells, such as different static random access memory cells, that can be implemented in the integrated circuit chip of FIG1.

[0028] Figure 36This is a partial layout schematic diagram of another memory device comprising different memory cells, illustrated in accordance with various aspects of this disclosure.

[0029] The reference numerals in the attached figures are explained below.

[0030] 10: Integrated circuit chips

[0031] 20: Semiconductor Structure

[0032] 20': Semiconductor structure

[0033] 20'': Semiconductor structure

[0034] 20''': Semiconductor structure

[0035] 30: Array

[0036] 40: Transition Zone

[0037] 100, 100': Method

[0038] 102, 104, 106, 108, 110, 112, 114: Boxes

[0039] 116, 118, 120, 122, 124, 126: Boxes

[0040] 150, 152, 154, 156, 158, 160: Boxes

[0041] 200, 200A, 200B, 200C, 200D: SRAM cells

[0042] 200R: Reader section

[0043] 200W: Write end section

[0044] 202: Substrate

[0045] 202t: Top

[0046] 204: Stacking

[0047] 205: Active Zone

[0048] 205C: Passage Area

[0049] 205SD: Source / Drain Region

[0050] 206: Sacrifice Layer

[0051] 208: Channel Layer

[0052] 207, 207a, 207b: Active regions

[0053] 209: Isolation component

[0054] 210: Dummy Gate Stack

[0055] 210a: Dummy dielectric layer

[0056] 210b: Dummy gate electrode layer

[0057] 210c: Hard masking layer on top of the gate

[0058] 211: Protective layer

[0059] 212: Gate spacer

[0060] 218: Source / Drain Opening

[0061] 219: Virtual Layer

[0062] 220: Inner spacer groove

[0063] 221: Internal spacer component

[0064] 222: Source / Drain Components

[0065] 222N0, 222N1, 222N2, 222N3, 222N4: N-type source / drain components

[0066] 222P0, 222P1, 222P2, 222P3, 222P4: P-type source / drain components

[0067] 236: Contact Etching Stop Layer

[0068] 238: First interlayer dielectric layer

[0069] 240, 240A, 240A1, 240A2, 240B: Gate structure

[0070] 240C, 240D, 240D1, 240D2: Gate Structure

[0071] 242: Etching Stop Layer

[0072] 244: Second interlayer dielectric layer

[0073] 246: Patterned Masking

[0074] 246A, 246B, 246C, 246D: Open

[0075] 246E, 246F, 246G, 246O: Open

[0076] 248, 248A, 248B, 248C, 248D: Source / Drain contact openings

[0077] 248E, 248F, 248G: Source / drain contact openings

[0078] 250: Dielectric insert

[0079] 252, 252', 252'': Patterned protective layer

[0080] 252L: Left boundary

[0081] 252M, 252M', 252M1, 252M2, 252M'', 252M''': Opening

[0082] 252R: Right Boundary

[0083] 256: Ion implantation process

[0084] 258: Doped region

[0085] 260: Doped region

[0086] 265: Curve

[0087] 270: Curve

[0088] 280, 280a, 280b: silicide layers

[0089] 285, 285A, 285B, 285C, 285D: Source / Drain Contacts

[0090] 285E, 285F, 285G: Source / Drain Contacts

[0091] 290: Dielectric structure

[0092] 290a: First floor

[0093] 290b: Second layer

[0094] 292: Trench

[0095] 294: Dielectric Liner

[0096] 296: Ion Implantation Process

[0097] 297: Doped region

[0098] 298: Silicide layer

[0099] 299: Rear guide hole

[0100] 300: Continuous polycrystalline components on the diffusion edge

[0101] 400: Eight-transistor SRAM cell

[0102] A: Area

[0103] AA, A'-A': hatching line

[0104] B: Region

[0105] BB: Section

[0106] C: Region

[0107] CC: Section

[0108] C1: Vertical centerline

[0109] C2: Vertical centerline

[0110] DD: Section line

[0111] EE: Section

[0112] FF: Section

[0113] L0: Undoped semiconductor layer

[0114] L1, L2, L3, L4: Doped semiconductor layers

[0115] M X :layout

[0116] M Y :layout

[0117] PD-1, PD-2: Pull-down transistors

[0118] PG-1, PG-2: Through gate transistors

[0119] PU-1, PU-2: Pull-up transistors

[0120] R0: Layout

[0121] R 180 :layout

[0122] R_BL: Read end bit line

[0123] R_WL: Read endword line

[0124] R-PG, R-PG': The read end is through the gate transistor.

[0125] SN: Storage Node

[0126] SNB: Complementary Storage Node

[0127] S1: Pitch

[0128] S2: Pitch

[0129] VDD: First voltage

[0130] VSS: Second voltage

[0131] W1: Channel width

[0132] W_BL: Bitline

[0133] W_BLB: Complementary bit line

[0134] W_WL: Character Line

[0135] X: Axis

[0136] Y: axis

[0137] Z: Axis Detailed Implementation

[0138] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, in the following disclosure, the formation of a component on another component, its connection to another component, and / or its coupling to another component may include embodiments where the components are formed in direct contact, and may also include embodiments where additional components are formed between components so that the components do not need to be in direct contact. Furthermore, spatially relative terms, such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “up,” “top,” “bottom,” and similar terms, and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), are used to facilitate the description of the relationship between one component and another in this disclosure. Spatially relative terms are intended to cover different orientations of the device, including the components.

[0139] Furthermore, when using terms such as "approximately" or "about," to describe a number or range of numbers, this terminology is intended to cover a reasonable range of numbers that takes into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing parts with the characteristics associated with that number, the number or range of numbers covers a reasonable range that includes the number, such as within + / - 10% of the number. For example, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is + / - 15%, and a material layer with a thickness of "approximately 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers. Additionally, reference values ​​and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and not to indicate a relationship between the different embodiments and / or configurations discussed.

[0140] As component sizes continue to shrink, memory devices containing SRAM cells are increasingly employing nanostructured transistors (e.g., gate-all-around field-effect transistors (GAA FETs)) to improve cell performance, such as cell current, operating voltage (e.g., Vmax, Vmin, etc.), SRAM margins (e.g., write margin and / or read margin), and / or operating speed. For compact dual-port SRAM cells capable of both writing and reading data, the read port can be formed above the same active region and have the same channel width via read-port pass-gate transistors (R-PG) and pull-up transistors PU-1 and PU-2. However, if the saturation current Isat of the gate transistor (R-PG) at the read end is substantially equal to or greater than the saturation current Isat of the pull-up transistors PU-1 and PU-2, then the “α ratio” of the saturation current, that is, the ratio of the Isat of the pull-up transistors to the Isat of the gate transistor (R-PG) at the read end, may be too low, resulting in a poor read range.

[0141] This disclosure provides features including a high α ratio and extended readout range, along with improved voltage dynamic data retention V. ddr This is a memory device with SRAM cells that utilize voltage dynamic data retention (VDRAM). In an exemplary process, after forming the source / drain components of pull-up transistors PU-1 and PU-2 and the read-through gate transistor (R-PG), an ion implantation process is performed to selectively form doped regions within the source / drain components of pull-up transistors PU-1 and PU-2. The formation of doped regions increases the dopant concentration of the source / drain components of pull-up transistors PU-1 and PU-2 and reduces parasitic resistances, thereby increasing the saturation current Isat of pull-up transistors PU-1 and PU-2. In some embodiments, one of the source / drain components of the read-through gate transistor (R-PG) also includes a doped region; however, its dopant concentration and depth are less than those of the doped regions of pull-up transistors PU-1 and PU-2. Therefore, the α ratio can be increased, and the read range can be expanded.

[0142] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. To avoid ambiguity, axes X, Y, and Z in the drawings are perpendicular to each other and are used consistently throughout this disclosure. Throughout this disclosure, unless otherwise stated, similar reference numerals are used to denote similar parts.

[0143] See Figure 1A This disclosure provides an integrated circuit (IC) wafer 10 formed on a substrate and including at least an array of memory cells (SRAM array, semiconductor structure 20). The array (SRAM array, semiconductor structure 20) may include static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, non-volatile random access memory (NVRAM) cells, flash memory cells, other suitable memory cells, or combinations thereof. The IC wafer 10 may further include a plurality of other elements, such as an array 30 of standard logic (STD) cells configured to provide various standard logic devices, such as inverters, AND gates, NAND gates, OR gates, XOR gates, NOR gates, other suitable devices, or combinations thereof. Additionally, the IC wafer 10 may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, bipolar transistors, high-voltage transistors, high-frequency transistors, other suitable devices, or combinations thereof. Additional components may be added to the integrated circuit chip 10, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the integrated circuit chip 10.

[0144] In an embodiment of the present invention, see Figure 1B The array (SRAM array, semiconductor structure 20) comprises multiple SRAM cells (such as SRAM cells 200A, 200B, 200C, and 200D), which typically provide a memory or storage device capable of retaining data when power is applied. Therefore, the array (SRAM array, semiconductor structure 20) is referred to below as an SRAM array. The array (SRAM array, semiconductor structure 20) may also be referred to as a memory device or a semiconductor device. In this disclosure, the memory device (SRAM array, semiconductor structure 20) may include one or more SRAM cells 200A-200D and front-side and back-side interconnect structures associated with said one or more SRAM cells. In embodiments of the invention, each of the SRAM cells 200A-200D includes one or more GAA transistors, which will be discussed in detail below.

[0145] In the embodiments of the present invention, see still Figure 1BSRAM cells 200A, 200B, 200C, and 200D collectively define a 2x2 grid, exhibiting mirror symmetry and / or rotational symmetry relative to each other. For example, using the layout of SRAM cell 200C as a reference (denoted as R0), the layout of SRAM cell 200A (denoted as M...) X The layout of SRAM cell 200C is a mirror image of the layout of SRAM cell 200A with respect to axis X. Similarly, the layout of SRAM cell 200B is a mirror image of the layout of SRAM cell 200A, while the layout of SRAM cell 200D (denoted as M) is a mirror image of the layout of SRAM cell 200A. Y The layout of SRAM cell 200B is a mirror image of the layout of SRAM cell 200C, both relative to the Y-axis. In other words, the layout of SRAM cell 200B (denoted as R) is a mirror image of the layout of SRAM cell 200C. 180 The layout of SRAM cell 200C is symmetrical about the geometric center of the grid, which is defined as the intersection of an imaginary line bisecting the rectangular grid along axis Y and an imaginary line bisecting the rectangular grid along axis X. Furthermore, in the illustrated embodiment, SRAM cells 200A-200D are substantially identical in size, i.e., they have substantially the same horizontal (long) pitch S1 along axis X and vertical (short) pitch S2 along axis Y. Therefore, for simplicity, each of SRAM cells 200A-200D may be referred to hereinafter as SRAM cell 200.

[0146] Figure 2A schematic circuit diagram illustrating a dual-port SRAM cell 200 comprising seven transistors (7T) is shown. The dual-port SRAM cell 200 includes a write end portion 200W. In an embodiment of the invention, the write end portion 200W includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and gate transistors PG-1 and PG-2. In the illustrated embodiment, pull-up transistors PU-1 and PU-2 are p-type transistors, while gate transistors PG-1 and PG-2, pull-down transistors PD-1 and PD-2 are n-type transistors. The drains of pull-up transistors PU-1 and PD-1 are coupled to each other, and the drains of pull-up transistors PU-2 and PD-2 are coupled to each other. Pull-up transistors PU-1 and PD-1 are cross-coupled with pull-up transistors PU-2 and PD-2 to form a data latch. The gates of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled to each other and to the common drain of pull-up transistor PU-2 and pull-down transistor PD-2 to form a memory node SN. The gates of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled to each other and to the common drain of pull-up transistor PU-1 and pull-down transistor PD-1 to form a complementary memory node SNB. The sources of pull-up transistors PU-1 and PU-2 are coupled to a power line configured to provide a first voltage VDD, and the sources of pull-down transistors PD-1 and PD-2 are coupled to a power line configured to provide a second voltage VSS, which in some embodiments may be electrically grounded.

[0147] The data latch's storage node SN is coupled to the 200W bit line W_BL (which can be referred to as the write port bit line W_BL) of the write section via gate transistor PG-2, and the complementary storage node SNB is coupled to the 200W complementary bit line W_BLB (which can be referred to as the write port complementary bit line W_BLB) of the write section via gate transistor PG-1. Storage node SN and complementary storage node SNB are complementary nodes that are constantly at opposite logic levels (logic high or logic low). The word line W_WL (which can be referred to as the write end word line W_WL) of the write section is coupled to the gates of gate transistors PG-1 and PG-2.

[0148] The dual-port SRAM cell 200 also includes a read portion 200R coupled to the write portion 200W. The read portion 200R of the SRAM cell 200 includes a read terminal via a gate transistor R-PG. The read terminal is electrically coupled to a bit line R_BL of the read portion 200R via one source / drain terminal (e.g., the source terminal) of the gate transistor R-PG. The bit line of the read portion 200R may be referred to as the read terminal bit line R_BL. The read terminal is electrically coupled to the gate of the memory node SN (or the gate of pull-up transistor PU-1 and pull-down transistor PD-1) via the other source / drain terminal (e.g., the drain terminal) of the gate transistor R-PG. The read terminal is coupled to a word line R_WL of the read portion 200R via the gate of the gate transistor R-PG. The word line R_WL of the read portion 200R may be referred to as the read terminal word line R_WL. In the illustrated embodiment, the gate transistors R-PG at the read end are p-type transistors. That is, in the dual-port SRAM cell 200, the gate transistors in the write end portion 200W are n-type transistors, and the gate transistors in the read end portion 200R are p-type transistors.

[0149] Figure 3 This is a partial layout schematic of an array (semiconductor structure 20) according to some embodiments of the present disclosure. In the illustrated embodiment, two SRAM cells 200A and 200B are shown, and the layout of SRAM cell 200A is a mirror image of the layout of SRAM cell 200B. The boundary of the dual-port SRAM cell 200B is shown using dashed lines. The dual-port SRAM cell 200B includes active regions 205 and 207b above the substrate 202. Figure 3 In the illustrated embodiment, active regions 205 and 207b each extend longitudinally along axis X. They can be spaced apart from each other along axis Y by isolation structures (e.g., shallow trench isolation (STI) components), such as... Figure 6BThe illustrated isolation component 209. In this embodiment of the invention, the active region 205 is a three-dimensional active region disposed above a doped region or well (e.g., a P-type well, not shown) and configured to provide a channel region for an N-type transistor, such as a pull-down transistor or a through-gate transistor, while the active region 207b is a three-dimensional active region disposed in another doped region (e.g., an N-type well, not shown) and configured to provide a channel region for a P-type transistor, such as a pull-up transistor. The active region 205 extends beyond the boundary of SRAM cell 200B and extends across the boundary of SRAM cell 200A. In other words, SRAM cells 200A and SRAM cells 200B share the same active region 205. SRAM cell 200A includes another active region 207a, which is a mirror image of the active region 207b of SRAM cell 200B. A portion of the active region 205 in SRAM cell 200B includes a channel region formed by nanostructures and N-type source / drain components 222N0-222N4. The active region 207b in SRAM cell 200B includes a channel region formed by nanostructures and P-type source / drain components 222P1-222P4. See also Figures 5-6 Describe in detail the formation of active regions 205, 207b, and 207a.

[0150] SRAM cell 200B also includes gate structures, such as gate structures 240A2, 240A1, 240B, 240C, 240D1, and 240D2, which are oriented longitudinally along the Y-axis and disposed above active region 205 and / or active region 207b to form various transistors. Each gate structure 240A2, 240A1, 240B, 240C, 240D1, and 240D2 spans the channel region of active region 205 and / or the channel region of active region 207b. In the described embodiment, see [reference needed]. Figure 4As an example, gate structure 240A1 is formed above active region 205 to form a through-gate transistor PG-1. Gate structure 240B engages active region 205 and active region 207b to form pull-down transistor PD-1 and pull-up transistor PU-1, respectively. Gate structure 240C engages active region 205 and active region 207b to form pull-down transistor PD-2 and pull-up transistor PU-2, respectively. Gate structure 240D1 engages active region 205 to form a through-gate transistor PG-2. Gate structure 240D2 engages active region 207b to form a read-end through-gate transistor R-PG. Gate structure 240A2 is formed at the end of active region 207b and is not engaged with active region 207b to form a transistor. Gate structures 240A2, 240A1, 240B, 240C, 240D1, and 240D2 can extend beyond the illustrated boundaries because these active regions and gate structures can also form elements of other adjacent SRAM cells. In an embodiment, gate structures 240A2 and 240A1 are multiple portions of a continuous gate structure similar to gate structures 240B / 240C, and gate structures 240D1 and 240D2 are multiple portions of a continuous gate structure similar to gate structures 240B / 240C. To achieve the desired functionality, isolation structures can be formed to divide the continuous gate structure into multiple electrically isolated and physically isolated portions. That is, the sidewalls of gate structures 240A2 and 240A1 are aligned along the Y-axis, and the sidewalls of gate structures 240D1 and 240D2 are aligned along the Y-axis. In this embodiment of the invention, pull-up transistors PU-1 and PU-2, and the read terminal via gate transistor R-PG are P-type GAA transistors, while pull-down transistors PD-1 and PD-2, and the read terminal via gate transistors PG-1 and PG-2 are N-type GAA transistors. The gate structure of SRAM cell 200A can be a mirror image of the gate structure of SRAM cell 200B, and repeated descriptions are omitted for simplicity.

[0151] The array (semiconductor structure 20) also includes source / drain contacts 285A-285G formed above SRAM cells 200A and 200B. For example, SRAM cell 200B includes a source / drain contact 285A that lands on and is electrically coupled to the N-type source / drain component 222N0 via gate transistor PG-1. The source / drain contact 285A can electrically connect the N-type source / drain component 222N0 via gate transistor PG-1 to the complementary bit line (W_BLB) of the write port. SRAM cell 200B further includes a source / drain contact 285B that electrically connects the common N-type source / drain component (e.g., drain component) 222N1 of gate transistor PG-1 and pull-down transistor PD-1 and the P-type source / drain component (e.g., drain component) 222P1 of pull-up transistor PU-1 to the complementary memory node (SNB); a source / drain contact 285C that electrically connects the common N-type source / drain component (e.g., source component) 222N2 of pull-down transistor PD-1 and pull-down transistor PD-2 to the power line of the second voltage VSS; and a source / drain contact that electrically connects the common P-type source / drain component (e.g., source component) 222P2 of pull-up transistor PU-1 and pull-up transistor PU-2 to the power line of the first voltage VDD. 285D includes a source / drain contact 285E that electrically connects the common N-type source / drain component (e.g., drain component) 222N3 of the gate transistor PG-2 and the pull-down transistor PD-2 and the common P-type source / drain component (e.g., drain component) 222P3 of the pull-up transistor PU-2 and the read terminal through the gate transistor R-PG to the memory node (SN); a source / drain contact 285F that electrically connects the N-type source / drain component (e.g., source element) 222N4 of the gate transistor PG-2 to the bit line (W_BL) of the write port; and a source / drain contact 285G that electrically connects the P-type source / drain component (e.g., source element) 222P4 of the read terminal through the gate transistor R-PG to the bit line (R_BL) of the read terminal. Source / drain contacts 285A are shared by SRAM cells 200A and 200B. Apart from source / drain contacts 285A, the other source / drain contacts of SRAM cell 200A are mirror images of source / drain contacts 285B-285G of SRAM cell 200B, and repeated descriptions are omitted for simplicity. In the illustrated embodiment, source / drain contacts 285A-285G are each elongated and have a longitudinal direction on the Y-axis, parallel to the extension direction of gate structures 240A1-240D2.As described above, in order to improve the performance of SRAM cells and memory devices, pull-up transistors PU-1 and / or PU-2 and the read terminal through-gate transistor (R-PG) are formed above the same active region, and pull-up transistors PU-1 and / or PU-2 are configured to have a higher saturation current than the read terminal through-gate transistor (R-PG). See below. Figures 4-18 A method for forming a memory device with improved performance is described, wherein... Figure 4 This is a schematic flow diagram illustrating a method 100 for forming a semiconductor structure (e.g., a memory device) (array, semiconductor structure 20) according to one or more aspects of this disclosure. Figures 5-18 It is illustrated in accordance with one or more aspects of this disclosure. Figure 4 The method includes partial layout schematics and / or cross-sectional schematics of the semiconductor structure 20 during various manufacturing stages.

[0152] See Figure 4 , Figure 5 , Figure 6 as well as Figures 6A-6B Method 100 includes a block 102 which forms an alternating stack 204 of channel layers and sacrificial layers over a substrate 202. Figure 5 A top view schematic diagram of a semiconductor structure 20 including an active region formed by stacks 204 is shown. The semiconductor structure 20 includes a first region for forming SRAM cells 200A and a second region for forming SRAM cells 200B. Figure 6 A top view schematic diagram of a semiconductor structure 20 including an active region and a stack of dummy gates is shown. Figure 6A It is drawn along Figure 6 The diagram shows a partial cross-sectional view of the semiconductor structure 20 taken along section line A'-A'. Figure 6B It is drawn along Figure 6 The diagram shows a partial cross-sectional view of the semiconductor structure 20 taken by the section line BB. The first region (SRAM cell 200A) is a mirror image of the second region (SRAM cell 200B). For ease of description, the following discussion will focus on the second region (SRAM cell 200B).

[0153] In one embodiment, substrate 202 (e.g. Figures 6A-6BThe substrate 202 (illustrated) is a silicon (Si) substrate. In some other embodiments, the substrate 202 may comprise other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or group III-V semiconductor materials. Exemplary group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlInAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also comprise an insulating layer, such as a silicon oxide layer, to have a semiconductor-on-insulator (SOI) structure. Although not explicitly illustrated, the substrate 202 may comprise n-type well regions and p-type well regions for fabricating transistors of different conductivity types. When present, each of the n-type and p-type wells is formed in the substrate 202 and includes a doping distribution. n-type wells can contain doping distributions of n-type dopants, such as phosphorus (P) or arsenic (As). p-type wells can contain doping distributions of p-type dopants, such as boron (B). The dopants in the n-type wells and p-type wells can be formed using ion implantation or thermal diffusion and can be considered as multiple parts of the substrate 202.

[0154] Stack 204 comprises multiple sacrificial layers 206 and multiple channel layers 208 interleaved with the sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 contain different materials to provide etch selectivity. Each channel layer 208 may contain a semiconductor material such as Si, Ge, SiC, SiGe, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while each sacrificial layer 206 has a different material than the channel layers 208. In one such example, the channel layer 208 may contain element Si and the sacrificial layer 206 may contain SiGe. The sacrificial layers 206 and the channel layers 208 can be deposited using epitaxial processes. Suitable epitaxial processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Figures 6A-6B As illustrated, sacrificial layer 206 and channel layer 208 are deposited alternately, one after the other, to form stack 204. It is worth noting that, as... Figures 6A-6BThe three sacrificial layers 206 and three channel layers 208 illustrated are arranged alternately and vertically, and are for illustrative purposes only and are not intended to impose any limitation beyond the scope expressly stated in the claims. It should be understood that any number of sacrificial layers and channel layers can be formed in the stack 204. The number of film layers depends on the desired number of channel components in the device (semiconductor structure 20). In some embodiments, the number of channel layers 208 ranges from 2 to 10, and the number of sacrificial layers 206 ranges from 2 to 10.

[0155] See still Figure 4 , Figures 5-6 as well as Figures 6A-6B Method 100 includes block 104, which patterns the top 202t of the stack 204 and the substrate 202 to form active regions 205 and 207 (e.g., Figure 5 (Illustrated). To pattern stack 204, a hard mask layer can be deposited over stack 204 to form an etch mask. The hard mask layer can be a single layer or multiple layers. For example, the hard mask layer can include a pad oxide layer and a pad nitride layer disposed above the pad oxide layer. Active regions 205 and 207 can be patterned from stack 204 and substrate 202 using photolithography and etching processes. The photolithography process can include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, washing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or other etching methods. In some implementations, dual patterning or multiple patterning processes can be used to define the active regions to create patterns with smaller pitches than those obtained using a single, direct lithography process. In this embodiment, active regions 205 and 207 have the same channel width W1 along the Y-axis.

[0156] After forming active regions 205 and 207, an active region dicing process can be performed to divide active region 207 into two separate segments, such as active regions 207a and 207b. The segment of active region 207 (active region 207a) is located in the first region (SRAM cell 200A), and the segment of active region 207 (active region 207b) is located in the second region (SRAM cell 200B). In this embodiment, unwanted portions of active region 207 can be removed by an active region dicing process that includes photolithography and etching processes. For example, after forming consecutive active regions 205 and 207, a photoresist layer is formed thereon using a spin coating process and a soft bake process. Then, a mask is used to expose the photoresist layer to radiation. The exposed photoresist layer is then developed and stripped to form a patterned photoresist layer. In the continuous active regions 207, portions corresponding to segments 207a and 207b are protected by a patterned photoresist layer, while unwanted portions in between are unprotected. Subsequently, the unwanted portions are etched through openings in the patterned photoresist layer. The patterned photoresist layer is then removed using a suitable process, such as wet stripping or plasma ashing. Isolation components, such as… Figure 3 as well as Figure 19 The isolation component 209 illustrated is located in the gap between the segmented active regions 207a and 207b. Therefore, isolation between the active regions is provided by the isolation component 209 (e.g., an STI component) to better protect the substrate leakage current performance. The isolation component 209 may comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-dielectric-constant dielectric, a combination of the above, and / or other suitable materials. In some embodiments, a protective layer 211 is formed on the isolation component 209 to prevent substantial etching of the isolation component 209 during subsequent processes. For example, the isolation component 209 may comprise silicon oxide, and the protective layer 211 may comprise silicon nitride.

[0157] See still Figure 4 , Figure 6 , Figures 6A-6B The operation of box 104 is also included in the channel area 205C of the active area 205 (shown in...). Figure 6A A dummy gate stack 210 is formed above the active regions 207a and 207b. The channel region 205C and the dummy gate stack 210 also define the source / drain region 205SD (illustrated in...). Figure 6AIn the middle, the source / drain regions 205SD do not vertically overlap with the dummy gate stack 210. Each of the channel regions 205C is disposed between the two source / drain regions 205SD along the X-axis. The dummy gate stack 210 includes a dummy dielectric layer 210a, a dummy gate electrode layer 210b above the dummy dielectric layer 210a, and a gate top hard mask layer 210c above the dummy gate electrode layer 210b. The dummy dielectric layer 210a may contain silicon oxide. The dummy gate electrode layer 210b may contain polysilicon. The gate top hard mask layer 210c may be a multilayer layer containing a silicon oxide layer and a silicon nitride layer formed on the silicon oxide layer. The dummy gate stack 210 can be formed using suitable deposition processes, photolithography processes, and etching processes. In this embodiment, a gate replacement process (or a post-gate process) is used, wherein the dummy gate stack 210 serves as the gate structure 240 (e.g., Figure 10A as well as Figure 11 (As shown in the illustration) Placement elements. Other processes and configurations may also be used.

[0158] Gate spacers 212 are formed extending along the sidewall surface of the dummy gate stack 210. In an exemplary process, the formation of gate spacers 212 includes conformally depositing a single or multiple dielectric layers (not shown) over the semiconductor structure 20 and etching the dielectric layers back from the top-facing surface of the semiconductor structure 20 using an anisotropic etching process. The dielectric layers are deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or sub-atmospheric chemical vapor deposition (SACVD), and may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide nitride, silicon carbide carbon, silicon carbide nitride, and / or combinations thereof. The term "conformally" may be used in this disclosure to describe a film layer having a substantially uniform thickness over various regions. Figure 6A The outline of the gate spacer 212 shown is merely illustrative and not intended to be limiting. For example, in some embodiments, the gate spacer 212 may have a non-uniform width from bottom to top, and the top surface of the gate spacer 212 may be lower than the top surface of the dummy gate stack 210. Although not shown, in some embodiments, the gate spacer 212 may also be formed with fin sidewall spacers directly above the isolation member 209 and extending along the lower portions of the active regions 205 and 207a-207b.

[0159] See Figure 4 as well as Figures 7A-7BMethod 100 includes block 106, which etches the active region 205 and the source / drain regions 205SD of 207a-207b to form source / drain openings 218. In some embodiments, the source / drain regions 205SD of the active region 205 are not covered by the dummy gate stack 210 and the gate spacer 212, and are anisotropically etched by dry etching or a suitable etching process to form the source / drain openings 218. Exemplary dry etching processes may use oxygen-containing gases, hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. The source / drain opening 218 extends through the stack 204 of the channel layer 208 and the sacrificial layer 206 and partially extends into the substrate 202. For example... Figure 7A As shown, the sidewalls of the channel layer 208 and the sacrificial layer 206 are exposed in the source / drain opening 218.

[0160] See Figure 4 as well as Figures 8A-8B Method 100 includes block 108, where the sacrificial layer 206 is replaced with a dummy layer. After forming the source / drain opening 218, the sacrificial layer 206 interleaved with the channel layer 208 in the channel region 205C is selectively removed. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form channel components (channel layer 208). Depending on the design, the channel components (channel layer 208) can be presented as nanowires, nanosheets, or other nanostructures. The selective removal of the sacrificial layer 206 creates spaces between and around adjacent channel components (channel layers 208). The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may involve using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., ammonium hydroxide-hydrogen peroxide-water mixture).

[0161] After selectively removing the sacrificial layer 206, a dielectric material layer is deposited around the channel components (channel layer 208) and over the source / drain openings 218 to fill the spaces between the channel components (channel layer 208). The dielectric material layer may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon carbide nitride, a high dielectric constant dielectric material (e.g., aluminum oxide, hafnium oxide), other suitable materials, or combinations thereof, and may be deposited using plasma-enhanced chemical vapor deposition (PECVD) or ALD or other suitable methods. In an embodiment, the dielectric material layer comprises silicon oxide. In an embodiment, the dielectric material layer extends compliantly over the substrate 202. After depositing the dielectric material layer, an etching process is performed to selectively etch the dielectric material layer, thereby forming dummy layers 219 interlaced with the channel components (channel layer 208). The etching process may further etch the dummy layers 219 laterally, thereby forming inner spacer recesses 220.

[0162] See Figure 4 as well as Figures 9A-9B Method 100 includes block 110, which forms an inner spacer component 221. After forming a dummy layer 219 and an inner spacer recess 220, an inner spacer material layer (not shown) is deposited over the semiconductor structure 20, including deposition in the inner spacer recess 220. The inner spacer material layer may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess inner spacer material layer, thereby forming the inner spacer component 221.

[0163] still Figure 4 as well as Figures 9A-9B Method 100 includes block 112, which forms an undoped semiconductor layer L0 in the lower portion of the source / drain opening 218, and forms a source / drain component 222 above the undoped semiconductor layer L0 and in the upper portion of the source / drain opening 218. In this embodiment of the invention, after forming the inner spacer component 221, the undoped semiconductor layer L0 (e.g., Figure 9A(As illustrated) Formed above the top surface of the substrate 202 exposed in the source / drain opening 218 by an epitaxial process. The undoped semiconductor layer L0 may be undoped or unintentionally doped and may comprise undoped silicon (Si), undoped germanium (Ge), undoped silicon-germanium (SiGe), or other suitable materials. In an embodiment, the undoped semiconductor layer L0 comprises undoped silicon (Si). Although the undoped semiconductor layer L0 is only illustrated in the region used to form p-type transistors (e.g., pull-up transistors PU-1 and PU-2 and readout through gate transistors R-PG), it should be understood that the undoped semiconductor layer L0 may also be formed in the region used to form n-type transistors (e.g., pull-down transistors PD-1 and PD2 and readout through gate transistors PG-1 and PG-2).

[0164] After the undoped semiconductor layer L0 is formed, source / drain components 222 are formed in the source / drain openings 218 and above the undoped semiconductor layer L0. Depending on the context, the source / drain components may refer individually or collectively to a source or a drain. The source / drain components 222 are coupled to the channel component (channel layer 208) of the channel region 205C, and each source / drain component 222 may be epitaxially and selectively formed from exposed semiconductor surfaces (e.g., the sidewalls of the channel component (channel layer 208) and the top surface of the undoped semiconductor layer L0) using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes.

[0165] The source / drain component 222 includes N-type source / drain components, such as pull-down transistors PD-1 and PD-1 formed in the second region (SRAM cell 200B) for forming SRAM cell 200B, and N-type source / drain components 222N0, 222N1, 222N2, 222N3, and 222N4 through gate transistors PG-1 and PG-2. Exemplary N-type source / drain components may comprise silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped during epitaxial processing by introducing N-type dopants, such as phosphorus, arsenic, or antimony, or ex-situ doped using a junction implantation process.

[0166] The source / drain component 222 further includes P-type source / drain components, such as pull-up transistors PU-1 and PU-2 formed in the second region (SRAM cell 200B) for forming SRAM cell 200B, and P-type source / drain components 222P1, 222P2, 222P3, and 222P4 whose read terminals are connected to the gate transistor R-PG. Exemplary P-type source / drain components may comprise germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be in-situ doped during the epitaxial process by introducing P-type dopants, such as boron or gallium, or ex-situ doped using a junction implantation process. In some embodiments, each source / drain component 222 may comprise multiple doped semiconductor layers L1, L2, L3, L4 (e.g., ...) with different dopant concentrations. Figure 10A (As illustrated). In the embodiment, the dopant of the P-type source / drain components 222P1, 222P2, 222P3, and 222P4 includes boron, such as a combination of boron-10 isotope and boron-11 isotope. 11 B can be used interchangeably to denote boron-11 isotopes. B-10 and... 10 B can be used interchangeably to represent the boron-10 isotope. B-10 and B-11 are different boron isotopes, each having five protons. However, isotope B-10 has five neutrons, while isotope B-11 has six neutrons. In the embodiments, in each of the P-type source / drain components 222P1, 222P2, 222P3, and 222P4, 10 B and 11 B exists in a ratio of approximately 20% / 80% (approximately 20%). 10 B and about 80% 11 B).

[0167] See still Figure 4 as well as Figures 9A-9B The operation in block 112 further includes forming a first interlayer dielectric (ILD) layer 238 over the source / drain component 222. After forming the source / drain component 222, a contact etch stop layer (CESL) 236 and the first interlayer dielectric (ILD) layer 238 are deposited over the semiconductor structure 20. The contact etch stop layer 236 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed by an ALD, plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation process. Figure 9AAs illustrated, a contact etch stop layer 236 can be deposited on the top surface of the source / drain component 222 and the sidewalls of the gate spacer 212. After depositing the contact etch stop layer 236, a first interlayer dielectric layer 238 is deposited on the semiconductor structure 20 using a PECVD process or other suitable deposition technique. The first interlayer dielectric layer 238 may comprise materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, after forming the first interlayer dielectric layer 238, the semiconductor structure 20 may be annealed to improve the integrity of the first interlayer dielectric layer 238.

[0168] See Figure 4 as well as Figures 10A-10BMethod 100 includes block 114, where a dummy gate stack 210 and a dummy layer 219 are replaced by a gate structure 240. A planarization process, such as chemical mechanical polishing (CMP), is performed on the semiconductor structure 20 to remove excess material and expose a dummy gate electrode layer 210b in the dummy gate stack 210. With the exposure of the dummy gate electrode layer 210b, the dummy gate stack 210 is selectively removed to form a gate trench (now filled by the outer portion of the gate structure 240). The removal of the dummy gate stack 210 may include one or more etching processes that selectively remove material from the dummy gate stack 210. For example, the removal of the dummy gate stack 210 may be performed using selective wet etching, selective dry etching, or a combination thereof. After the removal of the dummy gate stack 210, the dummy layer 219 is selectively removed to form a gate opening (now filled by the inner portion of the gate structure 240). Selective removal of the dummy layer can be performed by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective wet etching process may involve using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). An exemplary selective dry etching process may involve using fluoride (F2) gas, anhydrous hydrogen fluoride (HF) gas, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0169] Next, gate structures 240 are formed in the gate trench and gate opening. After releasing the channel components (channel layer 208), each gate structure 240 is formed to wrap around each channel component (channel layer 208), as follows: Figure 10AAs illustrated. Although not explicitly shown, each gate structure 240 includes a gate dielectric layer (not separately labeled) and a gate electrode layer (not separately labeled) above the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer disposed on a channel component (channel layer 208) and a high-k dielectric layer above the interface layer. A high-k dielectric layer is defined herein as a dielectric material with a dielectric constant greater than that of silicon dioxide, which has a dielectric constant of about 3.9. A low-k dielectric layer is defined as a dielectric material with a dielectric constant no greater than that of silicon dioxide. In some embodiments, the interface layer comprises silicon oxide. The high-k dielectric layer is then deposited on the interface layer using ALD, CVD, and / or other suitable methods. The high-k dielectric layer may comprise hafnium oxide. Alternatively, the high-dielectric-constant dielectric layer may comprise other high-dielectric-constant dielectrics, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, and SrTi. BaTi BaZrO, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba,Sr)Ti (BST), silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. A gate electrode layer is then deposited over the gate dielectric layer using ALD, physical vapor deposition (PVD), CVD, electron beam evaporation, or other suitable methods. The gate electrode layer may comprise a single layer or alternatively a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a substrate, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer may comprise titanium nitride, aluminum titanium nitride, aluminum titanium nitride, tantalum nitride, aluminum tantalum nitride, aluminum tantalum carbide, tantalum carbide, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, silicon tantalum nitride, copper, other refractory metals, or other suitable metallic materials, or combinations thereof. Furthermore, when the semiconductor structure 20 includes n-type transistors and p-type transistors, different gate electrode layers can be formed for the n-type transistors and p-type transistors respectively, which can include different work function metal layers (e.g., to provide different n-type and p-type work function metal layers).

[0170] Gate structure 240 includes gate structures 240A, 240B, 240C, and 240D in a first region for forming SRAM cell 200A, and gate structures 240A, 240B, 240C, and 240D in a second region for forming SRAM cell 200B. Gate structure 240A includes two-segment gate structures 240A1 and 240A2, while gate structure 240D includes two-segment gate structures 240D1 and 240D2. Gate isolation structures can be formed before or after forming gate structures 240 to divide some gate structures 240 (e.g., gate structures 240A and 240D) into multiple segments to achieve desired functionality. See also Figure 13 The gate transistor PG-1 includes a gate structure 240A1 and N-type source / drain components 222N0 and 222N1. The gate transistor PG-2 includes a gate structure 240D1 and N-type source / drain components 222N3 and 222N4. The pull-down transistor PD-1 includes a gate structure 240B and N-type source / drain components 222N1 and 222N2. The pull-down transistor PD-2 also includes a gate structure 240C and N-type source / drain components 222N2 and 222N3. Pull-up transistor PU-1 includes a gate structure 240A2 and P-type source / drain components 222P1 and 222P2. Pull-up transistor PU-2 includes a gate structure 240C and P-type source / drain components 222P2 and 222P3. The read terminal is connected via gate transistor R-PG, which includes a gate structure 240D2 and P-type source / drain components 222P3 and 222P4. In the above embodiment, the formation of gate structures 240A, 240B, 240C, and 240D includes selectively removing the sacrificial layer 206 to form a gate opening, forming a dummy layer 219 in the gate opening, and forming gate structures 240A, 240B, 240C, and 240D in the gate opening. In some other embodiments, the formation of gate structures 240A, 240B, 240C, and 240D does not include the formation and removal of the dummy layer 219. For example, the formation of gate structures 240A, 240B, 240C, and 240D involves selectively removing the sacrificial layer 206 to form a gate opening after forming the source / drain component 222, and forming gate structures 240A, 240B, 240C, and 240D within the gate opening. Compared to the performance of forming a p-type transistor that does not involve forming and removing the dummy layer 219, the performance of forming a p-type transistor involving forming and removing the dummy layer 219 can be improved by approximately 5% to approximately 15%.

[0171] See Figure 4 , Figure 11 as well as Figures 11A-11CMethod 100 includes a block 118, which forms a second interlayer dielectric (ILD) layer 244 over a substrate 202. Figure 11 A partial view and a simplified top view of the semiconductor structure 20 are shown. Figure 11A It is drawn along Figure 11 The diagram shows a partial cross-sectional view of the semiconductor structure 20 taken along section line A'-A'. Figure 11B It is drawn along Figure 11 The diagram shows a partial cross-sectional view of the semiconductor structure 20 taken by section BB. Figure 11C It is drawn along Figure 11 The diagram shows a partial cross-sectional view of the semiconductor structure 20 taken by section CC. After forming the metal gate structure 240, an etch stop layer 242 is formed over the first interlayer dielectric (ILD) layer 238. The etch stop layer 242 may comprise silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. The formation of the etch stop layer 242 facilitates the formation of gate vias over the metal gate structure 240 during subsequent manufacturing processes. A second interlayer dielectric layer 244 is deposited over the etch stop layer 242 over the semiconductor structure 20 by a PECVD process or other suitable deposition techniques. The second interlayer dielectric layer 244 may contain materials such as tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials.

[0172] See now Figure 4 , Figure 11 , Figure 11A-11C , Figure 12 as well as Figures 12A-12C Method 100 includes blocks 118, each forming a source / drain contact opening 248 to expose one or more source / drain components 222. See the embodiment illustrated here. Figure 11 as well as Figures 11A-11CA patterned mask 246 is formed over the semiconductor structure 20. The patterned mask 246 may comprise silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable dielectric materials. In an exemplary process for forming the patterned mask 246, a hard mask layer may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition techniques. A photoresist layer may then be deposited over the hard mask layer using spin coating, CVD, or other similar processes. The photoresist layer is baked in a pre-exposure baking process, exposed to a radiation source reflected or transmitted from the patterned mask, baked in a post-exposure baking process, and developed in a development process. Because the photoresist layer is selected to be radiation-sensitive, the exposed (or unexposed) portions of the photoresist layer undergo a chemical change during the subsequent development process to become soluble in the developer solution. The patterned photoresist layer has a pattern corresponding to the pattern of the mask. When a patterned photoresist layer is used as an etching mask, a hard mask layer is etched to form a patterned mask 246. In the embodiment illustrated here, the patterned mask 246 includes a plurality of openings (e.g., openings 246A, 246B, 246C, 246D, 246E, 246F, 246G in the second region (SRAM cell 200B) disposed directly above the source / drain component 222. More specifically, in the second region (SRAM cell 200B), opening 246A is located directly above the N-type source / drain component 222N0, opening 246B is located directly above the N-type source / drain component 222N1 and the P-type source / drain component 222P1, opening 246C is located directly above the N-type source / drain component 222N2, opening 246D is located directly above the P-type source / drain component 222P2, opening 246E is located directly above the N-type source / drain component 222N3 and the P-type source / drain component 222P3, opening 246F is located directly above the N-type source / drain component 222N4, and opening 246G is located directly above the P-type source / drain component 222P4. One or more of openings 246A-246G may be individually or collectively referred to as opening 246O. After forming the patterned mask 246, the photoresist layer is selectively removed.

[0173] See Figure 12 as well as Figures 12A-12CWhen patterned mask 246 is used as an etching mask, an etching process is performed to remove multiple portions of the dielectric layer (e.g., contact etch stop layer 236, first interlayer dielectric layer 238, etch stop layer 242, and second interlayer dielectric layer 244) to form source / drain contact openings 248 below opening 246O. The etching process can be a dry etching process, which includes using argon (Ar), fluorinated etchants (e.g., SF6, NF3, CH2F2, CHF3, C4F8, and / or C2F6), oxygen-containing etchants, chlorine-containing etchants (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing etchants (e.g., HBr and / or CHBr3), iodine-containing etchants, or combinations thereof. Each of the source / drain contact openings 248 exposes one or more source / drain components disposed directly below the corresponding opening 246O. More specifically, source / drain contact openings 248A, 248B, 248C, 248D, 248E, 248F, and 248G are formed below openings 246A, 246B, 246C, 246D, 246E, 246F, and 246G, respectively. One or more of the source / drain contact openings 248A-248G may be individually or collectively referred to as source / drain contact openings 248. In some embodiments, after forming the source / drain contact openings 248, a dielectric substrate 250 is formed above the substrate 202 and extends along the sidewalls of the source / drain contact openings 248. The dielectric substrate 250 may comprise silicon nitride, silicon oxide, silicon oxycarbide (SiOC), silicon oxynitride-carbon (SiOCN), or other suitable materials.

[0174] See now Figure 4 , Figure 13 as well as Figures 13A-13C Method 100 includes a box 120, which forms a patterned protective layer 252 over a substrate 202. Figure 13 A partial top view of a semiconductor structure 20 with a patterned protective layer 252 is shown. Figure 13A It is drawn along Figure 13 The diagram shows a partial cross-sectional view of the semiconductor structure 20 taken along section line A'-A'. Figure 13B It is drawn along Figure 13 The diagram shows a partial cross-sectional view of the semiconductor structure 20 taken by section BB. Figure 13C It is drawn along Figure 13 The diagram shows a partial cross-sectional view of the semiconductor structure 20 taken by the section CC.

[0175] In an embodiment, the patterned protective layer 252 may include a photoresist layer and may be formed by a combination of optical lithography processes (e.g., coating, pre-exposure baking, exposure, post-exposure baking, and development processes). The patterned protective layer 252 includes one or more openings (e.g., Figure 13 The illustrated opening 252M is configured to define the region where subsequent ion implantation processes will take place, while other regions are protected by a patterned protective layer 252. As described above, pull-up transistors PU-1 and PU-2 are configured to have a higher saturation current than the readout current through the gate transistor R-PG. In this disclosure, to obtain a higher α ratio, an ion implantation process is performed to further dope the source / drain components of pull-up transistors PU-1 and PU-2 without doping the source / drain components of other transistors (e.g., N-type source / drain components 222N0-222N4, P-type source / drain component 222P4). Furthermore, since the pull-up transistor PU-2 and the read-end share the P-type source / drain component 222P3 through the gate transistor R-PG, the ion implantation process only doped a portion of the P-type source / drain component 222P3 near the gate structure 240C of the pull-up transistor PU-2, and the other portion of the P-type source / drain component 222P3 near the gate structure 240D2 of the read-end through the gate transistor R-PG was not doped by the ion implantation process. In this embodiment, the right boundary 252R of the opening 252M located directly above the P-type source / drain component 222P3 (e.g., ...) Figure 13 as well as Figure 13A (As shown) and aligned with the center line of the P-type source / drain component 222P3, and the left boundary 252L of the opening 252M (as shown) Figure 13 (As shown in the diagram) Located directly above the adjacent SRAM cell 200A. See also Figure 13 as well as Figures 13A-13C In the second region (SRAM cell 200B), opening 252M exposes a portion of the source / drain contact opening 248B above the P-type source / drain component 222P1, the source / drain contact opening 248D above the P-type source / drain component 222P2, and the source / drain contact opening 248E above the P-type source / drain component 222P3. The first region (SRAM cell 200A) is a mirror image of the second region (SRAM cell 200B), and repeated descriptions are omitted for simplicity.

[0176] See now Figure 4 as well as Figures 14A-14CMethod 100 includes block 122, which performs an ion-planting process 256 on the semiconductor structure 20 while using a patterned protective layer 252 as a doping mask. After performing the ion-planting process 256, the patterned protective layer 252 can be selectively removed. For the second region (SRAM cell 200B), the ion-planting process 256 is performed to dope P-type source / drain components 222P1-222P2 and a portion of P-type source / drain components 222P3, while covering N-type source / drain components 222N0-222N4 and other P-type source / drain components (e.g., P-type source / drain components 222P4 and other portions of P-type source / drain components 222P3). In some embodiments, the ion-planting process 256 includes doping with boron, germanium, gallium, other suitable dopants, and / or combinations thereof. In the embodiment, the dopant in the ion implantation process 256 includes boron, and the boron contains... 11 The concentration of the boron isotope is greater than approximately 99.7%. For example, the dopant in the ion implantation process 256 is composed of… 11 Formed by boron isotopes. The ion implantation process 256 provides relatively heavy but shallow doping on the top portions of the source / drain components exposed by the patterned protective layer 252 (e.g., a portion of P-type source / drain components 222P1, 222P2, and 222P3), thereby forming doped regions 258 in the P-type source / drain components 222P1-222P2 and a doped region 260 in the P-type source / drain component 222P3. Because the patterned protective layer 252 is used as a doping mask, the doped region 260 formed in the P-type source / drain component 222P3 is closer to the gate structure 240C of the pull-up transistor PU-2 than the gate structure 240D2 of the gate transistor R-PG at the readout terminal. Although subsequent thermal processing may cause slight diffusion in doped regions 258 and 260, in the final structure, the vertical centerline C1 of doped region 260 (as shown in the image) remains constant. Figure 15A (As shown) The vertical center line C2 deviates from the P-type source / drain component 222P3 (as shown) Figure 15A (As illustrated). Furthermore, since at least half of the top surface of the P-type source / drain component 222P3 is covered by the patterned protective layer 252, the doping window for forming the doped region 260 is smaller than the doping window for forming the doped region 258. Therefore, due to, for example, a microloading effect, the depth spanned along the Z-direction of the doped region 260 is less than the depth spanned along the Z-direction of the doped region 258. Figure 14A as well as Figure 15A drawn.

[0177] The parameters of the ion implantation process 256 can be configured to form doped regions 258 and 260 with different dopant concentrations and depths. For example, in the illustrated embodiment where the transistor includes three channel components (channel layer 208), region A in the source / drain component 222 (e.g., Figure 17 (As illustrated) is defined as the region between the bottom surface of the outer portion of the gate and the horizontal center line of the topmost channel component (channel layer 208), region B in the source / drain component 222 (as shown) Figure 17 (As illustrated) is defined as the region between the horizontal centerline of the topmost channel component (channel layer 208) and the horizontal centerline of the central channel component (channel layer 208), region C in the source / drain component 222 (as shown) Figure 17 (As shown in the diagram) is defined as the area between the horizontal center line of the central channel component (channel layer 208) and the horizontal center line of the bottommost channel component (channel layer 208).

[0178] In one embodiment, in order to primarily drive the dopant to form a doped region 258 within region A, the ion implantation process 256 uses an implantation energy ranging from about 1.6 keV to about 3 keV and an energy ranging from about 1 × 10⁻⁶ keV. 15 atoms / cm 2 Approximately 8×10 15 atoms / cm 2 The implantation dose is used to implant the dopant. In one embodiment, in order to primarily drive the dopant to form doped regions 258 within regions B and C, the ion implantation process 256 uses an implantation energy ranging from about 3 keV to about 4 keV and a dose ranging from about 1 × 10⁻⁶ kilometres per kilometre voltammetric ... 15 atoms / cm 2 Approximately 8×10 15 atoms / cm 2 The dopant material is implanted using the implantation dosage. In some embodiments, the ion implantation process 256 performs two ion implantations using the above parameters, such that the doped region 258 extends from region A to region B / C. Figure 16 The diagram illustrates the final structure (e.g., Figure 15A as well as Figure 15C Curve 265 illustrates the dopant concentration distribution of the doped region 258 within a certain depth range. As shown in curve 265, the dopant in the doped region 258 exhibits a gradient distribution. It should be understood that if the transistor has a different number (e.g., 4-10) of channel components, the parameters of the ion implantation process 256 can be adjusted.

[0179] See now Figure 4 as well as Figures 15A-15CMethod 100 includes block 124, which forms a silicide layer 280 and a source / drain contact 285 in a source / drain contact opening. See also Figures 15A-15C After forming doped regions 258 and 260, a silicide layer 280 and source / drain contacts 285 are formed in the source / drain contact opening 248. To form the silicide layer 280, a metal precursor (e.g., titanium, tantalum, nickel, cobalt, or tungsten) is deposited over the semiconductor structure 20 on the exposed surface including the source / drain components 222. An annealing process is then performed to achieve silicide formation in the N-type transistor and germanation in the P-type transistor between the metal precursor and the exposed semiconductor surface. In some embodiments, unreacted metal precursor is selectively removed after forming the silicide layer 280. Some silicide layers 280 (e.g., silicide layer 280a) are in direct contact with doped regions 258 or 260, while other silicide layers (e.g., silicide layer 280b) are located above and in direct contact with the source / drain components 222. For those silicide layers 280a that are in direct contact with doped regions 258 or 260, doped regions 258 and 260 contain... 11 In embodiments where B-formed dopants are present, the interface between the source / drain components (e.g., P-type source / drain components 222P1-222P3) and the silicide layer 280a above them can be observed using, for example, atomic prove topography. 11 The B concentration is higher than the concentration associated with silicide layer 280b.

[0180] After the silicide layer 280 is formed, a conductive layer is deposited over the semiconductor structure 20, including in the source / drain contact openings 248 and on the silicide layer 280. The conductive layer may comprise aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), or other suitable materials, and may be formed by any suitable deposition process (e.g., CVD). A planarization process, such as a chemical mechanical polishing (CMP) process, may then be performed to remove excess portions of the conductive layer to form the source / drain contacts 285. Although not shown, in some embodiments, the source / drain contacts 285 may further include a conductive barrier layer (e.g., TiN, TaN) extending along the sidewalls and bottom surface of the conductive layer. Figure 17 A partial cross-sectional schematic diagram of the p-type transistors (pull-up transistors PU-1, PU-2 and the read terminal via gate transistor R-PG) in the second region (SRAM cell 200B) of semiconductor structure 20 is shown. Figure 18The diagram shows partial cross-sectional views of the p-type transistors (pull-up transistors PU-1, PU-2 and the read terminal via gate transistor R-PG) in the first region (SRAM cell 200A) and the second region (SRAM cell 200B) of the semiconductor structure 20. These views can also represent the semiconductor structure 20 along... Figure 3 The diagram shows a partial cross-section taken by section line AA.

[0181] See back Figure 4 Method 100 includes block 126, which performs further processes. After forming the source / drain contacts 285, further processes are performed to complete the fabrication of the semiconductor structure 20. For example, additional components such as gate vias and interconnect structures (multiple) may be formed above and / or below the semiconductor structure 20. In some embodiments, the interconnect structure may include multiple intermetallic dielectric (IMD) layers and multiple metal wires or contact vias in each IMD layer. In some cases, the IMD layers and the first intermetallic dielectric layer 238 may share similar compositions. The metal wires and contact vias in each IMD layer may be formed of metals such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal wires and contact vias may be lined with a barrier layer to prevent or reduce electron migration.

[0182] See Figures 4-18 In the embodiments described above, in order to achieve an increased α ratio between the pull-up transistors (e.g., pull-up transistors PU-1, PU-2) and the readout terminals through the gate transistors R-PG, an ion implantation process 256 is performed to form doped regions 258 and 260 from the front side of the substrate 202, and an ion implantation process 296 is performed after the formation of the source / drain contact opening 248 and before the formation of the source / drain contact 285.

[0183] To increase the design flexibility of the metal wires on the upper front side of the substrate 202 and to mitigate leakage and coverage issues, metal wires and conductive vias can be formed on the lower rear side of the substrate 202. Figures 19-26 In another embodiment, the alternative memory device (semiconductor structure 20') includes a rear-side via formed below the P-type source / drain component 222P2, and another ion implantation process 296 is performed from the rear side of the substrate 202 to form a doped region within the lower portion of the P-type source / drain component 222P2 after the formation of the source / drain contact 285. Figure 19 This is a schematic flow diagram illustrating a method 100' for forming a semiconductor structure (e.g., a memory device) 20', according to one or more aspects of this disclosure. Figures 20-26It is illustrated in accordance with one or more aspects of this disclosure. Figure 19 The schematic diagram and / or cross-sectional view of the partial layout of the semiconductor structure 20' during various manufacturing stages in the method. Figure 20 This is a partial layout schematic diagram of the semiconductor structure 20' shown in accordance with one or more aspects of this disclosure. The layout of the semiconductor structure 20' is similar to that described above. Figure 3 The semiconductor structure 20 is described in a layout, but one difference is that the semiconductor structure 20' includes a rear-side via 299 disposed below the P-type source / drain component 222P2 and in direct contact with the doped region 297 disposed in the lower part of the P-type source / drain component 222P2.

[0184] See Figure 19 Method 100' includes blocks 102-118 of method 100. The operations of blocks 102-118 have been described above and will not be repeated for simplicity.

[0185] See Figure 19 as well as Figure 21 Method 100' includes block 150, which forms a silicide layer 280b and a source / drain contact 285 in a source / drain contact opening 248. Figure 21 It is drawn along Figure 20 The diagram shows a partial cross-sectional view of the semiconductor structure 20' taken by the cross-section DD. That is, in the formation... Figure 12 as well as Figures 12A-12C Following the depiction of the source / drain contact opening 248, the operations in blocks 120-122 of method 100 are omitted, and method 100' continues with the operations in block 150. The formation of the silicide layer 280b and the source / drain contact 285 has been described above, and for simplicity, a repeated description is omitted.

[0186] See Figure 19 as well as Figure 22Method 100' includes block 152, where the thickness of substrate 202 is reduced from its rear side. After forming silicide layer 280b and source / drain contacts 285, other components such as gate vias and interconnect structures can be formed over the front side of substrate 202. A carrier substrate (not shown) is then bonded to the front-side interconnect structures. The carrier substrate may comprise a semiconductor material (such as silicon), sapphire, glass, polymer, or other suitable material. Once the carrier substrate is bonded, semiconductor structure 20' (not shown) is flipped. The rear side of semiconductor structure 20' is then planarized (e.g., by a planarization process such as chemical mechanical polishing (CMP)) to reduce the thickness of substrate 202 from its rear side. In embodiments, the planarization process may stop after exposing the bottom surface of the STI component (isolation component 209) and the top 202t of substrate 202. In some embodiments, the planarization process may also remove a portion of the STI component (isolation component 209). For ease of description, the positional relationships described below will be based on the semiconductor structure 20' before flipping, as illustrated in the figure.

[0187] See Figure 19 as well as Figures 22-23 Method 100' includes a block 154 that forms a trench to expose the bottom surface of the P-type source / drain component 222P2. See also Figure 22 A patterned dielectric structure 290 is formed beneath the substrate 202. See also Figure 22 A dielectric structure 290 is formed beneath the bottom surface of the planarized semiconductor structure 20'. In this embodiment, to provide the endpoint of a subsequent planarization process, the dielectric structure 290 includes a first layer 290a and a second layer 290b having a different material composition than the first layer 290a. In this embodiment, the first layer 290a includes a nitride layer (e.g., silicon nitride), while the second layer 290b includes an oxide layer (e.g., silicon oxide). See also Figure 23 The aforementioned dielectric structure 290 is patterned to form a trench 292. The trench 292 is disposed directly beneath at least a portion of the P-type source / drain component 222P2. Next, while using the patterned dielectric structure 290 as an etching mask, an etching process is performed to remove a portion of the substrate 202 disposed directly beneath the P-type source / drain component 222P2, thereby extending the trench 292 vertically. Figure 23 As illustrated, a vertically extending trench 292 extends into the P-type source / drain component 222P2. A dielectric substrate 294 can be formed in the vertically extending trench 292. The composition and formation of the dielectric substrate 294 can approximate those of the dielectric substrate 250.

[0188] See Figure 19 as well as Figure 24Method 100' includes block 156, which performs an ion implantation process 296 on the semiconductor structure 20' while using a patterned dielectric structure 290 as a doping mask. Ion implantation process 296 is similar to ion implantation process 256, and repeated descriptions are omitted for simplicity. The execution of ion implantation process 296 forms a doped region 297 in the lower portion of the P-type source / drain component 222P2. In some embodiments, the doped region 297 may extend into region C, region B, or even region A (e.g., ...). Figure 17 (As illustrated). In some other embodiments, the doped region 297 may be located below region C. It is worth noting that, compared to the ion implantation process 256, which requires a patterned protective layer as an etching mask, the ion implantation process 296 does not require the formation of an additional patterned protective layer as a doping mask. Figure 28 Curve 270 is plotted to represent the dopant concentration distribution of doped region 297 within a certain depth range. As shown by curve 270, the dopant in doped region 297 has a gradient distribution.

[0189] See Figure 19 as well as Figures 25-26 Method 100' includes a box 158 in which a silicide layer 298 and a rear via 299 are formed in a vertically extending trench 292. Figure 26 It is drawn along Figure 20 The diagram shows a partial cross-sectional view of the semiconductor structure 20' taken by section line AA. After forming the doped region 297, a silicide layer 298 and a back-side via 299 are formed. In terms of manufacturing process and composition, the silicide layer 298 is similar to the silicide layer 280a described above, and the back-side via 299 is similar to the source / drain contact 285 described above.

[0190] See Figure 19 Method 100' includes block 160, which performs a further process. This further process may include forming an interconnect structure below the rear via 299. In some embodiments, this interconnect structure may include a plurality of inter-metal dielectric (IMD) layers and a plurality of metal wires in each IMD layer and below the rear side of the substrate 202.

[0191] See Figures 4-26 In the described embodiments, semiconductor structure 20 includes doped regions 258 and 260 formed from the front side of substrate 202, and semiconductor structure 20' includes a doped region 297 formed from the rear side of substrate 202. Figure 27 In another alternative example illustrated, the alternative semiconductor structure 20'' includes both doped regions 258 and 260 formed from the front side of the substrate 202 and doped region 297 formed from the rear side of the substrate 202. Figure 28Two curves, 265 and 270, illustrate an example of the dopant concentration distribution over depth in the doped regions 258 and 297 of the P-type source / drain component 222P2. An illustrative step in forming the semiconductor structure 20'' may include performing the operations of blocks 102-126 of method 100, followed by the operations of blocks 150-160 of method 100'. These operations have been described in detail above, and repeated descriptions are omitted for simplicity.

[0192] See Figures 3-28 In the described embodiments, the formation of the semiconductor structure 20 / 20' / 20'' includes forming a continuous active region 207, followed by using an active region dicing process to dice the continuous active region 207 into two segments, active region 207a and 207b. In another alternative embodiment, Figure 29 A partial top view of the semiconductor structure 20''' is shown. Figure 30 Based on various aspects of this disclosure, the route along... (in part or in whole) Figure 29 The diagram shows a partial cross-sectional view of the semiconductor structure 20''' as shown by the section EE. Figure 31 Based on various aspects of this disclosure, the route along... (in part or in whole) Figure 29 The illustrated section FF shows a partial cross-sectional view of semiconductor structure 20'''. Semiconductor structure 20''' is approximately similar to semiconductor structure 20, but the difference between semiconductor structure 20 and semiconductor structure 20''' includes that semiconductor structure 20''' includes a continuous-poly-on-diffusion-edge (CPODE) component 300 configured to cut continuous active regions 207. The continuous-poly-on-diffusion-edge component 300 is formed in a CPODE process. For the purposes of this disclosure, "diffusion edge" can be equivalently referred to as an active edge, such as an active edge abutting adjacent active regions. In the exemplary process, an etching process is performed to remove a portion of the dummy gate stack 210 and a channel region of the continuous active regions 207 beneath said portion of the dummy gate stack 210, thereby forming a CPODE trench. The dielectric material filling the CPODE trench for isolation is referred to as the continuous-poly-on-diffusion-edge component 300. In some embodiments, after forming continuous polycrystalline components 300 on the diffusion edge, the remaining dummy gate stack 210 is replaced by a metal gate structure 240 in a replacement gate (post-gate) process, and is in direct contact with the gate structure 240A1. Figure 29In this configuration, the continuous polysilicon portion 300 on the diffusion edge is adjacent to and aligned with the gate structure 240A1. The continuous polysilicon portion 300 on the diffusion edge extends along the Y-axis and can further cut into another active region 207 of adjacent SRAM cells (e.g., SRAM cell 200D). That is, two adjacent SRAM cells (e.g., SRAM cells 200B and 200D) can share the continuous polysilicon portion 300 on the diffusion edge. The continuous polysilicon portion 300 on the diffusion edge can also be applied to other alternative embodiments described above, as shown in Figures 19-28.

[0193] See Figures 13-28 In the described embodiments, the patterned protective layer 252 includes an opening 252M (e.g., Figure 13 (As illustrated), it is configured to define the area to be subjected to the subsequent ion implantation process 256, while other areas are protected by a patterned protective layer 252, and the right boundary 252R of the opening 252M is aligned with the center line of the P-type source / drain component 222P3. Figure 32 In another alternative embodiment illustrated, different patterned protective layers 252' having openings 252M' can be used as doping masks for the ion implantation process 256. Patterned protective layers 252' are substantially similar to patterned protective layers 252, with one difference being that patterned protective layers 252' have different openings 252M'. For example... Figure 32 As illustrated, to further increase the α ratio between the pull-up transistors (PU-1 and PU-2) and the gate transistors R-PG at the read end in the SRAM cell, the opening 252M' does not expose the P-type source / drain component 222P3. That is, the right boundary 252R can be positioned directly above the gate structure 240C. Therefore, the P-type source / drain component 222P3 will not be doped by the ion implantation process 256 and is not shown in the diagram. Figures 14A-14C The doped region 260 is depicted in the figure. Therefore, the final structure of the memory device formed using the patterned protective layer 252' is similar to the memory device (semiconductor structure 20), with the difference being that the two source / drain components (i.e., 222P1 and 222P2) of the pull-up transistor PU-1 contain the doped region 258, and the two source / drain components (i.e., 222P3 and 222P4) of the gate transistor at the read end do not contain the doped region 258 / 260. The patterned protective layer 252 may also have other variations. For example, Figure 33The illustrated patterned protective layer 252'' approximates patterned protective layer 252 and has an opening 252M1 above the first region (SRAM cell 200A) and an opening 252M2 above the second region (SRAM cell 200B). The openings 252M1 and 252M2 are separated. The openings 252M1 / 252M2 of the patterned protective layer 252'' are configured to expose at least the P-type source / drain component 222P2, and the patterned protective layer 252'' is configured to cover at least half of the P-type source / drain component 222P3. In other words, when viewed from top, the left boundary 252L can be located between the gate structure 240A2 and the gate structure 240B, while the right boundary 252R can be located between half of the P-type source / drain component 222P3 and the gate structure 240B. Therefore, the final structure of the memory device formed using the patterned protective layer 252'' is similar to that of the memory device (semiconductor structure 20), with the differences including that the P-type source / drain components 222P1 and 222P3 may include doped regions 260, 258, or may not include doped regions 258 / 260, depending on the position of the left boundary 252L, and that the P-type source / drain component 222P2 may include a doped region 258. These patterned protective layers 252' and 252'' can also be used in the fabrication of [see above]. Figures 19-31 Other alternative structures described.

[0194] In some embodiments, such as Figure 34 As illustrated, the patterned protective layer 252 / 252' / 252'' also includes openings exposing P-type transistors in other areas. For example, the integrated circuit wafer 10 includes at least an array (semiconductor structure 20) of memory cells (e.g., SRAM cells 200A-200D) and an array 30 of standard logic (STD) cells. A transition region 40 may be disposed between the array (semiconductor structure 20) and the array 30 to provide isolation between transistors formed in the array (semiconductor structure 20) and transistors formed in the array 30. In an embodiment, the transition region 40 includes consecutive polycrystalline components 300 on two diffusion edges. The patterned protective layer 252 / 252' / 252'' also includes multiple openings (e.g., 252M'') exposing the P-type transistors in the transition region 40 and the P-type transistors in the array 30. The source / drain components of these P-type transistors are then doped using an ion implantation process 256 to include doped regions 258 / 260, thereby enabling those P-type transistors to have enhanced performance. This embodiment can also be seen above. Figures 19-33 Other embodiments described can be combined to create other alternative structures.

[0195] See Figures 2-34The above-described embodiments depict the structure of a memory device comprising a seven-transistor (7T) SRAM cell. The inventive concept (e.g., selecting to form doped regions 258 / 260 / 297 to obtain pull-up transistors and a saturation current difference between the read terminals and gate transistors R-PG) is also applicable to memory devices comprising a two-port SRAM cell having eight transistors (8T). Figure 35 Based on various aspects of this disclosure, a circuit schematic of an eight-transistor SRAM cell 400 that can be implemented in the integrated circuit chip of FIG1 is illustrated. The eight-transistor SRAM cell 400 is similar to a seven-transistor SRAM cell (e.g., SRAM cells 200A / 200B / 200C / 200D), and one difference between the two SRAM cells is that the eight-transistor SRAM cell 400 includes an additional read terminal through a gate transistor R-PG'. Figure 36 A simplified partial layout diagram of two eight-transistor SRAM cells 400 is shown in accordance with various aspects of this disclosure. Figure 36 As illustrated, the eight-transistor SRAM cell 400 also includes a P-type source / drain component 222P0. The read terminal includes P-type source / drain components 222P0 and 222P1 and a gate structure 240A2 via the gate transistor R-PG'. To further increase the saturation current difference (and thus a higher α ratio) between the pull-up transistor and the read terminal via the gate transistor R-PG', in a manner similar to the doped P-type source / drain component 222P3 described above, the P-type source / drain component 222P0 will not be doped by ion implantation process 256 and / or ion implantation process 296, while the P-type source / drain component 222P1 can be at most partially doped by ion implantation process 256 and will not be doped by ion implantation process 296. A patterned protective layer 252 with an opening 252M''' can be used as a doping mask for ion implantation process 256. The alternative embodiments described above can also be applied to form other eight-transistor SRAM cells 400 and other structures including eight-transistor SRAM cells 400, and repeated descriptions are omitted for simplicity.

[0196] While not intended to be limiting, one or more embodiments of this disclosure provide numerous advantages for memory devices and their formation. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor are specific advantages required for all embodiments. For example, this disclosure provides a memory device including SRAM cells, comprising pull-up transistors and a p-type read terminal via a gate transistor RPG. One or more ion-implanting processes can be selectively applied to the source / drain components of the pull-up transistor to improve its performance (e.g., higher saturation current) to achieve a higher α ratio. Therefore, the read range of the SRAM cell can be advantageously extended. In some embodiments, the voltage dynamic data of the SRAM cell is maintained at V. ddr It can improve the voltage by about 30mv to about 80mv.

[0197] This disclosure provides numerous different embodiments. Semiconductor devices and methods of manufacturing thereof are disclosed. In one exemplary aspect, this disclosure relates to a semiconductor device. The semiconductor device includes a memory cell including a write end portion and a read end portion electrically coupled to the write end portion. The read end portion includes a p-type transistor (R-PG) having a first source / drain component, having one or more epitaxial layers including p-type dopant, a second source / drain component substantially identical to the first source / drain component, and a p-type doped region extending into the one or more epitaxial layers of the first source / drain component.

[0198] In some embodiments, the p-type dopant comprises a combination of boron-11 isotopes and boron-10 isotopes. In some embodiments, the p-type doped region comprises boron-11 isotopes, germanium (Ge), or gallium (Ga). In some embodiments, the p-type doped region is disposed on top of a first source / drain component, and the p-type transistor further comprises a plurality of nanostructures extending between the first source / drain component and a second source / drain component, the bottom surface of the p-type doped region being lower than the bottom surface of the topmost nanostructure. In some embodiments, the semiconductor device further comprises source / drain contacts disposed above and electrically coupled to the first source / drain component, the centerline of the source / drain contacts being offset from the centerline of the p-type doped region. In some embodiments, the p-type transistor is a first p-type transistor, the p-type doped region is a first p-type doped region, and the write end portion includes a second p-type transistor. The second p-type transistor includes a first source / drain component, a third source / drain component, and a second p-type doped region. In the third source / drain component, the depth spanned by the second p-type doped region is greater than the depth spanned by the first p-type doped region. In some embodiments, the write end portion further includes a third p-type transistor. The third p-type transistor includes a third source / drain component, a second p-type doped region, a fourth source / drain component, and a third p-type doped region. In the fourth source / drain component, the third p-type doped region is substantially the same as the second p-type doped region. In some embodiments, the saturation current of the second p-type transistor is greater than the saturation current of the first p-type transistor. In some embodiments, the memory cell is a seven-transistor static random access memory (SRAM) cell or an eight-transistor SRAM cell.

[0199] In another illustrative aspect, this disclosure relates to a semiconductor device. The semiconductor device includes a first p-type transistor having a first gate structure disposed over a first portion of an active region, and a second p-type transistor having a second gate structure disposed over a second portion of the active region. The second p-type transistor includes a first source / drain component having a first dopant concentration and a second source / drain component having a second dopant concentration greater than the first dopant concentration.

[0200] In some embodiments, the boron-11 isotope concentration in the first source / drain component is less than that in the second source / drain component, and the boron-10 isotope concentration in the first source / drain component is equal to that in the second source / drain component. In some embodiments, the first p-type transistor includes a second source / drain component and a third source / drain component, wherein the dopant concentration of the third source / drain component is greater than that of the second dopant component. In some embodiments, the second source / drain component includes a doped epitaxial region having a first dopant, and a first doped region having a second dopant extending into the doped epitaxial region; the third source / drain component includes another doped epitaxial region having a first dopant, and a second doped region having a second dopant extending into the other doped epitaxial region, wherein the depth spanned by the second doped region is greater than the depth spanned by the first doped region. In some embodiments, a first portion of the active region is disposed directly below the first gate structure and includes a plurality of nanostructures, and the depth of the second doped region is lower than the bottom surface of the topmost nanostructure. In some embodiments, the second source / drain component includes an epitaxial region having a top surface and a bottom surface, a first doped region adjacent to the top surface of the epitaxial region, and a second doped region adjacent to the bottom surface of the epitaxial region and disposed below the first doped region. In some embodiments, the semiconductor device further includes a first silicide layer contacting the first source / drain component at a first interface, and a second silicide layer contacting the second source / drain component at a second interface, wherein the boron-11 isotope concentration at the second interface is greater than the boron-11 isotope concentration at the first interface.

[0201] In another exemplary aspect, this disclosure relates to a method. The method includes a receiving transistor including a gate structure, a first source / drain component and a second source / drain component coupled to the channel region over a channel region, and a dielectric structure, forming a first trench extending through the dielectric structure to expose the first source / drain component and forming a second trench extending through the dielectric structure to expose the second source / drain component, forming a mask layer covering the first trench, an opening of the mask layer exposing a portion of the second trench, performing an ion implantation process after forming the mask layer to form a doped region in the second source / drain component, and forming a first source / drain contact in the first trench and forming a second source / drain contact in the second trench after performing the ion implantation process.

[0202] In some embodiments, the transistor is a p-type transistor, and the step of performing the ion implantation process includes implanting multiple p-type dopants. In some embodiments, the channel region includes multiple nanostructures, and the gate structure further surrounds the nanostructures. In some embodiments, the centerline of the doped region is offset from the centerline of the second source / drain component.

[0203] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the concept and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A semiconductor device, comprising: a memory cell, comprising: a write side portion; and a read side portion electrically coupled to the write side portion and comprising a p-type transistor, the p-type transistor comprising: a first source / drain component having one or more epitaxial layers comprising a p-type dopant; a second source / drain component substantially identical to the first source / drain component; and a p-type doped region extending into the one or more epitaxial layers of the first source / drain component.

2. The semiconductor device of claim 1, wherein the p-type dopant comprises a combination of boron-11 isotope and boron-10 isotope.

3. The semiconductor device of claim 1, wherein the p-type doped region comprises boron-11 isotope, germanium, or gallium.

4. The semiconductor device of claim 1, wherein the p-type doped region is disposed in a top portion of the first source / drain component, and the p-type transistor further comprises a plurality of nanostructures extending between the first source / drain component and the second source / drain component, wherein a bottom surface of the p-type doped region is lower than a bottom surface of a topmost nanostructure of the plurality of nanostructures.

5. A semiconductor device, comprising: a first p-type transistor comprising a first gate structure disposed over a first portion of an active region; and a second p-type transistor comprising a second gate structure disposed over a second portion of the active region, wherein the second p-type transistor comprises a first source / drain component having a first dopant concentration and a second source / drain component having a second dopant concentration greater than the first dopant concentration.

6. The semiconductor device of claim 5, wherein a boron-11 isotope concentration in the first source / drain component is less than a boron-11 isotope concentration in the second source / drain component, and a boron-10 isotope concentration in the first source / drain component is equal to a boron-10 isotope concentration in the second source / drain component.

7. The semiconductor device of claim 5, wherein the second source / drain component comprises: an epitaxial region having a top surface and a bottom surface; a first doped region adjacent to the top surface of the epitaxial region; and a second doped region adjacent to the bottom surface of the epitaxial region and disposed below the first doped region.

8. The semiconductor device of claim 5, further comprising: a first silicide layer contacting the first source / drain component at a first interface; and a second silicide layer contacting the second source / drain component at a second interface, wherein a boron-11 isotope concentration of the second interface is greater than a boron-11 isotope concentration of the first interface.

9. A method of forming a semiconductor device, comprising: receiving a transistor comprising: a gate structure over a channel region; a first source / drain component and a second source / drain component coupled to the channel region; and a dielectric structure over the first source / drain component and the second source / drain component; ​ ​ ​ forming a first trench extending through the dielectric structure to expose the first source / drain component, and forming a second trench extending through the dielectric structure to expose the second source / drain component; forming a mask layer covering the first trench, wherein an opening of the mask layer exposes a portion of the second trench; after forming the mask layer, performing an ion implantation process to form a doped region in the second source / drain component; and after performing the ion implantation process, forming a first source / drain contact in the first trench, and forming a second source / drain contact in the second trench.

10. The method of claim 9, wherein a centerline of the doped region is offset from a centerline of the second source / drain component.

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