Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment. The semiconductor structure comprises a substrate; the transistor structure comprises two transistors which are arranged at an interval along the first direction; the transistor comprises a first source and drain electrode and a semiconductor layer which are sequentially arranged along a second direction perpendicular to the substrate, and a gate layer surrounding the side wall of the semiconductor layer; the bit line structure is located between the two transistors, extends in the third direction and is connected with the first source and drain electrodes of the transistors respectively; the third direction intersects the first direction. The method includes. The use performance of the transistor element can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) typically includes transistor elements.

[0003] In traditional technology, transistor devices often save area by shortening the channel length "L". However, as the oxide layer of transistor devices becomes thinner, short-channel effects also occur, making it easy for transistor devices to have uncontrollable leakage current, which greatly affects the performance of transistor devices.

[0004] Therefore, traditional transistor devices suffer from poor performance. Summary of the Invention

[0005] Based on this, it is necessary to address the aforementioned technical problems. This disclosure provides a semiconductor structure, which includes: a substrate;

[0006] A transistor structure includes two transistors spaced apart along a first direction; the transistors include a first source / drain electrode and a semiconductor layer arranged sequentially along a second direction perpendicular to the substrate, and a gate layer surrounding the sidewalls of the semiconductor layer;

[0007] The bitline structure is located between two transistors and extends along a third direction, connecting to the first source and drain of each transistor respectively; the third direction intersects with the first direction.

[0008] In some embodiments of this disclosure, it further includes: a bit line contact structure located on the top surface of the bit line structure away from the substrate, and respectively contacting the adjacent first source and drain electrodes; wherein the bit line structure is spaced apart from the gate layer.

[0009] In some embodiments of this disclosure, the bit line structure includes: a bit line; and an insulating layer located between the bit line and the substrate, respectively contacting the bottom of the bit line and the sidewall of the bit line.

[0010] In some embodiments of this disclosure, the two transistors in the transistor structure are mirror-symmetrical.

[0011] In some embodiments of this disclosure, the gate layer covers a portion of the sidewall of the semiconductor layer, and the sidewalls of the semiconductor layer in two transistors that are not covered by the gate layer are disposed opposite each other.

[0012] In some embodiments of this disclosure, it further includes: a word line structure located on the side of the transistor structure away from the substrate and extending along the first direction, including two word lines spaced apart along the third direction; wherein the two word lines in the word line structure and the gate layers of the two transistors in the transistor structure are respectively connected.

[0013] In some embodiments of this disclosure, the semiconductor structure includes a plurality of transistor structures arranged in an array, a plurality of transistor structures arranged in a column along the third direction sharing a bit line structure, and a plurality of transistor structures arranged in a row along the first direction sharing a word line structure.

[0014] In some embodiments of this disclosure, among a plurality of transistor structures arranged along the first direction, there is one word line in the odd-numbered transistor common word line structure and another word line in the even-numbered transistor common word line structure.

[0015] In some embodiments of this disclosure, the transistor further includes a second source / drain located on the top surface of the semiconductor layer away from the substrate. The semiconductor structure further includes a storage structure located on the side of the transistor structure away from the substrate, corresponding to the transistor, and connected to the second source / drain of the transistor.

[0016] Furthermore, this disclosure also provides a method for fabricating a semiconductor structure, the semiconductor structure including a transistor structure, the transistor structure including two transistors spaced apart along a first direction, the fabrication method comprising:

[0017] A first source / drain electrode and a semiconductor layer are formed on a substrate; the first source / drain electrode and the semiconductor layer are sequentially disposed along a second direction perpendicular to the substrate;

[0018] A bit line structure is formed on the substrate within the transistor structure. The bit line structure is located between two transistors and extends along a third direction, respectively connecting to the first source and drain of each transistor.

[0019] A gate layer is formed on the semiconductor layer, surrounding the sidewalls of the semiconductor layer.

[0020] In some embodiments of this disclosure, the step of forming a first source / drain electrode and a semiconductor layer in a transistor on the substrate includes: forming an active cell on the substrate, the active cell including two active regions spaced apart along a first direction; a bit line trench extending through the active regions along a second direction perpendicular to the substrate is formed between the two active regions, the active regions and the bit line trench both extending along a third direction; the third direction intersects the first direction; and performing an implantation process based on the bit line trench to form a first source / drain electrode and a second source / drain electrode spaced apart along the second direction in the active regions, the active region between the first source / drain electrode and the second source / drain electrode serving as the semiconductor layer.

[0021] In some embodiments of this disclosure, the step of performing an injection process based on the bit line trench to form a first source / drain electrode and a second source / drain electrode spaced apart along the second direction in the active region includes: dividing the active region into three parts along the vertical direction, forming a protective layer on the sidewall of the middle part, and using the protective layer as a mask to inject the other two parts.

[0022] In some embodiments of this disclosure, the step of forming a gate layer surrounding the sidewalls of the semiconductor layer on the semiconductor layer includes: forming a gate structure on the semiconductor layer that covers a portion of the sidewalls of the semiconductor layer; the gate structure includes a gate dielectric layer and a gate material; wherein the sidewalls of the semiconductor layer in the two transistors that are not covered by the gate structure are disposed opposite to each other; at least the gate material between adjacent active regions is removed to form a gate layer surrounding the sidewalls of the semiconductor layer.

[0023] In some embodiments of this disclosure, forming a bit line structure in a transistor structure on the substrate includes: forming an insulating layer in the bit line trench covering the bottom and sidewalls of the bit line trench; forming a bit line extending in the third direction at the bottom and sidewalls of the insulating layer; and removing a portion of the insulating layer so that the insulating layer contacts the bottom and sidewalls of the bit line, respectively, to form the bit line structure.

[0024] In some embodiments of this disclosure, the method further includes: extending a word line structure along the first direction on the side of the transistor structure away from the substrate; wherein the word line structure includes two word lines spaced apart along the third direction, and the two word lines in the word line structure and the gate layers of the two transistors in the transistor structure are respectively connected.

[0025] The transistor structure in the semiconductor structure provided in this disclosure includes two transistors spaced apart along a first direction; each transistor includes a first source / drain electrode and a semiconductor layer sequentially arranged along a second direction perpendicular to the substrate, and a gate layer surrounding the sidewalls of the semiconductor layer; a bit line structure is located between the two transistors and extends along a third direction, respectively connecting to the first source / drain electrode of each transistor; the third direction intersects the first direction; thus, the channel length of the transistor in the semiconductor device can be effectively increased, the electric field between the source and drain of the transistor can be reduced, leakage current in the transistor can be reduced, the drive current of the semiconductor device can be increased, and the lifespan and performance of the transistor device can be effectively improved.

[0026] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1A A three-dimensional diagram of a semiconductor structure;

[0029] Figure 1B for Figure 1A The side view of the semiconductor structure shown;

[0030] Figure 1C for Figure 1B The diagram shows a cross-sectional view of the semiconductor structure along BB'.

[0031] Figure 1D for Figure 1A The diagram shows a top view of the semiconductor structure.

[0032] Figure 2A A three-dimensional diagram of a semiconductor structure comprising multiple transistor structures arranged in an array;

[0033] Figure 2B for Figure 2A A three-dimensional schematic diagram of the connection structure formed by the semiconductor structure and the bit line structure shown.

[0034] Figure 2C for Figure 2A A top view of the interconnect structure formed by the semiconductor structure and the bit line structure shown.

[0035] Figure 2D for Figure 2A A three-dimensional schematic diagram of the connection structure formed by the semiconductor structure and the memory structure shown;

[0036] Figure 2E for Figure 2A A three-dimensional schematic diagram of the memory device formed by the semiconductor structure, memory structure, and bit line structure shown.

[0037] Figure 3 for Figure 2E The circuit diagram of the storage device shown;

[0038] Figure 4 This is a schematic diagram illustrating the steps of a semiconductor structure fabrication method in one embodiment.

[0039] Figure 5 This is a schematic diagram of step S101 in the method for fabricating a semiconductor structure in one embodiment;

[0040] Figure 6 This is a schematic diagram of step S102 in the method for fabricating a semiconductor structure in one embodiment;

[0041] Figure 7 This is a schematic diagram of step S103 in the method for fabricating a semiconductor structure in one embodiment;

[0042] Figure 8 This is a schematic diagram of step S104 in the method for fabricating a semiconductor structure in one embodiment;

[0043] Figure 9 This is a schematic diagram of step S105 in the method for fabricating a semiconductor structure in one embodiment;

[0044] Figure 10 This is a schematic diagram of step S106 in the method for fabricating a semiconductor structure in one embodiment;

[0045] Figure 11 This is a schematic diagram of step S107 in the method for fabricating a semiconductor structure in one embodiment;

[0046] Figure 12 This is a schematic diagram of step S108 in the method for fabricating a semiconductor structure in one embodiment;

[0047] Figure 13 This is a schematic diagram of step S109 in the method for fabricating a semiconductor structure in one embodiment;

[0048] Figure 14This is a schematic diagram of step S110 in the method for fabricating a semiconductor structure in one embodiment;

[0049] Figure 15 This is a schematic diagram of step S111 in the method for fabricating a semiconductor structure in one embodiment;

[0050] Figure 16 This is a schematic diagram of step S112 in the method for fabricating a semiconductor structure in one embodiment;

[0051] Figure 17 This is a schematic diagram of step S113 in the method for fabricating a semiconductor structure in one embodiment;

[0052] Figure 18 This is a schematic diagram of step S114 in the method for fabricating a semiconductor structure in one embodiment;

[0053] Figure 19 This is a schematic diagram of step S115 in the method for fabricating a semiconductor structure in one embodiment;

[0054] Figure 20 This is a schematic diagram of step S116 in the method for fabricating a semiconductor structure in one embodiment;

[0055] Figure 21 This is a schematic diagram of step S201 in the method for fabricating a semiconductor structure in one embodiment;

[0056] Figure 22 This is a schematic diagram of step S202 in the method for fabricating a semiconductor structure in one embodiment;

[0057] Figure 23 This is a schematic diagram of step S203 in the method for fabricating a semiconductor structure in one embodiment;

[0058] Figure 24 This is a schematic diagram of step S204 in the method for fabricating a semiconductor structure in one embodiment;

[0059] Figure 25 This is a schematic diagram of step S205 in the method for fabricating a semiconductor structure in one embodiment;

[0060] Figure 26 This is a schematic diagram of step S206 in the method for fabricating a semiconductor structure in one embodiment;

[0061] Figure 27 This is a schematic diagram of step S207 in the method for fabricating a semiconductor structure in one embodiment;

[0062] Figure 28This is a schematic diagram of step S208 in the method for fabricating a semiconductor structure in one embodiment;

[0063] Figure 29 This is a schematic diagram of step S209 in the method for fabricating a semiconductor structure in one embodiment;

[0064] Figure 30 This is a schematic diagram of step S210 in the method for fabricating a semiconductor structure in one embodiment;

[0065] Figure 31 This is a schematic diagram of step S211 in the method for fabricating a semiconductor structure in one embodiment;

[0066] Figure 32 This is a schematic diagram of step S212 in the method for fabricating a semiconductor structure in one embodiment;

[0067] Figure 33 This is a schematic diagram of step S301 in the method for fabricating a semiconductor structure in one embodiment;

[0068] Figure 34 This is a schematic diagram of step S302 in the method for fabricating a semiconductor structure in one embodiment;

[0069] Figure 35 This is a schematic diagram of step S303 in the method for fabricating a semiconductor structure in one embodiment;

[0070] Figure 36 This is a schematic diagram of step S304 in the method for fabricating a semiconductor structure in one embodiment;

[0071] Figure 37 This is a schematic diagram of step S305 in the method for fabricating a semiconductor structure in one embodiment;

[0072] Figure 38 This is a schematic diagram of step S306 in the method for fabricating a semiconductor structure in one embodiment;

[0073] Figure 39 This is a schematic diagram of step S307 in the method for fabricating a semiconductor structure in one embodiment;

[0074] Figure 40 This is a schematic diagram of step S308 in the method for fabricating a semiconductor structure in one embodiment;

[0075] Figure 41 This is a schematic diagram of step S309 in the method for fabricating a semiconductor structure in one embodiment;

[0076] Figure 42This is a schematic diagram of step S310 in the method for fabricating a semiconductor structure in one embodiment;

[0077] Figure 43 This is a schematic diagram of step S311 in the method for fabricating a semiconductor structure in one embodiment;

[0078] Figure 44 This is a schematic diagram of step S312 in the method for fabricating a semiconductor structure in one embodiment;

[0079] Figure 45 This is a schematic diagram of step S313 in the method for fabricating a semiconductor structure in one embodiment;

[0080] Figure 46 This is a schematic diagram of step S314 in the method for fabricating a semiconductor structure in one embodiment;

[0081] Figure 47 This is a schematic diagram of step S315 in the method for preparing a semiconductor structure in one embodiment.

[0082] The reference numerals and their meanings in the attached figures are as follows:

[0083] 100. Transistor structure; 1000. Transistor; 1000a. Odd-bit transistor; 1000b. Even-bit transistor; 1001. First source / drain; 1002. Semiconductor layer; 1003. Gate layer; 1004. Sidewall of semiconductor layer not covered by gate layer; 1005. Active pillar; 1006. Second source / drain; 200. Substrate; 300. Bit line structure; 3001. Bit line; 3002. Insulating layer; 400. Bit line contact structure; 500. Word line structure; 5001. Word line; 5001a. Word line connected to odd-bit transistor 1000a; 5001b. Word line connected to even-bit transistor 1000b; 5002. Word line contact structure; 600. Memory structure; 6001. Electrical... Container; 6002, Capacitor contact structure; 7001, First photomask layer; 7002, Active cell; 7002a, Active region; 7003, Bit line trench; 7004, Oxide material; 7005, Sacrificial oxide layer; 7006, Silicon nitride layer; 7007, Second photomask layer; 7008, Protective layer; 7009, Third photomask layer; 7010, Insulating layer; 7011, Oxide isolation layer; 7012, Fourth photomask layer; 7013, Gate material; 7014, Fifth photomask layer; 7015, Sixth photomask layer; 7016, Seventh photomask layer; 7017, Eighth photomask layer; 7018, Contact window photomask layer; 7019, Contact window; 7020, Tungsten metal. Detailed Implementation

[0084] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0086] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0087] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0088] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0089] Figure 1A This is a 3D diagram of a semiconductor structure. Figure 1B for Figure 1A The side view of the semiconductor structure shown; as Figures 1A to 1B As shown, this disclosure provides a semiconductor structure, including:

[0090] Base 200:

[0091] The transistor structure 100 includes two transistors 1000 spaced apart along a first direction; each transistor 1000 includes a first source / drain 1001 and a semiconductor layer 1002 arranged sequentially along a second direction perpendicular to the substrate 200, and a gate layer 1003 surrounding the sidewall of the semiconductor layer 1002.

[0092] Bit line structure 300 is located between two transistors 1000 and extends along a third direction, connecting to the first source and drain 1001 of each transistor 1000 respectively; the third direction intersects with the first direction.

[0093] It should be noted that in the described embodiments, the first direction may refer to the x-direction shown in the figure, the second direction may refer to the z-direction shown in the figure, and the third direction may refer to the y-direction shown in the figure.

[0094] In some examples of this embodiment, such as Figure 1A As shown, the two transistors 1000 in the transistor structure 100 are mirror-symmetrical.

[0095] It can be understood that the gate layer 1003 surrounding the sidewalls of the semiconductor layer 1002 can refer to the gate layer 1003 partially or entirely surrounding the sidewalls of the semiconductor layer 1002. That is, a portion of the sidewalls of the semiconductor layer 1002 may not be covered by the gate layer 1003.

[0096] In some examples of this embodiment, the gate layer 1003 covers a portion of the sidewall of the semiconductor layer, and the sidewalls 1004 of the semiconductor layer in the two transistors that are not covered by the gate layer are arranged opposite each other.

[0097] For ease of understanding by those skilled in the art, please refer to Figure 1C , Figure 1C for Figure 1B The diagram shows a cross-sectional view of the semiconductor structure along BB'; wherein the projection of the gate layer 1003 on the substrate 200 can partially surround the projection of the active pillar 1005 of the transistor 1000 on the substrate 200; further, the projection of the gate layer 1003 on the substrate 200 and the projection of the bit line structure 300 on the substrate 200 do not coincide at least partially or entirely.

[0098] In practical applications, the projection of the gate layer 1003 onto the substrate 200 can be a C-shape or a concave shape. In practical applications, the gate layer of this disclosure can be referred to as a three-dimensional C-shaped gate element or a three-dimensional C-shaped gate element.

[0099] In practical applications, the distance between the two gate layers 1003 in the transistor structure 100 is related to the shape and size of the two active pillars 1005 perpendicular to the substrate 200 in the transistor structure 100. For example, the smaller the shape of the two active pillars 1005 in the transistor structure 100, the smaller the interaction between the two gate layers 1003 when they cover their respective active pillars 1005. As the shape of the two active pillars 1005 decreases, the drive current of the transistor structure is also affected.

[0100] In some examples of this embodiment, such as Figures 1A to 1B As shown, the semiconductor structure also includes a bit line contact structure 400, which can be located on the top surface of the bit line structure 300 away from the substrate 200 and contact the adjacent first source and drain electrodes 1001 respectively; wherein, the bit line structure 300 is spaced apart from the gate layer 1003.

[0101] In practical applications, such as Figures 1A to 1B As shown, the bit line contact structure 400 extends along the third direction (i.e., the y direction in the figure); in other words, the bit line contact structure 400 is set in a one-to-one correspondence with the transistor 1000 and is arranged at intervals along the third direction, that is, one transistor structure 100 corresponds to one bit line contact structure 400.

[0102] In some examples of this embodiment, such as Figures 1A to 1B As shown, the bitline structure 300 includes:

[0103] A bit line 3001 is located between two transistors 1000 and extends along a third direction; the bit line 3001 is electrically connected to the first source-drain electrode 1001 through the bit line contact structure 400 described above.

[0104] The insulating layer 3002 is located between the bit line 3001 and the substrate 300, and is in contact with the bottom of the bit line 3001 and the sidewall of the bit line 3001, respectively.

[0105] For ease of understanding by those skilled in the art, please refer to Figure 1D , Figure 1D An exemplary top view of a semiconductor structure is provided; Figure 1D for Figure 1A The top view of the semiconductor structure shown; as Figure 1D As shown, the semiconductor structure also includes;

[0106] The word line structure 500 is located on the side of the transistor structure 100 away from the substrate 200, that is, above the transistor structure 100, and extends along a first direction (x direction in the figure). The word line structure 500 includes two word lines 5001 spaced apart along a third direction.

[0107] In this configuration, the two word lines 5001 in the word line structure 500 and the gate layers 1003 of the two transistors 1000 in the transistor structure 100 are respectively connected.

[0108] Specifically, the word line structure 500 includes a word line contact structure 5002, which is located between two word lines 5001 and the gate layer 1003 of the transistor 1000. The two word lines 5001 are respectively connected through the word line contact structure 5002. Figure 1D As shown, the word line 5001 located on the left side of the figure is electrically connected to the gate layer 1003 located on the lower side of the figure through the word line contact structure 5002 located on the left side of the figure; the word line 5001 located on the right side of the figure is electrically connected to the gate layer 1003 located on the upper side of the figure through the word line contact structure 5002 located on the right side of the figure.

[0109] It is understood that the transistor structure provided by the above embodiment includes two transistors spaced apart along a first direction; each transistor includes a first source / drain and a semiconductor layer sequentially arranged along a second direction perpendicular to the substrate, and a gate layer surrounding the sidewall of the semiconductor layer; a bit line structure is located between the two transistors and extends along a third direction, respectively connecting to the first source / drain of each transistor; the third direction intersects with the first direction; thus, the channel length of the transistor in the semiconductor device can be effectively increased, the electric field between the source and drain of the transistor can be reduced, leakage current in the transistor can be reduced, the driving current of the semiconductor device can be increased, and the lifespan and performance of the transistor device can be effectively improved.

[0110] Figure 2A This is a three-dimensional diagram of a semiconductor structure comprising multiple transistor structures arranged in an array. Figure 2B for Figure 2A A three-dimensional schematic diagram of the connection structure formed by the semiconductor structure and the bit line structure shown. Figure 2C for Figure 2A A top view of the interconnect structure formed by the semiconductor structure and the bit line structure shown; in some examples of this embodiment, such as Figure 2A As shown, the semiconductor structure includes multiple transistor structures 100 arranged in an array, such as... Figure 2B As shown, multiple transistor structures 100 arranged in a row along a third direction (y direction in the figure) share a bit line structure 300, and multiple transistor structures 100 arranged in a row along a first direction (x direction in the figure) share a word line structure 500.

[0111] Furthermore, such as Figure 2C As shown, among the multiple transistor structures 100 arranged along the first direction, the odd-numbered transistors 1000a share a word line 5001a in the word line structure, and the even-numbered transistors 1000b share another word line 5001b in the word line structure.

[0112] Figure 2D for Figure 2A A three-dimensional schematic diagram of the connection structure formed by the semiconductor structure and the memory structure shown; Figure 2E for Figure 2A The diagram shows a three-dimensional representation of a memory device formed by a semiconductor structure, a memory structure, and a bit line structure; in some examples of this embodiment, such as... Figure 2D As shown, each transistor 1000 also includes a second source / drain 1006, which is located on the top surface of the semiconductor layer 1002 away from the substrate 200. The semiconductor structure also includes a memory structure 600, which is located on the side of the transistor structure away from the substrate 200 and is correspondingly arranged with the transistor 1000. That is, one transistor 1000 corresponds to one memory structure 600 and is connected to the second source / drain 1006 of the transistor 1000.

[0113] In practical applications, the storage structure 600 may include a capacitor 6001 and a capacitor contact structure 6002; the capacitor 6001 is electrically connected to the second source-drain terminal 1006 of the transistor 1000 through the capacitor contact structure 6002.

[0114] For the convenience of those skilled in the art, Figure 3 Instance provided Figure 2E The circuit diagram of the memory device shown is provided. The memory device includes multiple memory cells arranged in an array. Each memory cell includes a transistor and a memory. The gates of the transistors in the multiple memory cells located in the same row are electrically connected to the same word line, and the source and drain of the transistors in the multiple memory cells located in the same column are electrically connected to the same bit line.

[0115] Figure 4 This is a schematic diagram illustrating the steps of a method for fabricating the aforementioned semiconductor structure. The semiconductor structure includes a transistor structure, which comprises two transistors spaced apart along a first direction. (Refer to...) Figure 4 As shown, the method for fabricating this semiconductor structure includes steps S402 to S406. Wherein:

[0116] In step S100, a first source / drain electrode and a semiconductor layer of transistor 1000 are formed on substrate 200; the first source / drain electrode and the semiconductor layer are sequentially arranged along a second direction perpendicular to the substrate.

[0117] In some examples of this embodiment, a substrate 200 is provided, and the material of the substrate 200 can be a semiconductor material. For example, the material of the substrate 200 can be selected from one or more of silicon, gallium arsenide, silicon carbide, and germanium. In this embodiment, the material of the substrate 200 can be silicon, which can be intrinsic silicon or doped silicon. Further, the material of the substrate 200 can be single-crystal silicon; for example, a single-crystal silicon wafer can be selected as the substrate 200.

[0118] In some examples of this embodiment, forming a first source / drain electrode and a semiconductor layer in a transistor on a substrate specifically includes: forming an active cell on the substrate, the active cell including two active regions spaced apart along a first direction; a bit line trench extending through the active regions along a second direction perpendicular to the substrate is formed between the two active regions, and both the active regions and the bit line trench extend along a third direction; the third direction intersects the first direction; and performing an implantation process based on the bit line trench to form a first source / drain electrode and a second source / drain electrode spaced apart along the second direction in the active regions, the active region between the first source / drain electrode and the second source / drain electrode serving as a semiconductor layer.

[0119] Specifically, the step of forming active units on the substrate may include:

[0120] In step S101, Figure 5 This is a schematic diagram of step S101 in the above semiconductor structure fabrication method, as shown below. Figure 5 As shown, a patterned first photomask layer 7001 is fabricated on a substrate 200.

[0121] In step S102, as Figure 6 As shown, an etching process is performed on the first photomask layer 7001 to etch the substrate 200 to form an active unit 7002 on the substrate 200. The active unit 7002 includes two active regions spaced apart along a first direction and is formed into a well by ion implantation.

[0122] In step S103, as Figure 7As shown, the first photomask layer 7001 on the substrate 200 is removed. The active unit 7002 includes two active regions 7002a spaced apart along a first direction; a bit line trench 7003 extending through the active regions along a second direction perpendicular to the substrate is formed between the two active regions.

[0123] Then, an implantation process is performed based on the bit line trench 7003 to form a first source / drain 1001 and a second source / drain 1006 spaced apart along the second direction in the active region. The active region between the first source / drain and the second source / drain serves as a semiconductor layer 1002. The active region can be divided into three parts along the vertical direction. A protective layer is formed on the sidewall of the middle part. Using the protective layer as a mask, the other two parts are implanted to form the first source / drain 1001 and the second source / drain 1006. Specific steps include:

[0124] In step S104, as Figure 8 As shown, oxide material 7004 is filled using a high-density plasma chemical vapor deposition (HDP) process, followed by chemical mechanical polishing.

[0125] In step S105, as Figure 9 As shown, a portion of the oxide material 7004 is removed by an etching process, exposing a portion of the active region 7002a.

[0126] In step S106, as Figure 10 As shown, a sacrificial oxide layer 7005 of a predetermined thickness is grown on the outer surface of the active region 7002a.

[0127] In step S107, as Figure 11 As shown, the sacrificial oxide layer not covering the sidewall of the active region 7002a is removed by etching, while the sacrificial oxide layer 7005 covering the sidewall of the active region 7002a is retained.

[0128] In step S108, as Figure 12 As shown, a silicon nitride (SiN) layer 7006 is filled in, and a chemical mechanical polishing process is performed to prepare a patterned second photomask layer 7007.

[0129] In step S109, as Figure 13 As shown, the height h of the oxide layer 7005 in the z direction is defined by an etching process to form a protective layer 7008 on the sidewall of the middle part of the active region.

[0130] In step S110, as Figure 14 As shown, the second photomask layer 7007 is removed, the silicon nitride layer 7006 is backfilled, and a chemical mechanical polishing process is performed.

[0131] In step S111, as Figure 15 As shown, a patterned third photomask layer 7009 is prepared.

[0132] In step S112, as Figure 16 As shown, an etching process is performed based on the third photomask layer 7009 to expose the filled oxide layer 7004, and then the third photomask layer 7009 is cleaned away.

[0133] In step S113, as Figure 17 As shown, the filling oxide layer is cleaned away.

[0134] In step S114, as Figure 18 As shown, the filled silicon nitride is cleaned away to expose the remaining sacrificial oxide layer, so as to form a protective layer 7008 on the sidewall of the middle part of the active region.

[0135] In some examples of this embodiment, an implantation process is performed based on bitline trenches to form a first source / drain electrode and a second source / drain electrode spaced apart along a second direction in the active region, wherein: the aforementioned protective layer is used as a mask to implant the other two portions. Specifically, this includes:

[0136] In step S115, as Figure 19 As shown, the first source / drain electrode and the second source / drain electrode of the device are formed by ion implantation using the aforementioned protective layer 7008 as a mask.

[0137] In step S116, as Figure 20 As shown, the sacrificial oxide layer is cleaned to remove the protective layer 7008; wherein, a first source-drain electrode 1001 and a second source-drain electrode 1006 are formed in the active region at intervals along the second direction, and the active region between the first source-drain electrode and the second source-drain electrode serves as the semiconductor layer 1002.

[0138] It can be understood that through steps S101 to S116, the first source / drain 1001, semiconductor layer 1002, and second source / drain 1006 of the transistor 1000 can be formed on the substrate 200; the first source / drain 1001, semiconductor layer 1002, and second source / drain 1006 are arranged sequentially along a second direction perpendicular to the substrate 200.

[0139] In step S200, a bit line structure 300 is formed on the substrate in the transistor structure 100. The bit line structure 300 is located between two transistors 1000 and extends along a third direction, and is connected to the first source and drain 1001 of each transistor 1000 respectively.

[0140] In some examples of this embodiment, forming a bit line structure 300 in the transistor structure 100 on the substrate 200 includes: forming an insulating layer 7010 in a bit line trench 7003 covering the bottom and sidewalls of the bit line trench 7003; forming a bit line 3002 extending in a third direction at the bottom and sidewalls of the insulating layer 7010; removing a portion of the insulating layer 7010 so that the insulating layer contacts the bottom and sidewalls of the bit line, respectively, to form the bit line structure 300; specifically including the following steps:

[0141] In step S201, as Figure 21 As shown, an oxide isolation layer 7011 is filled and a chemical mechanical polishing process is performed.

[0142] In step S202, as Figure 22 As shown, a patterned fourth photomask layer 7012 is prepared.

[0143] In step S203, as Figure 23 As shown, some of the oxide in the bit line trench 7003 is removed by etching, while some of the oxide isolation layer 7011 is retained.

[0144] In step S204, as Figure 24 As shown, the fourth photomask layer 7012 is removed.

[0145] In step S205, as Figure 25 As shown, silicon nitride thin films are generated using a chemical vapor deposition (CVD) process.

[0146] In step S206, as Figure 26 As shown, conductive material is deposited using a chemical vapor deposition (CVD) process to form a bit line 3001 extending in a third direction.

[0147] In step S207, as Figure 27 As shown, the oxide isolation layer 7011 is refilled and a chemical mechanical polishing process is performed.

[0148] In step S208, as Figure 28 As shown, a patterned fifth photomask layer 7014 is prepared.

[0149] In step S209, as Figure 29 As shown, part of the oxide isolation layer and the silicon nitride film at the edge are removed by etching to expose the bit line 3001, forming an insulating layer 3002. The insulating layer 3002 contacts the bottom and sidewall of the bit line 3001 to form the bit line structure 300.

[0150] In step S210, as Figure 30 As shown, fill in the bit line contact structure 5002.

[0151] In step S211, as Figure 31 As shown, the fifth photomask layer 7014 is removed and then the oxide isolation layer 7011 is filled in.

[0152] In step S212, as Figure 32 As shown, a portion of the oxide isolation layer 7011 at the top is removed by an etching process, exposing part of the active region 7002a.

[0153] It can be understood that through steps S201 to S212, a bit line structure 300 located in the transistor structure 100 can be formed on the substrate. The bit line structure 300 is located between two transistors 1000 and extends along a third direction, respectively connecting to the first source and drain 1001 of each transistor 1000.

[0154] In step S300, a gate layer is formed on the semiconductor layer surrounding the sidewalls of the semiconductor layer.

[0155] In some examples of this embodiment, the step of forming a gate layer surrounding the sidewalls of the semiconductor layer on the semiconductor layer includes: forming a gate structure covering a portion of the sidewalls of the semiconductor layer on the semiconductor layer; the gate structure includes a gate dielectric layer and a gate material; wherein the sidewalls of the semiconductor layers in the two transistors not covered by the gate structure are disposed opposite each other; at least the gate material between adjacent active regions is removed to form a gate layer surrounding the sidewalls of the semiconductor layer; specifically, this may include the following steps:

[0156] In step S301, as Figure 33 As shown, in Figure 32 An oxide of a predetermined thickness is grown on the surface of the structure shown, serving as the gate dielectric layer 7012.

[0157] In step S302, as Figure 34 The oxide that is not covered on the surface of the active region 7002a is removed by an etching process, as shown.

[0158] In step S303, as Figure 35 As shown, gate material 7013 is filled in and chemical mechanical polishing process is performed, wherein gate material 7013 can be polycrystalline silicon.

[0159] In step S304, as Figure 36 As shown, a patterned sixth photomask layer 7015 is prepared.

[0160] In step S305, as Figure 37 As shown, the gate layer is defined by an etching process so that the sidewalls 1004 of the semiconductor layers in the two transistors that are not covered by the gate structure are positioned opposite each other.

[0161] In step S306, as Figure 38 As shown, the oxide is refilled and then subjected to a chemical mechanical polishing process.

[0162] In step S307, as Figure 39 As shown, a patterned seventh photomask layer 7016 is prepared.

[0163] In step S308, as Figure 40 As shown, an etching process is used to remove at least the gate material between the third-party upward adjacent active cells 7002.

[0164] In step S309, as Figure 41 As shown, a patterned eighth photomask layer 7017 is fabricated to expose the second source / drain electrode 1006.

[0165] In step S310, as Figure 42 As shown, the second source / drain 1006 is exposed by removing part of the gate structure and oxide through an etching process.

[0166] In step S311, as Figure 43 As shown, silicon nitride is filled and then chemically mechanically polished to planarize it.

[0167] In step S312, as Figure 44 As shown, a contact window photomask layer 7018 was prepared.

[0168] In step S313, as Figure 45 As shown, the contact window 7019 is defined by an etching process, and the positions of the contact windows 7018 need to be staggered to ensure that components can be connected through different traces, thereby selectively opening or closing.

[0169] In step S314, as Figure 46 As shown, the impedance of the contact window 7019 is reduced by using ion implantation.

[0170] In step S315, as Figure 47 As shown, by filling contact window 7019 with tungsten metal 7020 and performing tungsten metal chemical mechanical polishing planarization, a capacitor contact structure 6002 and a word line contact structure 5002 are formed.

[0171] In some examples of this embodiment, the method further includes: extending a word line structure along a first direction on the side of the transistor structure away from the substrate; wherein the word line structure includes two word lines spaced apart along a third direction, and the two word lines in the word line structure are respectively connected to the gate layers of two transistors in the transistor structure through word line contact structures.

[0172] It is understandable that through steps S100 to S300, the following can be prepared: Figures 1A to 2C The semiconductor structure shown is illustrated. It can be understood that the transistor structure fabricated by the method of the above embodiments includes two transistors spaced apart along a first direction; each transistor includes a first source / drain electrode and a semiconductor layer sequentially arranged along a second direction perpendicular to the substrate, and a gate layer surrounding the sidewalls of the semiconductor layer; a bit line structure is located between the two transistors and extends along a third direction, connecting to the first source / drain electrode of each transistor; the third direction intersects the first direction; thus, the channel length of the transistor in the semiconductor device can be effectively increased, the electric field between the source and drain electrodes of the transistor can be reduced, leakage current in the transistor can be reduced, the drive current of the semiconductor device can be increased, and the lifespan and performance of the transistor device can be effectively improved.

[0173] This disclosure also provides an electronic device that may include the semiconductor structure as described in any of the above embodiments, or a semiconductor structure made by a method for preparing the semiconductor structure as described in any of the above embodiments.

[0174] Furthermore, the electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This application does not impose any special limitations on the specific form of the aforementioned electronic device.

[0175] It should be noted that the above embodiments are for illustrative purposes only and do not imply any limitation on this disclosure.

[0176] It should be understood that, unless explicitly stated herein, there is no strict order in which the steps are performed; these steps may be performed in other orders. Moreover, at least some steps in the preparation process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0177] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0178] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0179] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0180] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a transistor structure comprising two transistors arranged in a first direction; the transistor comprises a first source-drain electrode and a semiconductor layer arranged in a second direction perpendicular to the substrate in sequence, and a gate layer surrounding the sidewall of the semiconductor layer; a bit line structure arranged between the two transistors and extending in a third direction, and connected to the first source-drain electrode of each transistor respectively; the third direction intersects the first direction.

2. The semiconductor structure of claim 1, wherein, Further comprising: a bit line contact structure arranged on the top surface of the bit line structure away from the substrate, and in contact with the adjacent first source-drain electrode respectively; wherein the bit line structure is arranged apart from the gate layer.

3. The semiconductor structure of claim 1, wherein, The bit line structure comprises: a bit line; an insulating layer arranged between the bit line and the substrate, and in contact with the bottom of the bit line and the sidewall of the bit line respectively.

4. The semiconductor structure of claim 1, wherein, The two transistors in the transistor structure are mirror-symmetric.

5. The semiconductor structure of claim 1, wherein, The gate layer covers part of the sidewall of the semiconductor layer, and the sidewalls of the semiconductor layer in the two transistors not covered by the gate layer are arranged oppositely.

6. The semiconductor structure of claim 1, wherein, Further comprising: a word line structure arranged on the side of the transistor structure away from the substrate and extending in the first direction, comprising two word lines arranged in the third direction; wherein the two word lines in the word line structure and the gate layers of the two transistors in the transistor structure are connected correspondingly.

7. The semiconductor structure of claim 6, wherein, The semiconductor structure comprises a plurality of transistor structures arranged in an array, and a plurality of transistor structures arranged in a column in the third direction share one bit line structure, and a plurality of transistor structures arranged in a row in the first direction share one word line structure.

8. The semiconductor structure of claim 7, wherein, Among the plurality of transistor structures arranged in the first direction, the odd-numbered transistors share one word line in the word line structure, and the even-numbered transistors share another word line in the word line structure.

9. The semiconductor structure of claim 1, wherein, The transistor further comprises a second source-drain electrode, and the semiconductor structure further comprises: a storage structure arranged on the side of the transistor structure away from the substrate, arranged correspondingly to the transistor, and connected to the second source-drain electrode of the transistor.

10. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure comprises a transistor structure comprising two transistors arranged in a first direction, and the preparation method comprises: forming a first source-drain electrode and a semiconductor layer in a transistor on a substrate; the first source-drain electrode and the semiconductor layer are arranged in a second direction perpendicular to the substrate in sequence; forming a bit line structure in the transistor structure on the substrate, the bit line structure is arranged between the two transistors and extends in a third direction, and is connected to the first source-drain electrode of each transistor respectively; forming a gate layer surrounding the sidewall of the semiconductor layer on the semiconductor layer.

11. The method of claim 10, wherein, The step of forming a first source-drain electrode and a semiconductor layer in a transistor on the substrate comprises: forming an active unit on the substrate, the active unit comprising two active regions arranged in a first direction; a bit line trench is formed between the two active regions, the bit line trench penetrating the active regions in a second direction perpendicular to the substrate, the active regions and the bit line trench extending in a third direction; the third direction intersects the first direction; forming a first source / drain and a second source / drain in the active regions in the second direction based on the bit line trench, the active region between the first source / drain and the second source / drain being the semiconductor layer.

12. The method of claim 11, wherein, The step of forming a first source / drain and a second source / drain in the active regions in the second direction based on the bit line trench comprises: dividing the active region into three parts in a vertical direction, the sidewall of the middle part forming a protection layer, and using the protection layer as a mask to perform implantation on the other two parts.

13. The preparation method according to claim 11, characterized in that, The step of forming a gate layer surrounding the sidewall of the semiconductor layer on the semiconductor layer comprises: forming a gate structure on the semiconductor layer, the gate structure covering part of the sidewall of the semiconductor layer; the gate structure comprises a gate dielectric layer and a gate material; wherein the sidewalls of the semiconductor layer in the two transistors that are not covered by the gate structure are oppositely arranged; removing at least the gate material between adjacent active regions to form a gate layer surrounding the sidewall of the semiconductor layer.

14. The method of claim 11, wherein, The step of forming a bit line structure in the transistor structure on the substrate comprises: forming an insulating layer in the bit line trench, the insulating layer covering the bottom and sidewall of the bit line trench; forming a bit line extending in the third direction on the bottom and sidewall of the insulating layer; removing part of the insulating layer, so that the insulating layer is in contact with the bottom of the bit line and the sidewall of the bit line respectively, to form the bit line structure.

15. The preparation method according to claim 10, characterized in that, The method further comprises: forming a word line structure extending in the first direction on the side of the transistor structure away from the substrate; wherein the word line structure comprises two word lines arranged in the third direction, and the two word lines in the word line structure and the gate layers of the two transistors in the transistor structure are respectively connected.

16. An electronic device, comprising: The semiconductor structure according to any one of claims 1 to 9, or a semiconductor structure prepared by the preparation method according to any one of claims 10 to 15.

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